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Merge branch 'feature/dds'

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This commit is contained in:
T-moe
2016-06-12 22:50:42 +02:00
parent 9cfabb1772 2c49e35b54
commit 4e79e6316e
4 changed files with 15 additions and 356 deletions
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2
.gitignore vendored
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@@ -8,10 +8,10 @@
!*.ucf
!*.vhd
!*.sch
!*.gise
!*.xise
!*.jhd
!*.wcfg
!*.filter
!*/
!documentation/*
!screenshots/*

13
iseconfig/filter.filter Normal file
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@@ -0,0 +1,13 @@
<!-- -->
<!--This is an internal file that has been generated by the Xilinx ISE software. Any direct -->
<!--editing of this file may result in data corruption or in unpredictable behavior. It is strongly -->
<!--advised that users do not directly edit the contents of this file. -->
<!-- -->
<filters xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation='filter.xsd'>
<filter task="xst" file="Xst" num="1293" type="warning"><arg index="1">ret_state_8</arg><arg index="2">0</arg><arg index="3">lcd_driver</arg></filter>
<filter task="xst" file="Xst" num="1896" type="warning"><arg index="1">ret_state_6</arg><arg index="2">0</arg><arg index="3">lcd_driver</arg></filter>
<filter task="xst" file="Xst" num="643" type="warning"><arg index="1" match_type="wildcard">/home/timo/workspace/vhdl-yasg/controller.vhd</arg><arg index="2" match_type="wildcard">169</arg><arg index="3" match_type="wildcard">*</arg><arg index="4" match_type="wildcard">*</arg><arg index="5" match_type="wildcard">17</arg></filter>
<filter task="xst" file="Xst" num="1896" type="warning"><arg index="1">ret_state_7</arg><arg index="2">0</arg><arg index="3">lcd_driver</arg></filter>
<filter task="xst" file="Xst" num="1293" type="warning"><arg index="1">ret_state_reg_0</arg><arg index="2">0</arg><arg index="3">controller</arg></filter>
<filter task="xst" file="Xst" num="1293" type="warning"><arg index="1">lcd_data_reg_7</arg><arg index="2">0</arg><arg index="3">controller</arg></filter>
</filters>

355
yasg.gise
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@@ -1,355 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
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<!-- -->
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<transform xil_pn:end_ts="1465553455" xil_pn:in_ck="6038244062278950263" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6927427346963598489" xil_pn:start_ts="1465553453">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="toplevel.vhf"/>
</transform>
<transform xil_pn:end_ts="1465545216" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1929794406770174374" xil_pn:start_ts="1465545216">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1465545216" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1465545216">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1465545216" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2239360189155701135" xil_pn:start_ts="1465545216">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1465545216" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="9102341965431189672" xil_pn:start_ts="1465545216">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1465545216" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="7072966905182239268" xil_pn:start_ts="1465545216">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1465554370" xil_pn:in_ck="-5804926608689456155" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="1663716282806445198" xil_pn:start_ts="1465554354">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name=".lso"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="dds.ngr"/>
<outfile xil_pn:name="lcd_driver.ngr"/>
<outfile xil_pn:name="spi_driver.ngr"/>
<outfile xil_pn:name="toplevel.jhd"/>
<outfile xil_pn:name="toplevel.lso"/>
<outfile xil_pn:name="toplevel.ngc"/>
<outfile xil_pn:name="toplevel.ngr"/>
<outfile xil_pn:name="toplevel.prj"/>
<outfile xil_pn:name="toplevel.stx"/>
<outfile xil_pn:name="toplevel.syr"/>
<outfile xil_pn:name="toplevel.xst"/>
<outfile xil_pn:name="toplevel_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1465547155" xil_pn:in_ck="4242637380" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4784894232377633197" xil_pn:start_ts="1465547155">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1465554375" xil_pn:in_ck="-2091007341535647977" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1538882668640856751" xil_pn:start_ts="1465554370">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="toplevel.bld"/>
<outfile xil_pn:name="toplevel.ngd"/>
<outfile xil_pn:name="toplevel_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1465554381" xil_pn:in_ck="1621356785167787192" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="570889668722473129" xil_pn:start_ts="1465554375">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="toplevel.pcf"/>
<outfile xil_pn:name="toplevel_map.map"/>
<outfile xil_pn:name="toplevel_map.mrp"/>
<outfile xil_pn:name="toplevel_map.ncd"/>
<outfile xil_pn:name="toplevel_map.ngm"/>
<outfile xil_pn:name="toplevel_map.xrpt"/>
<outfile xil_pn:name="toplevel_summary.xml"/>
<outfile xil_pn:name="toplevel_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1465554399" xil_pn:in_ck="985354266144665770" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-988662182046631445" xil_pn:start_ts="1465554381">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="toplevel.ncd"/>
<outfile xil_pn:name="toplevel.pad"/>
<outfile xil_pn:name="toplevel.par"/>
<outfile xil_pn:name="toplevel.ptwx"/>
<outfile xil_pn:name="toplevel.unroutes"/>
<outfile xil_pn:name="toplevel.xpi"/>
<outfile xil_pn:name="toplevel_pad.csv"/>
<outfile xil_pn:name="toplevel_pad.txt"/>
<outfile xil_pn:name="toplevel_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1465554407" xil_pn:in_ck="8640606860472830956" xil_pn:name="TRANEXT_bitFile_spartan3a" xil_pn:prop_ck="-426368325978129584" xil_pn:start_ts="1465554399">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="toplevel.bgn"/>
<outfile xil_pn:name="toplevel.bit"/>
<outfile xil_pn:name="toplevel.drc"/>
<outfile xil_pn:name="toplevel.ut"/>
<outfile xil_pn:name="usage_statistics_webtalk.html"/>
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1465549412" xil_pn:in_ck="6038244062278931960" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5767926783713760761" xil_pn:start_ts="1465549411">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1465554399" xil_pn:in_ck="6034042283462732464" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1465554395">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="toplevel.twr"/>
<outfile xil_pn:name="toplevel.twx"/>
</transform>
</transforms>
</generated_project>

1
yasg.xise
View File

@@ -76,6 +76,7 @@
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s700an" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3A and Spartan3AN" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="Spartan-3AN Starter Kit" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|toplevel" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="toplevel.sch" xil_pn:valueState="non-default"/>