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Added controller testbench and screenshots.

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This commit is contained in:
T-moe
2016-06-19 20:30:02 +02:00
parent ed53854a38
commit 492d358a04
6 changed files with 189 additions and 35 deletions
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109
controller_tb.vhd
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@@ -3,13 +3,13 @@
-- Project Page: https://github.com/id101010/vhdl-yasg/
-- Authors: Aaron Schmocker & Timo Lang
-- License: GPL v3
-- Create Date: 20:08:51 06/06/2016
-- Create Date: 18:02:40 06/19/2016
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY controller_tb IS
END controller_tb;
@@ -21,13 +21,14 @@ ARCHITECTURE behavior OF controller_tb IS
PORT(
clk : IN std_logic;
rst : IN std_logic;
enc_updown : IN std_logic;
enc_right : IN std_logic;
enc_ce : IN std_logic;
enc_btn : IN std_logic;
enc_err : IN std_logic;
form : IN unsigned(1 downto 0);
lcd_busy : IN std_logic;
lcd_data : OUT unsigned(7 downto 0);
lcd_newchar : OUT std_logic;
lcd_newpos : OUT std_logic;
freq_out : OUT unsigned(16 downto 0)
);
END COMPONENT;
@@ -36,56 +37,122 @@ ARCHITECTURE behavior OF controller_tb IS
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal enc_updown : std_logic := '0';
signal enc_right : std_logic := '0';
signal enc_ce : std_logic := '0';
signal enc_btn : std_logic := '0';
signal enc_err : std_logic := '0';
signal form : unsigned(1 downto 0) := (others => '0');
signal lcd_busy : std_logic := '0';
--Outputs
--Outputs
signal lcd_data : unsigned(7 downto 0);
signal lcd_newchar : std_logic;
signal lcd_newpos : std_logic;
signal freq_out : unsigned(16 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
constant clk_period : time := 20 ns; --50mhz
BEGIN
-- Instantiate the Unit Under Test (UUT)
-- Instantiate the Unit Under Test (UUT)
uut: controller PORT MAP (
clk => clk,
rst => rst,
enc_updown => enc_updown,
enc_right => enc_right,
enc_ce => enc_ce,
enc_btn => enc_btn,
enc_err => enc_err,
form => form,
lcd_busy => lcd_busy,
lcd_data => lcd_data,
lcd_newchar => lcd_newchar,
lcd_newpos => lcd_newpos,
freq_out => freq_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
rst <= '1';
wait for 100 ns;
rst <= '0';
rst<= '0';
lcd_busy <= '0';
lcd_busy<='1'; --simulate lcd busy
wait for 200 ns;
lcd_busy<='0';
wait for 1000 ns;
wait until lcd_newchar = '1';
lcd_busy<='1'; --simulate lcd busy
wait for 150 ns;
lcd_busy<='0';
wait for 400 ns;
--init should be finished here
--Test encoder turn right
enc_right <='1';
enc_ce <= '1';
wait for clk_period;
enc_ce <= '0';
wait for 300 ns;
-- Now the same but with lcd_busy
enc_ce <= '1';
wait for clk_period;
enc_ce <= '0';
wait until lcd_newpos = '1';
lcd_busy<='1'; --simulate lcd busy
wait for 150 ns;
lcd_busy<='0';
wait for 300 ns;
--Test encoder turn left
enc_right <= '0';
enc_ce <= '1';
wait for clk_period;
enc_ce <= '0';
wait until lcd_newpos = '1';
lcd_busy<='1'; --simulate lcd busy
wait for 150 ns;
lcd_busy<='0';
wait for 300 ns;
--Test button press
enc_btn <= '1';
wait for clk_period;
enc_btn <= '0';
wait for 150 ns;
--Test another turn left
enc_ce <= '1';
wait for clk_period;
enc_ce <= '0';
wait until lcd_newpos = '1';
lcd_busy<='1'; --simulate lcd busy
wait for 150 ns;
lcd_busy<='0';
wait for 300 ns;
-- insert stimulus here

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87
simulate_controller.wcfg Normal file
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@@ -0,0 +1,87 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="/home/timo/workspace/vhdl-yasg/controller_tb_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="controller_tb" />
<top_module name="numeric_std" />
<top_module name="std_logic_1164" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="17" />
<wvobject fp_name="/controller_tb/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/controller_tb/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/controller_tb/enc_right" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">enc_right</obj_property>
<obj_property name="ObjectShortName">enc_right</obj_property>
</wvobject>
<wvobject fp_name="/controller_tb/enc_ce" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">enc_ce</obj_property>
<obj_property name="ObjectShortName">enc_ce</obj_property>
</wvobject>
<wvobject fp_name="/controller_tb/enc_btn" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">enc_btn</obj_property>
<obj_property name="ObjectShortName">enc_btn</obj_property>
</wvobject>
<wvobject fp_name="/controller_tb/form" type="array" db_ref_id="1">
<obj_property name="ElementShortName">form[1:0]</obj_property>
<obj_property name="ObjectShortName">form[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/controller_tb/lcd_busy" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">lcd_busy</obj_property>
<obj_property name="ObjectShortName">lcd_busy</obj_property>
</wvobject>
<wvobject fp_name="/controller_tb/lcd_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">lcd_data[7:0]</obj_property>
<obj_property name="ObjectShortName">lcd_data[7:0]</obj_property>
<obj_property name="Radix">ASCIIRADIX</obj_property>
</wvobject>
<wvobject fp_name="/controller_tb/lcd_newchar" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">lcd_newchar</obj_property>
<obj_property name="ObjectShortName">lcd_newchar</obj_property>
</wvobject>
<wvobject fp_name="/controller_tb/lcd_newpos" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">lcd_newpos</obj_property>
<obj_property name="ObjectShortName">lcd_newpos</obj_property>
</wvobject>
<wvobject fp_name="/controller_tb/freq_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">freq_out[16:0]</obj_property>
<obj_property name="ObjectShortName">freq_out[16:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/controller_tb/clk_period" type="other" db_ref_id="1">
<obj_property name="ElementShortName">clk_period</obj_property>
<obj_property name="ObjectShortName">clk_period</obj_property>
</wvobject>
<wvobject fp_name="/controller_tb/uut/state_reg" type="other" db_ref_id="1">
<obj_property name="ElementShortName">state_reg</obj_property>
<obj_property name="ObjectShortName">state_reg</obj_property>
</wvobject>
<wvobject fp_name="/controller_tb/uut/ret_state_reg" type="other" db_ref_id="1">
<obj_property name="ElementShortName">ret_state_reg</obj_property>
<obj_property name="ObjectShortName">ret_state_reg</obj_property>
</wvobject>
<wvobject fp_name="/controller_tb/uut/digpos_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">digpos_reg[2:0]</obj_property>
<obj_property name="ObjectShortName">digpos_reg[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/controller_tb/uut/charcnt_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">charcnt_reg[3:0]</obj_property>
<obj_property name="ObjectShortName">charcnt_reg[3:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/controller_tb/uut/digit_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">digit_reg[0:7]</obj_property>
<obj_property name="ObjectShortName">digit_reg[0:7]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
</wave_config>

28
yasg.xise
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@@ -16,19 +16,19 @@
<files>
<file xil_pn:name="lcd_driver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="dds.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="helpers.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="dds_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="27"/>
@@ -59,23 +59,23 @@
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="lcd_driver_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="132"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="132"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="132"/>
</file>
<file xil_pn:name="controller_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="143"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="143"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="143"/>
</file>
<file xil_pn:name="rotary_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="68"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="68"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="68"/>
</file>
<file xil_pn:name="controller_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="80"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="80"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="80"/>
</file>
</files>
<properties>
@@ -90,8 +90,8 @@
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/lcd_driver_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.lcd_driver_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/dds_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.dds_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
@@ -101,7 +101,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|lcd_driver_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|dds_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="yasg" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-05-09T19:06:02" xil_pn:valueState="non-default"/>