From 45b78fe93e35ff39d61ffcde7b3211226c89300c Mon Sep 17 00:00:00 2001 From: T-moe Date: Mon, 6 Jun 2016 20:44:55 +0200 Subject: [PATCH] Fixed controller lcd output by adding edge detection on lcd_busy. added testbench for controller. --- controller.vhd | 15 ++++-- controller_tb.vhd | 118 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 129 insertions(+), 4 deletions(-) create mode 100644 controller_tb.vhd diff --git a/controller.vhd b/controller.vhd index 16eeda6..b699bab 100644 --- a/controller.vhd +++ b/controller.vhd @@ -56,8 +56,12 @@ architecture Behavioral of controller is signal lcd_newchar_reg,lcd_newchar_next : std_logic := '0'; signal lcd_data_reg, lcd_data_next: unsigned(7 downto 0) :=(others => '0'); - type character_array is array (15 downto 0) of character; - constant line1 : character_array := ( 'h', 'e', 'l','l','o', others=> ' ' ); + type character_array is array (0 to 15) of character; + constant line1 : character_array := ( 'h', 'e', 'l','l','o',' ', 'A', 'a', 'r', 'o', 'n', others=> ' ' ); + + -- for edge detection on lcd_busy + signal busy_old_reg, busy_old_next : std_logic := '0'; + begin @@ -71,6 +75,7 @@ begin charcnt_reg <= (others => '0'); lcd_newchar_reg <= '0'; lcd_data_reg <= (others => '0'); + busy_old_reg <= '0'; elsif(rising_edge(clk)) then digpos_reg <= digpos_next; @@ -80,6 +85,7 @@ begin charcnt_reg <= charcnt_next; lcd_newchar_reg<= lcd_newchar_next; lcd_data_reg <= lcd_data_next; + busy_old_reg <= busy_old_next; end if; end process proc1; @@ -103,7 +109,7 @@ begin lcd_data <= lcd_data_reg; lcd_newchar <= lcd_newchar_reg; - proc2: process(digit_reg,enc_updown,enc_ce,enc_err,enc_btn,digpos_reg,btn_old_reg, charcnt_reg, lcd_busy, lcd_data_reg, lcd_newchar_reg) + proc2: process(digit_reg,enc_updown,enc_ce,enc_err,enc_btn,digpos_reg,btn_old_reg, charcnt_reg, lcd_busy, lcd_data_reg, lcd_newchar_reg, busy_old_reg) begin digit_next <= digit_reg; digpos_next <= digpos_reg; @@ -112,6 +118,7 @@ begin charcnt_next <= charcnt_reg; lcd_newchar_next <= '0'; lcd_data_next <= lcd_data_reg; + busy_old_next <= lcd_busy; if(enc_ce='1' and enc_err='0') then if(enc_updown='1') then @@ -127,7 +134,7 @@ begin end if; end if; - if(lcd_busy = '0' and charcnt_reg < 10) then + if(lcd_busy = '0' and busy_old_reg ='1' and charcnt_reg < 16) then lcd_data_next <= to_unsigned(character'pos(line1(to_integer(charcnt_reg))),8); lcd_newchar_next <= '1'; charcnt_next <= charcnt_reg + 1; diff --git a/controller_tb.vhd b/controller_tb.vhd new file mode 100644 index 0000000..196c2e0 --- /dev/null +++ b/controller_tb.vhd @@ -0,0 +1,118 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 20:08:51 06/06/2016 +-- Design Name: +-- Module Name: /home/timo/workspace/vhdl-yasg/controller_tb.vhd +-- Project Name: yasg +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: controller +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +USE ieee.numeric_std.ALL; + +ENTITY controller_tb IS +END controller_tb; + +ARCHITECTURE behavior OF controller_tb IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT controller + PORT( + clk : IN std_logic; + rst : IN std_logic; + enc_updown : IN std_logic; + enc_ce : IN std_logic; + enc_btn : IN std_logic; + enc_err : IN std_logic; + lcd_busy : IN std_logic; + lcd_data : OUT unsigned(7 downto 0); + lcd_newchar : OUT std_logic; + freq_out : OUT unsigned(16 downto 0) + ); + END COMPONENT; + + + --Inputs + signal clk : std_logic := '0'; + signal rst : std_logic := '0'; + signal enc_updown : std_logic := '0'; + signal enc_ce : std_logic := '0'; + signal enc_btn : std_logic := '0'; + signal enc_err : std_logic := '0'; + signal lcd_busy : std_logic := '0'; + + --Outputs + signal lcd_data : unsigned(7 downto 0); + signal lcd_newchar : std_logic; + signal freq_out : unsigned(16 downto 0); + + -- Clock period definitions + constant clk_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: controller PORT MAP ( + clk => clk, + rst => rst, + enc_updown => enc_updown, + enc_ce => enc_ce, + enc_btn => enc_btn, + enc_err => enc_err, + lcd_busy => lcd_busy, + lcd_data => lcd_data, + lcd_newchar => lcd_newchar, + freq_out => freq_out + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ns. + wait for 100 ns; + + wait for clk_period*10; + + rst<= '0'; + lcd_busy <= '0'; + + + -- insert stimulus here + + wait; + end process; + +END;