Added lcd_driver template.
This commit is contained in:
id101010
50
lcd_driver.vhd
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50
lcd_driver.vhd
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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 19:29:54 05/09/2016
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-- Design Name:
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-- Module Name: lcddriver - Behavioral
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-- Project Name: yasg
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity lcd_driver is
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Port ( clk : in STD_LOGIC; -- Systemclock (~50MHz)
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data : in STD_LOGIC_VECTOR (7 downto 0); -- either one ascii char (8bit) or new cursor position (0-31)
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new_character : in STD_LOGIC; -- a new character is available on the data bus
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new_pos : in STD_LOGIC; -- a new cursor position is available on the data bus
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auto_incr_cursor : in STD_LOGIC; -- the cursor should automatically be incremented after writing a new character
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lcd_db : out STD_LOGIC_VECTOR (7 downto 0); -- lcd databus
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lcd_en : out STD_LOGIC; -- lcd enable
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lcd_rw : out STD_LOGIC; -- lcd read/write
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lcd_rs : out STD_LOGIC); -- lcd register select
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end lcd_driver;
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architecture Behavioral of lcd_driver is
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begin
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end Behavioral;
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28
yasg.gise
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28
yasg.gise
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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<!-- -->
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<!-- For tool use only. Do not edit. -->
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<!-- -->
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<!-- ProjectNavigator created generated project file. -->
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<!-- For use in tracking generated file and other information -->
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<!-- allowing preservation of process status. -->
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<!-- -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
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<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="yasg.xise"/>
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<files xmlns="http://www.xilinx.com/XMLSchema"/>
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<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
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</generated_project>
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47
yasg.xise
47
yasg.xise
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<!-- along with the project source files, is sufficient to open and -->
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<!-- implement in ISE Project Navigator. -->
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<!-- -->
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<!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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</header>
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<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
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<files>
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<file xil_pn:name="lcd_driver.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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</file>
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</files>
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<properties>
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<property xil_pn:name="Project Description" xil_pn:value=""/>
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<property xil_pn:name="Working Directory" xil_pn:value="/home/aaron/Dokumente/STUDIUM/SEM6/EloSys/EloSysDigital/Projekt/vhdl-yasg"/>
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<property xil_pn:name="Top-Level Source Type" xil_pn:value="Schematic"/>
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<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
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<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)"/>
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<property xil_pn:name="Preferred Language" xil_pn:value="VHDL"/>
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<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only"/>
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<property xil_pn:name="Manual Compile Order" xil_pn:value="false"/>
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<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93"/>
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<property xil_pn:name="Enable Message Filtering" xil_pn:value="false"/>
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<property xil_pn:name="Device" xil_pn:value="xc3s700an" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Device Family" xil_pn:value="Spartan3A and Spartan3AN" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Evaluation Development Board" xil_pn:value="Spartan-3AN Starter Kit" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|lcd_driver|Behavioral" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top File" xil_pn:value="lcd_driver.vhd" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/lcd_driver" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
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<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Top-Level Source Type" xil_pn:value="Schematic" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
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<!-- -->
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<!-- The following properties are for internal use only. These should not be modified.-->
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<!-- -->
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<property xil_pn:name="PROP_DesignName" xil_pn:value="yasg" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-05-09T19:06:02" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="9244AF8635FECD2B4B24CA9D0188DD99" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
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</properties>
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<bindings/>
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<libraries/>
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<autoManagedFiles>
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<!-- The following files are identified by `include statements in verilog -->
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<!-- source files and are automatically managed by Project Navigator. -->
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<!-- -->
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<!-- Do not hand-edit this section, as it will be overwritten when the -->
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<!-- project is analyzed based on files automatically identified as -->
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<!-- include files. -->
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</autoManagedFiles>
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</project>
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