aaron/vhdl-yasg
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Added screenshots, modified testbench for lcd driver

Browse Source
This commit is contained in:
id101010
2016-06-19 17:54:54 +02:00
parent f7cbd02e6e d0ab7b7d16
commit 411ced7222
6 changed files with 257 additions and 150 deletions
Download Patch File Download Diff File Expand all files Collapse all files

176
controller.vhd
View File

@@ -11,6 +11,7 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; use IEEE.NUMERIC_STD.ALL;
entity controller is entity controller is
Generic (freq_res: natural:=17); -- width of frequency input (log2(max_freq))
Port ( clk : in STD_LOGIC; -- Clock Input Port ( clk : in STD_LOGIC; -- Clock Input
rst: in STD_LOGIC; -- High active, async reset rst: in STD_LOGIC; -- High active, async reset
enc_right : in STD_LOGIC; -- Encoder Input: 1= Direction Right, 0 = Direction Left enc_right : in STD_LOGIC; -- Encoder Input: 1= Direction Right, 0 = Direction Left
@@ -21,48 +22,51 @@ entity controller is
lcd_data: out unsigned(7 downto 0); -- LCD Output: Data output lcd_data: out unsigned(7 downto 0); -- LCD Output: Data output
lcd_newchar: out STD_LOGIC; -- LCD Output: Send a new character to the lcd lcd_newchar: out STD_LOGIC; -- LCD Output: Send a new character to the lcd
lcd_newpos : out STD_LOGIC; -- LCD Output: Send a new position/adress to the lcd lcd_newpos : out STD_LOGIC; -- LCD Output: Send a new position/adress to the lcd
freq_out : out unsigned (16 downto 0)); -- Frequency Ouput (Treshould in Hz) freq_out : out unsigned (freq_res-1 downto 0)); -- Frequency Output (Treshould in Hz)
end controller; end controller;
architecture Behavioral of controller is architecture Behavioral of controller is
type states is(S_WAIT, -- FSM with the following states:
type states is(S_WAIT, -- wait till the lcd is no longer busy, and returns in a specific state afterwards
S_FORM_PREF, -- prints the form prefix ("Form:") S_FORM_PREF, -- prints the form prefix ("Form:")
S_FREQ_PREF, -- frequenz prefix ("Freq: 00000 Hz") S_FREQ_PREF, -- frequenz prefix ("Freq: 00000 Hz")
S_FORM_CONT, -- form content ("Rechteck, Sinus...") S_FORM_CONT, -- form content ("Rechteck, Sinus...")
S_FREQ_CONT, -- frequenz content ("-----") S_FREQ_CONT, -- frequenz content ("-----")
S_IDLE ); S_IDLE ); -- controller is idle and waits on user input
signal state_reg, state_next : states := S_WAIT; signal state_reg, state_next : states := S_WAIT; -- Current State
signal ret_state_reg, ret_state_next: states := S_FORM_PREF; signal ret_state_reg, ret_state_next: states := S_FORM_PREF; -- State to return to, after S_WAIT
----- Edge detection registers ----- ----- Edge detection registers -----
signal btn_old_reg, btn_old_next : std_logic := '0'; signal btn_old_reg, btn_old_next : std_logic := '0';
signal enc_old_reg, enc_old_next: std_logic :='0'; signal enc_old_reg, enc_old_next: std_logic :='0';
signal busy_old_reg, busy_old_next : std_logic := '0';
signal form_old_reg, form_old_next : unsigned (1 downto 0) := (others => '0'); signal form_old_reg, form_old_next : unsigned (1 downto 0) := (others => '0');
--digitnr which is currently edited 0-4
signal digpos_reg, digpos_next : unsigned(2 downto 0) := (others => '0');
signal charcnt_reg, charcnt_next : unsigned(3 downto 0) := (others => '0');
-- array 5x 4bit(0-9) signal digpos_reg, digpos_next : unsigned(2 downto 0) := (others => '0'); -- digitnr which is currently edited 0-4
signal charcnt_reg, charcnt_next : unsigned(3 downto 0) := (others => '0'); -- character number which is currently being written out
-- Decimal value (0-9) of the sigle frequency digits (array 5x 4bit)
type storage_digit is array (0 to 7) of unsigned (3 downto 0); type storage_digit is array (0 to 7) of unsigned (3 downto 0);
signal digit_reg, digit_next : storage_digit := (others => (others => '0')); signal digit_reg, digit_next : storage_digit := (others => (others => '0'));
signal lcd_newchar_reg,lcd_newchar_next : std_logic := '0'; signal lcd_newchar_reg,lcd_newchar_next : std_logic := '0'; -- Register for the LCD Newchar signal
signal lcd_newpos_reg,lcd_newpos_next : std_logic := '0'; signal lcd_newpos_reg,lcd_newpos_next : std_logic := '0'; -- Register for the LCD Newpos signal
signal lcd_data_reg, lcd_data_next: unsigned(7 downto 0) :=(others => '0'); signal lcd_data_reg, lcd_data_next: unsigned(7 downto 0) :=(others => '0'); -- Register for the LCD Databus signal
signal freq_out_reg, freq_out_next : unsigned (16 downto 0) := (others => '0'); signal freq_out_reg, freq_out_next : unsigned (16 downto 0) := (others => '0'); -- Register for the frequency output (in hz)
----------------Constants--------------------------------- ----------------Constants---------------------------------
-- Signal Form Prefix:
type character_array_short is array (0 to 7) of character; type character_array_short is array (0 to 7) of character;
constant str_form_pref : character_array_short := ( 'F', 'o', 'r','m',':', others => ' ' ); constant str_form_pref : character_array_short := ( 'F', 'o', 'r','m',':', others => ' ' );
-- Signal Frequency Prefix/Postfix:
type character_array_long is array (0 to 15) of character; type character_array_long is array (0 to 15) of character;
constant str_freq_pref : character_array_long := ( 'F', 'r', 'e','q',':',' ','0','0','0','0','0',' ','H','z', others => ' ' ); constant str_freq_pref : character_array_long := ( 'F', 'r', 'e','q',':',' ','0','0','0','0','0',' ','H','z', others => ' ' );
-- Signal Form names:
type character_form_array is array (0 to 3, 0 to 7) of character; type character_form_array is array (0 to 3, 0 to 7) of character;
constant str_form : character_form_array := ( constant str_form : character_form_array := (
('S','q','u','a','r','e',' ',' '), ('S','q','u','a','r','e',' ',' '),
@@ -71,9 +75,11 @@ architecture Behavioral of controller is
('S','i','n','e',' ',' ',' ',' ') ('S','i','n','e',' ',' ',' ',' ')
); );
-- Possible improvement: Write a helper function which initializes those character arrays from a string
begin begin
-- State register process (sequential)
proc1: process(clk,rst) proc1: process(clk,rst)
begin begin
if(rst='1') then if(rst='1') then
@@ -82,7 +88,6 @@ begin
btn_old_reg <= '0'; btn_old_reg <= '0';
enc_old_reg <='0'; enc_old_reg <='0';
busy_old_reg <= '0';
form_old_reg <= "00"; form_old_reg <= "00";
charcnt_reg <= (others => '0'); charcnt_reg <= (others => '0');
@@ -92,6 +97,7 @@ begin
freq_out_reg <=(others => '0'); freq_out_reg <=(others => '0');
-- On reset: wait on display startup and then start with S_FORM_PREF state
state_reg <= S_WAIT; state_reg <= S_WAIT;
ret_state_reg <= S_FORM_PREF; ret_state_reg <= S_FORM_PREF;
@@ -101,7 +107,6 @@ begin
btn_old_reg <= btn_old_next; btn_old_reg <= btn_old_next;
enc_old_reg <= enc_old_next; enc_old_reg <= enc_old_next;
busy_old_reg <= busy_old_next;
form_old_reg <= form_old_next; form_old_reg <= form_old_next;
charcnt_reg <= charcnt_next; charcnt_reg <= charcnt_next;
@@ -117,143 +122,142 @@ begin
end if; end if;
end process proc1; end process proc1;
freq_out <= freq_out_reg; freq_out <= freq_out_reg;
lcd_data <= lcd_data_reg; lcd_data <= lcd_data_reg;
lcd_newchar <= lcd_newchar_reg; lcd_newchar <= lcd_newchar_reg;
lcd_newpos <= lcd_newpos_reg; lcd_newpos <= lcd_newpos_reg;
NSL: process(digit_reg,enc_right,enc_ce,enc_btn,digpos_reg,btn_old_reg, charcnt_reg, lcd_busy, lcd_data_reg, busy_old_reg, state_reg, ret_state_reg, enc_ce,enc_old_reg, form_old_reg, form) -- Next State logic process (combinational)
NSL: process(digit_reg,enc_right,enc_ce,enc_btn,digpos_reg,btn_old_reg, charcnt_reg, lcd_busy, lcd_data_reg, state_reg, ret_state_reg, enc_ce,enc_old_reg, form_old_reg, form)
begin begin
-- To avoid latches the most signals are assigned with their previous value (Exceptions marked)
digit_next <= digit_reg; digit_next <= digit_reg;
digpos_next <= digpos_reg; digpos_next <= digpos_reg;
busy_old_next <= lcd_busy;
btn_old_next <= btn_old_reg; btn_old_next <= btn_old_reg;
enc_old_next <= enc_old_reg; enc_old_next <= enc_old_reg;
form_old_next <= form_old_reg; form_old_next <= form_old_reg;
charcnt_next <= charcnt_reg; charcnt_next <= charcnt_reg;
lcd_newchar_next <= '0'; lcd_newchar_next <= '0'; -- next newchar is always 0, becasue normally we dont want to send anything
lcd_newpos_next <= '0'; lcd_newpos_next <= '0'; -- same for newpos
lcd_data_next <= lcd_data_reg; lcd_data_next <= lcd_data_reg;
state_next <= state_reg; state_next <= state_reg;
ret_state_next <= ret_state_reg; ret_state_next <= ret_state_reg;
-- The next statement produces two warnings which can be safely ignored: -- The next statement produces two warnings which can be safely ignored:
-- xst:643 - The result of a <...>-bit multiplication is partially used... -- xst:643 - The result of a <...>-bit multiplication is partially used...
freq_out_next <= resize( -- Put together the frequency as a 17 bit vector (in hz) out of the single decimal places
resize(digit_reg(0), 4) freq_out_next <= resize( resize(digit_reg(0), 4)
+ resize(digit_reg(1) ,4)* 10 + resize(digit_reg(1) ,4)* 10
+ resize(digit_reg(2) ,7)* 100 + resize(digit_reg(2) ,7)* 100
+ resize(digit_reg(3) ,10) * 1000 + resize(digit_reg(3) ,10) * 1000
+ resize(digit_reg(4) ,14) * 10000 + resize(digit_reg(4) ,14) * 10000
, 17); ,freq_res);
case state_reg is -- switch on current state
case state_reg is when S_WAIT => -- lcd is currently busy
when S_WAIT => -- switch on current state if(lcd_busy = '0') then --lcd is no longer busy
if(lcd_busy = '0' and busy_old_reg ='1' ) then state_next<= ret_state_reg; -- return to state given by ret_state
state_next<= ret_state_reg;
end if; end if;
when S_FORM_PREF => when S_FORM_PREF => -- print the form prefix
state_next <= S_WAIT; state_next <= S_WAIT; -- always wait for lcd_busy=0 after this state
if(charcnt_reg < 7 ) then if(charcnt_reg < 7 ) then -- not 8 characters written yet: Send characters
charcnt_next <= charcnt_reg + 1; charcnt_next <= charcnt_reg + 1; -- increase character position
ret_state_next <= S_FORM_PREF; ret_state_next <= S_FORM_PREF; -- return into this state after wait
-- Output current character (Multiplexer). Implemented as an array lookup with cast from character to ascii value
lcd_data_next <= to_unsigned(character'pos(str_form_pref(to_integer(resize(charcnt_reg,3)))),8); lcd_data_next <= to_unsigned(character'pos(str_form_pref(to_integer(resize(charcnt_reg,3)))),8);
lcd_newchar_next <= '1'; lcd_newchar_next <= '1'; -- signal the lcd driver that a new character is ready for writing
else else -- all 8 characters written: Change adress to line 2 (as preparation for S_FREQ_PREF)
charcnt_next <= (others => '0'); charcnt_next <= (others => '0'); -- reset charcnt
lcd_data_next <= x"40"; --Start adress for line 2 lcd_data_next <= x"40"; -- Start adress for line 2
lcd_newpos_next <= '1'; lcd_newpos_next <= '1'; -- signal the lcd driver that a new position is available
ret_state_next <= S_FREQ_PREF; ret_state_next <= S_FREQ_PREF; -- continue with S_FREQ_PREF state
end if; end if;
when S_FREQ_PREF =>
if(charcnt_reg < 15 ) then when S_FREQ_PREF => -- print the frequency prefix/postfix
if(charcnt_reg < 15 ) then -- not all 16 characters written yet
charcnt_next <= charcnt_reg + 1; charcnt_next <= charcnt_reg + 1;
state_next <= S_WAIT; state_next <= S_WAIT;
ret_state_next <= S_FREQ_PREF; ret_state_next <= S_FREQ_PREF;
lcd_data_next <= to_unsigned(character'pos(str_freq_pref(to_integer(charcnt_reg))),8); lcd_data_next <= to_unsigned(character'pos(str_freq_pref(to_integer(charcnt_reg))),8);
lcd_newchar_next <= '1'; lcd_newchar_next <= '1';
else else -- all charcters written
charcnt_next <= (others => '0'); charcnt_next <= (others => '0');
state_next <= S_FORM_CONT; state_next <= S_FORM_CONT; -- print the Form content now
end if; end if;
when S_FORM_CONT => -- print the form content
when S_FORM_CONT =>
state_next <= S_WAIT; state_next <= S_WAIT;
ret_state_next <= S_FORM_CONT; ret_state_next <= S_FORM_CONT;
charcnt_next <= charcnt_reg + 1; charcnt_next <= charcnt_reg + 1;
if(charcnt_reg < 1 ) then if(charcnt_reg < 1 ) then -- Step 1: Set address
lcd_data_next <= x"06"; --adress character 7 on line 1 lcd_data_next <= x"06"; -- adress character 7 on line 1
lcd_newpos_next <= '1'; lcd_newpos_next <= '1';
elsif(charcnt_reg < 9) then elsif(charcnt_reg < 9) then -- Step 2 (8x): Print a character of the form
lcd_data_next <= to_unsigned(character'pos(str_form(to_integer(form),to_integer(resize(charcnt_reg-1,3)))),8); lcd_data_next <= to_unsigned(character'pos(str_form(to_integer(form),to_integer(resize(charcnt_reg-1,3)))),8);
lcd_newchar_next <= '1'; lcd_newchar_next <= '1';
else else -- Step 3: Set adress/cursor back to current digit
charcnt_next <= (others => '0'); charcnt_next <= (others => '0');
lcd_data_next <= x"4A" - digpos_reg; -- adress character 11 on line 2 - digit position lcd_data_next <= x"4A" - digpos_reg; -- adress character 11 on line 2 - digit position
lcd_newpos_next <= '1'; lcd_newpos_next <= '1';
ret_state_next <= S_IDLE; ret_state_next <= S_IDLE;
end if; end if;
when S_FREQ_CONT =>
when S_FREQ_CONT => -- print the frequency content
state_next <= S_WAIT; state_next <= S_WAIT;
if(charcnt_reg < 1 ) then if(charcnt_reg < 1 ) then -- Step 1: Set address for current digit
charcnt_next <= charcnt_reg + 1; charcnt_next <= charcnt_reg + 1;
ret_state_next <= S_FREQ_CONT; ret_state_next <= S_FREQ_CONT;
lcd_data_next <= x"4A" - digpos_reg; -- adress character 11 on line 2 - digit position lcd_data_next <= x"4A" - digpos_reg; -- adress character 11 on line 2 - digit position
lcd_newpos_next <= '1'; lcd_newpos_next <= '1';
elsif(charcnt_reg = 1) then elsif(charcnt_reg = 1) then -- Step 2: Print current digit
charcnt_next <= charcnt_reg + 1; charcnt_next <= charcnt_reg + 1;
ret_state_next <= S_FREQ_CONT; ret_state_next <= S_FREQ_CONT;
lcd_data_next <= to_unsigned(character'pos('0'),8) + digit_reg(to_integer(digpos_reg)); lcd_data_next <= to_unsigned(character'pos('0'),8) + digit_reg(to_integer(digpos_reg));
lcd_newchar_next <= '1'; lcd_newchar_next <= '1';
else else -- Step 3: Reset adress/cursor back to current digit (auto increment of display cannot be disabled)
ret_state_next <= S_IDLE; ret_state_next <= S_IDLE;
charcnt_next <= (others => '0'); charcnt_next <= (others => '0');
lcd_data_next <= x"4A" - digpos_reg; -- adress character 11 on line 2 - digit position lcd_data_next <= x"4A" - digpos_reg; -- adress character 11 on line 2 - digit position
lcd_newpos_next <= '1'; lcd_newpos_next <= '1';
end if; end if;
when S_IDLE =>
when S_IDLE => -- Controller is idle and wait on user input
-- Update edge dectection helper registers:
btn_old_next <= enc_btn; btn_old_next <= enc_btn;
enc_old_next <= enc_ce; enc_old_next <= enc_ce;
form_old_next <= form; form_old_next <= form;
if(form /= form_old_reg) then if(form /= form_old_reg) then -- form changed
state_next <= S_FORM_CONT; state_next <= S_FORM_CONT; -- print form
elsif(enc_ce='1' and enc_old_reg ='0') then elsif(enc_ce='1' and enc_old_reg ='0') then -- positive egde on encoder clock enable
if(enc_right='1') then if(enc_right='1') then -- encoder was turned right
if(digit_reg(to_integer(digpos_reg)) = to_unsigned(9,4)) then if(digit_reg(to_integer(digpos_reg)) = to_unsigned(9,4)) then -- digit value = 9
digit_next(to_integer(digpos_reg)) <= to_unsigned(0,4); digit_next(to_integer(digpos_reg)) <= to_unsigned(0,4); -- set digit value to 0
else else -- digit value < 9
digit_next(to_integer(digpos_reg)) <= digit_reg(to_integer(digpos_reg)) + 1; digit_next(to_integer(digpos_reg)) <= digit_reg(to_integer(digpos_reg)) + 1; -- increase digit value
end if; end if;
else else -- encoder was turned left
if(digit_reg(to_integer(digpos_reg)) = to_unsigned(0,4)) then if(digit_reg(to_integer(digpos_reg)) = to_unsigned(0,4)) then -- digit value = 0
digit_next(to_integer(digpos_reg)) <= to_unsigned(9,4); digit_next(to_integer(digpos_reg)) <= to_unsigned(9,4); -- set digit value to 9
else else -- digit value > 0
digit_next(to_integer(digpos_reg)) <= digit_reg(to_integer(digpos_reg)) -1; digit_next(to_integer(digpos_reg)) <= digit_reg(to_integer(digpos_reg)) -1; -- decrease digit value
end if; end if;
end if; end if;
state_next <= S_FREQ_CONT; state_next <= S_FREQ_CONT; -- print frequency
elsif(enc_btn ='1' and btn_old_reg='0') then elsif(enc_btn ='1' and btn_old_reg='0') then -- positive edge on push button
if(digpos_reg = to_unsigned(4,3)) then if(digpos_reg = to_unsigned(4,3)) then -- digit_pos = 4
digpos_next <= to_unsigned(0,3); digpos_next <= to_unsigned(0,3); -- set digit pos = 0
else else -- digit pos < 4
digpos_next <= digpos_reg + 1; digpos_next <= digpos_reg + 1; -- increase digit pos
end if; end if;
state_next <= S_FREQ_CONT; state_next <= S_FREQ_CONT; -- print frequency (also updates the cursor position)
end if; end if;
when others => null; -- do nothing, if we are in a different state when others => null; -- do nothing, if we are in a different state
end case; end case;

56
dds.vhd
View File

@@ -15,7 +15,7 @@ use work.helpers.all;
entity dds is entity dds is
Generic (clk_freq: natural:= 50000000; -- Clock frequency in hz Generic (clk_freq: natural:= 50000000; -- Clock frequency in hz
freq_res: natural:=17; -- width of frequency input (log2(max_freq)) freq_res: natural:=17; -- width of frequency input (log2(max_freq))
adc_res: natural:=12; -- width of the ouput signal (=adc resolution) adc_res: natural:=12; -- width of the output signal (=adc resolution)
acc_res: natural:=32; -- width of the phase accumulator acc_res: natural:=32; -- width of the phase accumulator
phase_res: natural:=10); -- effective phase resolution for sin lookup table phase_res: natural:=10); -- effective phase resolution for sin lookup table
Port ( clk : in STD_LOGIC; -- Clock input Port ( clk : in STD_LOGIC; -- Clock input
@@ -25,66 +25,72 @@ entity dds is
end dds; end dds;
architecture Behavioral of dds is architecture Behavioral of dds is
signal m, idx : unsigned(acc_res -1 downto 0):= (others => '0'); signal m, idx : unsigned(acc_res -1 downto 0):= (others => '0'); -- phase jump size and accumulator (see Fundamentals of Direct Digital Synthesis for details about their function)
signal idx_phase : unsigned(phase_res-1 downto 0) := (others => '0'); signal idx_phase : unsigned(phase_res-1 downto 0) := (others => '0'); -- relevant (=leftmost) bits of the phase acccumulator
signal amp_rect, amp_saw, amp_tria, amp_sin : unsigned (adc_res-1 downto 0); signal amp_rect, amp_saw, amp_tria, amp_sin : unsigned (adc_res-1 downto 0); -- the current amplitudes of all 4 signal forms
-- Function to genenerate and store the sine wave in the rom.
-- Current code: Only store 1/4 of a sine wave and use symmetries.
-- Uncommented code: Store the entire sine wave (decrease adc_width to 8)
type storage is array (((2**phase_res)/4)-1 downto 0) of unsigned (adc_res-2 downto 0); type storage is array (((2**phase_res)/4)-1 downto 0) of unsigned (adc_res-2 downto 0);
--type storage is array (((2**phase_res))-1 downto 0) of unsigned (adc_res-1 downto 0); --type storage is array (((2**phase_res))-1 downto 0) of unsigned (adc_res-1 downto 0);
function gen_sin_wave return storage is function gen_sin_wave return storage is
variable temp : storage; variable temp : storage;
begin begin
forLoop: for i in 0 to temp'high loop forLoop: for i in 0 to temp'high loop -- for each element in the array
temp(i) := to_unsigned(integer(real((2**(adc_res-1))-1)*sin((real(i)*MATH_PI/2.0)/real(temp'high))),adc_res-1); temp(i) := to_unsigned(integer(real((2**(adc_res-1))-1)*sin((real(i)*MATH_PI/2.0)/real(temp'high))),adc_res-1);
--temp(i) := to_unsigned(integer(real(2**(adc_res-1) -1) + real((2**(adc_res-1))-1)*sin((real(i)*MATH_PI*2.0)/real(temp'high))),adc_res); --temp(i) := to_unsigned(integer(real(2**(adc_res-1) -1) + real((2**(adc_res-1))-1)*sin((real(i)*MATH_PI*2.0)/real(temp'high))),adc_res);
end loop; end loop;
return temp; return temp;
end function gen_sin_wave; end function gen_sin_wave;
constant sin_wave : storage := gen_sin_wave; constant sin_wave : storage := gen_sin_wave; -- rom for sin wave
begin begin
-- Calculate jump size according to input frequency
-- m = fout*(2^n)/fclk = fout*((2^n)*(2^k)/fclk)/(2^k) with k=ceil(log2(fclk)), n=acc_res -- m = fout*(2^n)/fclk = fout*((2^n)*(2^k)/fclk)/(2^k) with k=ceil(log2(fclk)), n=acc_res
m <= resize( (resize(freq,64) m <= resize( (resize(freq,64)
* *
(shift_left(to_unsigned(1,64),acc_res + log2_int(clk_freq)) / clk_freq)) (shift_left(to_unsigned(1,64),acc_res + log2_int(clk_freq)) / clk_freq))
/to_unsigned(2**log2_int(clk_freq),64),acc_res); /to_unsigned(2**log2_int(clk_freq),64),acc_res);
-- Amplitude of the square wave
amp_rect <= to_unsigned(0,adc_res) when idx(acc_res-1)='0' else -- 0 for half of the time
to_unsigned((2**adc_res)-1,adc_res); --1 for the rest
-- Amplitude of the sawtooth wave
amp_saw <= idx(acc_res -1 downto acc_res - adc_res); -- Exactly the value of the uppermost bits of the phase acc
-- Amplitude of the triangle wave
amp_tria <= idx(acc_res -2 downto acc_res - adc_res - 1) -- The value of the uppermost bits, except the uppermost one (= double the frequency)
when idx(acc_res-1)='0' else -- during half of the time
((2**adc_res)-1)- (idx(acc_res -2 downto acc_res - adc_res - 1)); -- and the complement, the rest of the time
amp_rect <= to_unsigned(0,adc_res) when idx(acc_res-1)='0' else
to_unsigned((2**adc_res)-1,adc_res);
amp_saw <= idx(acc_res -1 downto acc_res - adc_res);
amp_tria <= idx(acc_res -2 downto acc_res - adc_res) & "0" idx_phase <= idx(acc_res -1 downto acc_res - phase_res); -- take only the uppermost bits for the sine lookup
when idx(acc_res-1)='0' else
((2**adc_res)-1)- (idx(acc_res -2 downto acc_res - adc_res) & "0");
-- Amplitude of the sine wave
idx_phase <= idx(acc_res -1 downto acc_res - phase_res); -- Code if we had stored the whole sinewave:
-- amp_sin <= sin_wave(to_integer(idx_phase));
--amp_sin <= sin_wave(to_integer(idx_phase)); -- Current Code (only 1/4 of the sine wave stored)
amp_sin <= to_unsigned((2**(adc_res-1)) - 1,adc_res) + sin_wave(to_integer(idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="00" else amp_sin <= to_unsigned((2**(adc_res-1)) - 1,adc_res) + sin_wave(to_integer(idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="00" else
to_unsigned((2**(adc_res-1)) - 1,adc_res) + sin_wave(to_integer(((2**(phase_res-2))-1) - idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="01" else to_unsigned((2**(adc_res-1)) - 1,adc_res) + sin_wave(to_integer(((2**(phase_res-2))-1) - idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="01" else
to_unsigned((2**(adc_res-1)) - 1,adc_res) - sin_wave(to_integer(idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="10" else to_unsigned((2**(adc_res-1)) - 1,adc_res) - sin_wave(to_integer(idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="10" else
to_unsigned((2**(adc_res-1)) - 1,adc_res) - sin_wave(to_integer(((2**(phase_res-2))-1) - idx_phase(phase_res-3 downto 0))); to_unsigned((2**(adc_res-1)) - 1,adc_res) - sin_wave(to_integer(((2**(phase_res-2))-1) - idx_phase(phase_res-3 downto 0)));
-- Output the selected amplitue using a multiplexer (00=Rectancle, 01=Sawtooth, 10=Triangle, 11=Sine)
amp <= to_unsigned(0,adc_res) when freq = to_unsigned(0,freq_res) else amp <= to_unsigned(0,adc_res) when freq = to_unsigned(0,freq_res) else
amp_rect when form = "00" else amp_rect when form = "00" else
amp_saw when form ="01" else amp_saw when form ="01" else
amp_tria when form = "10" else amp_tria when form = "10" else
amp_sin; amp_sin;
-- Process for the phase accumulator (sequential)
P1: process(clk) P1: process(clk)
begin begin
if(rising_edge(clk)) then if(rising_edge(clk)) then
idx <= (idx+m); idx <= (idx+m); -- increment phase accumulator according to jump size. overflow is wanted.
end if; end if;
end process P1; end process P1;
end Behavioral; end Behavioral;

46
rotary.vhd
View File

@@ -11,10 +11,12 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; use IEEE.NUMERIC_STD.ALL;
entity rotary_dec is entity rotary_dec is
Generic (clk_freq: natural:= 50000000; -- Clock frequency in hz
debounce_time: natural := 10); -- Debounce time in ms
Port ( clk : in std_logic; -- Clock Input Port ( clk : in std_logic; -- Clock Input
A : in std_logic; -- Signal A A : in std_logic; -- Signal A
B : in std_logic; -- Signal B B : in std_logic; -- Signal B
btn : in std_logic; -- Button Input btn : in std_logic; -- Button Input
btn_deb : out std_logic; -- Button Output Debonced btn_deb : out std_logic; -- Button Output Debonced
enc_right: out std_logic; -- Direction Output: 1=right enc_right: out std_logic; -- Direction Output: 1=right
enc_ce : out std_logic); -- Clock Enable Output for signal above enc_ce : out std_logic); -- Clock Enable Output for signal above
@@ -23,44 +25,48 @@ end rotary_dec;
architecture Behavioral of rotary_dec is architecture Behavioral of rotary_dec is
signal a_old, b_old: std_logic := '0'; signal a_old, b_old: std_logic := '0'; -- Registers for edge detection on debounced A, B signals
signal a_debounced_reg, a_debounced_next, b_debounced_reg, b_debounced_next : std_logic := '0'; signal a_debounced_reg, a_debounced_next, -- Registers for debouncing A, B signals
signal btn_reg, btn_next: std_logic :='0'; b_debounced_reg, b_debounced_next : std_logic := '0';
signal counter_a_reg, counter_a_next, signal btn_reg, btn_next: std_logic :='0'; -- Registers for debouncing Button Press signal
signal counter_a_reg, counter_a_next, -- Counters to smooth chittering = debounce signals
counter_b_reg, counter_b_next, counter_b_reg, counter_b_next,
counter_btn_reg, counter_btn_next: unsigned(23 downto 0) := (others => '0'); counter_btn_reg, counter_btn_next: unsigned(23 downto 0) := (others => '0');
constant count_max: unsigned(23 downto 0) := to_unsigned(500000,24); --10ms constant count_max: unsigned(23 downto 0) := to_unsigned(clk_freq / (1000 / debounce_time),24); --Number of cycles during which a signal can't change it's value 50mhz*10ms= 500000 cycles
begin begin
-- State register process (sequential)
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
counter_a_reg <= counter_a_next; counter_a_reg <= counter_a_next;
counter_b_reg <= counter_b_next; counter_b_reg <= counter_b_next;
counter_btn_reg <= counter_btn_next; counter_btn_reg <= counter_btn_next;
a_debounced_reg <= a_debounced_next; a_debounced_reg <= a_debounced_next;
b_debounced_reg <= b_debounced_next; b_debounced_reg <= b_debounced_next;
btn_reg <= btn_next;
a_old <= a_debounced_reg; a_old <= a_debounced_reg;
b_old <= b_debounced_reg; b_old <= b_debounced_reg;
btn_reg <= btn_next;
end if; end if;
end process; end process;
-- Debounce process (combinational)
btn_deb <= btn_reg;
process(A,B, a_debounced_reg, b_debounced_reg, counter_a_reg, counter_b_reg, btn_reg, btn, counter_btn_reg) process(A,B, a_debounced_reg, b_debounced_reg, counter_a_reg, counter_b_reg, btn_reg, btn, counter_btn_reg)
begin begin
-- If signal a has changed (edge detection) and enough time passed since the last change
if(A /= a_debounced_reg and counter_a_reg > count_max) then if(A /= a_debounced_reg and counter_a_reg > count_max) then
a_debounced_next <= A; a_debounced_next <= A; -- accept change
counter_a_next <= (others => '0'); counter_a_next <= (others => '0'); -- reset counter
else else -- singal has not changed, or not enough time has passed
a_debounced_next <= a_debounced_reg; a_debounced_next <= a_debounced_reg; -- keep old signal value
counter_a_next <= counter_a_reg + 1; counter_a_next <= counter_a_reg + 1; -- increase counter by one
end if; end if;
-- Same as above for signal B
if(B /= b_debounced_reg and counter_b_reg > count_max) then if(B /= b_debounced_reg and counter_b_reg > count_max) then
b_debounced_next <= B; b_debounced_next <= B;
counter_b_next <= (others => '0'); counter_b_next <= (others => '0');
@@ -69,6 +75,7 @@ begin
counter_b_next <= counter_b_reg + 1; counter_b_next <= counter_b_reg + 1;
end if; end if;
-- Same as above for button press signal
if(btn /= btn_reg and counter_btn_reg > count_max) then if(btn /= btn_reg and counter_btn_reg > count_max) then
btn_next <= btn; btn_next <= btn;
counter_btn_next <= (others => '0'); counter_btn_next <= (others => '0');
@@ -79,17 +86,20 @@ begin
end process; end process;
btn_deb <= btn_reg; --Output debounced btn reg
-- Dekodierung der Ausgaenge -- Ouput decode for Rotary Signals (A,B)
process(a_debounced_reg, b_debounced_reg, a_old, b_old) process(a_debounced_reg, b_debounced_reg, a_old, b_old)
variable state: std_logic_vector(3 downto 0); variable state: std_logic_vector(3 downto 0);
begin begin
state := a_debounced_reg & b_debounced_reg & a_old & b_old; state := a_debounced_reg & b_debounced_reg & a_old & b_old; -- Concat to vector
case state is case state is
when "0001" => enc_right <= '0'; enc_ce <= '1'; when "0001" => enc_right <= '0'; enc_ce <= '1';
when "0010" => enc_right <= '1'; enc_ce <= '1'; when "0010" => enc_right <= '1'; enc_ce <= '1';
when others => enc_right <= '0'; enc_ce <= '0'; when others => enc_right <= '0'; enc_ce <= '0';
-- If you want a finer resolution you can simply add more cases here.
-- In our case we only have 1 case for left, and one for right, which works fine.
end case; end case;
end process; end process;

77
rotary_tb.vhd Normal file
View File

@@ -0,0 +1,77 @@
----------------------------------------------------------------------------------
-- Project: YASG (Yet another signal generator)
-- Project Page: https://github.com/id101010/vhdl-yasg/
-- Authors: Aaron Schmocker & Timo Lang
-- License: GPL v3
-- Create Date: 13:41:21 06/19/2016
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY rotary_tb IS
END rotary_tb;
ARCHITECTURE behavior OF rotary_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT rotary_dec
PORT(
clk : IN std_logic;
A : IN std_logic;
B : IN std_logic;
btn : IN std_logic;
btn_deb : OUT std_logic;
enc_right : OUT std_logic;
enc_ce : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal A : std_logic := '0';
signal B : std_logic := '0';
signal btn : std_logic := '0';
--Outputs
signal btn_deb : std_logic;
signal enc_right : std_logic;
signal enc_ce : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: rotary_dec PORT MAP (
clk => clk,
A => A,
B => B,
btn => btn,
btn_deb => btn_deb,
enc_right => enc_right,
enc_ce => enc_ce
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait;
end process;
END;

34
spi_driver.vhd
View File

@@ -22,11 +22,12 @@ entity spi_driver is
end spi_driver; end spi_driver;
architecture Behavioral of spi_driver is architecture Behavioral of spi_driver is
type states is(S_IDLE, S_WORK); type states is(S_IDLE, S_WORK); -- FSM: Idle and Work State
signal state_reg, state_next: states := S_IDLE; signal state_reg, state_next: states := S_IDLE; -- Current and next state register
signal counter_reg, counter_next: unsigned(5 downto 0) := (others => '0'); signal counter_reg, counter_next: unsigned(5 downto 0) := (others => '0'); -- Counter for the bit nr
signal shift_reg, shift_next: unsigned(19 downto 0):= (others => '0'); signal shift_reg, shift_next: unsigned(19 downto 0):= (others => '0'); -- Shift reg for the ouput
begin begin
-- State register process (combinational)
REGS: process (clk, rst) is REGS: process (clk, rst) is
begin -- process start begin -- process start
if rst = '1' then -- asynchronous reset (active high) if rst = '1' then -- asynchronous reset (active high)
@@ -40,32 +41,35 @@ begin
end if; end if;
end process REGS; end process REGS;
mosi <= shift_reg(shift_reg'high) when state_reg=S_WORK else '0'; mosi <= shift_reg(shift_reg'high) when state_reg=S_WORK else '0'; -- Mosi: Highest value of shift reg when in Work state, otherwise 0
sck <= '1' when state_reg=S_WORK and counter_reg(0)='1' else '0'; sck <= '1' when state_reg=S_WORK and counter_reg(0)='1' else '0'; -- Sck: High when in work state and lowest bit 1 (shift will be performed when lowest bit = 0)
cs <= '1' when state_reg =S_IDLE else '0'; cs <= '0' when state_reg =S_WORK else '1'; -- Cs (low active): Low when in state work
-- Next State logic process (combinational)
NSL: process (state_reg, counter_reg, shift_reg, val) is NSL: process (state_reg, counter_reg, shift_reg, val) is
begin begin
state_next <= state_reg; state_next <= state_reg;
counter_next <= counter_reg; counter_next <= counter_reg;
shift_next <= shift_reg; shift_next <= shift_reg;
case state_reg is -- switch on current state case state_reg is -- switch on current state
when S_IDLE => -- currently in idle state when S_IDLE => -- currently in idle state
state_next <= S_WORK; state_next <= S_WORK;
counter_next <= to_unsigned(0,counter_reg'length); counter_next <= to_unsigned(0,counter_reg'length);
shift_next(19 downto 16) <= "0011"; --Command: Write to and Update (Power Up) -- Initialize shift reg
shift_next(15 downto 12) <= "0000"; --Adress: DAC0 shift_next(19 downto 16) <= "0011"; -- Command: Write to and Update (Power Up)
shift_next(11 downto 0) <= val; -- DAC Value (12bit) shift_next(15 downto 12) <= "0000"; -- Adress: DAC0
shift_next(11 downto 0) <= val; -- DAC Value (12bit)
--shift_next(0 downto -3) <= "XXXX"; -- 4x don't care --shift_next(0 downto -3) <= "XXXX"; -- 4x don't care
when S_WORK => -- currently in work state when S_WORK => -- currently in work state
if(counter_reg = 24*2 -1) then if(counter_reg = 24*2 -1) then -- all bits sent
state_next <= S_IDLE; state_next <= S_IDLE; -- return to idle state
else else -- not all bits sent
counter_next<= counter_reg + 1; counter_next<= counter_reg + 1; -- increase bit counter
end if; end if;
if(counter_reg(0)='1') then if(counter_reg(0)='1') then -- peform shift when lowest bit = 1, shift will be performed when bit = 0
shift_next <= shift_left(shift_reg,1); shift_next <= shift_left(shift_reg,1);
end if; end if;
when others => null; -- do nothing, if we are in a different state when others => null; -- do nothing, if we are in a different state

18
yasg.xise
View File

@@ -16,7 +16,7 @@
<files> <files>
<file xil_pn:name="lcd_driver.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="lcd_driver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file> </file>
<file xil_pn:name="dds.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="dds.vhd" xil_pn:type="FILE_VHDL">
@@ -51,7 +51,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="rotary.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="rotary.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file> </file>
<file xil_pn:name="controller.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="controller.vhd" xil_pn:type="FILE_VHDL">
@@ -59,7 +59,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="6"/> <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file> </file>
<file xil_pn:name="lcd_driver_tb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="lcd_driver_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="132"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="132"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="132"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="132"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="132"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="132"/>
@@ -70,6 +70,12 @@
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="143"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="143"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="143"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="143"/>
</file> </file>
<file xil_pn:name="rotary_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="68"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="68"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="68"/>
</file>
</files> </files>
<properties> <properties>
@@ -84,8 +90,8 @@
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/> <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/> <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/> <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/lcd_driver_tb" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/rotary_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.lcd_driver_tb" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.rotary_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/> <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
@@ -95,7 +101,7 @@
<!-- --> <!-- -->
<!-- The following properties are for internal use only. These should not be modified.--> <!-- The following properties are for internal use only. These should not be modified.-->
<!-- --> <!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|lcd_driver_tb|behavior" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|rotary_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="yasg" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="yasg" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-05-09T19:06:02" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-05-09T19:06:02" xil_pn:valueState="non-default"/>