diff --git a/dds.vhd b/dds.vhd
index 77f1645..cba5adf 100644
--- a/dds.vhd
+++ b/dds.vhd
@@ -31,33 +31,47 @@ entity dds is
     Generic (clk_freq: natural:= 50000000;
              max_freq: natural := 100000;
              adc_res: natural:=12;
-             vector_res: natural :=8 );
+             acc_res: natural:=32;
+             phase_res: natural:=15);
     Port ( clk : in  STD_LOGIC;
            freq : in  unsigned (log2_int(max_freq)-1 downto 0);
            form : in  unsigned (1 downto 0);
-           amp : out  unsigned (adc_res-1 downto 0);
+           amp : out  signed (adc_res-1 downto 0);
            update : out  STD_LOGIC);
 end dds;
 
-architecture Behavioral of dds is
-    constant clk2 : natural := clk_freq/(2**vector_res);
-    constant clk2_us :unsigned (log2_int(clk2)-1 downto 0) :=to_unsigned(clk2,log2_int(clk2));
-    signal prescale,cnt_prescale :unsigned (log2_int(clk2)-1 downto 0) := (others => '0');   
-    signal m, idx : unsigned(vector_res -1  downto 0):= (others => '0');   
-    
+architecture Behavioral of dds is   
+    signal m, idx : unsigned(acc_res -1  downto 0):= (others => '0');   
+    signal idx_phase : unsigned(phase_res-1 downto 0) := (others => '0');  
+    signal amp_rect, amp_saw, amp_tria, amp_sin : signed (adc_res-1 downto 0);
+   
 begin
-    prescale <= divide(to_unsigned(clk2,prescale'length),freq);
-    m <= resize(divide(freq*prescale,to_unsigned(clk2,prescale'length)),m'length);
+    -- m = f0*2^n/fc
+    m <= resize(divide(shift_left(resize(freq,64),acc_res),to_unsigned(clk_freq,64)),m'length);
+    idx_phase <= idx(acc_res -1 downto acc_res - phase_res);
+       
+    amp_rect <= to_signed((2**(adc_res-1)) - 1,adc_res) when idx_phase(phase_res-1)='0' else 
+                to_signed(-(2**(adc_res-1)),adc_res);
     
+    amp_saw <=  to_signed(-(2**(adc_res-1)),adc_res)
+                + signed(resize(unsigned(((2**adc_res) -1)*idx_phase/2**phase_res),adc_res)) ;
+    
+    amp_tria <= to_signed(-(2**(adc_res-1)),adc_res)
+                + signed(resize(unsigned(((2**adc_res) -1)*idx_phase/2**(phase_res-1)),adc_res)) 
+                when idx_phase(phase_res-1)='0' else 
+                resize(to_signed((2**(adc_res))-1,adc_res+1)
+                - signed(resize(unsigned(((2**adc_res) -1)*idx_phase/2**(phase_res-1)),adc_res)),adc_res);
+    
+    
+    
+    amp <= amp_tria;
+        
+        
+        
     P1: process(clk) 
     begin
         if(rising_edge(clk)) then
-            if(cnt_prescale >= prescale) then
-                cnt_prescale <= to_unsigned(1, prescale'length);
-                idx <= (idx+m) mod (2**vector_res);
-            else
-                cnt_prescale <= cnt_prescale +1;
-            end if;
+            idx <= (idx+m);
         end if;
     end process P1;
 
diff --git a/dds_tb.vhd b/dds_tb.vhd
index c954bbf..31fed4e 100644
--- a/dds_tb.vhd
+++ b/dds_tb.vhd
@@ -41,7 +41,7 @@ ARCHITECTURE behavior OF dds_tb IS
          clk : IN  std_logic;
          freq : IN  unsigned(16 downto 0);
          form : IN  unsigned(1 downto 0);
-         amp : OUT  unsigned(11 downto 0);
+         amp : OUT  signed(11 downto 0);
          update : OUT  std_logic
         );
     END COMPONENT;
@@ -53,11 +53,11 @@ ARCHITECTURE behavior OF dds_tb IS
    signal form : unsigned(1 downto 0) := (others => '0');
 
  	--Outputs
-   signal amp : unsigned(11 downto 0);
+   signal amp : signed(11 downto 0);
    signal update : std_logic;
 
    -- Clock period definitions
-   constant clk_period : time := 10 ns;
+   constant clk_period : time := 20 ns; --50mhz
  
 BEGIN
  
@@ -86,21 +86,27 @@ BEGIN
       -- hold reset state for 100 ns.
       wait for 100 ns;	
 
-      wait for clk_period*10;
-      freq <= to_unsigned(1,17);
-        wait for clk_period*10;
-      freq <= to_unsigned(10,17);
-        wait for clk_period*10;
-      freq <= to_unsigned(100,17);
-        wait for clk_period*10;
-      freq <= to_unsigned(1000,17);
-      wait for clk_period*10;
-      freq <= to_unsigned(10000,17);
-      wait for clk_period*10;
-      freq <= to_unsigned(50000,17);
-      wait for clk_period*10;
+   
       freq <= to_unsigned(100000,17);
-
+      wait for 2000 ms;
+      
+      freq <= to_unsigned(10,17);
+       wait for 200 ms;
+       
+      freq <= to_unsigned(100,17);
+       wait for 20 ms;
+        
+      freq <= to_unsigned(1000,17);
+      wait for 2 ms;
+      
+      freq <= to_unsigned(10000,17);
+      wait for 1 ms;
+      
+      freq <= to_unsigned(50000,17);
+      wait for 1 ms;
+      
+      freq <= to_unsigned(100000,17);
+      wait for 1 ms;
       -- insert stimulus here 
 
       wait;
diff --git a/yasg.gise b/yasg.gise
index 9b04e0d..6799a8a 100644
--- a/yasg.gise
+++ b/yasg.gise
@@ -41,6 +41,7 @@
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="dds_tb_isim_beh.exe"/>
     <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="dds_tb_isim_beh.wdb"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="dds_tb_stx_beh.prj"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="dds_vhdl.prj"/>
     <file xil_pn:fileType="FILE_XRPT" xil_pn:name="dds_xst.xrpt"/>
     <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
@@ -59,9 +60,8 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1463396197" xil_pn:in_ck="-1527320413769792740" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1463396197">
+    <transform xil_pn:end_ts="1463423268" xil_pn:in_ck="-1527320413769792740" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1463423268">
       <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="dds.vhd"/>
       <outfile xil_pn:name="dds_tb.vhd"/>
@@ -80,7 +80,7 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1463396205" xil_pn:in_ck="-1527320413769792740" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1463396205">
+    <transform xil_pn:end_ts="1463423268" xil_pn:in_ck="-1527320413769792740" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1463423268">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="dds.vhd"/>
@@ -88,11 +88,9 @@
       <outfile xil_pn:name="helpers.vhd"/>
       <outfile xil_pn:name="lcd_driver.vhd"/>
     </transform>
-    <transform xil_pn:end_ts="1463396206" xil_pn:in_ck="-1527320413769792740" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-6917596232395121981" xil_pn:start_ts="1463396205">
+    <transform xil_pn:end_ts="1463423273" xil_pn:in_ck="-1527320413769792740" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-6917596232395121981" xil_pn:start_ts="1463423268">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForOutputs"/>
-      <status xil_pn:value="OutputChanged"/>
       <outfile xil_pn:name="dds_tb_beh.prj"/>
       <outfile xil_pn:name="dds_tb_isim_beh.exe"/>
       <outfile xil_pn:name="fuse.log"/>
@@ -100,7 +98,7 @@
       <outfile xil_pn:name="isim.log"/>
       <outfile xil_pn:name="xilinxsim.ini"/>
     </transform>
-    <transform xil_pn:end_ts="1463405352" xil_pn:in_ck="5986968781955972703" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7301171803071747408" xil_pn:start_ts="1463405351">
+    <transform xil_pn:end_ts="1463423273" xil_pn:in_ck="5986968781955972703" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7301171803071747408" xil_pn:start_ts="1463423273">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="dds_tb_isim_beh.wdb"/>
@@ -135,7 +133,7 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1463396180" xil_pn:in_ck="-8475077075915550756" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-7698400163542717516" xil_pn:start_ts="1463396172">
+    <transform xil_pn:end_ts="1463423247" xil_pn:in_ck="-8475077075915550756" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-7698400163542717516" xil_pn:start_ts="1463423207">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>