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Integrating new_pos wiring.

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This commit is contained in:
T-moe
2016-06-06 21:56:04 +02:00
parent 8b5315017e
commit 1b89ea9c71
6 changed files with 86 additions and 60 deletions
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31
controller.sym
View File

@@ -1,17 +1,18 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="controller"> <symbol version="7" name="controller">
<symboltype>BLOCK</symboltype> <symboltype>BLOCK</symboltype>
<timestamp>2016-6-3T16:4:48</timestamp> <timestamp>2016-6-6T19:48:13</timestamp>
<pin polarity="Input" x="0" y="-416" name="clk" /> <pin polarity="Input" x="0" y="-416" name="clk" />
<pin polarity="Input" x="0" y="-352" name="rst" /> <pin polarity="Input" x="0" y="-352" name="rst" />
<pin polarity="Input" x="0" y="-96" name="enc_err" /> <pin polarity="Input" x="0" y="-96" name="enc_err" />
<pin polarity="Input" x="0" y="-32" name="lcd_busy" /> <pin polarity="Input" x="0" y="-32" name="lcd_busy" />
<pin polarity="Output" x="432" y="-416" name="lcd_newchar" /> <pin polarity="Output" x="432" y="-416" name="lcd_newchar" />
<pin polarity="Output" x="432" y="-32" name="freq_out(16:0)" />
<pin polarity="Input" x="0" y="-224" name="enc_updown" />
<pin polarity="Input" x="0" y="-160" name="enc_ce" />
<pin polarity="Input" x="0" y="-288" name="enc_btn" /> <pin polarity="Input" x="0" y="-288" name="enc_btn" />
<pin polarity="Output" x="432" y="-352" name="lcd_data(7:0)" /> <pin polarity="Output" x="432" y="-352" name="lcd_newpos" />
<pin polarity="Output" x="432" y="-288" name="lcd_data(7:0)" />
<pin polarity="Output" x="432" y="-224" name="freq_out(16:0)" />
<pin polarity="Input" x="0" y="-160" name="enc_ce" />
<pin polarity="Input" x="0" y="-224" name="enc_updown" />
<graph> <graph>
<rect width="304" x="64" y="-448" height="448" /> <rect width="304" x="64" y="-448" height="448" />
<attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="216" y="-456" type="symbol" /> <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="216" y="-456" type="symbol" />
@@ -25,17 +26,19 @@
<line x2="0" y1="-32" y2="-32" x1="64" /> <line x2="0" y1="-32" y2="-32" x1="64" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-416" type="pin lcd_newchar" /> <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-416" type="pin lcd_newchar" />
<line x2="432" y1="-416" y2="-416" x1="368" /> <line x2="432" y1="-416" y2="-416" x1="368" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-32" type="pin freq_out(16:0)" />
<rect width="64" x="368" y="-44" height="24" />
<line x2="432" y1="-32" y2="-32" x1="368" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin enc_updown" />
<line x2="0" y1="-224" y2="-224" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin enc_ce" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-288" type="pin enc_btn" /> <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-288" type="pin enc_btn" />
<line x2="0" y1="-288" y2="-288" x1="64" /> <line x2="0" y1="-288" y2="-288" x1="64" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-352" type="pin lcd_data(7:0)" /> <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-352" type="pin lcd_newpos" />
<rect width="64" x="368" y="-364" height="24" />
<line x2="432" y1="-352" y2="-352" x1="368" /> <line x2="432" y1="-352" y2="-352" x1="368" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-288" type="pin lcd_data(7:0)" />
<rect width="64" x="368" y="-300" height="24" />
<line x2="432" y1="-288" y2="-288" x1="368" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-224" type="pin freq_out(16:0)" />
<rect width="64" x="368" y="-236" height="24" />
<line x2="432" y1="-224" y2="-224" x1="368" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin enc_ce" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin enc_updown" />
<line x2="0" y1="-224" y2="-224" x1="64" />
</graph> </graph>
</symbol> </symbol>

8
controller.vhd
View File

@@ -39,6 +39,7 @@ entity controller is
lcd_busy: in STD_LOGIC; lcd_busy: in STD_LOGIC;
lcd_data: out unsigned(7 downto 0); lcd_data: out unsigned(7 downto 0);
lcd_newchar: out STD_LOGIC; lcd_newchar: out STD_LOGIC;
lcd_newpos : out STD_LOGIC;
freq_out : out unsigned (16 downto 0)); freq_out : out unsigned (16 downto 0));
end controller; end controller;
@@ -54,6 +55,7 @@ architecture Behavioral of controller is
signal charcnt_reg, charcnt_next : unsigned(3 downto 0) := (others => '0'); signal charcnt_reg, charcnt_next : unsigned(3 downto 0) := (others => '0');
signal lcd_newchar_reg,lcd_newchar_next : std_logic := '0'; signal lcd_newchar_reg,lcd_newchar_next : std_logic := '0';
signal lcd_newpos_reg,lcd_newpos_next : std_logic := '0';
signal lcd_data_reg, lcd_data_next: unsigned(7 downto 0) :=(others => '0'); signal lcd_data_reg, lcd_data_next: unsigned(7 downto 0) :=(others => '0');
type character_array is array (0 to 15) of character; type character_array is array (0 to 15) of character;
@@ -76,6 +78,7 @@ begin
charcnt_reg <= (others => '0'); charcnt_reg <= (others => '0');
lcd_newchar_reg <= '0'; lcd_newchar_reg <= '0';
lcd_newpos_reg <= '0';
lcd_data_reg <= (others => '0'); lcd_data_reg <= (others => '0');
busy_old_reg <= '0'; busy_old_reg <= '0';
freq_out_reg <=(others => '0'); freq_out_reg <=(others => '0');
@@ -87,6 +90,7 @@ begin
charcnt_reg <= charcnt_next; charcnt_reg <= charcnt_next;
lcd_newchar_reg<= lcd_newchar_next; lcd_newchar_reg<= lcd_newchar_next;
lcd_newpos_reg<= lcd_newpos_next;
lcd_data_reg <= lcd_data_next; lcd_data_reg <= lcd_data_next;
busy_old_reg <= busy_old_next; busy_old_reg <= busy_old_next;
freq_out_reg <= freq_out_next; freq_out_reg <= freq_out_next;
@@ -99,8 +103,9 @@ begin
freq_out <= freq_out_reg; freq_out <= freq_out_reg;
lcd_data <= lcd_data_reg; lcd_data <= lcd_data_reg;
lcd_newchar <= lcd_newchar_reg; lcd_newchar <= lcd_newchar_reg;
lcd_newpos <= lcd_newpos_reg;
proc2: process(digit_reg,enc_updown,enc_ce,enc_err,enc_btn,digpos_reg,btn_old_reg, charcnt_reg, lcd_busy, lcd_data_reg, lcd_newchar_reg, busy_old_reg) proc2: process(digit_reg,enc_updown,enc_ce,enc_err,enc_btn,digpos_reg,btn_old_reg, charcnt_reg, lcd_busy, lcd_data_reg, busy_old_reg)
begin begin
digit_next <= digit_reg; digit_next <= digit_reg;
digpos_next <= digpos_reg; digpos_next <= digpos_reg;
@@ -108,6 +113,7 @@ begin
charcnt_next <= charcnt_reg; charcnt_next <= charcnt_reg;
lcd_newchar_next <= '0'; lcd_newchar_next <= '0';
lcd_newpos_next <= '0';
lcd_data_next <= lcd_data_reg; lcd_data_next <= lcd_data_reg;
busy_old_next <= lcd_busy; busy_old_next <= lcd_busy;

2
lcd_driver.vhd
View File

@@ -130,7 +130,7 @@ begin
-- type : sequential -- type : sequential
-- inputs : clk, cur_state -- inputs : clk, cur_state
-- outputs : none -- outputs : none
NSL: process(clk, cur_state, cur_counter, cur_lcd_db, cur_lcd_en, cur_lcd_rs, ret_state, ret_counter, new_character,data) is NSL: process(clk, cur_state, cur_counter, cur_lcd_db, cur_lcd_en, cur_lcd_rs, ret_state, ret_counter, new_character,data,new_pos) is
begin begin
next_counter <= cur_counter + 1; -- increment counter next_counter <= cur_counter + 1; -- increment counter

56
toplevel.sch
View File

@@ -6,7 +6,6 @@
<trait edittrait="all:0" /> <trait edittrait="all:0" />
</attr> </attr>
<netlist> <netlist>
<signal name="XLXN_131" />
<signal name="FORM(1:0)" /> <signal name="FORM(1:0)" />
<signal name="FORM(0)" /> <signal name="FORM(0)" />
<signal name="FORM(1)" /> <signal name="FORM(1)" />
@@ -33,15 +32,15 @@
<signal name="XLXN_79" /> <signal name="XLXN_79" />
<signal name="LCD_busy" /> <signal name="LCD_busy" />
<signal name="LCD_RS" /> <signal name="LCD_RS" />
<signal name="XLXN_170" />
<signal name="XLXN_70" /> <signal name="XLXN_70" />
<signal name="LCD_E" /> <signal name="LCD_E" />
<signal name="XLXN_176" /> <signal name="XLXN_176" />
<signal name="XLXN_177(7:0)" />
<signal name="LCD_DB(7:0)" /> <signal name="LCD_DB(7:0)" />
<signal name="LCD_RW" /> <signal name="LCD_RW" />
<signal name="XLXN_30" /> <signal name="XLXN_30" />
<signal name="DAC_CLR" /> <signal name="DAC_CLR" />
<signal name="XLXN_179" />
<signal name="XLXN_180(7:0)" />
<port polarity="Input" name="CLK_50MHZ" /> <port polarity="Input" name="CLK_50MHZ" />
<port polarity="Output" name="SPI_SCK" /> <port polarity="Output" name="SPI_SCK" />
<port polarity="Output" name="DAC_CS" /> <port polarity="Output" name="DAC_CS" />
@@ -107,20 +106,21 @@
<line x2="32" y1="-64" y2="-64" x1="96" /> <line x2="32" y1="-64" y2="-64" x1="96" />
</blockdef> </blockdef>
<blockdef name="controller"> <blockdef name="controller">
<timestamp>2016-6-3T16:4:48</timestamp> <timestamp>2016-6-6T19:48:13</timestamp>
<rect width="304" x="64" y="-448" height="448" /> <rect width="304" x="64" y="-448" height="448" />
<line x2="0" y1="-416" y2="-416" x1="64" /> <line x2="0" y1="-416" y2="-416" x1="64" />
<line x2="0" y1="-352" y2="-352" x1="64" /> <line x2="0" y1="-352" y2="-352" x1="64" />
<line x2="0" y1="-96" y2="-96" x1="64" /> <line x2="0" y1="-96" y2="-96" x1="64" />
<line x2="0" y1="-32" y2="-32" x1="64" /> <line x2="0" y1="-32" y2="-32" x1="64" />
<line x2="432" y1="-416" y2="-416" x1="368" /> <line x2="432" y1="-416" y2="-416" x1="368" />
<rect width="64" x="368" y="-44" height="24" />
<line x2="432" y1="-32" y2="-32" x1="368" />
<line x2="0" y1="-224" y2="-224" x1="64" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<line x2="0" y1="-288" y2="-288" x1="64" /> <line x2="0" y1="-288" y2="-288" x1="64" />
<rect width="64" x="368" y="-364" height="24" />
<line x2="432" y1="-352" y2="-352" x1="368" /> <line x2="432" y1="-352" y2="-352" x1="368" />
<rect width="64" x="368" y="-300" height="24" />
<line x2="432" y1="-288" y2="-288" x1="368" />
<rect width="64" x="368" y="-236" height="24" />
<line x2="432" y1="-224" y2="-224" x1="368" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<line x2="0" y1="-224" y2="-224" x1="64" />
</blockdef> </blockdef>
<blockdef name="rotary_dec"> <blockdef name="rotary_dec">
<timestamp>2016-5-23T16:56:27</timestamp> <timestamp>2016-5-23T16:56:27</timestamp>
@@ -201,11 +201,12 @@
<blockpin signalname="XLXN_79" name="enc_err" /> <blockpin signalname="XLXN_79" name="enc_err" />
<blockpin signalname="LCD_busy" name="lcd_busy" /> <blockpin signalname="LCD_busy" name="lcd_busy" />
<blockpin signalname="XLXN_176" name="lcd_newchar" /> <blockpin signalname="XLXN_176" name="lcd_newchar" />
<blockpin signalname="FREQ(16:0)" name="freq_out(16:0)" />
<blockpin signalname="XLXN_77" name="enc_updown" />
<blockpin signalname="XLXN_78" name="enc_ce" />
<blockpin signalname="ROT_CENTER" name="enc_btn" /> <blockpin signalname="ROT_CENTER" name="enc_btn" />
<blockpin signalname="XLXN_177(7:0)" name="lcd_data(7:0)" /> <blockpin signalname="XLXN_179" name="lcd_newpos" />
<blockpin signalname="XLXN_180(7:0)" name="lcd_data(7:0)" />
<blockpin signalname="FREQ(16:0)" name="freq_out(16:0)" />
<blockpin signalname="XLXN_78" name="enc_ce" />
<blockpin signalname="XLXN_77" name="enc_updown" />
</block> </block>
<block symbolname="rotary_dec" name="XLXI_43"> <block symbolname="rotary_dec" name="XLXI_43">
<blockpin signalname="CLK_50MHZ" name="clk" /> <blockpin signalname="CLK_50MHZ" name="clk" />
@@ -222,8 +223,8 @@
<blockpin signalname="CLK_50MHZ" name="clk" /> <blockpin signalname="CLK_50MHZ" name="clk" />
<blockpin signalname="XLXN_70" name="reset" /> <blockpin signalname="XLXN_70" name="reset" />
<blockpin signalname="XLXN_176" name="new_character" /> <blockpin signalname="XLXN_176" name="new_character" />
<blockpin name="new_pos" /> <blockpin signalname="XLXN_179" name="new_pos" />
<blockpin signalname="XLXN_177(7:0)" name="data(7:0)" /> <blockpin signalname="XLXN_180(7:0)" name="data(7:0)" />
<blockpin signalname="LCD_busy" name="busy" /> <blockpin signalname="LCD_busy" name="busy" />
<blockpin signalname="LCD_E" name="lcd_en" /> <blockpin signalname="LCD_E" name="lcd_en" />
<blockpin signalname="LCD_RS" name="lcd_rs" /> <blockpin signalname="LCD_RS" name="lcd_rs" />
@@ -298,11 +299,10 @@
<wire x2="4304" y1="1984" y2="1984" x1="3952" /> <wire x2="4304" y1="1984" y2="1984" x1="3952" />
</branch> </branch>
<branch name="FREQ(16:0)"> <branch name="FREQ(16:0)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="2763" y="2096" type="branch" /> <attrtext style="alignment:SOFT-LEFT;fontsize:28;fontname:Arial" attrname="Name" x="2763" y="2096" type="branch" />
<wire x2="2592" y1="1728" y2="1728" x1="2224" /> <wire x2="2592" y1="1536" y2="1536" x1="2224" />
<wire x2="2592" y1="1728" y2="2096" x1="2592" /> <wire x2="2592" y1="1536" y2="2096" x1="2592" />
<wire x2="2763" y1="2096" y2="2096" x1="2592" /> <wire x2="2944" y1="2096" y2="2096" x1="2592" />
<wire x2="2944" y1="2096" y2="2096" x1="2763" />
</branch> </branch>
<instance x="4080" y="1840" name="XLXI_14" orien="R0" /> <instance x="4080" y="1840" name="XLXI_14" orien="R0" />
<branch name="J18_IO4"> <branch name="J18_IO4">
@@ -428,12 +428,6 @@
<wire x2="2480" y1="1296" y2="1344" x1="2480" /> <wire x2="2480" y1="1296" y2="1344" x1="2480" />
<wire x2="2736" y1="1296" y2="1296" x1="2480" /> <wire x2="2736" y1="1296" y2="1296" x1="2480" />
</branch> </branch>
<branch name="XLXN_177(7:0)">
<wire x2="2240" y1="1408" y2="1408" x1="2224" />
<wire x2="2480" y1="1408" y2="1408" x1="2240" />
<wire x2="2480" y1="1408" y2="1424" x1="2480" />
<wire x2="2736" y1="1424" y2="1424" x1="2480" />
</branch>
<branch name="LCD_DB(7:0)"> <branch name="LCD_DB(7:0)">
<wire x2="3168" y1="1408" y2="1408" x1="3152" /> <wire x2="3168" y1="1408" y2="1408" x1="3152" />
<wire x2="3232" y1="1408" y2="1408" x1="3168" /> <wire x2="3232" y1="1408" y2="1408" x1="3168" />
@@ -461,5 +455,15 @@
</branch> </branch>
<instance x="3856" y="2192" name="XLXI_20" orien="R0" /> <instance x="3856" y="2192" name="XLXI_20" orien="R0" />
<iomarker fontsize="28" x="4208" y="2192" name="DAC_CLR" orien="R0" /> <iomarker fontsize="28" x="4208" y="2192" name="DAC_CLR" orien="R0" />
<branch name="XLXN_179">
<wire x2="2480" y1="1408" y2="1408" x1="2224" />
<wire x2="2480" y1="1360" y2="1408" x1="2480" />
<wire x2="2736" y1="1360" y2="1360" x1="2480" />
</branch>
<branch name="XLXN_180(7:0)">
<wire x2="2480" y1="1472" y2="1472" x1="2224" />
<wire x2="2480" y1="1424" y2="1472" x1="2480" />
<wire x2="2736" y1="1424" y2="1424" x1="2480" />
</branch>
</sheet> </sheet>
</drawing> </drawing>

25
yasg.gise
View File

@@ -225,7 +225,7 @@
</transform> </transform>
<transform xil_pn:end_ts="1464954092" xil_pn:in_ck="-1222633688712987584" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7301171803071747408" xil_pn:start_ts="1464954092"> <transform xil_pn:end_ts="1464954092" xil_pn:in_ck="-1222633688712987584" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7301171803071747408" xil_pn:start_ts="1464954092">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="NotReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/> <status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
@@ -237,7 +237,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1465241870" xil_pn:in_ck="6038244062278950263" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6927427346963598489" xil_pn:start_ts="1465241869"> <transform xil_pn:end_ts="1465242537" xil_pn:in_ck="6038244062278950263" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6927427346963598489" xil_pn:start_ts="1465242536">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="toplevel.vhf"/> <outfile xil_pn:name="toplevel.vhf"/>
@@ -262,7 +262,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1465242071" xil_pn:in_ck="-5804926608689456155" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="1663716282806445198" xil_pn:start_ts="1465242061"> <transform xil_pn:end_ts="1465242740" xil_pn:in_ck="-5804926608689456155" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="1663716282806445198" xil_pn:start_ts="1465242726">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
@@ -270,7 +270,9 @@
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name=".lso"/> <outfile xil_pn:name=".lso"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/> <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="dds.ngr"/>
<outfile xil_pn:name="lcd_driver.ngr"/> <outfile xil_pn:name="lcd_driver.ngr"/>
<outfile xil_pn:name="spi_driver.ngr"/>
<outfile xil_pn:name="toplevel.jhd"/> <outfile xil_pn:name="toplevel.jhd"/>
<outfile xil_pn:name="toplevel.lso"/> <outfile xil_pn:name="toplevel.lso"/>
<outfile xil_pn:name="toplevel.ngc"/> <outfile xil_pn:name="toplevel.ngc"/>
@@ -287,7 +289,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1465242075" xil_pn:in_ck="-7078274988114474919" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1538882668640856751" xil_pn:start_ts="1465242071"> <transform xil_pn:end_ts="1465242745" xil_pn:in_ck="-2091007341535647977" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1538882668640856751" xil_pn:start_ts="1465242740">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/> <outfile xil_pn:name="_ngo"/>
@@ -296,9 +298,11 @@
<outfile xil_pn:name="toplevel.ngd"/> <outfile xil_pn:name="toplevel.ngd"/>
<outfile xil_pn:name="toplevel_ngdbuild.xrpt"/> <outfile xil_pn:name="toplevel_ngdbuild.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1465242080" xil_pn:in_ck="4873113828297183478" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="570889668722473129" xil_pn:start_ts="1465242075"> <transform xil_pn:end_ts="1465242752" xil_pn:in_ck="1621356785167787192" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="570889668722473129" xil_pn:start_ts="1465242745">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="toplevel.pcf"/> <outfile xil_pn:name="toplevel.pcf"/>
<outfile xil_pn:name="toplevel_map.map"/> <outfile xil_pn:name="toplevel_map.map"/>
@@ -309,9 +313,8 @@
<outfile xil_pn:name="toplevel_summary.xml"/> <outfile xil_pn:name="toplevel_summary.xml"/>
<outfile xil_pn:name="toplevel_usage.xml"/> <outfile xil_pn:name="toplevel_usage.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1465242098" xil_pn:in_ck="2913749866623724303" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-988662182046631445" xil_pn:start_ts="1465242080"> <transform xil_pn:end_ts="1465242770" xil_pn:in_ck="985354266144665770" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-988662182046631445" xil_pn:start_ts="1465242752">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="toplevel.ncd"/> <outfile xil_pn:name="toplevel.ncd"/>
@@ -324,7 +327,7 @@
<outfile xil_pn:name="toplevel_pad.txt"/> <outfile xil_pn:name="toplevel_pad.txt"/>
<outfile xil_pn:name="toplevel_par.xrpt"/> <outfile xil_pn:name="toplevel_par.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1465242105" xil_pn:in_ck="6038244062278944814" xil_pn:name="TRANEXT_bitFile_spartan3a" xil_pn:prop_ck="-426368325978129584" xil_pn:start_ts="1465242098"> <transform xil_pn:end_ts="1465242777" xil_pn:in_ck="8640606860472830956" xil_pn:name="TRANEXT_bitFile_spartan3a" xil_pn:prop_ck="-426368325978129584" xil_pn:start_ts="1465242770">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
@@ -339,8 +342,12 @@
<transform xil_pn:end_ts="1465242109" xil_pn:in_ck="6038244062278931960" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5767926783713760761" xil_pn:start_ts="1465242105"> <transform xil_pn:end_ts="1465242109" xil_pn:in_ck="6038244062278931960" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5767926783713760761" xil_pn:start_ts="1465242105">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform> </transform>
<transform xil_pn:end_ts="1465242098" xil_pn:in_ck="4873113828297183346" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1465242095"> <transform xil_pn:end_ts="1465242770" xil_pn:in_ck="6034042283462732464" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1465242766">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>

24
yasg.xise
View File

@@ -20,25 +20,25 @@
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file> </file>
<file xil_pn:name="dds.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="dds.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/> <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file> </file>
<file xil_pn:name="helpers.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="helpers.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file> </file>
<file xil_pn:name="dds_tb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="dds_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="27"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="27"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="27"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="27"/>
</file> </file>
<file xil_pn:name="spi_driver.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="spi_driver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file> </file>
<file xil_pn:name="spi_driver_tb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="spi_driver_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="48"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="48"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="48"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="48"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="48"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="48"/>
@@ -59,11 +59,17 @@
<association xil_pn:name="Implementation" xil_pn:seqID="6"/> <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file> </file>
<file xil_pn:name="lcd_driver_tb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="lcd_driver_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="132"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="132"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="132"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="132"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="132"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="132"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="132"/>
</file> </file>
<file xil_pn:name="controller_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="143"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="143"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="143"/>
</file>
</files> </files>
<properties> <properties>
@@ -77,8 +83,8 @@
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/> <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/> <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/> <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/dds_tb" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/spi_driver_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.dds_tb" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.spi_driver_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/> <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
@@ -88,7 +94,7 @@
<!-- --> <!-- -->
<!-- The following properties are for internal use only. These should not be modified.--> <!-- The following properties are for internal use only. These should not be modified.-->
<!-- --> <!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|dds_tb|behavior" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|spi_driver_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="yasg" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="yasg" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-05-09T19:06:02" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-05-09T19:06:02" xil_pn:valueState="non-default"/>