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Added toplevel schema. DDS works at 1khz. Measured with oscilloscope

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This commit is contained in:
T-moe
2016-05-20 13:53:56 +02:00
parent 71b8cdb490
commit 16b7cc71ee
8 changed files with 560 additions and 42 deletions
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16
dds.sym
View File

@@ -1,26 +1,24 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="dds"> <symbol version="7" name="dds">
<symboltype>BLOCK</symboltype> <symboltype>BLOCK</symboltype>
<timestamp>2016-5-16T9:25:36</timestamp> <timestamp>2016-5-20T8:58:58</timestamp>
<pin polarity="Input" x="0" y="-160" name="clk" /> <pin polarity="Input" x="0" y="-160" name="clk" />
<pin polarity="Input" x="0" y="-96" name="freq" /> <pin polarity="Input" x="0" y="-96" name="freq(16:0)" />
<pin polarity="Input" x="0" y="-32" name="form(1:0)" /> <pin polarity="Input" x="0" y="-32" name="form(1:0)" />
<pin polarity="Output" x="384" y="-160" name="update" /> <pin polarity="Output" x="384" y="-160" name="amp(11:0)" />
<pin polarity="Output" x="384" y="-32" name="amp(11:0)" />
<graph> <graph>
<rect width="256" x="64" y="-192" height="192" /> <rect width="256" x="64" y="-192" height="192" />
<attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-200" type="symbol" /> <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-200" type="symbol" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin clk" /> <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin clk" />
<line x2="0" y1="-160" y2="-160" x1="64" /> <line x2="0" y1="-160" y2="-160" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin freq" /> <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin freq(16:0)" />
<rect width="64" x="0" y="-108" height="24" />
<line x2="0" y1="-96" y2="-96" x1="64" /> <line x2="0" y1="-96" y2="-96" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin form(1:0)" /> <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin form(1:0)" />
<rect width="64" x="0" y="-44" height="24" /> <rect width="64" x="0" y="-44" height="24" />
<line x2="0" y1="-32" y2="-32" x1="64" /> <line x2="0" y1="-32" y2="-32" x1="64" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin update" /> <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin amp(11:0)" />
<rect width="64" x="320" y="-172" height="24" />
<line x2="384" y1="-160" y2="-160" x1="320" /> <line x2="384" y1="-160" y2="-160" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin amp(11:0)" />
<rect width="64" x="320" y="-44" height="24" />
<line x2="384" y1="-32" y2="-32" x1="320" />
</graph> </graph>
</symbol> </symbol>

2
dds.vhd
View File

@@ -30,7 +30,7 @@ entity dds is
acc_res: natural:=32; acc_res: natural:=32;
phase_res: natural:=15); phase_res: natural:=15);
Port ( clk : in STD_LOGIC; Port ( clk : in STD_LOGIC;
freq : in unsigned (log2_int(max_freq)-1 downto 0); freq : in unsigned (16 downto 0); --log2_int(max_freq)-1
form : in unsigned (1 downto 0); form : in unsigned (1 downto 0);
amp : out unsigned (adc_res-1 downto 0)); amp : out unsigned (adc_res-1 downto 0));
end dds; end dds;

19
io.ucf Normal file
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@@ -0,0 +1,19 @@
NET "CLK_50MHZ" LOC = "E12"| IOSTANDARD = LVCMOS33 ;
NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;
NET "SPI_MOSI" LOC = "AB14" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "SPI_SCK" LOC = "AA20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "DAC_CS" LOC = "W7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "DAC_CLR" LOC = "AB13" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
#NET "DAC_OUT" LOC = "V7" | IOSTANDARD = LVCMOS33
NET "J18_IO1" LOC = "AA21" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "J18_IO2" LOC = "AB21" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "J18_IO3" LOC = "AA19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "J18_IO4" LOC = "AB19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "LED0" LOC = "R20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "SW0" LOC = "V8" | IOSTANDARD = LVCMOS33 ;
NET "SW1" LOC = "U10"| IOSTANDARD = LVCMOS33 ;

28
spi_driver.sym Normal file
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@@ -0,0 +1,28 @@
<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="spi_driver">
<symboltype>BLOCK</symboltype>
<timestamp>2016-5-20T8:33:2</timestamp>
<pin polarity="Input" x="0" y="-160" name="clk" />
<pin polarity="Input" x="0" y="-96" name="rst" />
<pin polarity="Input" x="0" y="-32" name="val(11:0)" />
<pin polarity="Output" x="384" y="-160" name="sck" />
<pin polarity="Output" x="384" y="-96" name="cs" />
<pin polarity="Output" x="384" y="-32" name="mosi" />
<graph>
<rect width="256" x="64" y="-192" height="192" />
<attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-200" type="symbol" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin clk" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin rst" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin val(11:0)" />
<rect width="64" x="0" y="-44" height="24" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin sck" />
<line x2="384" y1="-160" y2="-160" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-96" type="pin cs" />
<line x2="384" y1="-96" y2="-96" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin mosi" />
<line x2="384" y1="-32" y2="-32" x1="320" />
</graph>
</symbol>

5
toplevel.jhd Normal file
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@@ -0,0 +1,5 @@
MODULE toplevel
SUBMODULE spi_driver
INSTANCE XLXI_1
SUBMODULE dds
INSTANCE XLXI_2

299
toplevel.sch Normal file
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@@ -0,0 +1,299 @@
<?xml version="1.0" encoding="UTF-8"?>
<drawing version="7">
<attr value="spartan3a" name="DeviceFamilyName">
<trait delete="all:0" />
<trait editname="all:0" />
<trait edittrait="all:0" />
</attr>
<netlist>
<signal name="FORM(1:0)" />
<signal name="FORM(0)">
</signal>
<signal name="FORM(1)">
</signal>
<signal name="CLK_50MHZ" />
<signal name="XLXN_9(11:0)" />
<signal name="XLXN_10" />
<signal name="SPI_SCK" />
<signal name="DAC_CS" />
<signal name="SPI_MOSI" />
<signal name="FREQ(16:0)" />
<signal name="FREQ(15:0)" />
<signal name="J18_IO4" />
<signal name="J18_IO2" />
<signal name="J18_IO3" />
<signal name="J18_IO1" />
<signal name="XLXN_30" />
<signal name="DAC_CLR" />
<signal name="LED0" />
<signal name="SW0" />
<signal name="SW1" />
<signal name="XLXN_40" />
<signal name="FREQ(16)" />
<port polarity="Input" name="CLK_50MHZ" />
<port polarity="Output" name="SPI_SCK" />
<port polarity="Output" name="DAC_CS" />
<port polarity="Output" name="SPI_MOSI" />
<port polarity="Output" name="J18_IO4" />
<port polarity="Output" name="J18_IO2" />
<port polarity="Output" name="J18_IO3" />
<port polarity="Output" name="J18_IO1" />
<port polarity="Output" name="DAC_CLR" />
<port polarity="Output" name="LED0" />
<port polarity="Input" name="SW0" />
<port polarity="Input" name="SW1" />
<blockdef name="spi_driver">
<timestamp>2016-5-20T8:33:2</timestamp>
<rect width="256" x="64" y="-192" height="192" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<rect width="64" x="0" y="-44" height="24" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<line x2="384" y1="-160" y2="-160" x1="320" />
<line x2="384" y1="-96" y2="-96" x1="320" />
<line x2="384" y1="-32" y2="-32" x1="320" />
</blockdef>
<blockdef name="dds">
<timestamp>2016-5-20T8:58:58</timestamp>
<rect width="256" x="64" y="-192" height="192" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<rect width="64" x="0" y="-108" height="24" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<rect width="64" x="0" y="-44" height="24" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<rect width="64" x="320" y="-172" height="24" />
<line x2="384" y1="-160" y2="-160" x1="320" />
</blockdef>
<blockdef name="constant">
<timestamp>2006-1-1T10:10:10</timestamp>
<rect width="112" x="0" y="0" height="64" />
<line x2="112" y1="32" y2="32" x1="144" />
</blockdef>
<blockdef name="gnd">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-64" y2="-96" x1="64" />
<line x2="52" y1="-48" y2="-48" x1="76" />
<line x2="60" y1="-32" y2="-32" x1="68" />
<line x2="40" y1="-64" y2="-64" x1="88" />
<line x2="64" y1="-64" y2="-80" x1="64" />
<line x2="64" y1="-128" y2="-96" x1="64" />
</blockdef>
<blockdef name="buf">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-32" y2="-32" x1="0" />
<line x2="128" y1="-32" y2="-32" x1="224" />
<line x2="128" y1="0" y2="-32" x1="64" />
<line x2="64" y1="-32" y2="-64" x1="128" />
<line x2="64" y1="-64" y2="0" x1="64" />
</blockdef>
<blockdef name="vcc">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-32" y2="-64" x1="64" />
<line x2="64" y1="0" y2="-32" x1="64" />
<line x2="32" y1="-64" y2="-64" x1="96" />
</blockdef>
<block symbolname="spi_driver" name="XLXI_1">
<blockpin signalname="CLK_50MHZ" name="clk" />
<blockpin signalname="XLXN_10" name="rst" />
<blockpin signalname="XLXN_9(11:0)" name="val(11:0)" />
<blockpin signalname="SPI_SCK" name="sck" />
<blockpin signalname="DAC_CS" name="cs" />
<blockpin signalname="SPI_MOSI" name="mosi" />
</block>
<block symbolname="dds" name="XLXI_2">
<blockpin signalname="CLK_50MHZ" name="clk" />
<blockpin signalname="FREQ(16:0)" name="freq(16:0)" />
<blockpin signalname="FORM(1:0)" name="form(1:0)" />
<blockpin signalname="XLXN_9(11:0)" name="amp(11:0)" />
</block>
<block symbolname="gnd" name="XLXI_7">
<blockpin signalname="XLXN_10" name="G" />
</block>
<block symbolname="gnd" name="XLXI_10">
<blockpin signalname="FREQ(16)" name="G" />
</block>
<block symbolname="constant" name="XLXI_3">
<attr value="03E8" name="CValue">
<trait delete="all:1 sym:0" />
<trait editname="all:1 sch:0" />
<trait valuetype="BitVector 32 Hexadecimal" />
</attr>
<blockpin signalname="FREQ(15:0)" name="O" />
</block>
<block symbolname="buf" name="XLXI_14">
<blockpin signalname="SPI_SCK" name="I" />
<blockpin signalname="J18_IO4" name="O" />
</block>
<block symbolname="buf" name="XLXI_15">
<blockpin signalname="DAC_CS" name="I" />
<blockpin signalname="J18_IO2" name="O" />
</block>
<block symbolname="buf" name="XLXI_16">
<blockpin signalname="SPI_MOSI" name="I" />
<blockpin signalname="J18_IO3" name="O" />
</block>
<block symbolname="buf" name="XLXI_17">
<blockpin signalname="CLK_50MHZ" name="I" />
<blockpin signalname="J18_IO1" name="O" />
</block>
<block symbolname="vcc" name="XLXI_20">
<blockpin signalname="XLXN_30" name="P" />
</block>
<block symbolname="buf" name="XLXI_19">
<blockpin signalname="XLXN_30" name="I" />
<blockpin signalname="DAC_CLR" name="O" />
</block>
<block symbolname="buf" name="XLXI_25">
<blockpin signalname="SW0" name="I" />
<blockpin signalname="FORM(0)" name="O" />
</block>
<block symbolname="buf" name="XLXI_26">
<blockpin signalname="SW1" name="I" />
<blockpin signalname="FORM(1)" name="O" />
</block>
<block symbolname="buf" name="XLXI_27">
<blockpin signalname="SW0" name="I" />
<blockpin signalname="LED0" name="O" />
</block>
</netlist>
<sheet sheetnum="1" width="3520" height="2720">
<instance x="976" y="992" name="XLXI_2" orien="R0">
</instance>
<instance x="1568" y="848" name="XLXI_1" orien="R0">
</instance>
<branch name="FORM(1:0)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="848" y="960" type="branch" />
<wire x2="848" y1="960" y2="976" x1="848" />
<wire x2="848" y1="976" y2="1008" x1="848" />
<wire x2="976" y1="960" y2="960" x1="848" />
</branch>
<bustap x2="752" y1="976" y2="976" x1="848" />
<bustap x2="752" y1="1008" y2="1008" x1="848" />
<branch name="FORM(0)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="656" y="976" type="branch" />
<wire x2="656" y1="976" y2="976" x1="544" />
<wire x2="752" y1="976" y2="976" x1="656" />
</branch>
<branch name="FORM(1)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="656" y="1040" type="branch" />
<wire x2="656" y1="1040" y2="1040" x1="544" />
<wire x2="752" y1="1040" y2="1040" x1="656" />
<wire x2="752" y1="1008" y2="1040" x1="752" />
</branch>
<branch name="CLK_50MHZ">
<wire x2="976" y1="832" y2="832" x1="944" />
</branch>
<iomarker fontsize="28" x="944" y="832" name="CLK_50MHZ" orien="R180" />
<branch name="XLXN_9(11:0)">
<wire x2="1456" y1="832" y2="832" x1="1360" />
<wire x2="1456" y1="816" y2="832" x1="1456" />
<wire x2="1568" y1="816" y2="816" x1="1456" />
</branch>
<instance x="1296" y="736" name="XLXI_7" orien="R0" />
<branch name="XLXN_10">
<wire x2="1360" y1="544" y2="608" x1="1360" />
<wire x2="1440" y1="544" y2="544" x1="1360" />
<wire x2="1440" y1="544" y2="752" x1="1440" />
<wire x2="1568" y1="752" y2="752" x1="1440" />
</branch>
<branch name="SPI_SCK">
<wire x2="1984" y1="688" y2="688" x1="1952" />
<wire x2="2112" y1="688" y2="688" x1="1984" />
<wire x2="1984" y1="608" y2="688" x1="1984" />
<wire x2="2112" y1="608" y2="608" x1="1984" />
</branch>
<branch name="DAC_CS">
<wire x2="1984" y1="752" y2="752" x1="1952" />
<wire x2="2112" y1="752" y2="752" x1="1984" />
<wire x2="1984" y1="720" y2="752" x1="1984" />
<wire x2="2336" y1="720" y2="720" x1="1984" />
</branch>
<branch name="SPI_MOSI">
<wire x2="1984" y1="816" y2="816" x1="1952" />
<wire x2="2112" y1="816" y2="816" x1="1984" />
<wire x2="1984" y1="784" y2="816" x1="1984" />
<wire x2="2336" y1="784" y2="784" x1="1984" />
</branch>
<branch name="FREQ(16:0)">
<attrtext style="alignment:SOFT-LEFT;fontsize:28;fontname:Arial" attrname="Name" x="795" y="896" type="branch" />
<wire x2="624" y1="816" y2="864" x1="624" />
<wire x2="624" y1="864" y2="896" x1="624" />
<wire x2="976" y1="896" y2="896" x1="624" />
</branch>
<bustap x2="528" y1="816" y2="816" x1="624" />
<bustap x2="528" y1="864" y2="864" x1="624" />
<branch name="FREQ(15:0)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="464" y="864" type="branch" />
<wire x2="464" y1="864" y2="864" x1="352" />
<wire x2="528" y1="864" y2="864" x1="464" />
</branch>
<instance x="352" y="768" name="XLXI_10" orien="R0" />
<instance x="208" y="832" name="XLXI_3" orien="R0">
</instance>
<instance x="2112" y="640" name="XLXI_14" orien="R0" />
<iomarker fontsize="28" x="2112" y="688" name="SPI_SCK" orien="R0" />
<branch name="J18_IO4">
<wire x2="2368" y1="608" y2="608" x1="2336" />
</branch>
<iomarker fontsize="28" x="2112" y="752" name="DAC_CS" orien="R0" />
<iomarker fontsize="28" x="2112" y="816" name="SPI_MOSI" orien="R0" />
<instance x="2336" y="752" name="XLXI_15" orien="R0" />
<instance x="2336" y="816" name="XLXI_16" orien="R0" />
<branch name="J18_IO2">
<wire x2="2592" y1="720" y2="720" x1="2560" />
</branch>
<iomarker fontsize="28" x="2592" y="720" name="J18_IO2" orien="R0" />
<branch name="J18_IO3">
<wire x2="2592" y1="784" y2="784" x1="2560" />
</branch>
<iomarker fontsize="28" x="2592" y="784" name="J18_IO3" orien="R0" />
<branch name="CLK_50MHZ">
<wire x2="1552" y1="432" y2="432" x1="1504" />
<wire x2="1552" y1="432" y2="688" x1="1552" />
<wire x2="1568" y1="688" y2="688" x1="1552" />
<wire x2="1664" y1="432" y2="432" x1="1552" />
</branch>
<instance x="1664" y="464" name="XLXI_17" orien="R0" />
<branch name="J18_IO1">
<wire x2="1920" y1="432" y2="432" x1="1888" />
</branch>
<iomarker fontsize="28" x="1920" y="432" name="J18_IO1" orien="R0" />
<iomarker fontsize="28" x="2368" y="608" name="J18_IO4" orien="R0" />
<iomarker fontsize="28" x="1504" y="432" name="CLK_50MHZ" orien="R180" />
<instance x="1856" y="1312" name="XLXI_19" orien="R0" />
<branch name="XLXN_30">
<wire x2="1856" y1="1280" y2="1280" x1="1824" />
</branch>
<branch name="DAC_CLR">
<wire x2="2112" y1="1280" y2="1280" x1="2080" />
</branch>
<iomarker fontsize="28" x="2112" y="1280" name="DAC_CLR" orien="R0" />
<instance x="1760" y="1280" name="XLXI_20" orien="R0" />
<branch name="LED0">
<wire x2="592" y1="1120" y2="1120" x1="544" />
</branch>
<iomarker fontsize="28" x="592" y="1120" name="LED0" orien="R0" />
<instance x="320" y="1008" name="XLXI_25" orien="R0" />
<instance x="320" y="1072" name="XLXI_26" orien="R0" />
<branch name="SW0">
<wire x2="288" y1="976" y2="976" x1="224" />
<wire x2="288" y1="976" y2="1120" x1="288" />
<wire x2="320" y1="1120" y2="1120" x1="288" />
<wire x2="320" y1="976" y2="976" x1="288" />
</branch>
<branch name="SW1">
<wire x2="320" y1="1040" y2="1040" x1="224" />
</branch>
<instance x="320" y="1152" name="XLXI_27" orien="R0" />
<iomarker fontsize="28" x="224" y="1040" name="SW1" orien="R180" />
<iomarker fontsize="28" x="224" y="976" name="SW0" orien="R180" />
<branch name="FREQ(16)">
<attrtext style="alignment:SOFT-TVCENTER;fontsize:28;fontname:Arial" attrname="Name" x="512" y="736" type="branch" />
<wire x2="416" y1="624" y2="640" x1="416" />
<wire x2="512" y1="624" y2="624" x1="416" />
<wire x2="512" y1="624" y2="736" x1="512" />
<wire x2="512" y1="736" y2="816" x1="512" />
<wire x2="528" y1="816" y2="816" x1="512" />
</branch>
</sheet>
</drawing>

206
yasg.gise
View File

@@ -23,19 +23,40 @@
<files xmlns="http://www.xilinx.com/XMLSchema"> <files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name=".lso"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name=".lso"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/> <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="dds.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="dds.cmd_log"/> <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="dds.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="dds.lso"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="dds.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="dds.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="dds.ngc"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="dds.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="dds.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="dds.ngr"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="dds.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="dds.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="dds.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="dds.prj"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="dds.prj"/>
<file xil_pn:fileType="FILE_SPL" xil_pn:name="dds.spl"/> <file xil_pn:fileType="FILE_SPL" xil_pn:name="dds.spl"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="dds.stx"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="dds.stx"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="dds.sym" xil_pn:origination="imported"/> <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="dds.sym" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="dds.syr"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="dds.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="dds.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="dds.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="dds.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="dds.vhi"/> <file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="dds.vhi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="dds.xst"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="dds.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="dds_envsettings.html"/> <file xil_pn:fileType="FILE_HTML" xil_pn:name="dds_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="dds_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="dds_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="dds_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="dds_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="dds_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="dds_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="dds_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="dds_summary.html"/> <file xil_pn:fileType="FILE_HTML" xil_pn:name="dds_summary.html"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="dds_tb_isim_beh.exe"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="dds_tb_isim_beh.exe"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="dds_tb_stx_beh.prj"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="dds_tb_stx_beh.prj"/>
@@ -44,6 +65,7 @@
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/> <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/> <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="lcd_driver.prj"/> <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="lcd_driver.prj"/>
<file xil_pn:fileType="FILE_XST_STX" xil_pn:name="lcd_driver.stx"/> <file xil_pn:fileType="FILE_XST_STX" xil_pn:name="lcd_driver.stx"/>
<file xil_pn:fileType="FILE_XST" xil_pn:name="lcd_driver.xst"/> <file xil_pn:fileType="FILE_XST" xil_pn:name="lcd_driver.xst"/>
@@ -52,17 +74,63 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="spi_driver.ngc"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="spi_driver.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="spi_driver.ngr"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="spi_driver.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="spi_driver.prj"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="spi_driver.prj"/>
<file xil_pn:fileType="FILE_SPL" xil_pn:name="spi_driver.spl"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="spi_driver.stx"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="spi_driver.stx"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="spi_driver.sym" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="spi_driver.syr"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="spi_driver.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="spi_driver.xst"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="spi_driver.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="spi_driver_envsettings.html"/> <file xil_pn:fileType="FILE_HTML" xil_pn:name="spi_driver_envsettings.html"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="spi_driver_isim_beh.exe"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="spi_driver_summary.html"/> <file xil_pn:fileType="FILE_HTML" xil_pn:name="spi_driver_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="spi_driver_tb_beh.prj"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="spi_driver_tb_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="spi_driver_tb_isim_beh.exe"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="spi_driver_tb_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="spi_driver_tb_isim_beh.wdb"/> <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="spi_driver_tb_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="spi_driver_xst.xrpt"/> <file xil_pn:fileType="FILE_XRPT" xil_pn:name="spi_driver_xst.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="toplevel.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="toplevel.bit" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="toplevel.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="toplevel.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="toplevel.drc" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_JHD" xil_pn:name="toplevel.jhd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="toplevel.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="toplevel.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="toplevel.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="toplevel.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="toplevel.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="toplevel.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="toplevel.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="toplevel.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="toplevel.prj"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="toplevel.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="toplevel.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="toplevel.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="toplevel.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="toplevel.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="toplevel.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="toplevel.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="toplevel.vhf"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="toplevel.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="toplevel.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="toplevel_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="toplevel_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="toplevel_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="toplevel_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="toplevel_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="toplevel_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="toplevel_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="toplevel_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="toplevel_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="toplevel_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="toplevel_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="toplevel_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="toplevel_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="toplevel_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="toplevel_xst.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/> <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/> <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files> </files>
@@ -74,6 +142,10 @@
<transform xil_pn:end_ts="1463492912" xil_pn:in_ck="-5764019863604259361" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1463492912"> <transform xil_pn:end_ts="1463492912" xil_pn:in_ck="-5764019863604259361" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1463492912">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="dds.vhd"/> <outfile xil_pn:name="dds.vhd"/>
<outfile xil_pn:name="dds_tb.vhd"/> <outfile xil_pn:name="dds_tb.vhd"/>
<outfile xil_pn:name="helpers.vhd"/> <outfile xil_pn:name="helpers.vhd"/>
@@ -81,21 +153,30 @@
<outfile xil_pn:name="spi_driver.vhd"/> <outfile xil_pn:name="spi_driver.vhd"/>
<outfile xil_pn:name="spi_driver_tb.vhd"/> <outfile xil_pn:name="spi_driver_tb.vhd"/>
</transform> </transform>
<transform xil_pn:end_ts="1463492818" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="9076618275249177275" xil_pn:start_ts="1463492818"> <transform xil_pn:end_ts="1463508117" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="9076618275249177275" xil_pn:start_ts="1463508117">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1463492818" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="983764721944091843" xil_pn:start_ts="1463492818"> <transform xil_pn:end_ts="1463508117" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="983764721944091843" xil_pn:start_ts="1463508117">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
</transform> </transform>
<transform xil_pn:end_ts="1463492319" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="7922287241511046268" xil_pn:start_ts="1463492319"> <transform xil_pn:end_ts="1463492319" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="7922287241511046268" xil_pn:start_ts="1463492319">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
</transform> </transform>
<transform xil_pn:end_ts="1463492912" xil_pn:in_ck="-5764019863604259361" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1463492912"> <transform xil_pn:end_ts="1463492912" xil_pn:in_ck="-5764019863604259361" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1463492912">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="dds.vhd"/> <outfile xil_pn:name="dds.vhd"/>
<outfile xil_pn:name="dds_tb.vhd"/> <outfile xil_pn:name="dds_tb.vhd"/>
<outfile xil_pn:name="helpers.vhd"/> <outfile xil_pn:name="helpers.vhd"/>
@@ -103,72 +184,151 @@
<outfile xil_pn:name="spi_driver.vhd"/> <outfile xil_pn:name="spi_driver.vhd"/>
<outfile xil_pn:name="spi_driver_tb.vhd"/> <outfile xil_pn:name="spi_driver_tb.vhd"/>
</transform> </transform>
<transform xil_pn:end_ts="1463492916" xil_pn:in_ck="-5764019863604259361" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-6914626614812979269" xil_pn:start_ts="1463492912"> <transform xil_pn:end_ts="1463573880" xil_pn:in_ck="-5764019863604259361" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-6914626614812979269" xil_pn:start_ts="1463573878">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="fuse.log"/> <outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/> <outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="spi_driver_tb_beh.prj"/> <outfile xil_pn:name="spi_driver_tb_beh.prj"/>
<outfile xil_pn:name="spi_driver_tb_isim_beh.exe"/> <outfile xil_pn:name="spi_driver_tb_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/> <outfile xil_pn:name="xilinxsim.ini"/>
</transform> </transform>
<transform xil_pn:end_ts="1463492916" xil_pn:in_ck="3473449341593533562" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="4788567445176171336" xil_pn:start_ts="1463492916"> <transform xil_pn:end_ts="1463573880" xil_pn:in_ck="-1222633688712987584" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="4788567445176171336" xil_pn:start_ts="1463573880">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="isim.cmd"/> <outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="spi_driver_tb_isim_beh.wdb"/> <outfile xil_pn:name="spi_driver_tb_isim_beh.wdb"/>
</transform> </transform>
<transform xil_pn:end_ts="1463390963" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1463390963"> <transform xil_pn:end_ts="1463732677" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1463732677">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1463492899" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4283474513315137243" xil_pn:start_ts="1463492899"> <transform xil_pn:end_ts="1463744693" xil_pn:in_ck="6038244062278950263" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6927427346963598489" xil_pn:start_ts="1463744692">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="toplevel.vhf"/>
</transform>
<transform xil_pn:end_ts="1463733715" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1929794406770174374" xil_pn:start_ts="1463733715">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1463492899" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7922287241511046268" xil_pn:start_ts="1463492899"> <transform xil_pn:end_ts="1463733715" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1463733715">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1463492899" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1463492899"> <transform xil_pn:end_ts="1463733715" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2239360189155701135" xil_pn:start_ts="1463733715">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1463492899" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-6021373413463586381" xil_pn:start_ts="1463492899"> <transform xil_pn:end_ts="1463734910" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="9102341965431189672" xil_pn:start_ts="1463734910">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1463492899" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="9102341965431189672" xil_pn:start_ts="1463492899"> <transform xil_pn:end_ts="1463733715" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="7072966905182239268" xil_pn:start_ts="1463733715">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1463492899" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5717942653304215546" xil_pn:start_ts="1463492899"> <transform xil_pn:end_ts="1463744766" xil_pn:in_ck="-1719981268874910048" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="1663716282806445198" xil_pn:start_ts="1463744693">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1463492907" xil_pn:in_ck="-2379736742458753213" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="3948038486698552048" xil_pn:start_ts="1463492899">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name=".lso"/> <outfile xil_pn:name=".lso"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/> <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="spi_driver.lso"/> <outfile xil_pn:name="dds.ngr"/>
<outfile xil_pn:name="spi_driver.ngc"/>
<outfile xil_pn:name="spi_driver.ngr"/> <outfile xil_pn:name="spi_driver.ngr"/>
<outfile xil_pn:name="spi_driver.prj"/> <outfile xil_pn:name="toplevel.jhd"/>
<outfile xil_pn:name="spi_driver.stx"/> <outfile xil_pn:name="toplevel.lso"/>
<outfile xil_pn:name="spi_driver.syr"/> <outfile xil_pn:name="toplevel.ngc"/>
<outfile xil_pn:name="spi_driver.xst"/> <outfile xil_pn:name="toplevel.ngr"/>
<outfile xil_pn:name="spi_driver_tb_beh.prj"/> <outfile xil_pn:name="toplevel.prj"/>
<outfile xil_pn:name="spi_driver_xst.xrpt"/> <outfile xil_pn:name="toplevel.stx"/>
<outfile xil_pn:name="toplevel.syr"/>
<outfile xil_pn:name="toplevel.xst"/>
<outfile xil_pn:name="toplevel_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/> <outfile xil_pn:name="xst"/>
</transform> </transform>
<transform xil_pn:end_ts="1463744766" xil_pn:in_ck="4242637380" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4784894232377633197" xil_pn:start_ts="1463744766">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1463744772" xil_pn:in_ck="2169537708537049843" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1538882668640856751" xil_pn:start_ts="1463744766">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="toplevel.bld"/>
<outfile xil_pn:name="toplevel.ngd"/>
<outfile xil_pn:name="toplevel_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1463744783" xil_pn:in_ck="1621356785167787192" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="570889668722473129" xil_pn:start_ts="1463744772">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="toplevel.pcf"/>
<outfile xil_pn:name="toplevel_map.map"/>
<outfile xil_pn:name="toplevel_map.mrp"/>
<outfile xil_pn:name="toplevel_map.ncd"/>
<outfile xil_pn:name="toplevel_map.ngm"/>
<outfile xil_pn:name="toplevel_map.xrpt"/>
<outfile xil_pn:name="toplevel_summary.xml"/>
<outfile xil_pn:name="toplevel_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1463744826" xil_pn:in_ck="985354266144665770" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-988662182046631445" xil_pn:start_ts="1463744783">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="toplevel.ncd"/>
<outfile xil_pn:name="toplevel.pad"/>
<outfile xil_pn:name="toplevel.par"/>
<outfile xil_pn:name="toplevel.ptwx"/>
<outfile xil_pn:name="toplevel.unroutes"/>
<outfile xil_pn:name="toplevel.xpi"/>
<outfile xil_pn:name="toplevel_pad.csv"/>
<outfile xil_pn:name="toplevel_pad.txt"/>
<outfile xil_pn:name="toplevel_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1463744842" xil_pn:in_ck="8640606860472830956" xil_pn:name="TRANEXT_bitFile_spartan3a" xil_pn:prop_ck="-426368325978129584" xil_pn:start_ts="1463744826">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="toplevel.bgn"/>
<outfile xil_pn:name="toplevel.bit"/>
<outfile xil_pn:name="toplevel.drc"/>
<outfile xil_pn:name="toplevel.ut"/>
<outfile xil_pn:name="usage_statistics_webtalk.html"/>
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1463743826" xil_pn:in_ck="6038244062278931960" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5767926783713760761" xil_pn:start_ts="1463743825">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1463744826" xil_pn:in_ck="6034042283462732464" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1463744821">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="toplevel.twr"/>
<outfile xil_pn:name="toplevel.twx"/>
</transform>
</transforms> </transforms>
</generated_project> </generated_project>

27
yasg.xise
View File

@@ -21,11 +21,11 @@
</file> </file>
<file xil_pn:name="dds.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="dds.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file> </file>
<file xil_pn:name="helpers.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="helpers.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file> </file>
<file xil_pn:name="dds_tb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="dds_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -35,7 +35,7 @@
</file> </file>
<file xil_pn:name="spi_driver.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="spi_driver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file> </file>
<file xil_pn:name="spi_driver_tb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="spi_driver_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
@@ -43,6 +43,13 @@
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="48"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="48"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="48"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="48"/>
</file> </file>
<file xil_pn:name="toplevel.sch" xil_pn:type="FILE_SCHEMATIC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="io.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files> </files>
<properties> <properties>
@@ -50,14 +57,14 @@
<property xil_pn:name="Device" xil_pn:value="xc3s700an" xil_pn:valueState="non-default"/> <property xil_pn:name="Device" xil_pn:value="xc3s700an" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3A and Spartan3AN" xil_pn:valueState="non-default"/> <property xil_pn:name="Device Family" xil_pn:value="Spartan3A and Spartan3AN" xil_pn:valueState="non-default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="Spartan-3AN Starter Kit" xil_pn:valueState="non-default"/> <property xil_pn:name="Evaluation Development Board" xil_pn:value="Spartan-3AN Starter Kit" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spi_driver|Behavioral" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top" xil_pn:value="Module|toplevel" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="spi_driver.vhd" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top File" xil_pn:value="toplevel.sch" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spi_driver" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/toplevel" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/> <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/> <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/> <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/spi_driver_tb" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/dds_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.spi_driver_tb" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.dds_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/> <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
@@ -76,7 +83,9 @@
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties> </properties>
<bindings/> <bindings>
<binding xil_pn:location="/toplevel" xil_pn:name="io.ucf"/>
</bindings>
<libraries/> <libraries/>