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<a href="#func-members">Functions</a> </div>
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<div class="title">FLASH Interface configuration functions<div class="ingroups"><a class="el" href="group___s_t_m32_f4xx___std_periph___driver.html">STM32F4xx_StdPeriph_Driver</a> » <a class="el" href="group___f_l_a_s_h.html">RAMFUNC</a> » <a class="el" href="group___f_l_a_s_h___private___functions.html">FLASH_Private_Functions</a></div></div> </div>
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</div><!--header-->
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<div class="contents">
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<p>FLASH Interface configuration functions.
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<a href="#details">More...</a></p>
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<div class="dynheader">
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Collaboration diagram for FLASH Interface configuration functions:</div>
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<div class="dyncontent">
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<center><table><tr><td><img src="group___f_l_a_s_h___group1.png" border="0" alt="" usemap="#group______f__l__a__s__h______group1"/>
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<map name="group______f__l__a__s__h______group1" id="group______f__l__a__s__h______group1">
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<area shape="rect" id="node2" href="group___f_l_a_s_h___private___functions.html" title="FLASH_Private_Functions" alt="" coords="5,13,180,39"/></map>
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</td></tr></table></center>
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</div>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
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Functions</h2></td></tr>
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<tr class="memitem:ga54bcb96270215c752c3479c8c9e438c0"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___f_l_a_s_h___group1.html#ga54bcb96270215c752c3479c8c9e438c0">FLASH_SetLatency</a> (uint32_t FLASH_Latency)</td></tr>
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<tr class="memdesc:ga54bcb96270215c752c3479c8c9e438c0"><td class="mdescLeft"> </td><td class="mdescRight">Sets the code latency value. <a href="#ga54bcb96270215c752c3479c8c9e438c0">More...</a><br /></td></tr>
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<tr class="separator:ga54bcb96270215c752c3479c8c9e438c0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafaa24b6176b587bdda46abbe755af986"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___f_l_a_s_h___group1.html#gafaa24b6176b587bdda46abbe755af986">FLASH_PrefetchBufferCmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:gafaa24b6176b587bdda46abbe755af986"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the Prefetch Buffer. <a href="#gafaa24b6176b587bdda46abbe755af986">More...</a><br /></td></tr>
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<tr class="separator:gafaa24b6176b587bdda46abbe755af986"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7d5a9a35e792d844c329d7f1656b50ae"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___f_l_a_s_h___group1.html#ga7d5a9a35e792d844c329d7f1656b50ae">FLASH_InstructionCacheCmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga7d5a9a35e792d844c329d7f1656b50ae"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the Instruction Cache feature. <a href="#ga7d5a9a35e792d844c329d7f1656b50ae">More...</a><br /></td></tr>
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<tr class="separator:ga7d5a9a35e792d844c329d7f1656b50ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga937a824493f3c6949289401a767a0360"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___f_l_a_s_h___group1.html#ga937a824493f3c6949289401a767a0360">FLASH_DataCacheCmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga937a824493f3c6949289401a767a0360"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the Data Cache feature. <a href="#ga937a824493f3c6949289401a767a0360">More...</a><br /></td></tr>
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<tr class="separator:ga937a824493f3c6949289401a767a0360"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf6f1e54d9df32f3c196d67e59eb80a49"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___f_l_a_s_h___group1.html#gaf6f1e54d9df32f3c196d67e59eb80a49">FLASH_InstructionCacheReset</a> (void)</td></tr>
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<tr class="memdesc:gaf6f1e54d9df32f3c196d67e59eb80a49"><td class="mdescLeft"> </td><td class="mdescRight">Resets the Instruction Cache. <a href="#gaf6f1e54d9df32f3c196d67e59eb80a49">More...</a><br /></td></tr>
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<tr class="separator:gaf6f1e54d9df32f3c196d67e59eb80a49"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8332da89b072373b7f116e0b7c137a22"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___f_l_a_s_h___group1.html#ga8332da89b072373b7f116e0b7c137a22">FLASH_DataCacheReset</a> (void)</td></tr>
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<tr class="memdesc:ga8332da89b072373b7f116e0b7c137a22"><td class="mdescLeft"> </td><td class="mdescRight">Resets the Data Cache. <a href="#ga8332da89b072373b7f116e0b7c137a22">More...</a><br /></td></tr>
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<tr class="separator:ga8332da89b072373b7f116e0b7c137a22"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<p>FLASH Interface configuration functions. </p>
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<pre class="fragment"> ===============================================================================
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##### FLASH Interface configuration functions #####
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===============================================================================
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[..]
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This group includes the following functions:
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(+) void FLASH_SetLatency(uint32_t FLASH_Latency)
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To correctly read data from FLASH memory, the number of wait states (LATENCY)
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must be correctly programmed according to the frequency of the CPU clock
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(HCLK) and the supply voltage of the device.
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[..]
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For STM32F405xx/07xx and STM32F415xx/17xx devices
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+-------------------------------------------------------------------------------------+
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| Latency | HCLK clock frequency (MHz) |
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| |---------------------------------------------------------------------|
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| | voltage range | voltage range | voltage range | voltage range |
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| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
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|---------------|----------------|----------------|-----------------|-----------------|
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|0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
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|---------------|----------------|----------------|-----------------|-----------------|
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|1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
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|---------------|----------------|----------------|-----------------|-----------------|
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|2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
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|---------------|----------------|----------------|-----------------|-----------------|
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|3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
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|---------------|----------------|----------------|-----------------|-----------------|
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|4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
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|---------------|----------------|----------------|-----------------|-----------------|
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|5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
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|---------------|----------------|----------------|-----------------|-----------------|
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|6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
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|---------------|----------------|----------------|-----------------|-----------------|
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|7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160|
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+---------------|----------------|----------------|-----------------|-----------------+
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[..]
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For STM32F42xxx/43xxx devices
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+-------------------------------------------------------------------------------------+
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| Latency | HCLK clock frequency (MHz) |
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| |---------------------------------------------------------------------|
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| | voltage range | voltage range | voltage range | voltage range |
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| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
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|---------------|----------------|----------------|-----------------|-----------------|
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|0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
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|---------------|----------------|----------------|-----------------|-----------------|
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|1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
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|---------------|----------------|----------------|-----------------|-----------------|
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|2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
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|---------------|----------------|----------------|-----------------|-----------------|
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|3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
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|---------------|----------------|----------------|-----------------|-----------------|
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|4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
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|---------------|----------------|----------------|-----------------|-----------------|
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|5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
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|---------------|----------------|----------------|-----------------|-----------------|
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|6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
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|---------------|----------------|----------------|-----------------|-----------------|
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|7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160|
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|---------------|----------------|----------------|-----------------|-----------------|
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|8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168|
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+-------------------------------------------------------------------------------------+
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[..]
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For STM32F401x devices
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+-------------------------------------------------------------------------------------+
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| Latency | HCLK clock frequency (MHz) |
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| |---------------------------------------------------------------------|
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| | voltage range | voltage range | voltage range | voltage range |
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| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
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|---------------|----------------|----------------|-----------------|-----------------|
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|0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
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|---------------|----------------|----------------|-----------------|-----------------|
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|1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
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|---------------|----------------|----------------|-----------------|-----------------|
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|2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
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|---------------|----------------|----------------|-----------------|-----------------|
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|3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 |
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|---------------|----------------|----------------|-----------------|-----------------|
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|4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 |
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+-------------------------------------------------------------------------------------+
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[..]
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For STM32F411xE devices
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+-------------------------------------------------------------------------------------+
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| Latency | HCLK clock frequency (MHz) |
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| |---------------------------------------------------------------------|
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| | voltage range | voltage range | voltage range | voltage range |
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| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
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|---------------|----------------|----------------|-----------------|-----------------|
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|0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |
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|---------------|----------------|----------------|-----------------|-----------------|
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|1WS(2CPU cycle)|30 < HCLK <= 64 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 |
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|---------------|----------------|----------------|-----------------|-----------------|
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|2WS(3CPU cycle)|64 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |
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|---------------|----------------|----------------|-----------------|-----------------|
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|3WS(4CPU cycle)|90 < HCLK <= 100|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
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|---------------|----------------|----------------|-----------------|-----------------|
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|4WS(5CPU cycle)| NA |96 < HCLK <= 100|72 < HCLK <= 90 |64 < HCLK <= 80 |
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|---------------|----------------|----------------|-----------------|-----------------|
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|5WS(6CPU cycle)| NA | NA |90 < HCLK <= 100 |80 < HCLK <= 96 |
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|---------------|----------------|----------------|-----------------|-----------------|
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|6WS(7CPU cycle)| NA | NA | NA |96 < HCLK <= 100 |
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+-------------------------------------------------------------------------------------+
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[..]
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+-------------------------------------------------------------------------------------------------------------------+
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| | voltage range | voltage range | voltage range | voltage range | voltage range 2.7 V - 3.6 V |
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| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | with External Vpp = 9V |
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|---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
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|Max Parallelism| x32 | x16 | x8 | x64 |
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|---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
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|PSIZE[1:0] | 10 | 01 | 00 | 11 |
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+-------------------------------------------------------------------------------------------------------------------+
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-@- On STM32F405xx/407xx and STM32F415xx/417xx devices:
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(++) when VOS = '0' Scale 2 mode, the maximum value of fHCLK = 144MHz.
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(++) when VOS = '1' Scale 1 mode, the maximum value of fHCLK = 168MHz.
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[..]
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On STM32F42xxx/43xxx devices:
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(++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 120MHz.
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(++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 144MHz if OverDrive OFF and 168MHz if OverDrive ON.
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(++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 168MHz if OverDrive OFF and 180MHz if OverDrive ON.
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[..]
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On STM32F401x devices:
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(++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 60MHz.
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(++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz.
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[..]
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On STM32F411xE devices:
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(++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 64MHz.
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(++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz.
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(++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 100MHz.
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For more details please refer product DataSheet
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You can use PWR_MainRegulatorModeConfig() function to control VOS bits.
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(+) void FLASH_PrefetchBufferCmd(FunctionalState NewState)
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(+) void FLASH_InstructionCacheCmd(FunctionalState NewState)
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(+) void FLASH_DataCacheCmd(FunctionalState NewState)
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(+) void FLASH_InstructionCacheReset(void)
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(+) void FLASH_DataCacheReset(void)
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[..]
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The unlock sequence is not needed for these functions.</pre> <h2 class="groupheader">Function Documentation</h2>
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<a class="anchor" id="ga937a824493f3c6949289401a767a0360"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void FLASH_DataCacheCmd </td>
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<td>(</td>
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<td class="paramtype">FunctionalState </td>
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<td class="paramname"><em>NewState</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Enables or disables the Data Cache feature. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">NewState</td><td>new state of the Data Cache. This parameter can be: ENABLE or DISABLE. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
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<table class="retval">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="ga8332da89b072373b7f116e0b7c137a22"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void FLASH_DataCacheReset </td>
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<td>(</td>
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<td class="paramtype">void </td>
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<td class="paramname"></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Resets the Data Cache. </p>
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<dl class="section note"><dt>Note</dt><dd>This function must be used only when the Data Cache is disabled. </dd></dl>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
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<table class="retval">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="ga7d5a9a35e792d844c329d7f1656b50ae"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void FLASH_InstructionCacheCmd </td>
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<td>(</td>
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<td class="paramtype">FunctionalState </td>
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<td class="paramname"><em>NewState</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Enables or disables the Instruction Cache feature. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">NewState</td><td>new state of the Instruction Cache. This parameter can be: ENABLE or DISABLE. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
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<table class="retval">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="gaf6f1e54d9df32f3c196d67e59eb80a49"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void FLASH_InstructionCacheReset </td>
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<td>(</td>
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<td class="paramtype">void </td>
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<td class="paramname"></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Resets the Instruction Cache. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>This function must be used only when the Instruction Cache is disabled. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
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</dl>
|
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</div>
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</div>
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<a class="anchor" id="gafaa24b6176b587bdda46abbe755af986"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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|
<td class="memname">void FLASH_PrefetchBufferCmd </td>
|
|
<td>(</td>
|
|
<td class="paramtype">FunctionalState </td>
|
|
<td class="paramname"><em>NewState</em></td><td>)</td>
|
|
<td></td>
|
|
</tr>
|
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</table>
|
|
</div><div class="memdoc">
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|
|
<p>Enables or disables the Prefetch Buffer. </p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">NewState</td><td>new state of the Prefetch Buffer. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
|
</div>
|
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</div>
|
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<a class="anchor" id="ga54bcb96270215c752c3479c8c9e438c0"></a>
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<div class="memitem">
|
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<div class="memproto">
|
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<table class="memname">
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<tr>
|
|
<td class="memname">void FLASH_SetLatency </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>FLASH_Latency</em></td><td>)</td>
|
|
<td></td>
|
|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
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|
|
|
<p>Sets the code latency value. </p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">FLASH_Latency</td><td>specifies the FLASH Latency value. This parameter can be one of the following values: <ul>
|
|
<li>FLASH_Latency_0: FLASH Zero Latency cycle </li>
|
|
<li>FLASH_Latency_1: FLASH One Latency cycle </li>
|
|
<li>FLASH_Latency_2: FLASH Two Latency cycles </li>
|
|
<li>FLASH_Latency_3: FLASH Three Latency cycles </li>
|
|
<li>FLASH_Latency_4: FLASH Four Latency cycles </li>
|
|
<li>FLASH_Latency_5: FLASH Five Latency cycles </li>
|
|
<li>FLASH_Latency_6: FLASH Six Latency cycles </li>
|
|
<li>FLASH_Latency_7: FLASH Seven Latency cycles </li>
|
|
<li>FLASH_Latency_8: FLASH Eight Latency cycles </li>
|
|
<li>FLASH_Latency_9: FLASH Nine Latency cycles </li>
|
|
<li>FLASH_Latency_10: FLASH Teen Latency cycles </li>
|
|
<li>FLASH_Latency_11: FLASH Eleven Latency cycles </li>
|
|
<li>FLASH_Latency_12: FLASH Twelve Latency cycles </li>
|
|
<li>FLASH_Latency_13: FLASH Thirteen Latency cycles </li>
|
|
<li>FLASH_Latency_14: FLASH Fourteen Latency cycles </li>
|
|
<li>FLASH_Latency_15: FLASH Fifteen Latency cycles</li>
|
|
</ul>
|
|
</td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="section note"><dt>Note</dt><dd>For STM32F405xx/407xx, STM32F415xx/417xx and STM32F401xx/411xE devices this parameter can be a value between FLASH_Latency_0 and FLASH_Latency_7.</dd>
|
|
<dd>
|
|
For STM32F42xxx/43xxx devices this parameter can be a value between FLASH_Latency_0 and FLASH_Latency_15.</dd></dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
|
</div>
|
|
</div>
|
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