8351 lines
1.9 MiB
8351 lines
1.9 MiB
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<div class="title">stm32f4xx.h</div> </div>
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<div class="contents">
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<a href="stm32f4xx_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno"> 1</span> </div>
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<div class="line"><a name="l00053"></a><span class="lineno"> 53</span> <span class="preprocessor">#ifndef __STM32F4xx_H</span></div>
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<div class="line"><a name="l00054"></a><span class="lineno"> 54</span> <span class="preprocessor">#define __STM32F4xx_H</span></div>
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<div class="line"><a name="l00055"></a><span class="lineno"> 55</span> </div>
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<div class="line"><a name="l00056"></a><span class="lineno"> 56</span> <span class="preprocessor">#ifdef __cplusplus</span></div>
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<div class="line"><a name="l00057"></a><span class="lineno"> 57</span>  <span class="keyword">extern</span> <span class="stringliteral">"C"</span> {</div>
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<div class="line"><a name="l00058"></a><span class="lineno"> 58</span> <span class="preprocessor">#endif </span><span class="comment">/* __cplusplus */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00059"></a><span class="lineno"> 59</span>  </div>
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<div class="line"><a name="l00064"></a><span class="lineno"> 64</span> <span class="comment">/* Uncomment the line below according to the target STM32 device used in your</span></div>
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<div class="line"><a name="l00065"></a><span class="lineno"> 65</span> <span class="comment"> application </span></div>
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<div class="line"><a name="l00066"></a><span class="lineno"> 66</span> <span class="comment"> */</span></div>
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<div class="line"><a name="l00067"></a><span class="lineno"> 67</span> </div>
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<div class="line"><a name="l00068"></a><span class="lineno"> 68</span> <span class="preprocessor">#if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) && !defined (STM32F411xE)</span></div>
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<div class="line"><a name="l00069"></a><span class="lineno"><a class="line" href="group___library__configuration__section.html#ga317241f394c57389b4699c5f1bf9b897"> 69</a></span> <span class="preprocessor"> #define STM32F40_41xxx </span></div>
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<div class="line"><a name="l00073"></a><span class="lineno"> 73</span> <span class="preprocessor"> </span><span class="comment">/* #define STM32F427_437xx */</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l00076"></a><span class="lineno"> 76</span> <span class="preprocessor"> </span><span class="comment">/* #define STM32F429_439xx */</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l00081"></a><span class="lineno"> 81</span> <span class="preprocessor"> </span><span class="comment">/* #define STM32F401xx */</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l00084"></a><span class="lineno"> 84</span> <span class="preprocessor"> </span><span class="comment">/* #define STM32F411xE */</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l00085"></a><span class="lineno"> 85</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00086"></a><span class="lineno"> 86</span> </div>
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<div class="line"><a name="l00087"></a><span class="lineno"> 87</span> <span class="comment">/* Old STM32F40XX definition, maintained for legacy purpose */</span></div>
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<div class="line"><a name="l00088"></a><span class="lineno"> 88</span> <span class="preprocessor">#ifdef STM32F40XX</span></div>
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<div class="line"><a name="l00089"></a><span class="lineno"> 89</span> <span class="preprocessor"> #define STM32F40_41xxx</span></div>
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<div class="line"><a name="l00090"></a><span class="lineno"> 90</span> <span class="preprocessor">#endif </span><span class="comment">/* STM32F40XX */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00091"></a><span class="lineno"> 91</span> </div>
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<div class="line"><a name="l00092"></a><span class="lineno"> 92</span> <span class="comment">/* Old STM32F427X definition, maintained for legacy purpose */</span></div>
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<div class="line"><a name="l00093"></a><span class="lineno"> 93</span> <span class="preprocessor">#ifdef STM32F427X</span></div>
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<div class="line"><a name="l00094"></a><span class="lineno"> 94</span> <span class="preprocessor"> #define STM32F427_437xx</span></div>
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<div class="line"><a name="l00095"></a><span class="lineno"> 95</span> <span class="preprocessor">#endif </span><span class="comment">/* STM32F427X */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00096"></a><span class="lineno"> 96</span> </div>
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<div class="line"><a name="l00097"></a><span class="lineno"> 97</span> <span class="comment">/* Tip: To avoid modifying this file each time you need to switch between these</span></div>
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<div class="line"><a name="l00098"></a><span class="lineno"> 98</span> <span class="comment"> devices, you can define the device in your toolchain compiler preprocessor.</span></div>
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<div class="line"><a name="l00099"></a><span class="lineno"> 99</span> <span class="comment"> */</span></div>
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<div class="line"><a name="l00100"></a><span class="lineno"> 100</span> </div>
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<div class="line"><a name="l00101"></a><span class="lineno"> 101</span> <span class="preprocessor">#if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) && !defined (STM32F411xE)</span></div>
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<div class="line"><a name="l00102"></a><span class="lineno"> 102</span> <span class="preprocessor"> #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"</span></div>
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<div class="line"><a name="l00103"></a><span class="lineno"> 103</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00104"></a><span class="lineno"> 104</span> </div>
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<div class="line"><a name="l00105"></a><span class="lineno"> 105</span> <span class="preprocessor">#if !defined (USE_STDPERIPH_DRIVER)</span></div>
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<div class="line"><a name="l00106"></a><span class="lineno"> 106</span> </div>
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<div class="line"><a name="l00111"></a><span class="lineno"> 111</span> <span class="preprocessor"> #define USE_STDPERIPH_DRIVER </span></div>
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<div class="line"><a name="l00112"></a><span class="lineno"> 112</span> <span class="preprocessor">#endif </span><span class="comment">/* USE_STDPERIPH_DRIVER */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00113"></a><span class="lineno"><a class="line" href="group___library__configuration__section.html#gaca81a6c87370480adbdaa6083efd243d"> 113</a></span> </div>
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<div class="line"><a name="l00122"></a><span class="lineno"> 122</span> <span class="preprocessor">#if !defined (HSE_VALUE) </span></div>
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<div class="line"><a name="l00123"></a><span class="lineno"> 123</span>  <span class="comment">//#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */</span></div>
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<div class="line"><a name="l00124"></a><span class="lineno"> 124</span> <span class="preprocessor"> #define HSE_VALUE ((uint32_t)8000000) </span></div>
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<div class="line"><a name="l00125"></a><span class="lineno"> 125</span> <span class="preprocessor">#endif </span><span class="comment">/* HSE_VALUE */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00126"></a><span class="lineno"><a class="line" href="group___library__configuration__section.html#gaeafcff4f57440c60e64812dddd13e7cb"> 126</a></span> </div>
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<div class="line"><a name="l00131"></a><span class="lineno"> 131</span> <span class="preprocessor">#if !defined (HSE_STARTUP_TIMEOUT) </span></div>
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<div class="line"><a name="l00132"></a><span class="lineno"> 132</span> <span class="preprocessor"> #define HSE_STARTUP_TIMEOUT ((uint16_t)0x05000) </span></div>
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<div class="line"><a name="l00133"></a><span class="lineno"> 133</span> <span class="preprocessor">#endif </span><span class="comment">/* HSE_STARTUP_TIMEOUT */</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l00134"></a><span class="lineno"><a class="line" href="group___library__configuration__section.html#ga68ecbc9b0a1a40a1ec9d18d5e9747c4f"> 134</a></span> </div>
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<div class="line"><a name="l00135"></a><span class="lineno"> 135</span> <span class="preprocessor">#if !defined (HSI_VALUE) </span></div>
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<div class="line"><a name="l00136"></a><span class="lineno"> 136</span> <span class="preprocessor"> #define HSI_VALUE ((uint32_t)16000000) </span></div>
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<div class="line"><a name="l00137"></a><span class="lineno"> 137</span> <span class="preprocessor">#endif </span><span class="comment">/* HSI_VALUE */</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l00138"></a><span class="lineno"><a class="line" href="group___library__configuration__section.html#gaaa8c76e274d0f6dd2cefb5d0b17fbc37"> 138</a></span> </div>
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<div class="line"><a name="l00142"></a><span class="lineno"> 142</span> <span class="preprocessor">#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) </span></div>
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<div class="line"><a name="l00143"></a><span class="lineno"> 143</span> <span class="preprocessor">#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x04) </span></div>
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<div class="line"><a name="l00144"></a><span class="lineno"><a class="line" href="group___library__configuration__section.html#gab16ffe03509714c63d5e530131c494f4"> 144</a></span> <span class="preprocessor">#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) </span></div>
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<div class="line"><a name="l00145"></a><span class="lineno"><a class="line" href="group___library__configuration__section.html#gadce716e810a51b042298fb21b63e5366"> 145</a></span> <span class="preprocessor">#define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) </span></div>
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<div class="line"><a name="l00146"></a><span class="lineno"><a class="line" href="group___library__configuration__section.html#ga4b16607e43a35289dc5ebb608b1261d4"> 146</a></span> <span class="preprocessor">#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\</span></div>
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<div class="line"><a name="l00147"></a><span class="lineno"><a class="line" href="group___library__configuration__section.html#gad5bec5e54ac96b9238a6363f2088f85c"> 147</a></span> <span class="preprocessor"> |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\</span></div>
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<div class="line"><a name="l00148"></a><span class="lineno"> 148</span> <span class="preprocessor"> |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\</span></div>
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<div class="line"><a name="l00149"></a><span class="lineno"> 149</span> <span class="preprocessor"> |(__STM32F4XX_STDPERIPH_VERSION_RC))</span></div>
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<div class="line"><a name="l00150"></a><span class="lineno"> 150</span>  </div>
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<div class="line"><a name="l00162"></a><span class="lineno"> 162</span> <span class="preprocessor">#define __CM4_REV 0x0001 </span></div>
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<div class="line"><a name="l00163"></a><span class="lineno"> 163</span> <span class="preprocessor">#define __MPU_PRESENT 1 </span></div>
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<div class="line"><a name="l00164"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#ga45a97e4bb8b6ce7c334acc5f45ace3ba"> 164</a></span> <span class="preprocessor">#define __NVIC_PRIO_BITS 4 </span></div>
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<div class="line"><a name="l00165"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#ga4127d1b31aaf336fab3d7329d117f448"> 165</a></span> <span class="preprocessor">#define __Vendor_SysTickConfig 0 </span></div>
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<div class="line"><a name="l00166"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460"> 166</a></span> <span class="preprocessor">#define __FPU_PRESENT 1 </span></div>
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<div class="line"><a name="l00172"></a><span class="lineno"> 172</span> <span class="preprocessor">typedef enum IRQn</span></div>
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<div class="line"><a name="l00173"></a><span class="lineno"> 173</span> {</div>
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<div class="line"><a name="l00174"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#ga666eb0caeb12ec0e281415592ae89083"> 174</a></span> <span class="comment">/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/</span></div>
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<div class="line"><a name="l00175"></a><span class="lineno"> 175</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ade177d9c70c89e084093024b932a4e30">NonMaskableInt_IRQn</a> = -14, </div>
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<div class="line"><a name="l00176"></a><span class="lineno"> 176</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a33ff1cf7098de65d61b6354fee6cd5aa">MemoryManagement_IRQn</a> = -12, </div>
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<div class="line"><a name="l00177"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ade177d9c70c89e084093024b932a4e30"> 177</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a8693500eff174f16119e96234fee73af">BusFault_IRQn</a> = -11, </div>
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<div class="line"><a name="l00178"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a33ff1cf7098de65d61b6354fee6cd5aa"> 178</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a6895237c9443601ac832efa635dd8bbf">UsageFault_IRQn</a> = -10, </div>
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<div class="line"><a name="l00179"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a8693500eff174f16119e96234fee73af"> 179</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a4ce820b3cc6cf3a796b41aadc0cf1237">SVCall_IRQn</a> = -5, </div>
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<div class="line"><a name="l00180"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a6895237c9443601ac832efa635dd8bbf"> 180</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a8e033fcef7aed98a31c60a7de206722c">DebugMonitor_IRQn</a> = -4, </div>
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<div class="line"><a name="l00181"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a4ce820b3cc6cf3a796b41aadc0cf1237"> 181</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a03c3cc89984928816d81793fc7bce4a2">PendSV_IRQn</a> = -2, </div>
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<div class="line"><a name="l00182"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a8e033fcef7aed98a31c60a7de206722c"> 182</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a6dbff8f8543325f3474cbae2446776e7">SysTick_IRQn</a> = -1, </div>
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<div class="line"><a name="l00183"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a03c3cc89984928816d81793fc7bce4a2"> 183</a></span> <span class="comment">/****** STM32 specific Interrupt Numbers **********************************************************************/</span></div>
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<div class="line"><a name="l00184"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a6dbff8f8543325f3474cbae2446776e7"> 184</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a971089d7566ef902dfa0c80ac3a8fd52">WWDG_IRQn</a> = 0, </div>
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<div class="line"><a name="l00185"></a><span class="lineno"> 185</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab0b51ffcc4dcf5661141b79c8e5bd924">PVD_IRQn</a> = 1, </div>
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<div class="line"><a name="l00186"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a971089d7566ef902dfa0c80ac3a8fd52"> 186</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ac127cca7ae48bcf93924209f04e5e5a1">TAMP_STAMP_IRQn</a> = 2, </div>
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<div class="line"><a name="l00187"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab0b51ffcc4dcf5661141b79c8e5bd924"> 187</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a173ccc3f31df1f7e43de2ddeab3d1777">RTC_WKUP_IRQn</a> = 3, </div>
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<div class="line"><a name="l00188"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ac127cca7ae48bcf93924209f04e5e5a1"> 188</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a91b73963ce243a1d031576d49e137fab">FLASH_IRQn</a> = 4, </div>
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<div class="line"><a name="l00189"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a173ccc3f31df1f7e43de2ddeab3d1777"> 189</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a5710b22392997bac63daa5c999730f77">RCC_IRQn</a> = 5, </div>
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<div class="line"><a name="l00190"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a91b73963ce243a1d031576d49e137fab"> 190</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab6aa6f87d26bbc6cf99b067b8d75c2f7">EXTI0_IRQn</a> = 6, </div>
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<div class="line"><a name="l00191"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a5710b22392997bac63daa5c999730f77"> 191</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ae4badcdecdb94eb10129c4c0577c5e19">EXTI1_IRQn</a> = 7, </div>
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<div class="line"><a name="l00192"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab6aa6f87d26bbc6cf99b067b8d75c2f7"> 192</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a082cb3f7839069a0715fd76c7eacbbc9">EXTI2_IRQn</a> = 8, </div>
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<div class="line"><a name="l00193"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ae4badcdecdb94eb10129c4c0577c5e19"> 193</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083add889c84ba5de466ced209069e05d602">EXTI3_IRQn</a> = 9, </div>
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<div class="line"><a name="l00194"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a082cb3f7839069a0715fd76c7eacbbc9"> 194</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab70a40106ca4486770df5d2072d9ac0e">EXTI4_IRQn</a> = 10, </div>
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<div class="line"><a name="l00195"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083add889c84ba5de466ced209069e05d602"> 195</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9ee33e72512c4cfb301b216f4fb9d68c">DMA1_Stream0_IRQn</a> = 11, </div>
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<div class="line"><a name="l00196"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab70a40106ca4486770df5d2072d9ac0e"> 196</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa45ca2c955060e2c2a7cbbe1d6753285">DMA1_Stream1_IRQn</a> = 12, </div>
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<div class="line"><a name="l00197"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9ee33e72512c4cfb301b216f4fb9d68c"> 197</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a0d9ec75e4478e70235b705d5a6b3efd8">DMA1_Stream2_IRQn</a> = 13, </div>
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<div class="line"><a name="l00198"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa45ca2c955060e2c2a7cbbe1d6753285"> 198</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af77770e080206a7558decf09344fb2e2">DMA1_Stream3_IRQn</a> = 14, </div>
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<div class="line"><a name="l00199"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a0d9ec75e4478e70235b705d5a6b3efd8"> 199</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aee2aaf365c6c297a63cee41ecae2301a">DMA1_Stream4_IRQn</a> = 15, </div>
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<div class="line"><a name="l00200"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af77770e080206a7558decf09344fb2e2"> 200</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ac92efa72399fe58fa615d8bf8fd64a4e">DMA1_Stream5_IRQn</a> = 16, </div>
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<div class="line"><a name="l00201"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aee2aaf365c6c297a63cee41ecae2301a"> 201</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aef5e2b68f62f6f1781fab894f0b8f486">DMA1_Stream6_IRQn</a> = 17, </div>
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<div class="line"><a name="l00202"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ac92efa72399fe58fa615d8bf8fd64a4e"> 202</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a4d69175258ae261dd545001e810421b3">ADC_IRQn</a> = 18, </div>
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<div class="line"><a name="l00204"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a4d69175258ae261dd545001e810421b3"> 204</a></span> <span class="preprocessor">#if defined (STM32F40_41xxx)</span></div>
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<div class="line"><a name="l00205"></a><span class="lineno"> 205</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9ceb5175f7c10cf436955173c2246877">CAN1_TX_IRQn</a> = 19, </div>
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<div class="line"><a name="l00206"></a><span class="lineno"> 206</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab6bf73ac43a9856b3f2759a59f3d25b5">CAN1_RX0_IRQn</a> = 20, </div>
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<div class="line"><a name="l00207"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9ceb5175f7c10cf436955173c2246877"> 207</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af71ef06c4f9ff0e1691c21ff3670acd4">CAN1_RX1_IRQn</a> = 21, </div>
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<div class="line"><a name="l00208"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab6bf73ac43a9856b3f2759a59f3d25b5"> 208</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a0f5f129d88a5606a378811e43039e274">CAN1_SCE_IRQn</a> = 22, </div>
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<div class="line"><a name="l00209"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af71ef06c4f9ff0e1691c21ff3670acd4"> 209</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa3aa50e0353871985facf62d055faa52">EXTI9_5_IRQn</a> = 23, </div>
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<div class="line"><a name="l00210"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a0f5f129d88a5606a378811e43039e274"> 210</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab35b4ce63cfb11453f84a3695c6df368">TIM1_BRK_TIM9_IRQn</a> = 24, </div>
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<div class="line"><a name="l00211"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa3aa50e0353871985facf62d055faa52"> 211</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa3879e49013035601e17f83a51e0829f">TIM1_UP_TIM10_IRQn</a> = 25, </div>
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<div class="line"><a name="l00212"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab35b4ce63cfb11453f84a3695c6df368"> 212</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab1a744bdceb8eface6ff57dd036e608e">TIM1_TRG_COM_TIM11_IRQn</a> = 26, </div>
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<div class="line"><a name="l00213"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa3879e49013035601e17f83a51e0829f"> 213</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af312f0a21f600f9b286427e50c549ca9">TIM1_CC_IRQn</a> = 27, </div>
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<div class="line"><a name="l00214"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab1a744bdceb8eface6ff57dd036e608e"> 214</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3a4e2095a926e4095d3c846eb1c98afa">TIM2_IRQn</a> = 28, </div>
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<div class="line"><a name="l00215"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af312f0a21f600f9b286427e50c549ca9"> 215</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a985574288f66e2a00e97387424a9a2d8">TIM3_IRQn</a> = 29, </div>
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<div class="line"><a name="l00216"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3a4e2095a926e4095d3c846eb1c98afa"> 216</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a368b899ca740b9ae0d75841f3abf68c4">TIM4_IRQn</a> = 30, </div>
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<div class="line"><a name="l00217"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a985574288f66e2a00e97387424a9a2d8"> 217</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9852dbbe8c014e716ce7e03a7b809751">I2C1_EV_IRQn</a> = 31, </div>
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<div class="line"><a name="l00218"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a368b899ca740b9ae0d75841f3abf68c4"> 218</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a2ec363869f4488782dc10a60abce3b34">I2C1_ER_IRQn</a> = 32, </div>
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<div class="line"><a name="l00219"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9852dbbe8c014e716ce7e03a7b809751"> 219</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3020193786527c47d2e4d8c92ceee804">I2C2_EV_IRQn</a> = 33, </div>
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<div class="line"><a name="l00220"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a2ec363869f4488782dc10a60abce3b34"> 220</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a60c35f2d48d512bd6818bc9fef7053d7">I2C2_ER_IRQn</a> = 34, </div>
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<div class="line"><a name="l00221"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3020193786527c47d2e4d8c92ceee804"> 221</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aacdff1a9c42582ed663214cbe62c1174">SPI1_IRQn</a> = 35, </div>
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<div class="line"><a name="l00222"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a60c35f2d48d512bd6818bc9fef7053d7"> 222</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a505fbd4ccf7c2a14c8b76dc9e58f7ede">SPI2_IRQn</a> = 36, </div>
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<div class="line"><a name="l00223"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aacdff1a9c42582ed663214cbe62c1174"> 223</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ad97cb163e1f678367e37c50d54d161ab">USART1_IRQn</a> = 37, </div>
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<div class="line"><a name="l00224"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a505fbd4ccf7c2a14c8b76dc9e58f7ede"> 224</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3f9c48714d0e5baaba6613343f0da68e">USART2_IRQn</a> = 38, </div>
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<div class="line"><a name="l00225"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ad97cb163e1f678367e37c50d54d161ab"> 225</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083afb13802afc1f5fdf5c90e73ee99e5ff3">USART3_IRQn</a> = 39, </div>
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<div class="line"><a name="l00226"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3f9c48714d0e5baaba6613343f0da68e"> 226</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9fb0ad0c850234d1983fafdb17378e2f">EXTI15_10_IRQn</a> = 40, </div>
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<div class="line"><a name="l00227"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083afb13802afc1f5fdf5c90e73ee99e5ff3"> 227</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083afe09d6563a21a1540f658163a76a3b37">RTC_Alarm_IRQn</a> = 41, </div>
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<div class="line"><a name="l00228"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9fb0ad0c850234d1983fafdb17378e2f"> 228</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa612f35c4440359c35acbaa3c1458c5f">OTG_FS_WKUP_IRQn</a> = 42, </div>
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<div class="line"><a name="l00229"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083afe09d6563a21a1540f658163a76a3b37"> 229</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3e01328006d19f7d32354271b9f61dce">TIM8_BRK_TIM12_IRQn</a> = 43, </div>
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<div class="line"><a name="l00230"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa612f35c4440359c35acbaa3c1458c5f"> 230</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa8d8f67a98f24de6f0b36ad6b1f29a7d">TIM8_UP_TIM13_IRQn</a> = 44, </div>
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<div class="line"><a name="l00231"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3e01328006d19f7d32354271b9f61dce"> 231</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ae252b31c3a341acbe9a467e243137307">TIM8_TRG_COM_TIM14_IRQn</a> = 45, </div>
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<div class="line"><a name="l00232"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa8d8f67a98f24de6f0b36ad6b1f29a7d"> 232</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a637750639eff4e2b4aae80ed6f3cf67f">TIM8_CC_IRQn</a> = 46, </div>
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<div class="line"><a name="l00233"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ae252b31c3a341acbe9a467e243137307"> 233</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aedaa9c14e7e5fa9c0dcbb0c2455546e8">DMA1_Stream7_IRQn</a> = 47, </div>
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<div class="line"><a name="l00234"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a637750639eff4e2b4aae80ed6f3cf67f"> 234</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a70450df88125476d5771f2ff3f562536">FSMC_IRQn</a> = 48, </div>
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<div class="line"><a name="l00235"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aedaa9c14e7e5fa9c0dcbb0c2455546e8"> 235</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a16fe70a39348f3f27906dc268b5654e3">SDIO_IRQn</a> = 49, </div>
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<div class="line"><a name="l00236"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a70450df88125476d5771f2ff3f562536"> 236</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aed2eb3f4bb721d55fcc1003125956645">TIM5_IRQn</a> = 50, </div>
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<div class="line"><a name="l00237"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a16fe70a39348f3f27906dc268b5654e3"> 237</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a4e9331739fb76a2ca7781fede070ae44">SPI3_IRQn</a> = 51, </div>
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<div class="line"><a name="l00238"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aed2eb3f4bb721d55fcc1003125956645"> 238</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aded5314b20c6e4e80cb6ab0668ffb8d5">UART4_IRQn</a> = 52, </div>
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<div class="line"><a name="l00239"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a4e9331739fb76a2ca7781fede070ae44"> 239</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ac55a11a64aae7432544d0ab0d4f7de09">UART5_IRQn</a> = 53, </div>
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<div class="line"><a name="l00240"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aded5314b20c6e4e80cb6ab0668ffb8d5"> 240</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a5f581e9aedfaccd9b1db9ec793804b45">TIM6_DAC_IRQn</a> = 54, </div>
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<div class="line"><a name="l00241"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ac55a11a64aae7432544d0ab0d4f7de09"> 241</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a53cadc1e164ec85d0ea4cd143608e8e1">TIM7_IRQn</a> = 55, </div>
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<div class="line"><a name="l00242"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a5f581e9aedfaccd9b1db9ec793804b45"> 242</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a1e5055722630fd4b12aff421964c2ebb">DMA2_Stream0_IRQn</a> = 56, </div>
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<div class="line"><a name="l00243"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a53cadc1e164ec85d0ea4cd143608e8e1"> 243</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a98abb3f02c1feb3831706bc1b82307cb">DMA2_Stream1_IRQn</a> = 57, </div>
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<div class="line"><a name="l00244"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a1e5055722630fd4b12aff421964c2ebb"> 244</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083abf5e189f3ac7aad9f65e65ea5a0f3b36">DMA2_Stream2_IRQn</a> = 58, </div>
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<div class="line"><a name="l00245"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a98abb3f02c1feb3831706bc1b82307cb"> 245</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3ff8f3439f509e6e985eb960e63e1be4">DMA2_Stream3_IRQn</a> = 59, </div>
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<div class="line"><a name="l00246"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083abf5e189f3ac7aad9f65e65ea5a0f3b36"> 246</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ae54eb8b30273b38a0576f75aba24eec0">DMA2_Stream4_IRQn</a> = 60, </div>
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<div class="line"><a name="l00247"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3ff8f3439f509e6e985eb960e63e1be4"> 247</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ad71328dd95461b7c55b568cf25966f6a">ETH_IRQn</a> = 61, </div>
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<div class="line"><a name="l00248"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ae54eb8b30273b38a0576f75aba24eec0"> 248</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a0485578005e12c2e2c0fb253a844ec6f">ETH_WKUP_IRQn</a> = 62, </div>
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<div class="line"><a name="l00249"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ad71328dd95461b7c55b568cf25966f6a"> 249</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af6b8fbc990ac71c8425647bb684788a4">CAN2_TX_IRQn</a> = 63, </div>
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<div class="line"><a name="l00250"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a0485578005e12c2e2c0fb253a844ec6f"> 250</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a851fd2f2ab1418710e7da80e1bdf348a">CAN2_RX0_IRQn</a> = 64, </div>
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<div class="line"><a name="l00251"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af6b8fbc990ac71c8425647bb684788a4"> 251</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab5023ff845be31a488ab63a0b8cf2b7a">CAN2_RX1_IRQn</a> = 65, </div>
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<div class="line"><a name="l00252"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a851fd2f2ab1418710e7da80e1bdf348a"> 252</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a56c0b5758f26f31494e74aab9273f9fd">CAN2_SCE_IRQn</a> = 66, </div>
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<div class="line"><a name="l00253"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab5023ff845be31a488ab63a0b8cf2b7a"> 253</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa60a30b7ef03446a46fd72e084911f7e">OTG_FS_IRQn</a> = 67, </div>
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<div class="line"><a name="l00254"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a56c0b5758f26f31494e74aab9273f9fd"> 254</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a933d4686213973abc01845a3da1c8a03">DMA2_Stream5_IRQn</a> = 68, </div>
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<div class="line"><a name="l00255"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa60a30b7ef03446a46fd72e084911f7e"> 255</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a21570761ad0b5ed751adc831691b7800">DMA2_Stream6_IRQn</a> = 69, </div>
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<div class="line"><a name="l00256"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a933d4686213973abc01845a3da1c8a03"> 256</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3d4cc0cd9b4d71e7ee002c4f8c1f8a77">DMA2_Stream7_IRQn</a> = 70, </div>
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<div class="line"><a name="l00257"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a21570761ad0b5ed751adc831691b7800"> 257</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa92bcb2bc3a87be869f05c5b07f04b8c">USART6_IRQn</a> = 71, </div>
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<div class="line"><a name="l00258"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3d4cc0cd9b4d71e7ee002c4f8c1f8a77"> 258</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a8326db2d570cb865ffa1d49fa29d562a">I2C3_EV_IRQn</a> = 72, </div>
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<div class="line"><a name="l00259"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa92bcb2bc3a87be869f05c5b07f04b8c"> 259</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a6e954232d164a6942ebc7a6bd6f7736e">I2C3_ER_IRQn</a> = 73, </div>
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<div class="line"><a name="l00260"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a8326db2d570cb865ffa1d49fa29d562a"> 260</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a60b6cc4b6dbeca39e29a475d26c9e080">OTG_HS_EP1_OUT_IRQn</a> = 74, </div>
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<div class="line"><a name="l00261"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a6e954232d164a6942ebc7a6bd6f7736e"> 261</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a1b040a7f76278a73cf5ea4c51f1be047">OTG_HS_EP1_IN_IRQn</a> = 75, </div>
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<div class="line"><a name="l00262"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a60b6cc4b6dbeca39e29a475d26c9e080"> 262</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9e5c9d81dd3985a88094f8158c0f0267">OTG_HS_WKUP_IRQn</a> = 76, </div>
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<div class="line"><a name="l00263"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a1b040a7f76278a73cf5ea4c51f1be047"> 263</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aad2d5e47d27fe3a02f7059b20bb729c0">OTG_HS_IRQn</a> = 77, </div>
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<div class="line"><a name="l00264"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9e5c9d81dd3985a88094f8158c0f0267"> 264</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ace3c0fc2c4d05a7c02e3c987da5bc8e8">DCMI_IRQn</a> = 78, </div>
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<div class="line"><a name="l00265"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aad2d5e47d27fe3a02f7059b20bb729c0"> 265</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a70c9645bf48ca539510cc8f7d974f017">CRYP_IRQn</a> = 79, </div>
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<div class="line"><a name="l00266"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ace3c0fc2c4d05a7c02e3c987da5bc8e8"> 266</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a86a161642b54055f9bbea3937e6352de">HASH_RNG_IRQn</a> = 80, </div>
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<div class="line"><a name="l00267"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a70c9645bf48ca539510cc8f7d974f017"> 267</a></span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa6b8ff01b016a798c6e639728c179e4f">FPU_IRQn</a> = 81 </div>
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<div class="line"><a name="l00268"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a86a161642b54055f9bbea3937e6352de"> 268</a></span> <span class="preprocessor">#endif </span><span class="comment">/* STM32F40_41xxx */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00269"></a><span class="lineno"><a class="line" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa6b8ff01b016a798c6e639728c179e4f"> 269</a></span> </div>
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<div class="line"><a name="l00270"></a><span class="lineno"> 270</span> <span class="preprocessor">#if defined (STM32F427_437xx)</span></div>
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<div class="line"><a name="l00271"></a><span class="lineno"> 271</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9ceb5175f7c10cf436955173c2246877">CAN1_TX_IRQn</a> = 19, </div>
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<div class="line"><a name="l00272"></a><span class="lineno"> 272</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab6bf73ac43a9856b3f2759a59f3d25b5">CAN1_RX0_IRQn</a> = 20, </div>
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<div class="line"><a name="l00273"></a><span class="lineno"> 273</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af71ef06c4f9ff0e1691c21ff3670acd4">CAN1_RX1_IRQn</a> = 21, </div>
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<div class="line"><a name="l00274"></a><span class="lineno"> 274</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a0f5f129d88a5606a378811e43039e274">CAN1_SCE_IRQn</a> = 22, </div>
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<div class="line"><a name="l00275"></a><span class="lineno"> 275</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa3aa50e0353871985facf62d055faa52">EXTI9_5_IRQn</a> = 23, </div>
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<div class="line"><a name="l00276"></a><span class="lineno"> 276</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab35b4ce63cfb11453f84a3695c6df368">TIM1_BRK_TIM9_IRQn</a> = 24, </div>
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<div class="line"><a name="l00277"></a><span class="lineno"> 277</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa3879e49013035601e17f83a51e0829f">TIM1_UP_TIM10_IRQn</a> = 25, </div>
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<div class="line"><a name="l00278"></a><span class="lineno"> 278</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab1a744bdceb8eface6ff57dd036e608e">TIM1_TRG_COM_TIM11_IRQn</a> = 26, </div>
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<div class="line"><a name="l00279"></a><span class="lineno"> 279</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af312f0a21f600f9b286427e50c549ca9">TIM1_CC_IRQn</a> = 27, </div>
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<div class="line"><a name="l00280"></a><span class="lineno"> 280</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3a4e2095a926e4095d3c846eb1c98afa">TIM2_IRQn</a> = 28, </div>
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<div class="line"><a name="l00281"></a><span class="lineno"> 281</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a985574288f66e2a00e97387424a9a2d8">TIM3_IRQn</a> = 29, </div>
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<div class="line"><a name="l00282"></a><span class="lineno"> 282</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a368b899ca740b9ae0d75841f3abf68c4">TIM4_IRQn</a> = 30, </div>
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<div class="line"><a name="l00283"></a><span class="lineno"> 283</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9852dbbe8c014e716ce7e03a7b809751">I2C1_EV_IRQn</a> = 31, </div>
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<div class="line"><a name="l00284"></a><span class="lineno"> 284</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a2ec363869f4488782dc10a60abce3b34">I2C1_ER_IRQn</a> = 32, </div>
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<div class="line"><a name="l00285"></a><span class="lineno"> 285</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3020193786527c47d2e4d8c92ceee804">I2C2_EV_IRQn</a> = 33, </div>
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<div class="line"><a name="l00286"></a><span class="lineno"> 286</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a60c35f2d48d512bd6818bc9fef7053d7">I2C2_ER_IRQn</a> = 34, </div>
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<div class="line"><a name="l00287"></a><span class="lineno"> 287</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aacdff1a9c42582ed663214cbe62c1174">SPI1_IRQn</a> = 35, </div>
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<div class="line"><a name="l00288"></a><span class="lineno"> 288</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a505fbd4ccf7c2a14c8b76dc9e58f7ede">SPI2_IRQn</a> = 36, </div>
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<div class="line"><a name="l00289"></a><span class="lineno"> 289</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ad97cb163e1f678367e37c50d54d161ab">USART1_IRQn</a> = 37, </div>
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<div class="line"><a name="l00290"></a><span class="lineno"> 290</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3f9c48714d0e5baaba6613343f0da68e">USART2_IRQn</a> = 38, </div>
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<div class="line"><a name="l00291"></a><span class="lineno"> 291</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083afb13802afc1f5fdf5c90e73ee99e5ff3">USART3_IRQn</a> = 39, </div>
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<div class="line"><a name="l00292"></a><span class="lineno"> 292</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9fb0ad0c850234d1983fafdb17378e2f">EXTI15_10_IRQn</a> = 40, </div>
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<div class="line"><a name="l00293"></a><span class="lineno"> 293</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083afe09d6563a21a1540f658163a76a3b37">RTC_Alarm_IRQn</a> = 41, </div>
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<div class="line"><a name="l00294"></a><span class="lineno"> 294</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa612f35c4440359c35acbaa3c1458c5f">OTG_FS_WKUP_IRQn</a> = 42, </div>
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<div class="line"><a name="l00295"></a><span class="lineno"> 295</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3e01328006d19f7d32354271b9f61dce">TIM8_BRK_TIM12_IRQn</a> = 43, </div>
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<div class="line"><a name="l00296"></a><span class="lineno"> 296</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa8d8f67a98f24de6f0b36ad6b1f29a7d">TIM8_UP_TIM13_IRQn</a> = 44, </div>
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<div class="line"><a name="l00297"></a><span class="lineno"> 297</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ae252b31c3a341acbe9a467e243137307">TIM8_TRG_COM_TIM14_IRQn</a> = 45, </div>
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<div class="line"><a name="l00298"></a><span class="lineno"> 298</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a637750639eff4e2b4aae80ed6f3cf67f">TIM8_CC_IRQn</a> = 46, </div>
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<div class="line"><a name="l00299"></a><span class="lineno"> 299</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aedaa9c14e7e5fa9c0dcbb0c2455546e8">DMA1_Stream7_IRQn</a> = 47, </div>
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<div class="line"><a name="l00300"></a><span class="lineno"> 300</span>  FMC_IRQn = 48, </div>
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<div class="line"><a name="l00301"></a><span class="lineno"> 301</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a16fe70a39348f3f27906dc268b5654e3">SDIO_IRQn</a> = 49, </div>
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<div class="line"><a name="l00302"></a><span class="lineno"> 302</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aed2eb3f4bb721d55fcc1003125956645">TIM5_IRQn</a> = 50, </div>
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<div class="line"><a name="l00303"></a><span class="lineno"> 303</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a4e9331739fb76a2ca7781fede070ae44">SPI3_IRQn</a> = 51, </div>
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<div class="line"><a name="l00304"></a><span class="lineno"> 304</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aded5314b20c6e4e80cb6ab0668ffb8d5">UART4_IRQn</a> = 52, </div>
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<div class="line"><a name="l00305"></a><span class="lineno"> 305</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ac55a11a64aae7432544d0ab0d4f7de09">UART5_IRQn</a> = 53, </div>
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<div class="line"><a name="l00306"></a><span class="lineno"> 306</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a5f581e9aedfaccd9b1db9ec793804b45">TIM6_DAC_IRQn</a> = 54, </div>
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<div class="line"><a name="l00307"></a><span class="lineno"> 307</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a53cadc1e164ec85d0ea4cd143608e8e1">TIM7_IRQn</a> = 55, </div>
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<div class="line"><a name="l00308"></a><span class="lineno"> 308</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a1e5055722630fd4b12aff421964c2ebb">DMA2_Stream0_IRQn</a> = 56, </div>
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<div class="line"><a name="l00309"></a><span class="lineno"> 309</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a98abb3f02c1feb3831706bc1b82307cb">DMA2_Stream1_IRQn</a> = 57, </div>
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<div class="line"><a name="l00310"></a><span class="lineno"> 310</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083abf5e189f3ac7aad9f65e65ea5a0f3b36">DMA2_Stream2_IRQn</a> = 58, </div>
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<div class="line"><a name="l00311"></a><span class="lineno"> 311</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3ff8f3439f509e6e985eb960e63e1be4">DMA2_Stream3_IRQn</a> = 59, </div>
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<div class="line"><a name="l00312"></a><span class="lineno"> 312</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ae54eb8b30273b38a0576f75aba24eec0">DMA2_Stream4_IRQn</a> = 60, </div>
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<div class="line"><a name="l00313"></a><span class="lineno"> 313</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ad71328dd95461b7c55b568cf25966f6a">ETH_IRQn</a> = 61, </div>
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<div class="line"><a name="l00314"></a><span class="lineno"> 314</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a0485578005e12c2e2c0fb253a844ec6f">ETH_WKUP_IRQn</a> = 62, </div>
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<div class="line"><a name="l00315"></a><span class="lineno"> 315</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af6b8fbc990ac71c8425647bb684788a4">CAN2_TX_IRQn</a> = 63, </div>
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<div class="line"><a name="l00316"></a><span class="lineno"> 316</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a851fd2f2ab1418710e7da80e1bdf348a">CAN2_RX0_IRQn</a> = 64, </div>
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<div class="line"><a name="l00317"></a><span class="lineno"> 317</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab5023ff845be31a488ab63a0b8cf2b7a">CAN2_RX1_IRQn</a> = 65, </div>
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<div class="line"><a name="l00318"></a><span class="lineno"> 318</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a56c0b5758f26f31494e74aab9273f9fd">CAN2_SCE_IRQn</a> = 66, </div>
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<div class="line"><a name="l00319"></a><span class="lineno"> 319</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa60a30b7ef03446a46fd72e084911f7e">OTG_FS_IRQn</a> = 67, </div>
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<div class="line"><a name="l00320"></a><span class="lineno"> 320</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a933d4686213973abc01845a3da1c8a03">DMA2_Stream5_IRQn</a> = 68, </div>
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<div class="line"><a name="l00321"></a><span class="lineno"> 321</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a21570761ad0b5ed751adc831691b7800">DMA2_Stream6_IRQn</a> = 69, </div>
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<div class="line"><a name="l00322"></a><span class="lineno"> 322</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3d4cc0cd9b4d71e7ee002c4f8c1f8a77">DMA2_Stream7_IRQn</a> = 70, </div>
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<div class="line"><a name="l00323"></a><span class="lineno"> 323</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa92bcb2bc3a87be869f05c5b07f04b8c">USART6_IRQn</a> = 71, </div>
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<div class="line"><a name="l00324"></a><span class="lineno"> 324</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a8326db2d570cb865ffa1d49fa29d562a">I2C3_EV_IRQn</a> = 72, </div>
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<div class="line"><a name="l00325"></a><span class="lineno"> 325</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a6e954232d164a6942ebc7a6bd6f7736e">I2C3_ER_IRQn</a> = 73, </div>
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<div class="line"><a name="l00326"></a><span class="lineno"> 326</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a60b6cc4b6dbeca39e29a475d26c9e080">OTG_HS_EP1_OUT_IRQn</a> = 74, </div>
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<div class="line"><a name="l00327"></a><span class="lineno"> 327</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a1b040a7f76278a73cf5ea4c51f1be047">OTG_HS_EP1_IN_IRQn</a> = 75, </div>
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<div class="line"><a name="l00328"></a><span class="lineno"> 328</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9e5c9d81dd3985a88094f8158c0f0267">OTG_HS_WKUP_IRQn</a> = 76, </div>
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<div class="line"><a name="l00329"></a><span class="lineno"> 329</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aad2d5e47d27fe3a02f7059b20bb729c0">OTG_HS_IRQn</a> = 77, </div>
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<div class="line"><a name="l00330"></a><span class="lineno"> 330</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ace3c0fc2c4d05a7c02e3c987da5bc8e8">DCMI_IRQn</a> = 78, </div>
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<div class="line"><a name="l00331"></a><span class="lineno"> 331</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a70c9645bf48ca539510cc8f7d974f017">CRYP_IRQn</a> = 79, </div>
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<div class="line"><a name="l00332"></a><span class="lineno"> 332</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a86a161642b54055f9bbea3937e6352de">HASH_RNG_IRQn</a> = 80, </div>
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<div class="line"><a name="l00333"></a><span class="lineno"> 333</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa6b8ff01b016a798c6e639728c179e4f">FPU_IRQn</a> = 81, </div>
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<div class="line"><a name="l00334"></a><span class="lineno"> 334</span>  UART7_IRQn = 82, </div>
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<div class="line"><a name="l00335"></a><span class="lineno"> 335</span>  UART8_IRQn = 83, </div>
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<div class="line"><a name="l00336"></a><span class="lineno"> 336</span>  SPI4_IRQn = 84, </div>
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<div class="line"><a name="l00337"></a><span class="lineno"> 337</span>  SPI5_IRQn = 85, </div>
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<div class="line"><a name="l00338"></a><span class="lineno"> 338</span>  SPI6_IRQn = 86, </div>
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<div class="line"><a name="l00339"></a><span class="lineno"> 339</span>  SAI1_IRQn = 87, </div>
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<div class="line"><a name="l00340"></a><span class="lineno"> 340</span>  DMA2D_IRQn = 90 </div>
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<div class="line"><a name="l00341"></a><span class="lineno"> 341</span> <span class="preprocessor">#endif </span><span class="comment">/* STM32F427_437xx */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00342"></a><span class="lineno"> 342</span>  </div>
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<div class="line"><a name="l00343"></a><span class="lineno"> 343</span> <span class="preprocessor">#if defined (STM32F429_439xx)</span></div>
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<div class="line"><a name="l00344"></a><span class="lineno"> 344</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9ceb5175f7c10cf436955173c2246877">CAN1_TX_IRQn</a> = 19, </div>
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<div class="line"><a name="l00345"></a><span class="lineno"> 345</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab6bf73ac43a9856b3f2759a59f3d25b5">CAN1_RX0_IRQn</a> = 20, </div>
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<div class="line"><a name="l00346"></a><span class="lineno"> 346</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af71ef06c4f9ff0e1691c21ff3670acd4">CAN1_RX1_IRQn</a> = 21, </div>
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<div class="line"><a name="l00347"></a><span class="lineno"> 347</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a0f5f129d88a5606a378811e43039e274">CAN1_SCE_IRQn</a> = 22, </div>
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<div class="line"><a name="l00348"></a><span class="lineno"> 348</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa3aa50e0353871985facf62d055faa52">EXTI9_5_IRQn</a> = 23, </div>
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<div class="line"><a name="l00349"></a><span class="lineno"> 349</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab35b4ce63cfb11453f84a3695c6df368">TIM1_BRK_TIM9_IRQn</a> = 24, </div>
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<div class="line"><a name="l00350"></a><span class="lineno"> 350</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa3879e49013035601e17f83a51e0829f">TIM1_UP_TIM10_IRQn</a> = 25, </div>
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<div class="line"><a name="l00351"></a><span class="lineno"> 351</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab1a744bdceb8eface6ff57dd036e608e">TIM1_TRG_COM_TIM11_IRQn</a> = 26, </div>
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<div class="line"><a name="l00352"></a><span class="lineno"> 352</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af312f0a21f600f9b286427e50c549ca9">TIM1_CC_IRQn</a> = 27, </div>
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<div class="line"><a name="l00353"></a><span class="lineno"> 353</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3a4e2095a926e4095d3c846eb1c98afa">TIM2_IRQn</a> = 28, </div>
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<div class="line"><a name="l00354"></a><span class="lineno"> 354</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a985574288f66e2a00e97387424a9a2d8">TIM3_IRQn</a> = 29, </div>
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<div class="line"><a name="l00355"></a><span class="lineno"> 355</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a368b899ca740b9ae0d75841f3abf68c4">TIM4_IRQn</a> = 30, </div>
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<div class="line"><a name="l00356"></a><span class="lineno"> 356</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9852dbbe8c014e716ce7e03a7b809751">I2C1_EV_IRQn</a> = 31, </div>
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<div class="line"><a name="l00357"></a><span class="lineno"> 357</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a2ec363869f4488782dc10a60abce3b34">I2C1_ER_IRQn</a> = 32, </div>
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<div class="line"><a name="l00358"></a><span class="lineno"> 358</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3020193786527c47d2e4d8c92ceee804">I2C2_EV_IRQn</a> = 33, </div>
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<div class="line"><a name="l00359"></a><span class="lineno"> 359</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a60c35f2d48d512bd6818bc9fef7053d7">I2C2_ER_IRQn</a> = 34, </div>
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<div class="line"><a name="l00360"></a><span class="lineno"> 360</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aacdff1a9c42582ed663214cbe62c1174">SPI1_IRQn</a> = 35, </div>
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<div class="line"><a name="l00361"></a><span class="lineno"> 361</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a505fbd4ccf7c2a14c8b76dc9e58f7ede">SPI2_IRQn</a> = 36, </div>
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<div class="line"><a name="l00362"></a><span class="lineno"> 362</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ad97cb163e1f678367e37c50d54d161ab">USART1_IRQn</a> = 37, </div>
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<div class="line"><a name="l00363"></a><span class="lineno"> 363</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3f9c48714d0e5baaba6613343f0da68e">USART2_IRQn</a> = 38, </div>
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<div class="line"><a name="l00364"></a><span class="lineno"> 364</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083afb13802afc1f5fdf5c90e73ee99e5ff3">USART3_IRQn</a> = 39, </div>
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<div class="line"><a name="l00365"></a><span class="lineno"> 365</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9fb0ad0c850234d1983fafdb17378e2f">EXTI15_10_IRQn</a> = 40, </div>
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<div class="line"><a name="l00366"></a><span class="lineno"> 366</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083afe09d6563a21a1540f658163a76a3b37">RTC_Alarm_IRQn</a> = 41, </div>
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<div class="line"><a name="l00367"></a><span class="lineno"> 367</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa612f35c4440359c35acbaa3c1458c5f">OTG_FS_WKUP_IRQn</a> = 42, </div>
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<div class="line"><a name="l00368"></a><span class="lineno"> 368</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3e01328006d19f7d32354271b9f61dce">TIM8_BRK_TIM12_IRQn</a> = 43, </div>
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<div class="line"><a name="l00369"></a><span class="lineno"> 369</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa8d8f67a98f24de6f0b36ad6b1f29a7d">TIM8_UP_TIM13_IRQn</a> = 44, </div>
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<div class="line"><a name="l00370"></a><span class="lineno"> 370</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ae252b31c3a341acbe9a467e243137307">TIM8_TRG_COM_TIM14_IRQn</a> = 45, </div>
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<div class="line"><a name="l00371"></a><span class="lineno"> 371</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a637750639eff4e2b4aae80ed6f3cf67f">TIM8_CC_IRQn</a> = 46, </div>
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<div class="line"><a name="l00372"></a><span class="lineno"> 372</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aedaa9c14e7e5fa9c0dcbb0c2455546e8">DMA1_Stream7_IRQn</a> = 47, </div>
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<div class="line"><a name="l00373"></a><span class="lineno"> 373</span>  FMC_IRQn = 48, </div>
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<div class="line"><a name="l00374"></a><span class="lineno"> 374</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a16fe70a39348f3f27906dc268b5654e3">SDIO_IRQn</a> = 49, </div>
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<div class="line"><a name="l00375"></a><span class="lineno"> 375</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aed2eb3f4bb721d55fcc1003125956645">TIM5_IRQn</a> = 50, </div>
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<div class="line"><a name="l00376"></a><span class="lineno"> 376</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a4e9331739fb76a2ca7781fede070ae44">SPI3_IRQn</a> = 51, </div>
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<div class="line"><a name="l00377"></a><span class="lineno"> 377</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aded5314b20c6e4e80cb6ab0668ffb8d5">UART4_IRQn</a> = 52, </div>
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<div class="line"><a name="l00378"></a><span class="lineno"> 378</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ac55a11a64aae7432544d0ab0d4f7de09">UART5_IRQn</a> = 53, </div>
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<div class="line"><a name="l00379"></a><span class="lineno"> 379</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a5f581e9aedfaccd9b1db9ec793804b45">TIM6_DAC_IRQn</a> = 54, </div>
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<div class="line"><a name="l00380"></a><span class="lineno"> 380</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a53cadc1e164ec85d0ea4cd143608e8e1">TIM7_IRQn</a> = 55, </div>
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<div class="line"><a name="l00381"></a><span class="lineno"> 381</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a1e5055722630fd4b12aff421964c2ebb">DMA2_Stream0_IRQn</a> = 56, </div>
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<div class="line"><a name="l00382"></a><span class="lineno"> 382</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a98abb3f02c1feb3831706bc1b82307cb">DMA2_Stream1_IRQn</a> = 57, </div>
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<div class="line"><a name="l00383"></a><span class="lineno"> 383</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083abf5e189f3ac7aad9f65e65ea5a0f3b36">DMA2_Stream2_IRQn</a> = 58, </div>
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<div class="line"><a name="l00384"></a><span class="lineno"> 384</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3ff8f3439f509e6e985eb960e63e1be4">DMA2_Stream3_IRQn</a> = 59, </div>
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<div class="line"><a name="l00385"></a><span class="lineno"> 385</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ae54eb8b30273b38a0576f75aba24eec0">DMA2_Stream4_IRQn</a> = 60, </div>
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<div class="line"><a name="l00386"></a><span class="lineno"> 386</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ad71328dd95461b7c55b568cf25966f6a">ETH_IRQn</a> = 61, </div>
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<div class="line"><a name="l00387"></a><span class="lineno"> 387</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a0485578005e12c2e2c0fb253a844ec6f">ETH_WKUP_IRQn</a> = 62, </div>
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<div class="line"><a name="l00388"></a><span class="lineno"> 388</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af6b8fbc990ac71c8425647bb684788a4">CAN2_TX_IRQn</a> = 63, </div>
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<div class="line"><a name="l00389"></a><span class="lineno"> 389</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a851fd2f2ab1418710e7da80e1bdf348a">CAN2_RX0_IRQn</a> = 64, </div>
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<div class="line"><a name="l00390"></a><span class="lineno"> 390</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab5023ff845be31a488ab63a0b8cf2b7a">CAN2_RX1_IRQn</a> = 65, </div>
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<div class="line"><a name="l00391"></a><span class="lineno"> 391</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a56c0b5758f26f31494e74aab9273f9fd">CAN2_SCE_IRQn</a> = 66, </div>
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<div class="line"><a name="l00392"></a><span class="lineno"> 392</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa60a30b7ef03446a46fd72e084911f7e">OTG_FS_IRQn</a> = 67, </div>
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<div class="line"><a name="l00393"></a><span class="lineno"> 393</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a933d4686213973abc01845a3da1c8a03">DMA2_Stream5_IRQn</a> = 68, </div>
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<div class="line"><a name="l00394"></a><span class="lineno"> 394</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a21570761ad0b5ed751adc831691b7800">DMA2_Stream6_IRQn</a> = 69, </div>
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<div class="line"><a name="l00395"></a><span class="lineno"> 395</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3d4cc0cd9b4d71e7ee002c4f8c1f8a77">DMA2_Stream7_IRQn</a> = 70, </div>
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<div class="line"><a name="l00396"></a><span class="lineno"> 396</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa92bcb2bc3a87be869f05c5b07f04b8c">USART6_IRQn</a> = 71, </div>
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<div class="line"><a name="l00397"></a><span class="lineno"> 397</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a8326db2d570cb865ffa1d49fa29d562a">I2C3_EV_IRQn</a> = 72, </div>
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<div class="line"><a name="l00398"></a><span class="lineno"> 398</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a6e954232d164a6942ebc7a6bd6f7736e">I2C3_ER_IRQn</a> = 73, </div>
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<div class="line"><a name="l00399"></a><span class="lineno"> 399</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a60b6cc4b6dbeca39e29a475d26c9e080">OTG_HS_EP1_OUT_IRQn</a> = 74, </div>
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<div class="line"><a name="l00400"></a><span class="lineno"> 400</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a1b040a7f76278a73cf5ea4c51f1be047">OTG_HS_EP1_IN_IRQn</a> = 75, </div>
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<div class="line"><a name="l00401"></a><span class="lineno"> 401</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9e5c9d81dd3985a88094f8158c0f0267">OTG_HS_WKUP_IRQn</a> = 76, </div>
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<div class="line"><a name="l00402"></a><span class="lineno"> 402</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aad2d5e47d27fe3a02f7059b20bb729c0">OTG_HS_IRQn</a> = 77, </div>
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<div class="line"><a name="l00403"></a><span class="lineno"> 403</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ace3c0fc2c4d05a7c02e3c987da5bc8e8">DCMI_IRQn</a> = 78, </div>
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<div class="line"><a name="l00404"></a><span class="lineno"> 404</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a70c9645bf48ca539510cc8f7d974f017">CRYP_IRQn</a> = 79, </div>
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<div class="line"><a name="l00405"></a><span class="lineno"> 405</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a86a161642b54055f9bbea3937e6352de">HASH_RNG_IRQn</a> = 80, </div>
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<div class="line"><a name="l00406"></a><span class="lineno"> 406</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa6b8ff01b016a798c6e639728c179e4f">FPU_IRQn</a> = 81, </div>
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<div class="line"><a name="l00407"></a><span class="lineno"> 407</span>  UART7_IRQn = 82, </div>
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<div class="line"><a name="l00408"></a><span class="lineno"> 408</span>  UART8_IRQn = 83, </div>
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<div class="line"><a name="l00409"></a><span class="lineno"> 409</span>  SPI4_IRQn = 84, </div>
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<div class="line"><a name="l00410"></a><span class="lineno"> 410</span>  SPI5_IRQn = 85, </div>
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<div class="line"><a name="l00411"></a><span class="lineno"> 411</span>  SPI6_IRQn = 86, </div>
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<div class="line"><a name="l00412"></a><span class="lineno"> 412</span>  SAI1_IRQn = 87, </div>
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<div class="line"><a name="l00413"></a><span class="lineno"> 413</span>  LTDC_IRQn = 88, </div>
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<div class="line"><a name="l00414"></a><span class="lineno"> 414</span>  LTDC_ER_IRQn = 89, </div>
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<div class="line"><a name="l00415"></a><span class="lineno"> 415</span>  DMA2D_IRQn = 90 </div>
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<div class="line"><a name="l00416"></a><span class="lineno"> 416</span> <span class="preprocessor">#endif </span><span class="comment">/* STM32F429_439xx */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00417"></a><span class="lineno"> 417</span>  </div>
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<div class="line"><a name="l00418"></a><span class="lineno"> 418</span> <span class="preprocessor">#if defined (STM32F401xx) || defined (STM32F411xE)</span></div>
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<div class="line"><a name="l00419"></a><span class="lineno"> 419</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa3aa50e0353871985facf62d055faa52">EXTI9_5_IRQn</a> = 23, </div>
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<div class="line"><a name="l00420"></a><span class="lineno"> 420</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab35b4ce63cfb11453f84a3695c6df368">TIM1_BRK_TIM9_IRQn</a> = 24, </div>
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<div class="line"><a name="l00421"></a><span class="lineno"> 421</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa3879e49013035601e17f83a51e0829f">TIM1_UP_TIM10_IRQn</a> = 25, </div>
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<div class="line"><a name="l00422"></a><span class="lineno"> 422</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab1a744bdceb8eface6ff57dd036e608e">TIM1_TRG_COM_TIM11_IRQn</a> = 26, </div>
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<div class="line"><a name="l00423"></a><span class="lineno"> 423</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af312f0a21f600f9b286427e50c549ca9">TIM1_CC_IRQn</a> = 27, </div>
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<div class="line"><a name="l00424"></a><span class="lineno"> 424</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3a4e2095a926e4095d3c846eb1c98afa">TIM2_IRQn</a> = 28, </div>
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<div class="line"><a name="l00425"></a><span class="lineno"> 425</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a985574288f66e2a00e97387424a9a2d8">TIM3_IRQn</a> = 29, </div>
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<div class="line"><a name="l00426"></a><span class="lineno"> 426</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a368b899ca740b9ae0d75841f3abf68c4">TIM4_IRQn</a> = 30, </div>
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<div class="line"><a name="l00427"></a><span class="lineno"> 427</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9852dbbe8c014e716ce7e03a7b809751">I2C1_EV_IRQn</a> = 31, </div>
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<div class="line"><a name="l00428"></a><span class="lineno"> 428</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a2ec363869f4488782dc10a60abce3b34">I2C1_ER_IRQn</a> = 32, </div>
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<div class="line"><a name="l00429"></a><span class="lineno"> 429</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3020193786527c47d2e4d8c92ceee804">I2C2_EV_IRQn</a> = 33, </div>
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<div class="line"><a name="l00430"></a><span class="lineno"> 430</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a60c35f2d48d512bd6818bc9fef7053d7">I2C2_ER_IRQn</a> = 34, </div>
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<div class="line"><a name="l00431"></a><span class="lineno"> 431</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aacdff1a9c42582ed663214cbe62c1174">SPI1_IRQn</a> = 35, </div>
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<div class="line"><a name="l00432"></a><span class="lineno"> 432</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a505fbd4ccf7c2a14c8b76dc9e58f7ede">SPI2_IRQn</a> = 36, </div>
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<div class="line"><a name="l00433"></a><span class="lineno"> 433</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ad97cb163e1f678367e37c50d54d161ab">USART1_IRQn</a> = 37, </div>
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<div class="line"><a name="l00434"></a><span class="lineno"> 434</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3f9c48714d0e5baaba6613343f0da68e">USART2_IRQn</a> = 38, </div>
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<div class="line"><a name="l00435"></a><span class="lineno"> 435</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9fb0ad0c850234d1983fafdb17378e2f">EXTI15_10_IRQn</a> = 40, </div>
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<div class="line"><a name="l00436"></a><span class="lineno"> 436</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083afe09d6563a21a1540f658163a76a3b37">RTC_Alarm_IRQn</a> = 41, </div>
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<div class="line"><a name="l00437"></a><span class="lineno"> 437</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa612f35c4440359c35acbaa3c1458c5f">OTG_FS_WKUP_IRQn</a> = 42, </div>
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<div class="line"><a name="l00438"></a><span class="lineno"> 438</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aedaa9c14e7e5fa9c0dcbb0c2455546e8">DMA1_Stream7_IRQn</a> = 47, </div>
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<div class="line"><a name="l00439"></a><span class="lineno"> 439</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a16fe70a39348f3f27906dc268b5654e3">SDIO_IRQn</a> = 49, </div>
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<div class="line"><a name="l00440"></a><span class="lineno"> 440</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aed2eb3f4bb721d55fcc1003125956645">TIM5_IRQn</a> = 50, </div>
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<div class="line"><a name="l00441"></a><span class="lineno"> 441</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a4e9331739fb76a2ca7781fede070ae44">SPI3_IRQn</a> = 51, </div>
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<div class="line"><a name="l00442"></a><span class="lineno"> 442</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a1e5055722630fd4b12aff421964c2ebb">DMA2_Stream0_IRQn</a> = 56, </div>
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<div class="line"><a name="l00443"></a><span class="lineno"> 443</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a98abb3f02c1feb3831706bc1b82307cb">DMA2_Stream1_IRQn</a> = 57, </div>
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<div class="line"><a name="l00444"></a><span class="lineno"> 444</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083abf5e189f3ac7aad9f65e65ea5a0f3b36">DMA2_Stream2_IRQn</a> = 58, </div>
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<div class="line"><a name="l00445"></a><span class="lineno"> 445</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3ff8f3439f509e6e985eb960e63e1be4">DMA2_Stream3_IRQn</a> = 59, </div>
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<div class="line"><a name="l00446"></a><span class="lineno"> 446</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ae54eb8b30273b38a0576f75aba24eec0">DMA2_Stream4_IRQn</a> = 60, </div>
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<div class="line"><a name="l00447"></a><span class="lineno"> 447</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa60a30b7ef03446a46fd72e084911f7e">OTG_FS_IRQn</a> = 67, </div>
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<div class="line"><a name="l00448"></a><span class="lineno"> 448</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a933d4686213973abc01845a3da1c8a03">DMA2_Stream5_IRQn</a> = 68, </div>
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<div class="line"><a name="l00449"></a><span class="lineno"> 449</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a21570761ad0b5ed751adc831691b7800">DMA2_Stream6_IRQn</a> = 69, </div>
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<div class="line"><a name="l00450"></a><span class="lineno"> 450</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3d4cc0cd9b4d71e7ee002c4f8c1f8a77">DMA2_Stream7_IRQn</a> = 70, </div>
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<div class="line"><a name="l00451"></a><span class="lineno"> 451</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa92bcb2bc3a87be869f05c5b07f04b8c">USART6_IRQn</a> = 71, </div>
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<div class="line"><a name="l00452"></a><span class="lineno"> 452</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a8326db2d570cb865ffa1d49fa29d562a">I2C3_EV_IRQn</a> = 72, </div>
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<div class="line"><a name="l00453"></a><span class="lineno"> 453</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a6e954232d164a6942ebc7a6bd6f7736e">I2C3_ER_IRQn</a> = 73, </div>
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<div class="line"><a name="l00454"></a><span class="lineno"> 454</span>  <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa6b8ff01b016a798c6e639728c179e4f">FPU_IRQn</a> = 81, </div>
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<div class="line"><a name="l00455"></a><span class="lineno"> 455</span> <span class="preprocessor">#if defined (STM32F401xx)</span></div>
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<div class="line"><a name="l00456"></a><span class="lineno"> 456</span>  SPI4_IRQn = 84 </div>
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<div class="line"><a name="l00457"></a><span class="lineno"> 457</span> <span class="preprocessor">#endif </span><span class="comment">/* STM32F411xE */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00458"></a><span class="lineno"> 458</span> <span class="preprocessor">#if defined (STM32F411xE)</span></div>
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<div class="line"><a name="l00459"></a><span class="lineno"> 459</span>  SPI4_IRQn = 84, </div>
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<div class="line"><a name="l00460"></a><span class="lineno"> 460</span>  SPI5_IRQn = 85 </div>
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<div class="line"><a name="l00461"></a><span class="lineno"> 461</span> <span class="preprocessor">#endif </span><span class="comment">/* STM32F411xE */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00462"></a><span class="lineno"> 462</span> <span class="preprocessor">#endif </span><span class="comment">/* STM32F401xx || STM32F411xE */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00463"></a><span class="lineno"> 463</span> </div>
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<div class="line"><a name="l00464"></a><span class="lineno"> 464</span> } <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gac3af4a32370fb28c4ade8bf2add80251">IRQn_Type</a>;</div>
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<div class="line"><a name="l00465"></a><span class="lineno"> 465</span> </div>
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<div class="line"><a name="l00470"></a><span class="lineno"> 470</span> <span class="preprocessor">#include "<a class="code" href="core__cm4_8h.html">core_cm4.h</a>"</span> <span class="comment">/* Cortex-M4 processor and core peripherals */</span></div>
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<div class="line"><a name="l00471"></a><span class="lineno"> 471</span> <span class="preprocessor">#include "<a class="code" href="system__stm32f4xx_8h.html">system_stm32f4xx.h</a>"</span></div>
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<div class="line"><a name="l00472"></a><span class="lineno"> 472</span> <span class="preprocessor">#include <stdint.h></span></div>
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<div class="line"><a name="l00473"></a><span class="lineno"> 473</span> </div>
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<div class="line"><a name="l00478"></a><span class="lineno"> 478</span> <span class="keyword">typedef</span> int32_t <a class="code" href="group___exported__types.html#gae9b1af5c037e57a98884758875d3a7c4">s32</a>;</div>
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<div class="line"><a name="l00479"></a><span class="lineno"> 479</span> <span class="keyword">typedef</span> int16_t s16;</div>
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<div class="line"><a name="l00480"></a><span class="lineno"><a class="line" href="group___exported__types.html#gae9b1af5c037e57a98884758875d3a7c4"> 480</a></span> <span class="keyword">typedef</span> int8_t s8;</div>
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<div class="line"><a name="l00481"></a><span class="lineno"> 481</span> </div>
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<div class="line"><a name="l00482"></a><span class="lineno"> 482</span> <span class="keyword">typedef</span> <span class="keyword">const</span> int32_t <a class="code" href="group___exported__types.html#gad97679599f3791409523fdb1c6156a28">sc32</a>; </div>
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<div class="line"><a name="l00483"></a><span class="lineno"> 483</span> <span class="keyword">typedef</span> <span class="keyword">const</span> int16_t <a class="code" href="group___exported__types.html#ga66ab742a0751bb4e7661b8e874f2ddda">sc16</a>; </div>
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<div class="line"><a name="l00484"></a><span class="lineno"><a class="line" href="group___exported__types.html#gad97679599f3791409523fdb1c6156a28"> 484</a></span> <span class="keyword">typedef</span> <span class="keyword">const</span> int8_t <a class="code" href="group___exported__types.html#ga30e6c0f6718e1b6d26dc9d94ddcf9d11">sc8</a>; </div>
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<div class="line"><a name="l00486"></a><span class="lineno"><a class="line" href="group___exported__types.html#ga30e6c0f6718e1b6d26dc9d94ddcf9d11"> 486</a></span> <span class="keyword">typedef</span> <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> int32_t vs32;</div>
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<div class="line"><a name="l00487"></a><span class="lineno"> 487</span> <span class="keyword">typedef</span> <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> int16_t vs16;</div>
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<div class="line"><a name="l00488"></a><span class="lineno"> 488</span> <span class="keyword">typedef</span> <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> int8_t vs8;</div>
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<div class="line"><a name="l00489"></a><span class="lineno"> 489</span> </div>
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<div class="line"><a name="l00490"></a><span class="lineno"> 490</span> <span class="keyword">typedef</span> <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> int32_t <a class="code" href="group___exported__types.html#gaec1d22666cf030b79051e5daa372fbc8">vsc32</a>; </div>
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<div class="line"><a name="l00491"></a><span class="lineno"> 491</span> <span class="keyword">typedef</span> <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> int16_t <a class="code" href="group___exported__types.html#ga369ae0177b957e5afa7c1e62312f97c3">vsc16</a>; </div>
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<div class="line"><a name="l00492"></a><span class="lineno"><a class="line" href="group___exported__types.html#gaec1d22666cf030b79051e5daa372fbc8"> 492</a></span> <span class="keyword">typedef</span> <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> int8_t <a class="code" href="group___exported__types.html#ga47463bcded079ac61d5da46aff497803">vsc8</a>; </div>
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<div class="line"><a name="l00494"></a><span class="lineno"><a class="line" href="group___exported__types.html#ga47463bcded079ac61d5da46aff497803"> 494</a></span> <span class="keyword">typedef</span> uint32_t u32;</div>
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<div class="line"><a name="l00495"></a><span class="lineno"> 495</span> <span class="keyword">typedef</span> uint16_t u16;</div>
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<div class="line"><a name="l00496"></a><span class="lineno"> 496</span> <span class="keyword">typedef</span> uint8_t u8;</div>
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<div class="line"><a name="l00497"></a><span class="lineno"> 497</span> </div>
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<div class="line"><a name="l00498"></a><span class="lineno"> 498</span> <span class="keyword">typedef</span> <span class="keyword">const</span> uint32_t <a class="code" href="group___exported__types.html#ga5b628e6a05856ff67e535fa391a57683">uc32</a>; </div>
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<div class="line"><a name="l00499"></a><span class="lineno"> 499</span> <span class="keyword">typedef</span> <span class="keyword">const</span> uint16_t <a class="code" href="group___exported__types.html#gabc715ea3779494b5a4f53173a397f7cb">uc16</a>; </div>
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<div class="line"><a name="l00500"></a><span class="lineno"><a class="line" href="group___exported__types.html#ga5b628e6a05856ff67e535fa391a57683"> 500</a></span> <span class="keyword">typedef</span> <span class="keyword">const</span> uint8_t <a class="code" href="group___exported__types.html#gac74022c74a461f810e0d4fdc9bfea480">uc8</a>; </div>
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<div class="line"><a name="l00502"></a><span class="lineno"><a class="line" href="group___exported__types.html#gac74022c74a461f810e0d4fdc9bfea480"> 502</a></span> <span class="keyword">typedef</span> <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t vu32;</div>
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<div class="line"><a name="l00503"></a><span class="lineno"> 503</span> <span class="keyword">typedef</span> <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t vu16;</div>
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<div class="line"><a name="l00504"></a><span class="lineno"> 504</span> <span class="keyword">typedef</span> <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint8_t vu8;</div>
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<div class="line"><a name="l00505"></a><span class="lineno"> 505</span> </div>
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<div class="line"><a name="l00506"></a><span class="lineno"> 506</span> <span class="keyword">typedef</span> <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="group___exported__types.html#ga2e08e321a35a55e72c5b3a507e76371f">vuc32</a>; </div>
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<div class="line"><a name="l00507"></a><span class="lineno"> 507</span> <span class="keyword">typedef</span> <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint16_t <a class="code" href="group___exported__types.html#ga7f6037565f0caa27727c8b871daf0d56">vuc16</a>; </div>
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<div class="line"><a name="l00508"></a><span class="lineno"><a class="line" href="group___exported__types.html#ga2e08e321a35a55e72c5b3a507e76371f"> 508</a></span> <span class="keyword">typedef</span> <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint8_t <a class="code" href="group___exported__types.html#gab0ec90ac9b2c5864755998c8d37c264a">vuc8</a>; </div>
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<div class="line"><a name="l00510"></a><span class="lineno"><a class="line" href="group___exported__types.html#gab0ec90ac9b2c5864755998c8d37c264a"> 510</a></span> <span class="keyword">typedef</span> <span class="keyword">enum</span> {RESET = 0, SET = !RESET} FlagStatus, ITStatus;</div>
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<div class="line"><a name="l00511"></a><span class="lineno"> 511</span> </div>
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<div class="line"><a name="l00512"></a><span class="lineno"> 512</span> <span class="keyword">typedef</span> <span class="keyword">enum</span> {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;</div>
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<div class="line"><a name="l00513"></a><span class="lineno"> 513</span> <span class="preprocessor">#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))</span></div>
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<div class="line"><a name="l00514"></a><span class="lineno"> 514</span> </div>
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<div class="line"><a name="l00515"></a><span class="lineno"> 515</span> <span class="keyword">typedef</span> <span class="keyword">enum</span> {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;</div>
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<div class="line"><a name="l00516"></a><span class="lineno"> 516</span> </div>
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<div class="line"><a name="l00529"></a><span class="lineno"> 529</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00530"></a><span class="lineno"> 530</span> {</div>
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<div class="line"><a name="l00531"></a><span class="lineno"><a class="line" href="struct_a_d_c___type_def.html"> 531</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SR; </div>
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<div class="line"><a name="l00532"></a><span class="lineno"> 532</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CR1; </div>
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<div class="line"><a name="l00533"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga9745df96e98f3cdc2d05ccefce681f64"> 533</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CR2; </div>
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<div class="line"><a name="l00534"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga89b1ff4376683dd2896ea8b32ded05b2"> 534</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SMPR1; </div>
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<div class="line"><a name="l00535"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga1053a65a21af0d27afe1bf9cf7b7aca7"> 535</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SMPR2; </div>
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<div class="line"><a name="l00536"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga73009a8122fcc628f467a4e997109347"> 536</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t JOFR1; </div>
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<div class="line"><a name="l00537"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga9e68fe36c4c8fbbac294b5496ccf7130"> 537</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t JOFR2; </div>
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<div class="line"><a name="l00538"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaa005e656f528aaad28d70d61c9db9b81"> 538</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t JOFR3; </div>
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<div class="line"><a name="l00539"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaa20f76044c11042dde41c1060853fb82"> 539</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t JOFR4; </div>
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<div class="line"><a name="l00540"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gae9c78142f6edf8122384263878d09015"> 540</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t HTR; </div>
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<div class="line"><a name="l00541"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga92f5c1a5aaa8b286317f923482e09d35"> 541</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t LTR; </div>
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<div class="line"><a name="l00542"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga297ac2d83a1837bfdc0333474b977de0"> 542</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SQR1; </div>
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<div class="line"><a name="l00543"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gafdaf8050fb01739206a92c9ad610f396"> 543</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SQR2; </div>
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<div class="line"><a name="l00544"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga0185aa54962ba987f192154fb7a2d673"> 544</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SQR3; </div>
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<div class="line"><a name="l00545"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga6b6e55e6c667042e5a46a76518b73d5a"> 545</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t JSQR; </div>
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<div class="line"><a name="l00546"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga51dbdba74c4d3559157392109af68fc6"> 546</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t JDR1; </div>
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<div class="line"><a name="l00547"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga5438a76a93ac1bd2526e92ef298dc193"> 547</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t JDR2; </div>
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<div class="line"><a name="l00548"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gab4b0a79a9e4a9d5b0a24d7285cf55bdc"> 548</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t JDR3; </div>
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<div class="line"><a name="l00549"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga898b87cab4f099bcca981cc4c9318b51"> 549</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t JDR4; </div>
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<div class="line"><a name="l00550"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga40999cd0a255ef62b2340e2726695063"> 550</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DR; </div>
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<div class="line"><a name="l00551"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gabae6e9d688b16ef350878998f5e21c0b"> 551</a></span> } <a class="code" href="struct_a_d_c___type_def.html">ADC_TypeDef</a>;</div>
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<div class="line"><a name="l00552"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga84114accead82bd11a0e12a429cdfed9"> 552</a></span> </div>
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<div class="line"><a name="l00553"></a><span class="lineno"> 553</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00554"></a><span class="lineno"> 554</span> {</div>
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<div class="line"><a name="l00555"></a><span class="lineno"><a class="line" href="struct_a_d_c___common___type_def.html"> 555</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CSR; </div>
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<div class="line"><a name="l00556"></a><span class="lineno"> 556</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CCR; </div>
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<div class="line"><a name="l00557"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gac38e24f600f9e134a54a0c43b976a4f4"> 557</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CDR; </div>
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<div class="line"><a name="l00559"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga6f7399bf70f677ef5de46a3038f414e1"> 559</a></span> } <a class="code" href="struct_a_d_c___common___type_def.html">ADC_Common_TypeDef</a>;</div>
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<div class="line"><a name="l00560"></a><span class="lineno"> 560</span> </div>
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<div class="line"><a name="l00561"></a><span class="lineno"> 561</span> </div>
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<div class="line"><a name="l00566"></a><span class="lineno"> 566</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00567"></a><span class="lineno"> 567</span> {</div>
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<div class="line"><a name="l00568"></a><span class="lineno"><a class="line" href="struct_c_a_n___tx_mail_box___type_def.html"> 568</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t TIR; </div>
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<div class="line"><a name="l00569"></a><span class="lineno"> 569</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t TDTR; </div>
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<div class="line"><a name="l00570"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga22f525c909de2dcec1d4093fe1d562b8"> 570</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t TDLR; </div>
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<div class="line"><a name="l00571"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga2351cb865d064cf75f61642aaa887f76"> 571</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t TDHR; </div>
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<div class="line"><a name="l00572"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga408c96501b1cc8bd527432736d132a39"> 572</a></span> } <a class="code" href="struct_c_a_n___tx_mail_box___type_def.html">CAN_TxMailBox_TypeDef</a>;</div>
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<div class="line"><a name="l00573"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga98c6bcd7c9bae378ebf83fd9f5b59020"> 573</a></span> </div>
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<div class="line"><a name="l00578"></a><span class="lineno"> 578</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00579"></a><span class="lineno"> 579</span> {</div>
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<div class="line"><a name="l00580"></a><span class="lineno"><a class="line" href="struct_c_a_n___f_i_f_o_mail_box___type_def.html"> 580</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RIR; </div>
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<div class="line"><a name="l00581"></a><span class="lineno"> 581</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RDTR; </div>
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<div class="line"><a name="l00582"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga034504d43f7b16b320745a25b3a8f12d"> 582</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RDLR; </div>
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<div class="line"><a name="l00583"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga49d74ca8b402c2b9596bfcbe4cd051a9"> 583</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RDHR; </div>
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<div class="line"><a name="l00584"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gac7d62861de29d0b4fcf11fabbdbd76e7"> 584</a></span> } <a class="code" href="struct_c_a_n___f_i_f_o_mail_box___type_def.html">CAN_FIFOMailBox_TypeDef</a>;</div>
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<div class="line"><a name="l00585"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga95890984bd67845015d40e82fb091c93"> 585</a></span> </div>
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<div class="line"><a name="l00590"></a><span class="lineno"> 590</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00591"></a><span class="lineno"> 591</span> {</div>
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<div class="line"><a name="l00592"></a><span class="lineno"><a class="line" href="struct_c_a_n___filter_register___type_def.html"> 592</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t FR1; </div>
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<div class="line"><a name="l00593"></a><span class="lineno"> 593</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t FR2; </div>
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<div class="line"><a name="l00594"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gac9bc1e42212239d6830582bf0c696fc5"> 594</a></span> } <a class="code" href="struct_c_a_n___filter_register___type_def.html">CAN_FilterRegister_TypeDef</a>;</div>
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<div class="line"><a name="l00595"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga77959e28a302b05829f6a1463be7f800"> 595</a></span> </div>
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<div class="line"><a name="l00600"></a><span class="lineno"> 600</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00601"></a><span class="lineno"> 601</span> {</div>
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<div class="line"><a name="l00602"></a><span class="lineno"><a class="line" href="struct_c_a_n___type_def.html"> 602</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MCR; </div>
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<div class="line"><a name="l00603"></a><span class="lineno"> 603</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MSR; </div>
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<div class="line"><a name="l00604"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga1282eee79a22003257a7a5daa7f4a35f"> 604</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t TSR; </div>
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<div class="line"><a name="l00605"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaf98b957a4e887751fbd407d3e2cf93b5"> 605</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RF0R; </div>
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<div class="line"><a name="l00606"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gacbc82ac4e87e75350fc586be5e56d95b"> 606</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RF1R; </div>
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<div class="line"><a name="l00607"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gad8e858479e26ab075ee2ddb630e8769d"> 607</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t IER; </div>
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<div class="line"><a name="l00608"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga69a528d1288c1de666df68655af1d20e"> 608</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ESR; </div>
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<div class="line"><a name="l00609"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga530babbc4b9584c93a1bf87d6ce8b8dc"> 609</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BTR; </div>
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<div class="line"><a name="l00610"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gab1a1b6a7c587443a03d654d3b9a94423"> 610</a></span>  uint32_t RESERVED0[88]; </div>
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<div class="line"><a name="l00611"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaccad1e4155459a13369f5ad0e7c6da29"> 611</a></span>  <a class="code" href="struct_c_a_n___tx_mail_box___type_def.html">CAN_TxMailBox_TypeDef</a> sTxMailBox[3]; </div>
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<div class="line"><a name="l00612"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gad0cc7fb26376c435bbf148e962739337"> 612</a></span>  <a class="code" href="struct_c_a_n___f_i_f_o_mail_box___type_def.html">CAN_FIFOMailBox_TypeDef</a> sFIFOMailBox[2]; </div>
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<div class="line"><a name="l00613"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga328925e230f68a775f6f4ad1076c27ce"> 613</a></span>  uint32_t RESERVED1[12]; </div>
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<div class="line"><a name="l00614"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaa6053bc607535d9ecf7a3d887c0cc053"> 614</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t FMR; </div>
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<div class="line"><a name="l00615"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga046ef464378aaaaafaf999c23a4dc55e"> 615</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t FM1R; </div>
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<div class="line"><a name="l00616"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga1a6a0f78ca703a63bb0a6b6f231f612f"> 616</a></span>  uint32_t RESERVED2; </div>
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<div class="line"><a name="l00617"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaefe6a26ee25947b7eb5be9d485f4d3b0"> 617</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t FS1R; </div>
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<div class="line"><a name="l00618"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gab29069c9fd10eeec47414abd8d06822f"> 618</a></span>  uint32_t RESERVED3; </div>
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<div class="line"><a name="l00619"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gac6296402924b37966c67ccf14a381976"> 619</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t FFA1R; </div>
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<div class="line"><a name="l00620"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaf730af32307f845895465e8ead57d20c"> 620</a></span>  uint32_t RESERVED4; </div>
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<div class="line"><a name="l00621"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gae2decd14b26f851e00a31b42d15293ce"> 621</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t FA1R; </div>
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<div class="line"><a name="l00622"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga51c408c7c352b8080f0c6d42bf811d43"> 622</a></span>  uint32_t RESERVED5[8]; </div>
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<div class="line"><a name="l00623"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gab57a3a6c337a8c6c7cb39d0cefc2459a"> 623</a></span>  <a class="code" href="struct_c_a_n___filter_register___type_def.html">CAN_FilterRegister_TypeDef</a> sFilterRegister[28]; </div>
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<div class="line"><a name="l00624"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gad4339975b6064cfe2aaeb642f916d6e0"> 624</a></span> } <a class="code" href="struct_c_a_n___type_def.html">CAN_TypeDef</a>;</div>
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<div class="line"><a name="l00625"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga23a22b903fdc909ac9f61edd68029f35"> 625</a></span> </div>
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<div class="line"><a name="l00630"></a><span class="lineno"> 630</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00631"></a><span class="lineno"> 631</span> {</div>
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<div class="line"><a name="l00632"></a><span class="lineno"><a class="line" href="struct_c_r_c___type_def.html"> 632</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DR; </div>
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<div class="line"><a name="l00633"></a><span class="lineno"> 633</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint8_t IDR; </div>
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<div class="line"><a name="l00634"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga50cb22870dbb9001241cec694994e5ef"> 634</a></span>  uint8_t RESERVED0; </div>
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<div class="line"><a name="l00635"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gad84e8694cd4b5375ee533c2d875c3b5a"> 635</a></span>  uint16_t RESERVED1; </div>
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<div class="line"><a name="l00636"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga70dfd1730dba65041550ef55a44db87c"> 636</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CR; </div>
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<div class="line"><a name="l00637"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga8b205c6e25b1808ac016db2356b3021d"> 637</a></span> } <a class="code" href="struct_c_r_c___type_def.html">CRC_TypeDef</a>;</div>
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<div class="line"><a name="l00638"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaf33fa5c173e1c102e6d0242fe60e569f"> 638</a></span> </div>
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<div class="line"><a name="l00643"></a><span class="lineno"> 643</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00644"></a><span class="lineno"> 644</span> {</div>
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<div class="line"><a name="l00645"></a><span class="lineno"><a class="line" href="struct_d_a_c___type_def.html"> 645</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CR; </div>
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<div class="line"><a name="l00646"></a><span class="lineno"> 646</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SWTRIGR; </div>
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<div class="line"><a name="l00647"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga394324f0b573837ca15a87127b2a37ea"> 647</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DHR12R1; </div>
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<div class="line"><a name="l00648"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga4ccb66068a1ebee1179574dda20206b6"> 648</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DHR12L1; </div>
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<div class="line"><a name="l00649"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gafbfd2855cdb81939b4efc58e08aaf3e5"> 649</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DHR8R1; </div>
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<div class="line"><a name="l00650"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga5eb63912e39085e3e13d64bdb0cf38bd"> 650</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DHR12R2; </div>
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<div class="line"><a name="l00651"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga3a382d341fb608a04390bacb8c00b0f0"> 651</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DHR12L2; </div>
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<div class="line"><a name="l00652"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gab1f777540c487c26bf27e6fa37a644cc"> 652</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DHR8R2; </div>
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<div class="line"><a name="l00653"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga9f612b6b3e065e810e5a2fb254d6a40b"> 653</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DHR12RD; </div>
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<div class="line"><a name="l00654"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga3b096b71656f8fb32cd18b4c8b1d2334"> 654</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DHR12LD; </div>
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<div class="line"><a name="l00655"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaffa5cc9fe0cc9eb594d703bdc9d9abd9"> 655</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DHR8RD; </div>
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<div class="line"><a name="l00656"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaea4d055e3697999b44cdcf2702d79d40"> 656</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DOR1; </div>
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<div class="line"><a name="l00657"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga03f8d95bbf0ce3a53cb79506d5bf995a"> 657</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DOR2; </div>
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<div class="line"><a name="l00658"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga50b4f0b0d2a376f729c8d7acf47864c3"> 658</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SR; </div>
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<div class="line"><a name="l00659"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga1bde8391647d6422b39ab5ba4f13848b"> 659</a></span> } <a class="code" href="struct_d_a_c___type_def.html">DAC_TypeDef</a>;</div>
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<div class="line"><a name="l00660"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga1d3fd83d6ed8b2d90b471db4509b0e70"> 660</a></span> </div>
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<div class="line"><a name="l00665"></a><span class="lineno"> 665</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00666"></a><span class="lineno"> 666</span> {</div>
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<div class="line"><a name="l00667"></a><span class="lineno"><a class="line" href="struct_d_b_g_m_c_u___type_def.html"> 667</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t IDCODE; </div>
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<div class="line"><a name="l00668"></a><span class="lineno"> 668</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CR; </div>
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<div class="line"><a name="l00669"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga0cc3561c124d06bb57dfa855e43ed99f"> 669</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t APB1FZ; </div>
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<div class="line"><a name="l00670"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga15981828f2b915d38570cf6684e99a53"> 670</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t APB2FZ; </div>
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<div class="line"><a name="l00671"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaac341c7e09cd5224327eeb7d9f122bed"> 671</a></span> }<a class="code" href="struct_d_b_g_m_c_u___type_def.html">DBGMCU_TypeDef</a>;</div>
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<div class="line"><a name="l00672"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga011f892d86367dbe786964b14bc515a6"> 672</a></span> </div>
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<div class="line"><a name="l00677"></a><span class="lineno"> 677</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00678"></a><span class="lineno"> 678</span> {</div>
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<div class="line"><a name="l00679"></a><span class="lineno"><a class="line" href="struct_d_c_m_i___type_def.html"> 679</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CR; </div>
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<div class="line"><a name="l00680"></a><span class="lineno"> 680</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SR; </div>
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<div class="line"><a name="l00681"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga3cfcc9860ca551cbcb10c1c3dd4304f0"> 681</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RISR; </div>
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<div class="line"><a name="l00682"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga1bbe4b3cc5d9552526bec462b42164d5"> 682</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t IER; </div>
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<div class="line"><a name="l00683"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gae0aba9f38498cccbe0186b7813825026"> 683</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MISR; </div>
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<div class="line"><a name="l00684"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga91ce93b57d8382147574c678ee497c63"> 684</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ICR; </div>
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<div class="line"><a name="l00685"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gab367c4ca2e8ac87238692e6d55d622ec"> 685</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ESCR; </div>
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<div class="line"><a name="l00686"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga0371fc07916e3043e1151eaa97e172c9"> 686</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ESUR; </div>
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<div class="line"><a name="l00687"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga52c16b920a3f25fda961d0cd29749433"> 687</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CWSTRTR; </div>
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<div class="line"><a name="l00688"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaf00a94620e33f4eff74430ff25c12b94"> 688</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CWSIZER; </div>
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<div class="line"><a name="l00689"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga4d58830323e567117c12ae3feac613b9"> 689</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DR; </div>
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<div class="line"><a name="l00690"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga1b9c8048339e19b110ecfbea486f55df"> 690</a></span> } <a class="code" href="struct_d_c_m_i___type_def.html">DCMI_TypeDef</a>;</div>
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<div class="line"><a name="l00691"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga266cec1031b0be730b0e35523f5e2934"> 691</a></span> </div>
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<div class="line"><a name="l00696"></a><span class="lineno"> 696</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00697"></a><span class="lineno"> 697</span> {</div>
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<div class="line"><a name="l00698"></a><span class="lineno"><a class="line" href="struct_d_m_a___stream___type_def.html"> 698</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CR; </div>
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<div class="line"><a name="l00699"></a><span class="lineno"> 699</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t NDTR; </div>
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<div class="line"><a name="l00700"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaf893adc5e821b15d813237b2bfe4378b"> 700</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PAR; </div>
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<div class="line"><a name="l00701"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga2cc2a52628182f9e79ab1e49bb78a1eb"> 701</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t M0AR; </div>
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<div class="line"><a name="l00702"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gadbeac1d47cb85ab52dac71d520273947"> 702</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t M1AR; </div>
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<div class="line"><a name="l00703"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga965da718db7d0303bff185d367d96fd6"> 703</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t FCR; </div>
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<div class="line"><a name="l00704"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga142ca5a1145ba9cf4cfa557655af1c13"> 704</a></span> } <a class="code" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a>;</div>
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<div class="line"><a name="l00705"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaad3d78ab35e7af48951be5be53392f9f"> 705</a></span> </div>
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<div class="line"><a name="l00706"></a><span class="lineno"> 706</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00707"></a><span class="lineno"> 707</span> {</div>
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<div class="line"><a name="l00708"></a><span class="lineno"><a class="line" href="struct_d_m_a___type_def.html"> 708</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t LISR; </div>
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<div class="line"><a name="l00709"></a><span class="lineno"> 709</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t HISR; </div>
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<div class="line"><a name="l00710"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaacb4a0977d281bc809cb5974e178bc2b"> 710</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t LIFCR; </div>
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<div class="line"><a name="l00711"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga01a90a5fcd6459e10b81c0ab737dd2e3"> 711</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t HIFCR; </div>
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<div class="line"><a name="l00712"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga11adb689c874d38b49fa44990323b653"> 712</a></span> } <a class="code" href="struct_d_m_a___type_def.html">DMA_TypeDef</a>;</div>
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<div class="line"><a name="l00713"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga1e4f50b935bab2520788ae936f2e55c1"> 713</a></span>  </div>
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<div class="line"><a name="l00718"></a><span class="lineno"> 718</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00719"></a><span class="lineno"> 719</span> {</div>
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<div class="line"><a name="l00720"></a><span class="lineno"><a class="line" href="struct_d_m_a2_d___type_def.html"> 720</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CR; </div>
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<div class="line"><a name="l00721"></a><span class="lineno"> 721</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ISR; </div>
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<div class="line"><a name="l00722"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gafb0ef686f69afae3e9614a9b30558dcf"> 722</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t IFCR; </div>
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<div class="line"><a name="l00723"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga03ffbd962bae5def253311b5b385cd07"> 723</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t FGMAR; </div>
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<div class="line"><a name="l00724"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaede126199a74ea2a7477c1361537f3c4"> 724</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t FGOR; </div>
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<div class="line"><a name="l00725"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga8f6597d73722df5394be67c0ac22fe66"> 725</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BGMAR; </div>
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<div class="line"><a name="l00726"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga9a1b3799763c47fefd4772f10b7df91b"> 726</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BGOR; </div>
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<div class="line"><a name="l00727"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga9d9d6051b0db4c369c7aa77c0c8740d0"> 727</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t FGPFCCR; </div>
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<div class="line"><a name="l00728"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga93ae9fddd0bab5c8938015a540e6371e"> 728</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t FGCOLR; </div>
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<div class="line"><a name="l00729"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gae98f793825b09b2b70300582d2f8a9fe"> 729</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BGPFCCR; </div>
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<div class="line"><a name="l00730"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga8e2ca425d2b5655573fd89bca5efb272"> 730</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BGCOLR; </div>
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<div class="line"><a name="l00731"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga2469616cbbe6a9e9afa1b943f326add0"> 731</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t FGCMAR; </div>
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<div class="line"><a name="l00732"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga9dad401dfd995251a189d457bc6a5ebd"> 732</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BGCMAR; </div>
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<div class="line"><a name="l00733"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gafdbd6e3f06436d655b464e1ea804ea31"> 733</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t OPFCCR; </div>
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<div class="line"><a name="l00734"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga7b6a846a09e204c29664759983853ec0"> 734</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t OCOLR; </div>
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<div class="line"><a name="l00735"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga50f9ee49cd295305a56ac58b96d11ded"> 735</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t OMAR; </div>
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<div class="line"><a name="l00736"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga07566e4390ac1c55a3fd7f58dd6e33c6"> 736</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t OOR; </div>
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<div class="line"><a name="l00737"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga4ecac7187f1a8fcd108b14abdfb4934d"> 737</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t NLR; </div>
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<div class="line"><a name="l00738"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga118208b8645815a2aa670e92d6277199"> 738</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t LWR; </div>
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<div class="line"><a name="l00739"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga96a187a30051332f029676b6ecd36167"> 739</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t AMTCR; </div>
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<div class="line"><a name="l00740"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaa78b34a419d5a35c5504f1818ef9f122"> 740</a></span>  uint32_t RESERVED[236]; </div>
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<div class="line"><a name="l00741"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga5e5f5a73a2c943723044960897daccc3"> 741</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t FGCLUT[256]; </div>
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<div class="line"><a name="l00742"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga996362d8114c5c841da6c763b0df3df1"> 742</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BGCLUT[256]; </div>
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<div class="line"><a name="l00743"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga4f8c1dc3470960b18ec9e3c358d0b0ad"> 743</a></span> } <a class="code" href="struct_d_m_a2_d___type_def.html">DMA2D_TypeDef</a>;</div>
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<div class="line"><a name="l00744"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga2ee6a30b394faf8442becbfa8b737413"> 744</a></span> </div>
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<div class="line"><a name="l00749"></a><span class="lineno"> 749</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00750"></a><span class="lineno"> 750</span> {</div>
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<div class="line"><a name="l00751"></a><span class="lineno"><a class="line" href="struct_e_t_h___type_def.html"> 751</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MACCR;</div>
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<div class="line"><a name="l00752"></a><span class="lineno"> 752</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MACFFR;</div>
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<div class="line"><a name="l00753"></a><span class="lineno"> 753</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MACHTHR;</div>
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<div class="line"><a name="l00754"></a><span class="lineno"> 754</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MACHTLR;</div>
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<div class="line"><a name="l00755"></a><span class="lineno"> 755</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MACMIIAR;</div>
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<div class="line"><a name="l00756"></a><span class="lineno"> 756</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MACMIIDR;</div>
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<div class="line"><a name="l00757"></a><span class="lineno"> 757</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MACFCR;</div>
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<div class="line"><a name="l00758"></a><span class="lineno"> 758</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MACVLANTR; <span class="comment">/* 8 */</span></div>
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<div class="line"><a name="l00759"></a><span class="lineno"> 759</span>  uint32_t RESERVED0[2];</div>
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<div class="line"><a name="l00760"></a><span class="lineno"> 760</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MACRWUFFR; <span class="comment">/* 11 */</span></div>
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<div class="line"><a name="l00761"></a><span class="lineno"> 761</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MACPMTCSR;</div>
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<div class="line"><a name="l00762"></a><span class="lineno"> 762</span>  uint32_t RESERVED1[2];</div>
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<div class="line"><a name="l00763"></a><span class="lineno"> 763</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MACSR; <span class="comment">/* 15 */</span></div>
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|
<div class="line"><a name="l00764"></a><span class="lineno"> 764</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MACIMR;</div>
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|
<div class="line"><a name="l00765"></a><span class="lineno"> 765</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MACA0HR;</div>
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|
<div class="line"><a name="l00766"></a><span class="lineno"> 766</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MACA0LR;</div>
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|
<div class="line"><a name="l00767"></a><span class="lineno"> 767</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MACA1HR;</div>
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|
<div class="line"><a name="l00768"></a><span class="lineno"> 768</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MACA1LR;</div>
|
|
<div class="line"><a name="l00769"></a><span class="lineno"> 769</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MACA2HR;</div>
|
|
<div class="line"><a name="l00770"></a><span class="lineno"> 770</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MACA2LR;</div>
|
|
<div class="line"><a name="l00771"></a><span class="lineno"> 771</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MACA3HR;</div>
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|
<div class="line"><a name="l00772"></a><span class="lineno"> 772</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MACA3LR; <span class="comment">/* 24 */</span></div>
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|
<div class="line"><a name="l00773"></a><span class="lineno"> 773</span>  uint32_t RESERVED2[40];</div>
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|
<div class="line"><a name="l00774"></a><span class="lineno"> 774</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MMCCR; <span class="comment">/* 65 */</span></div>
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|
<div class="line"><a name="l00775"></a><span class="lineno"> 775</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MMCRIR;</div>
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|
<div class="line"><a name="l00776"></a><span class="lineno"> 776</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MMCTIR;</div>
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|
<div class="line"><a name="l00777"></a><span class="lineno"> 777</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MMCRIMR;</div>
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|
<div class="line"><a name="l00778"></a><span class="lineno"> 778</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MMCTIMR; <span class="comment">/* 69 */</span></div>
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|
<div class="line"><a name="l00779"></a><span class="lineno"> 779</span>  uint32_t RESERVED3[14];</div>
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|
<div class="line"><a name="l00780"></a><span class="lineno"> 780</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MMCTGFSCCR; <span class="comment">/* 84 */</span></div>
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<div class="line"><a name="l00781"></a><span class="lineno"> 781</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MMCTGFMSCCR;</div>
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|
<div class="line"><a name="l00782"></a><span class="lineno"> 782</span>  uint32_t RESERVED4[5];</div>
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|
<div class="line"><a name="l00783"></a><span class="lineno"> 783</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MMCTGFCR;</div>
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|
<div class="line"><a name="l00784"></a><span class="lineno"> 784</span>  uint32_t RESERVED5[10];</div>
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|
<div class="line"><a name="l00785"></a><span class="lineno"> 785</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MMCRFCECR;</div>
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|
<div class="line"><a name="l00786"></a><span class="lineno"> 786</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MMCRFAECR;</div>
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|
<div class="line"><a name="l00787"></a><span class="lineno"> 787</span>  uint32_t RESERVED6[10];</div>
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|
<div class="line"><a name="l00788"></a><span class="lineno"> 788</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MMCRGUFCR;</div>
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|
<div class="line"><a name="l00789"></a><span class="lineno"> 789</span>  uint32_t RESERVED7[334];</div>
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|
<div class="line"><a name="l00790"></a><span class="lineno"> 790</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PTPTSCR;</div>
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|
<div class="line"><a name="l00791"></a><span class="lineno"> 791</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PTPSSIR;</div>
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<div class="line"><a name="l00792"></a><span class="lineno"> 792</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PTPTSHR;</div>
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<div class="line"><a name="l00793"></a><span class="lineno"> 793</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PTPTSLR;</div>
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<div class="line"><a name="l00794"></a><span class="lineno"> 794</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PTPTSHUR;</div>
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<div class="line"><a name="l00795"></a><span class="lineno"> 795</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PTPTSLUR;</div>
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<div class="line"><a name="l00796"></a><span class="lineno"> 796</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PTPTSAR;</div>
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<div class="line"><a name="l00797"></a><span class="lineno"> 797</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PTPTTHR;</div>
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<div class="line"><a name="l00798"></a><span class="lineno"> 798</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PTPTTLR;</div>
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<div class="line"><a name="l00799"></a><span class="lineno"> 799</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RESERVED8;</div>
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<div class="line"><a name="l00800"></a><span class="lineno"> 800</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PTPTSSR;</div>
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<div class="line"><a name="l00801"></a><span class="lineno"> 801</span>  uint32_t RESERVED9[565];</div>
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<div class="line"><a name="l00802"></a><span class="lineno"> 802</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DMABMR;</div>
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<div class="line"><a name="l00803"></a><span class="lineno"> 803</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DMATPDR;</div>
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<div class="line"><a name="l00804"></a><span class="lineno"> 804</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DMARPDR;</div>
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<div class="line"><a name="l00805"></a><span class="lineno"> 805</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DMARDLAR;</div>
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<div class="line"><a name="l00806"></a><span class="lineno"> 806</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DMATDLAR;</div>
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<div class="line"><a name="l00807"></a><span class="lineno"> 807</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DMASR;</div>
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<div class="line"><a name="l00808"></a><span class="lineno"> 808</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DMAOMR;</div>
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<div class="line"><a name="l00809"></a><span class="lineno"> 809</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DMAIER;</div>
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<div class="line"><a name="l00810"></a><span class="lineno"> 810</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DMAMFBOCR;</div>
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<div class="line"><a name="l00811"></a><span class="lineno"> 811</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DMARSWTR;</div>
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<div class="line"><a name="l00812"></a><span class="lineno"> 812</span>  uint32_t RESERVED10[8];</div>
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<div class="line"><a name="l00813"></a><span class="lineno"> 813</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DMACHTDR;</div>
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<div class="line"><a name="l00814"></a><span class="lineno"> 814</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DMACHRDR;</div>
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<div class="line"><a name="l00815"></a><span class="lineno"> 815</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DMACHTBAR;</div>
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<div class="line"><a name="l00816"></a><span class="lineno"> 816</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DMACHRBAR;</div>
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<div class="line"><a name="l00817"></a><span class="lineno"> 817</span> } <a class="code" href="struct_e_t_h___type_def.html">ETH_TypeDef</a>;</div>
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<div class="line"><a name="l00818"></a><span class="lineno"> 818</span> </div>
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<div class="line"><a name="l00823"></a><span class="lineno"> 823</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00824"></a><span class="lineno"> 824</span> {</div>
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<div class="line"><a name="l00825"></a><span class="lineno"><a class="line" href="struct_e_x_t_i___type_def.html"> 825</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t IMR; </div>
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<div class="line"><a name="l00826"></a><span class="lineno"> 826</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t EMR; </div>
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<div class="line"><a name="l00827"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga17d061db586d4a5aa646b68495a8e6a4"> 827</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RTSR; </div>
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<div class="line"><a name="l00828"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga9c5bff67bf9499933959df7eb91a1bd6"> 828</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t FTSR; </div>
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<div class="line"><a name="l00829"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gac019d211d8c880b327a1b90a06cc0675"> 829</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SWIER; </div>
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<div class="line"><a name="l00830"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaee667dc148250bbf37fdc66dc4a9874d"> 830</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PR; </div>
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<div class="line"><a name="l00831"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga5c1f538e64ee90918cd158b808f5d4de"> 831</a></span> } <a class="code" href="struct_e_x_t_i___type_def.html">EXTI_TypeDef</a>;</div>
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<div class="line"><a name="l00832"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga133294b87dbe6a01e8d9584338abc39a"> 832</a></span> </div>
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<div class="line"><a name="l00837"></a><span class="lineno"> 837</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00838"></a><span class="lineno"> 838</span> {</div>
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<div class="line"><a name="l00839"></a><span class="lineno"><a class="line" href="struct_f_l_a_s_h___type_def.html"> 839</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ACR; </div>
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<div class="line"><a name="l00840"></a><span class="lineno"> 840</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t KEYR; </div>
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<div class="line"><a name="l00841"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaaf432a8a8948613f4f66fcace5d2e5fe"> 841</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t OPTKEYR; </div>
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<div class="line"><a name="l00842"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga802e9a26a89b44decd2d32d97f729dd3"> 842</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SR; </div>
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<div class="line"><a name="l00843"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga793cd13a4636c9785fdb99316f7fd7ab"> 843</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CR; </div>
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<div class="line"><a name="l00844"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga52c4943c64904227a559bf6f14ce4de6"> 844</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t OPTCR; </div>
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<div class="line"><a name="l00845"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga7919306d0e032a855200420a57f884d7"> 845</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t OPTCR1; </div>
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<div class="line"><a name="l00846"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga54026c3b5bc2059f1b187acb6c4817ac"> 846</a></span> } <a class="code" href="struct_f_l_a_s_h___type_def.html">FLASH_TypeDef</a>;</div>
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<div class="line"><a name="l00847"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga180354afdf5ff27d04befd794c46156d"> 847</a></span> </div>
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<div class="line"><a name="l00848"></a><span class="lineno"> 848</span> <span class="preprocessor">#if defined (STM32F40_41xxx)</span></div>
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<div class="line"><a name="l00849"></a><span class="lineno"> 849</span> </div>
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<div class="line"><a name="l00853"></a><span class="lineno"> 853</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00854"></a><span class="lineno"> 854</span> {</div>
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<div class="line"><a name="l00855"></a><span class="lineno"><a class="line" href="struct_f_s_m_c___bank1___type_def.html"> 855</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BTCR[8]; </div>
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<div class="line"><a name="l00856"></a><span class="lineno"> 856</span> } <a class="code" href="struct_f_s_m_c___bank1___type_def.html">FSMC_Bank1_TypeDef</a>; </div>
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<div class="line"><a name="l00857"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga6d3aefd66a99e71ae4a22444a507a720"> 857</a></span> </div>
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<div class="line"><a name="l00862"></a><span class="lineno"> 862</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00863"></a><span class="lineno"> 863</span> {</div>
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<div class="line"><a name="l00864"></a><span class="lineno"><a class="line" href="struct_f_s_m_c___bank1_e___type_def.html"> 864</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BWTR[7]; </div>
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<div class="line"><a name="l00865"></a><span class="lineno"> 865</span> } <a class="code" href="struct_f_s_m_c___bank1_e___type_def.html">FSMC_Bank1E_TypeDef</a>;</div>
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<div class="line"><a name="l00866"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gafe650877ca972faff9c61fcb364c7b66"> 866</a></span> </div>
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<div class="line"><a name="l00871"></a><span class="lineno"> 871</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00872"></a><span class="lineno"> 872</span> {</div>
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<div class="line"><a name="l00873"></a><span class="lineno"><a class="line" href="struct_f_s_m_c___bank2___type_def.html"> 873</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PCR2; </div>
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|
<div class="line"><a name="l00874"></a><span class="lineno"> 874</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SR2; </div>
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<div class="line"><a name="l00875"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gad1eabc89a4eadb5cc6a42c1e39a39ff8"> 875</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PMEM2; </div>
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<div class="line"><a name="l00876"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga38ad7403e05c899dc266cf47f932cc8f"> 876</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PATT2; </div>
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<div class="line"><a name="l00877"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga29b2b75e74520e304e31c18cf9e4a7f8"> 877</a></span>  uint32_t RESERVED0; </div>
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<div class="line"><a name="l00878"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga9b2c273e4b84f24efbd731bd4ba76a84"> 878</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ECCR2; </div>
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<div class="line"><a name="l00879"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gac0433330a92f2bd04812384f63bb4a52"> 879</a></span> } <a class="code" href="struct_f_s_m_c___bank2___type_def.html">FSMC_Bank2_TypeDef</a>;</div>
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<div class="line"><a name="l00880"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gafebea17b3ac79d86ad59ce299ab5dd83"> 880</a></span> </div>
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<div class="line"><a name="l00885"></a><span class="lineno"> 885</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00886"></a><span class="lineno"> 886</span> {</div>
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<div class="line"><a name="l00887"></a><span class="lineno"><a class="line" href="struct_f_s_m_c___bank3___type_def.html"> 887</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PCR3; </div>
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|
<div class="line"><a name="l00888"></a><span class="lineno"> 888</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SR3; </div>
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<div class="line"><a name="l00889"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga1f772e1028641cab7b923bf02115b919"> 889</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PMEM3; </div>
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<div class="line"><a name="l00890"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gab89f16f64018a1f1e55d36f92b84be94"> 890</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PATT3; </div>
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|
<div class="line"><a name="l00891"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga756258d9266b1eee3455bc850107beb6"> 891</a></span>  uint32_t RESERVED0; </div>
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|
<div class="line"><a name="l00892"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga0cbf1b4647f98914238202828de47416"> 892</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ECCR3; </div>
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|
<div class="line"><a name="l00893"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga2e9cac528ee7bfce11b0b9a36db3b954"> 893</a></span> } <a class="code" href="struct_f_s_m_c___bank3___type_def.html">FSMC_Bank3_TypeDef</a>;</div>
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<div class="line"><a name="l00894"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga6935beb5bbc2de668024c1989eecd46c"> 894</a></span> </div>
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<div class="line"><a name="l00899"></a><span class="lineno"> 899</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00900"></a><span class="lineno"> 900</span> {</div>
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<div class="line"><a name="l00901"></a><span class="lineno"><a class="line" href="struct_f_s_m_c___bank4___type_def.html"> 901</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PCR4; </div>
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|
<div class="line"><a name="l00902"></a><span class="lineno"> 902</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SR4; </div>
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<div class="line"><a name="l00903"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga0470b5bbb53e9f1bbde09829371eb72f"> 903</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PMEM4; </div>
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|
<div class="line"><a name="l00904"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga1e0f09be7fa48bb7b14233866da1dd9f"> 904</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PATT4; </div>
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<div class="line"><a name="l00905"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga4ed4ce751e7a8b3207bd20675b1d9085"> 905</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PIO4; </div>
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<div class="line"><a name="l00906"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga4cccc7802b573135311cc38e7f247ff5"> 906</a></span> } <a class="code" href="struct_f_s_m_c___bank4___type_def.html">FSMC_Bank4_TypeDef</a>; </div>
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<div class="line"><a name="l00907"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga531ebc38c47bebfb198eafb4de24cb2a"> 907</a></span> <span class="preprocessor">#endif </span><span class="comment">/* STM32F40_41xxx */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00908"></a><span class="lineno"> 908</span> </div>
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<div class="line"><a name="l00909"></a><span class="lineno"> 909</span> <span class="preprocessor">#if defined (STM32F427_437xx) || defined (STM32F429_439xx)</span></div>
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<div class="line"><a name="l00910"></a><span class="lineno"> 910</span> </div>
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<div class="line"><a name="l00914"></a><span class="lineno"> 914</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00915"></a><span class="lineno"> 915</span> {</div>
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<div class="line"><a name="l00916"></a><span class="lineno"> 916</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BTCR[8]; </div>
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<div class="line"><a name="l00917"></a><span class="lineno"> 917</span> } FMC_Bank1_TypeDef; </div>
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<div class="line"><a name="l00918"></a><span class="lineno"> 918</span> </div>
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<div class="line"><a name="l00923"></a><span class="lineno"> 923</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00924"></a><span class="lineno"> 924</span> {</div>
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<div class="line"><a name="l00925"></a><span class="lineno"> 925</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BWTR[7]; </div>
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<div class="line"><a name="l00926"></a><span class="lineno"> 926</span> } FMC_Bank1E_TypeDef;</div>
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<div class="line"><a name="l00927"></a><span class="lineno"> 927</span> </div>
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<div class="line"><a name="l00932"></a><span class="lineno"> 932</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00933"></a><span class="lineno"> 933</span> {</div>
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<div class="line"><a name="l00934"></a><span class="lineno"> 934</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PCR2; </div>
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<div class="line"><a name="l00935"></a><span class="lineno"> 935</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SR2; </div>
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<div class="line"><a name="l00936"></a><span class="lineno"> 936</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PMEM2; </div>
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<div class="line"><a name="l00937"></a><span class="lineno"> 937</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PATT2; </div>
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<div class="line"><a name="l00938"></a><span class="lineno"> 938</span>  uint32_t RESERVED0; </div>
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<div class="line"><a name="l00939"></a><span class="lineno"> 939</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ECCR2; </div>
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|
<div class="line"><a name="l00940"></a><span class="lineno"> 940</span> } FMC_Bank2_TypeDef;</div>
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<div class="line"><a name="l00941"></a><span class="lineno"> 941</span> </div>
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<div class="line"><a name="l00946"></a><span class="lineno"> 946</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00947"></a><span class="lineno"> 947</span> {</div>
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<div class="line"><a name="l00948"></a><span class="lineno"> 948</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PCR3; </div>
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<div class="line"><a name="l00949"></a><span class="lineno"> 949</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SR3; </div>
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<div class="line"><a name="l00950"></a><span class="lineno"> 950</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PMEM3; </div>
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<div class="line"><a name="l00951"></a><span class="lineno"> 951</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PATT3; </div>
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<div class="line"><a name="l00952"></a><span class="lineno"> 952</span>  uint32_t RESERVED0; </div>
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<div class="line"><a name="l00953"></a><span class="lineno"> 953</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ECCR3; </div>
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<div class="line"><a name="l00954"></a><span class="lineno"> 954</span> } FMC_Bank3_TypeDef;</div>
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<div class="line"><a name="l00955"></a><span class="lineno"> 955</span> </div>
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<div class="line"><a name="l00960"></a><span class="lineno"> 960</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00961"></a><span class="lineno"> 961</span> {</div>
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<div class="line"><a name="l00962"></a><span class="lineno"> 962</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PCR4; </div>
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<div class="line"><a name="l00963"></a><span class="lineno"> 963</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SR4; </div>
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<div class="line"><a name="l00964"></a><span class="lineno"> 964</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PMEM4; </div>
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<div class="line"><a name="l00965"></a><span class="lineno"> 965</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PATT4; </div>
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<div class="line"><a name="l00966"></a><span class="lineno"> 966</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PIO4; </div>
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<div class="line"><a name="l00967"></a><span class="lineno"> 967</span> } FMC_Bank4_TypeDef; </div>
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<div class="line"><a name="l00968"></a><span class="lineno"> 968</span> </div>
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<div class="line"><a name="l00973"></a><span class="lineno"> 973</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00974"></a><span class="lineno"> 974</span> {</div>
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<div class="line"><a name="l00975"></a><span class="lineno"> 975</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SDCR[2]; </div>
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<div class="line"><a name="l00976"></a><span class="lineno"> 976</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SDTR[2]; </div>
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<div class="line"><a name="l00977"></a><span class="lineno"> 977</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SDCMR; </div>
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<div class="line"><a name="l00978"></a><span class="lineno"> 978</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SDRTR; </div>
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<div class="line"><a name="l00979"></a><span class="lineno"> 979</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SDSR; </div>
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<div class="line"><a name="l00980"></a><span class="lineno"> 980</span> } FMC_Bank5_6_TypeDef; </div>
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<div class="line"><a name="l00981"></a><span class="lineno"> 981</span> <span class="preprocessor">#endif </span><span class="comment">/* STM32F427_437xx || STM32F429_439xx */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00982"></a><span class="lineno"> 982</span> </div>
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<div class="line"><a name="l00987"></a><span class="lineno"> 987</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00988"></a><span class="lineno"> 988</span> {</div>
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<div class="line"><a name="l00989"></a><span class="lineno"><a class="line" href="struct_g_p_i_o___type_def.html"> 989</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MODER; </div>
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<div class="line"><a name="l00990"></a><span class="lineno"> 990</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t OTYPER; </div>
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<div class="line"><a name="l00991"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gac2505d096b6b650f1647b8e0ff8b196b"> 991</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t OSPEEDR; </div>
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<div class="line"><a name="l00992"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga910885e4d881c3a459dd11640237107f"> 992</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PUPDR; </div>
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<div class="line"><a name="l00993"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga0d233d720f18ae2050f9131fa6faf7c6"> 993</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t IDR; </div>
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<div class="line"><a name="l00994"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga44ada3bfbe891e2efc1e06bda4c8014e"> 994</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ODR; </div>
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<div class="line"><a name="l00995"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gacf11156409414ad8841bb0b62959ee96"> 995</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t BSRRL; </div>
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<div class="line"><a name="l00996"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga6fb78f4a978a36032cdeac93ac3c9c8b"> 996</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t BSRRH; </div>
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<div class="line"><a name="l00997"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gad2528bbb921532be8116534651b1faee"> 997</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t LCKR; </div>
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<div class="line"><a name="l00998"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gad4b5f8bc936e26e3980686d2aba9d882"> 998</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t AFR[2]; </div>
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<div class="line"><a name="l00999"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga95a59d4b1d52be521f3246028be32f3e"> 999</a></span> } <a class="code" href="struct_g_p_i_o___type_def.html">GPIO_TypeDef</a>;</div>
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<div class="line"><a name="l01000"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga2245603433e102f0fd8a85f7de020755"> 1000</a></span> </div>
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<div class="line"><a name="l01005"></a><span class="lineno"> 1005</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l01006"></a><span class="lineno"> 1006</span> {</div>
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<div class="line"><a name="l01007"></a><span class="lineno"><a class="line" href="struct_s_y_s_c_f_g___type_def.html"> 1007</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MEMRMP; </div>
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|
<div class="line"><a name="l01008"></a><span class="lineno"> 1008</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PMC; </div>
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|
<div class="line"><a name="l01009"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga85b9d3df2274b730327b181c402a7bf5"> 1009</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t EXTICR[4]; </div>
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<div class="line"><a name="l01010"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gab5c47c570566cb8ff9d0436c17cc9241"> 1010</a></span>  uint32_t RESERVED[2]; </div>
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<div class="line"><a name="l01011"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga66a06b3aab7ff5c8fa342f7c1994bf7d"> 1011</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CMPCR; </div>
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|
<div class="line"><a name="l01012"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga43926e6d31a976a0018b2d1f5c92645d"> 1012</a></span> } <a class="code" href="struct_s_y_s_c_f_g___type_def.html">SYSCFG_TypeDef</a>;</div>
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|
<div class="line"><a name="l01013"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gada13497abc6402300570ff5f430a612e"> 1013</a></span> </div>
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<div class="line"><a name="l01018"></a><span class="lineno"> 1018</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l01019"></a><span class="lineno"> 1019</span> {</div>
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<div class="line"><a name="l01020"></a><span class="lineno"><a class="line" href="struct_i2_c___type_def.html"> 1020</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t CR1; </div>
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|
<div class="line"><a name="l01021"></a><span class="lineno"> 1021</span>  uint16_t RESERVED0; </div>
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|
<div class="line"><a name="l01022"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gad35ea0b199cefb757de20e9b78168534"> 1022</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t CR2; </div>
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|
<div class="line"><a name="l01023"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaee6ec4cf81ee0bb5b038576ba0d738a2"> 1023</a></span>  uint16_t RESERVED1; </div>
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|
<div class="line"><a name="l01024"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gac8bff45acc455489620d50e697a24c9d"> 1024</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t OAR1; </div>
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|
<div class="line"><a name="l01025"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga6c3d147223993f2b832b508ee5a5178e"> 1025</a></span>  uint16_t RESERVED2; </div>
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|
<div class="line"><a name="l01026"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gad218fdcb9606477c1d63f8ee38d3c5c9"> 1026</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t OAR2; </div>
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|
<div class="line"><a name="l01027"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga5e98c83a176deeb4a8a68f9ca12fdfd2"> 1027</a></span>  uint16_t RESERVED3; </div>
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|
<div class="line"><a name="l01028"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga03189e2a57c81ae5d103739b72f52c93"> 1028</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t DR; </div>
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|
<div class="line"><a name="l01029"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga355b2c5aa0dd467de1f9dea4a9afe986"> 1029</a></span>  uint16_t RESERVED4; </div>
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|
<div class="line"><a name="l01030"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga5c1551b886fbb8e801b9203f6d7dc7c5"> 1030</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t SR1; </div>
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|
<div class="line"><a name="l01031"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga05a1a3482d9534ba9ef976e3277040f0"> 1031</a></span>  uint16_t RESERVED5; </div>
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|
<div class="line"><a name="l01032"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gae1602cd1c9cad449523099c97138f991"> 1032</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t SR2; </div>
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|
<div class="line"><a name="l01033"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gae736412dcff4daa38bfa8bf8628df316"> 1033</a></span>  uint16_t RESERVED6; </div>
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|
<div class="line"><a name="l01034"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga95c7f729b10eb2acafe499d9c9a81a83"> 1034</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t CCR; </div>
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|
<div class="line"><a name="l01035"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaaf1b319262f53669f49e244d94955a60"> 1035</a></span>  uint16_t RESERVED7; </div>
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|
<div class="line"><a name="l01036"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga1775e779008da2b4d1807c2b5033b8a5"> 1036</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t TRISE; </div>
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|
<div class="line"><a name="l01037"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga0f398bdcc3f24e7547c3cb9343111fd0"> 1037</a></span>  uint16_t RESERVED8; </div>
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|
<div class="line"><a name="l01038"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaaba7a808e4dfae5cc06b197c298af206"> 1038</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t FLTR; </div>
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|
<div class="line"><a name="l01039"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga6e762751c9d5a1e41efb6033a26d8ed8"> 1039</a></span>  uint16_t RESERVED9; </div>
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|
<div class="line"><a name="l01040"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga932d5b47f494828fbe8e2448bb324ca8"> 1040</a></span> } <a class="code" href="struct_i2_c___type_def.html">I2C_TypeDef</a>;</div>
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<div class="line"><a name="l01041"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga669f1406f19f2944cb73d02b3620880f"> 1041</a></span> </div>
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<div class="line"><a name="l01046"></a><span class="lineno"> 1046</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l01047"></a><span class="lineno"> 1047</span> {</div>
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<div class="line"><a name="l01048"></a><span class="lineno"><a class="line" href="struct_i_w_d_g___type_def.html"> 1048</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t KR; </div>
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<div class="line"><a name="l01049"></a><span class="lineno"> 1049</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PR; </div>
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<div class="line"><a name="l01050"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga63089aaa5f4ad34ee2677ebcdee49cd9"> 1050</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RLR; </div>
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|
<div class="line"><a name="l01051"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga5f2717885ff171e686e0347af9e6b68d"> 1051</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SR; </div>
|
|
<div class="line"><a name="l01052"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaa3703eaa40e447dcacc69c0827595532"> 1052</a></span> } <a class="code" href="struct_i_w_d_g___type_def.html">IWDG_TypeDef</a>;</div>
|
|
<div class="line"><a name="l01053"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga9bbfbe921f2acfaf58251849bd0a511c"> 1053</a></span> </div>
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|
<div class="line"><a name="l01058"></a><span class="lineno"> 1058</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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|
<div class="line"><a name="l01059"></a><span class="lineno"> 1059</span> {</div>
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<div class="line"><a name="l01060"></a><span class="lineno"><a class="line" href="struct_l_t_d_c___type_def.html"> 1060</a></span>  uint32_t RESERVED0[2]; </div>
|
|
<div class="line"><a name="l01061"></a><span class="lineno"> 1061</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SSCR; </div>
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|
<div class="line"><a name="l01062"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga1a43b1a297bbe2126e6697a09d21612d"> 1062</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BPCR; </div>
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|
<div class="line"><a name="l01063"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaa5bb98a48470eaf50559e916bce23278"> 1063</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t AWCR; </div>
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|
<div class="line"><a name="l01064"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaefc3daf9db06d441115572be02bb49bd"> 1064</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t TWCR; </div>
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|
<div class="line"><a name="l01065"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga20602a2e34b3e4e97e07474e5ad9c22b"> 1065</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t GCR; </div>
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|
<div class="line"><a name="l01066"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga7a7b8762321bdcdc8def7a6ace94a455"> 1066</a></span>  uint32_t RESERVED1[2]; </div>
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|
<div class="line"><a name="l01067"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga154e0514cfca7449156dd5a9133631ac"> 1067</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SRCR; </div>
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|
<div class="line"><a name="l01068"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaadd4b8262474fe610f5414e1ff2fbcbe"> 1068</a></span>  uint32_t RESERVED2[1]; </div>
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|
<div class="line"><a name="l01069"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga502dd9d2d17025a90bdf968eb29827f2"> 1069</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BCCR; </div>
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|
<div class="line"><a name="l01070"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gae3e85d4ed370a42e7fd46d059dffaaa8"> 1070</a></span>  uint32_t RESERVED3[1]; </div>
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<div class="line"><a name="l01071"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gacf20a59c07d3e013d0207b1719b973b6"> 1071</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t IER; </div>
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<div class="line"><a name="l01072"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gafffbe3c266a4f2bd842eb96103b65dac"> 1072</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ISR; </div>
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<div class="line"><a name="l01073"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga0ab6c92574cc246707aa1371e3c5cb85"> 1073</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ICR; </div>
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<div class="line"><a name="l01074"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga2e3f3fba908b85d2fcf1eaab6b5600bf"> 1074</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t LIPCR; </div>
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<div class="line"><a name="l01075"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga7c7225eb9029a81f17b60cf4104eaffb"> 1075</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CPSR; </div>
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<div class="line"><a name="l01076"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga74a5f74bb4f174bbda1e2dc3cce9f536"> 1076</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CDSR; </div>
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<div class="line"><a name="l01077"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaf019d85ce2b876ee99d994a09de12ec3"> 1077</a></span> } <a class="code" href="struct_l_t_d_c___type_def.html">LTDC_TypeDef</a>; </div>
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<div class="line"><a name="l01078"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga6d6675f23322e241122468935ee60ed1"> 1078</a></span> </div>
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<div class="line"><a name="l01083"></a><span class="lineno"> 1083</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l01084"></a><span class="lineno"> 1084</span> { </div>
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<div class="line"><a name="l01085"></a><span class="lineno"><a class="line" href="struct_l_t_d_c___layer___type_def.html"> 1085</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CR; </div>
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<div class="line"><a name="l01086"></a><span class="lineno"> 1086</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t WHPCR; </div>
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<div class="line"><a name="l01087"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga3f9827b30a402fd3d85fe4f4b8eb49c9"> 1087</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t WVPCR; </div>
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<div class="line"><a name="l01088"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga9c72a83598a0ee20148f01a486f54ac0"> 1088</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CKCR; </div>
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<div class="line"><a name="l01089"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaa3238d4c30b3ec500b2007bc061020db"> 1089</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PFCR; </div>
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<div class="line"><a name="l01090"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga1037f0255519c1c6c14af5b17a4de3ca"> 1090</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CACR; </div>
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<div class="line"><a name="l01091"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga401b8bbdd7d666b112a747b1a6d163ae"> 1091</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DCCR; </div>
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<div class="line"><a name="l01092"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaf3708f47198ca52e0149584a8c382362"> 1092</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BFCR; </div>
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<div class="line"><a name="l01093"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaaedb1dc65cb10a98f4c53f162b19bb39"> 1093</a></span>  uint32_t RESERVED0[2]; </div>
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<div class="line"><a name="l01094"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gad597faecb079859e9cdb849c8cf78aec"> 1094</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CFBAR; </div>
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<div class="line"><a name="l01095"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga69d1bd327c7b02f9a1c9372992939406"> 1095</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CFBLR; </div>
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<div class="line"><a name="l01096"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaa79c0c2be9b6f8e4f034d8d5fe8e9345"> 1096</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CFBLNR; </div>
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<div class="line"><a name="l01097"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gae4673c5b4a2df7b770d82e43b1806ccf"> 1097</a></span>  uint32_t RESERVED1[3]; </div>
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<div class="line"><a name="l01098"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gadbd3ad2a70d1578d630acfdb9a526320"> 1098</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CLUTWR; </div>
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<div class="line"><a name="l01100"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gae4ce84d11912847542fcdc03ae337176"> 1100</a></span> } <a class="code" href="struct_l_t_d_c___layer___type_def.html">LTDC_Layer_TypeDef</a>;</div>
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<div class="line"><a name="l01101"></a><span class="lineno"> 1101</span> </div>
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<div class="line"><a name="l01106"></a><span class="lineno"> 1106</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l01107"></a><span class="lineno"> 1107</span> {</div>
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<div class="line"><a name="l01108"></a><span class="lineno"><a class="line" href="struct_p_w_r___type_def.html"> 1108</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CR; </div>
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<div class="line"><a name="l01109"></a><span class="lineno"> 1109</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CSR; </div>
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<div class="line"><a name="l01110"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaeb6bcdb2b99d58b9a0ffd86deb606eac"> 1110</a></span> } <a class="code" href="struct_p_w_r___type_def.html">PWR_TypeDef</a>;</div>
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<div class="line"><a name="l01111"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gae17097e69c88b6c00033d6fb84a8182b"> 1111</a></span> </div>
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<div class="line"><a name="l01116"></a><span class="lineno"> 1116</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l01117"></a><span class="lineno"> 1117</span> {</div>
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<div class="line"><a name="l01118"></a><span class="lineno"><a class="line" href="struct_r_c_c___type_def.html"> 1118</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CR; </div>
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<div class="line"><a name="l01119"></a><span class="lineno"> 1119</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PLLCFGR; </div>
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<div class="line"><a name="l01120"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gabcb9ff48b9afb990283fefad0554b5b3"> 1120</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CFGR; </div>
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<div class="line"><a name="l01121"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga2a7ccb4e23cb05a574f243f6278b7b26"> 1121</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CIR; </div>
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<div class="line"><a name="l01122"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga0721b1b729c313211126709559fad371"> 1122</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t AHB1RSTR; </div>
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<div class="line"><a name="l01123"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaeadf3a69dd5795db4638f71938704ff0"> 1123</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t AHB2RSTR; </div>
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<div class="line"><a name="l01124"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gad6abf71a348744aa3f2b7e8b214c1ca4"> 1124</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t AHB3RSTR; </div>
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<div class="line"><a name="l01125"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga343e0230ded55920ff2a04fbde0e5bcd"> 1125</a></span>  uint32_t RESERVED0; </div>
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<div class="line"><a name="l01126"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga39a90d838fbd0b8515f03e4a1be6374f"> 1126</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t APB1RSTR; </div>
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<div class="line"><a name="l01127"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga646631532167f3386763a2d10a881a04"> 1127</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t APB2RSTR; </div>
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|
<div class="line"><a name="l01128"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga600f4d6d592f43edb2fc653c5cba023a"> 1128</a></span>  uint32_t RESERVED1[2]; </div>
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<div class="line"><a name="l01129"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga4491ab20a44b70bf7abd247791676a59"> 1129</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t AHB1ENR; </div>
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<div class="line"><a name="l01130"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga291f9ae23a96c1bfbab257aad87597a5"> 1130</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t AHB2ENR; </div>
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<div class="line"><a name="l01131"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaf58a7ad868f07f8759eac3e31b6fa79e"> 1131</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t AHB3ENR; </div>
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<div class="line"><a name="l01132"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaf326cb98c318fc08894a8dd79c2c675f"> 1132</a></span>  uint32_t RESERVED2; </div>
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<div class="line"><a name="l01133"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gad4ea7be562b42e2ae1a84db44121195d"> 1133</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t APB1ENR; </div>
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<div class="line"><a name="l01134"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga94cb7e7b923ebacab99c967d0f808235"> 1134</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t APB2ENR; </div>
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<div class="line"><a name="l01135"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaec7622ba90341c9faf843d9ee54a759f"> 1135</a></span>  uint32_t RESERVED3[2]; </div>
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<div class="line"><a name="l01136"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga619b4c22f630a269dfd0c331f90f6868"> 1136</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t AHB1LPENR; </div>
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<div class="line"><a name="l01137"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga74071ea325d6bc064817ed0a7a4d7def"> 1137</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t AHB2LPENR; </div>
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<div class="line"><a name="l01138"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga89d6c21f02196b7f59bcc30c1061dd87"> 1138</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t AHB3LPENR; </div>
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<div class="line"><a name="l01139"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga1de344446cba3f4dd15c56fbe20eb0dd"> 1139</a></span>  uint32_t RESERVED4; </div>
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<div class="line"><a name="l01140"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga95edda857c3725bfb410d3a4707edfd8"> 1140</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t APB1LPENR; </div>
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<div class="line"><a name="l01141"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga0f009e4bd1777ac1b86ca27e23361a0e"> 1141</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t APB2LPENR; </div>
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<div class="line"><a name="l01142"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga5c8e710c40b642dcbf296201a7ecb2da"> 1142</a></span>  uint32_t RESERVED5[2]; </div>
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<div class="line"><a name="l01143"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga7e46c65220f00a6858a5b35b74a37b51"> 1143</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BDCR; </div>
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<div class="line"><a name="l01144"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaf9159a971013ef0592be8be3e256a344"> 1144</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CSR; </div>
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<div class="line"><a name="l01145"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga05be375db50e8c9dd24fb3bcf42d7cf1"> 1145</a></span>  uint32_t RESERVED6[2]; </div>
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<div class="line"><a name="l01146"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga7e913b8bf59d4351e1f3d19387bd05b9"> 1146</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SSCGR; </div>
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<div class="line"><a name="l01147"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga30cfd1a2f2eb931bacfd2be965e53d1b"> 1147</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PLLI2SCFGR; </div>
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<div class="line"><a name="l01148"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga52270ad1423c68cd536f62657bb669f5"> 1148</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PLLSAICFGR; </div>
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<div class="line"><a name="l01149"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gac3beb02dccd9131d6ce55bb29c5fa69f"> 1149</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DCKCFGR; </div>
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<div class="line"><a name="l01151"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga877ad70fcd4a215bc8f9bb31fdc8d3d1"> 1151</a></span> } <a class="code" href="struct_r_c_c___type_def.html">RCC_TypeDef</a>;</div>
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<div class="line"><a name="l01152"></a><span class="lineno"> 1152</span> </div>
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<div class="line"><a name="l01157"></a><span class="lineno"> 1157</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l01158"></a><span class="lineno"> 1158</span> {</div>
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<div class="line"><a name="l01159"></a><span class="lineno"><a class="line" href="struct_r_t_c___type_def.html"> 1159</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t TR; </div>
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<div class="line"><a name="l01160"></a><span class="lineno"> 1160</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DR; </div>
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<div class="line"><a name="l01161"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga2e8783857f8644a4eb80ebc51e1cba42"> 1161</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CR; </div>
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<div class="line"><a name="l01162"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga8750eae683cb3d382476dc7cdcd92b96"> 1162</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ISR; </div>
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<div class="line"><a name="l01163"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga731d9209ce40dce6ea61fcc6f818c892"> 1163</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t PRER; </div>
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<div class="line"><a name="l01164"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga5a7b104d80b48b5708b50cdc487d6a78"> 1164</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t WUTR; </div>
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<div class="line"><a name="l01165"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga5f43a11e0873212f598e41db5f2dcf6a"> 1165</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CALIBR; </div>
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<div class="line"><a name="l01166"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gad93017bb0a778a2aad9cd71211fc770a"> 1166</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ALRMAR; </div>
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<div class="line"><a name="l01167"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga2403d29b2bfffb734ebef6642c0d2724"> 1167</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ALRMBR; </div>
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<div class="line"><a name="l01168"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gad7e54d5c5a4b9fd1e26aca85b1e36c7f"> 1168</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t WPR; </div>
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<div class="line"><a name="l01169"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga9816616e1f00955c8982469d0dd9c953"> 1169</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SSR; </div>
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<div class="line"><a name="l01170"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gad54765af56784498a3ae08686b79a1ff"> 1170</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SHIFTR; </div>
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<div class="line"><a name="l01171"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaefbd38be87117d1fced289bf9c534414"> 1171</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t TSTR; </div>
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<div class="line"><a name="l01172"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga6082856c9191f5003b6163c0d3afcaff"> 1172</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t TSDR; </div>
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<div class="line"><a name="l01173"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga1ddbb2a5eaa54ff43835026dec99ae1c"> 1173</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t TSSSR; </div>
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<div class="line"><a name="l01174"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaa4633dbcdb5dd41a714020903fd67c82"> 1174</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CALR; </div>
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|
<div class="line"><a name="l01175"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga1e8b4b987496ee1c0c6f16b0a94ea1a1"> 1175</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t TAFCR; </div>
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<div class="line"><a name="l01176"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaea66ea813830c2f3ff207464794397a4"> 1176</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ALRMASSR;</div>
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<div class="line"><a name="l01177"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga498ecce9715c916dd09134fddd0072c0"> 1177</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ALRMBSSR;</div>
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<div class="line"><a name="l01178"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gac5b2e3c0dcdcb569f3fe15dfe3794bc1"> 1178</a></span>  uint32_t RESERVED7; </div>
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<div class="line"><a name="l01179"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga249009cd672e7bcd52df1a41de4619e1"> 1179</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BKP0R; </div>
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|
<div class="line"><a name="l01180"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga09936292ef8d82974b55a03a1080534e"> 1180</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BKP1R; </div>
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<div class="line"><a name="l01181"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gab32c76ca1f3bd0f0f46d42c2dfa74524"> 1181</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BKP2R; </div>
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<div class="line"><a name="l01182"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga5439bfca3708c6b8be6a74626f06111f"> 1182</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BKP3R; </div>
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<div class="line"><a name="l01183"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaa845c401b24d2ef1049f489f26d35626"> 1183</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BKP4R; </div>
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<div class="line"><a name="l01184"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gac3802c3b17482a0667fb34ddd1863434"> 1184</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BKP5R; </div>
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<div class="line"><a name="l01185"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga6131b2f2896c122cf223206e4cfd2bd0"> 1185</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BKP6R; </div>
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<div class="line"><a name="l01186"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga0f3a33de81247ec5729e400a1261f917"> 1186</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BKP7R; </div>
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|
<div class="line"><a name="l01187"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga766e2071c5826e3a299ae1cd5bbf06f7"> 1187</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BKP8R; </div>
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|
<div class="line"><a name="l01188"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga9934af6ae6b3f5660204d48ceb2f3192"> 1188</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BKP9R; </div>
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|
<div class="line"><a name="l01189"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga0e7fca11f1c953270ee0ee6028860add"> 1189</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BKP10R; </div>
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|
<div class="line"><a name="l01190"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gabadf1ac26350bf00575428be6a05708b"> 1190</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BKP11R; </div>
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|
<div class="line"><a name="l01191"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga5feba3d5adae3f234b3d172459163c5a"> 1191</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BKP12R; </div>
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|
<div class="line"><a name="l01192"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga8fef38e1e122778601e18f5b757c037a"> 1192</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BKP13R; </div>
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|
<div class="line"><a name="l01193"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga6606b5d249f923aa15ab74b382cbaf7e"> 1193</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BKP14R; </div>
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|
<div class="line"><a name="l01194"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga138903d4681455a660dccbaf3409263d"> 1194</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BKP15R; </div>
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|
<div class="line"><a name="l01195"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gadaae50f5c3213014fb9818eaee389676"> 1195</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BKP16R; </div>
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|
<div class="line"><a name="l01196"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga797f43f9cc1858baebd1799be288dff6"> 1196</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BKP17R; </div>
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|
<div class="line"><a name="l01197"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga181ad73082bde7d74010aac16bd373fc"> 1197</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BKP18R; </div>
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|
<div class="line"><a name="l01198"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga90a305a8e00b357f28daef5041e5a8b1"> 1198</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t BKP19R; </div>
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|
<div class="line"><a name="l01199"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga171288f82cab2623832de779fb435d74"> 1199</a></span> } <a class="code" href="struct_r_t_c___type_def.html">RTC_TypeDef</a>;</div>
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|
<div class="line"><a name="l01200"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga993f54e8feff9254f795dfd3e000fc55"> 1200</a></span> </div>
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<div class="line"><a name="l01201"></a><span class="lineno"> 1201</span> </div>
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<div class="line"><a name="l01206"></a><span class="lineno"> 1206</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l01207"></a><span class="lineno"> 1207</span> {</div>
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<div class="line"><a name="l01208"></a><span class="lineno"><a class="line" href="struct_s_a_i___type_def.html"> 1208</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t GCR; </div>
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<div class="line"><a name="l01209"></a><span class="lineno"> 1209</span> } <a class="code" href="struct_s_a_i___type_def.html">SAI_TypeDef</a>;</div>
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<div class="line"><a name="l01210"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gada6999b49bbe697c1dd5fdabc9bad7f4"> 1210</a></span> </div>
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<div class="line"><a name="l01211"></a><span class="lineno"> 1211</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l01212"></a><span class="lineno"> 1212</span> {</div>
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<div class="line"><a name="l01213"></a><span class="lineno"><a class="line" href="struct_s_a_i___block___type_def.html"> 1213</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CR1; </div>
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<div class="line"><a name="l01214"></a><span class="lineno"> 1214</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CR2; </div>
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<div class="line"><a name="l01215"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga8935f3f22c733c1cb5a05cecf3cfa38c"> 1215</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t FRCR; </div>
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<div class="line"><a name="l01216"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gad9976416e6199c8c1f7bcdabe20e4bd2"> 1216</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SLOTR; </div>
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<div class="line"><a name="l01217"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga56001d4b130f392c99dde9a06379af96"> 1217</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t IMR; </div>
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<div class="line"><a name="l01218"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaaef957d89b76c3fa2c09ff61ee0db11d"> 1218</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SR; </div>
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<div class="line"><a name="l01219"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaefcc864961c2bb0465e2ced3bd8b4a14"> 1219</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CLRFR; </div>
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<div class="line"><a name="l01220"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gad1505a32bdca9a2f8da708c7372cdafc"> 1220</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DR; </div>
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<div class="line"><a name="l01221"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga52dffdfbe572129cc142023f3daeeffe"> 1221</a></span> } <a class="code" href="struct_s_a_i___block___type_def.html">SAI_Block_TypeDef</a>;</div>
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<div class="line"><a name="l01222"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga9217ce4fb1e7e16dc0ead8523a6c045a"> 1222</a></span> </div>
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<div class="line"><a name="l01227"></a><span class="lineno"> 1227</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l01228"></a><span class="lineno"> 1228</span> {</div>
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<div class="line"><a name="l01229"></a><span class="lineno"><a class="line" href="struct_s_d_i_o___type_def.html"> 1229</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t POWER; </div>
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<div class="line"><a name="l01230"></a><span class="lineno"> 1230</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CLKCR; </div>
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<div class="line"><a name="l01231"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga7c156bc55f6d970a846a459d57a9e940"> 1231</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ARG; </div>
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<div class="line"><a name="l01232"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaeb1e30ce2038628e45264f75e5e926bb"> 1232</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CMD; </div>
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<div class="line"><a name="l01233"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga3e24392875e98cd09043e54a0990ab7a"> 1233</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t RESPCMD; </div>
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<div class="line"><a name="l01234"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gabbbdc3174e12dab21123d746d65f345d"> 1234</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t RESP1; </div>
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<div class="line"><a name="l01235"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga9d881ed6c2fdecf77e872bcc6b404774"> 1235</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t RESP2; </div>
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<div class="line"><a name="l01236"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga2b6f1ca5a5a50f8ef5417fe7be22553c"> 1236</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t RESP3; </div>
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<div class="line"><a name="l01237"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga9228c8a38c07c508373644220dd322f0"> 1237</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t RESP4; </div>
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<div class="line"><a name="l01238"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga70f3e911570bd326bff852664fd8a7d5"> 1238</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DTIMER; </div>
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<div class="line"><a name="l01239"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gac7b45c7672922d38ffb0a1415a122716"> 1239</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DLEN; </div>
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<div class="line"><a name="l01240"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga5af1984c7c00890598ca74fc85449f9f"> 1240</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DCTRL; </div>
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<div class="line"><a name="l01241"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaa98ab507ed05468ca4baccd1731231cd"> 1241</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t DCOUNT; </div>
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<div class="line"><a name="l01242"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga801519a7af801ad43b88007bf4e2e906"> 1242</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t STA; </div>
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<div class="line"><a name="l01243"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga0366564e2795952d520c0de4be70020f"> 1243</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ICR; </div>
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<div class="line"><a name="l01244"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga6b917b09c127e77bd3128bbe19a00499"> 1244</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MASK; </div>
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<div class="line"><a name="l01245"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gae3c052b85cc438d2b3069f99620e5139"> 1245</a></span>  uint32_t RESERVED0[2]; </div>
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<div class="line"><a name="l01246"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga9a08e405ab985c60ff9031025ab37d31"> 1246</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t FIFOCNT; </div>
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<div class="line"><a name="l01247"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga33cb9d9c17ad0f0c3071cac5e75297a9"> 1247</a></span>  uint32_t RESERVED1[13]; </div>
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<div class="line"><a name="l01248"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gae30d52b6556f5d17db8e5cfd2641e7b4"> 1248</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t FIFO; </div>
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<div class="line"><a name="l01249"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga4017b35303754e115249d3c75bdf6894"> 1249</a></span> } <a class="code" href="struct_s_d_i_o___type_def.html">SDIO_TypeDef</a>;</div>
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<div class="line"><a name="l01250"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gab4757027388ea3a0a6f114d7de2ed4cf"> 1250</a></span> </div>
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<div class="line"><a name="l01255"></a><span class="lineno"> 1255</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l01256"></a><span class="lineno"> 1256</span> {</div>
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<div class="line"><a name="l01257"></a><span class="lineno"><a class="line" href="struct_s_p_i___type_def.html"> 1257</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t CR1; </div>
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<div class="line"><a name="l01258"></a><span class="lineno"> 1258</span>  uint16_t RESERVED0; </div>
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<div class="line"><a name="l01259"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga1e398155ddd013fcdd41309b4bd0bd5f"> 1259</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t CR2; </div>
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<div class="line"><a name="l01260"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga7f16c40933b8a713085436be72d30a46"> 1260</a></span>  uint16_t RESERVED1; </div>
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<div class="line"><a name="l01261"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gac891e34644b8dc27bacc906cfd18b235"> 1261</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t SR; </div>
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<div class="line"><a name="l01262"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga1b7a800c0f56532a431b19cf868e4102"> 1262</a></span>  uint16_t RESERVED2; </div>
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<div class="line"><a name="l01263"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga017d7d54a7bf1925facea6b5e02fec83"> 1263</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t DR; </div>
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<div class="line"><a name="l01264"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga09ce56649bb5477e2fcf3e92bca8f735"> 1264</a></span>  uint16_t RESERVED3; </div>
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<div class="line"><a name="l01265"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gae192c943732b6ab5e5611e860cc05544"> 1265</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t CRCPR; </div>
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<div class="line"><a name="l01266"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaeb1d1d561f1d51232369197fa7acb53a"> 1266</a></span>  uint16_t RESERVED4; </div>
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<div class="line"><a name="l01267"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga353c64e49ec9ae93b950668941f41175"> 1267</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t RXCRCR; </div>
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<div class="line"><a name="l01268"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga20e3ac1445ed1e7a9792ca492c46a73a"> 1268</a></span>  uint16_t RESERVED5; </div>
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<div class="line"><a name="l01269"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gab53da6fb851d911ae0b1166be2cfe48a"> 1269</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t TXCRCR; </div>
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<div class="line"><a name="l01270"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gab63440e38c7872a8ed11fb2d8d94714e"> 1270</a></span>  uint16_t RESERVED6; </div>
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<div class="line"><a name="l01271"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga3c0c1be66bc0a1846274a7511f4a36f5"> 1271</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t I2SCFGR; </div>
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<div class="line"><a name="l01272"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga0870177921541602a44f744f1b66e823"> 1272</a></span>  uint16_t RESERVED7; </div>
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<div class="line"><a name="l01273"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga20a4775ce461eec0d9a437bed464c0a5"> 1273</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t I2SPR; </div>
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<div class="line"><a name="l01274"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga98df0a538eb077b2cfc5194eda200f1b"> 1274</a></span>  uint16_t RESERVED8; </div>
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<div class="line"><a name="l01275"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaecee11b0d2e534b5243e9db6a0e10026"> 1275</a></span> } <a class="code" href="struct_s_p_i___type_def.html">SPI_TypeDef</a>;</div>
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<div class="line"><a name="l01276"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga0ffe762827b71caff20c75bf105387f6"> 1276</a></span> </div>
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<div class="line"><a name="l01281"></a><span class="lineno"> 1281</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l01282"></a><span class="lineno"> 1282</span> {</div>
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<div class="line"><a name="l01283"></a><span class="lineno"><a class="line" href="struct_t_i_m___type_def.html"> 1283</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t CR1; </div>
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<div class="line"><a name="l01284"></a><span class="lineno"> 1284</span>  uint16_t RESERVED0; </div>
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<div class="line"><a name="l01285"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga410988826004fdd21d55071215144ba9"> 1285</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t CR2; </div>
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<div class="line"><a name="l01286"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga88caad1e82960cc6df99d935ece26c1b"> 1286</a></span>  uint16_t RESERVED1; </div>
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<div class="line"><a name="l01287"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga954eb69fd4e2e6b43ba6c80986f691d8"> 1287</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t SMCR; </div>
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<div class="line"><a name="l01288"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga59c46ac3a56c6966a7f8f379a2fd1e3e"> 1288</a></span>  uint16_t RESERVED2; </div>
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<div class="line"><a name="l01289"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga476012f1b4567ffc21ded0b5fd50985e"> 1289</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t DIER; </div>
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<div class="line"><a name="l01290"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaf62f86f55f2a387518f3de10d916eb7c"> 1290</a></span>  uint16_t RESERVED3; </div>
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<div class="line"><a name="l01291"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga25b145e57a694bb384eee08fcd107c3a"> 1291</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t SR; </div>
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|
<div class="line"><a name="l01292"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga8f952613a22049f3ea2b50b7e0d10472"> 1292</a></span>  uint16_t RESERVED4; </div>
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<div class="line"><a name="l01293"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaf686e22c1792dc59dfeffe451d47cf13"> 1293</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t EGR; </div>
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<div class="line"><a name="l01294"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga36afe894c9b0878347d0c038c80e4c22"> 1294</a></span>  uint16_t RESERVED5; </div>
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<div class="line"><a name="l01295"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga724fd21b7131fb9ac78c1b661dee3a8d"> 1295</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t CCMR1; </div>
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<div class="line"><a name="l01296"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga15944db86d7a7a69db35512f68eca15c"> 1296</a></span>  uint16_t RESERVED6; </div>
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<div class="line"><a name="l01297"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga9094f9bb312461d2fc1499f5f8d91c64"> 1297</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t CCMR2; </div>
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|
<div class="line"><a name="l01298"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga7fd09a4911f813464a454b507832a0b9"> 1298</a></span>  uint16_t RESERVED7; </div>
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<div class="line"><a name="l01299"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga22bb9f39aae46365d3ec3c5973f90039"> 1299</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t CCER; </div>
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<div class="line"><a name="l01300"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga4157fa8f6e188281292f019ea24f5599"> 1300</a></span>  uint16_t RESERVED8; </div>
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<div class="line"><a name="l01301"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga2a7ebf9d3041dc20da591668d916f5bc"> 1301</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CNT; </div>
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<div class="line"><a name="l01302"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gac708e4f0f142ac14d7e1c46778ed6f96"> 1302</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t PSC; </div>
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<div class="line"><a name="l01303"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga6fdd2a7fb88d28670b472aaac0d9d262"> 1303</a></span>  uint16_t RESERVED9; </div>
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<div class="line"><a name="l01304"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gad58e05db30d309608402a69d87c36505"> 1304</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ARR; </div>
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<div class="line"><a name="l01305"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga6754dd714ff0885e8e511977d2f393ce"> 1305</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t RCR; </div>
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<div class="line"><a name="l01306"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga6a42766a6ca3c7fe10a810ebd6b9d627"> 1306</a></span>  uint16_t RESERVED10; </div>
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<div class="line"><a name="l01307"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaa6957ece6ee709031ab5241d6019fcce"> 1307</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CCR1; </div>
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<div class="line"><a name="l01308"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gab0e228ff39a37b472aa48ba3afd18333"> 1308</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CCR2; </div>
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<div class="line"><a name="l01309"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga0dd9c06729a5eb6179c6d0d60faca7ed"> 1309</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CCR3; </div>
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<div class="line"><a name="l01310"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga4d1171e9a61538424b8ef1f2571986d0"> 1310</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CCR4; </div>
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<div class="line"><a name="l01311"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gac83441bfb8d0287080dcbd945a272a74"> 1311</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t BDTR; </div>
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<div class="line"><a name="l01312"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga5ba381c3f312fdf5e0b4119641b3b0aa"> 1312</a></span>  uint16_t RESERVED11; </div>
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<div class="line"><a name="l01313"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga32bbedb8b418359c6873375ec949cf8b"> 1313</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t DCR; </div>
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<div class="line"><a name="l01314"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga7a96436f300141eb48768ffa90ee6e71"> 1314</a></span>  uint16_t RESERVED12; </div>
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<div class="line"><a name="l01315"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gad3186a43824621f049e7eff37c88ad4e"> 1315</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t DMAR; </div>
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<div class="line"><a name="l01316"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga994061b8b26ae9b2e8ddb981cb3eec11"> 1316</a></span>  uint16_t RESERVED13; </div>
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<div class="line"><a name="l01317"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga4e0fbb52e6dd4bdabcb3f3b2f4bae40c"> 1317</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t OR; </div>
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<div class="line"><a name="l01318"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga5a831b0a42a5428fbbfd550b7a9c8108"> 1318</a></span>  uint16_t RESERVED14; </div>
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<div class="line"><a name="l01319"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga145760563b46fcdeedddf7c92ee68d61"> 1319</a></span> } <a class="code" href="struct_t_i_m___type_def.html">TIM_TypeDef</a>;</div>
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<div class="line"><a name="l01320"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga548510ebbe395a3947dbbc49fcccec0d"> 1320</a></span> </div>
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<div class="line"><a name="l01325"></a><span class="lineno"> 1325</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l01326"></a><span class="lineno"> 1326</span> {</div>
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<div class="line"><a name="l01327"></a><span class="lineno"><a class="line" href="struct_u_s_a_r_t___type_def.html"> 1327</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t SR; </div>
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<div class="line"><a name="l01328"></a><span class="lineno"> 1328</span>  uint16_t RESERVED0; </div>
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<div class="line"><a name="l01329"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga3f1fd9f0c004d3087caeba4815faa41c"> 1329</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t DR; </div>
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<div class="line"><a name="l01330"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga84ccd64c74c8dbc78b94172ce759de10"> 1330</a></span>  uint16_t RESERVED1; </div>
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<div class="line"><a name="l01331"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaccee34aaec89aad4aeef512bba173ae5"> 1331</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t BRR; </div>
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<div class="line"><a name="l01332"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga6d78680272a465db0ee43eba4e9c54f3"> 1332</a></span>  uint16_t RESERVED2; </div>
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<div class="line"><a name="l01333"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga2044eb2a0a8a731400d309741bceb2f7"> 1333</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t CR1; </div>
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<div class="line"><a name="l01334"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaf2b7924854e56d0ebd3e8699dfd0e369"> 1334</a></span>  uint16_t RESERVED3; </div>
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<div class="line"><a name="l01335"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga5de50313b1437f7f926093f00902d37a"> 1335</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t CR2; </div>
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<div class="line"><a name="l01336"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga158066c974911c14efd7ea492ea31137"> 1336</a></span>  uint16_t RESERVED4; </div>
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<div class="line"><a name="l01337"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga2a494156d185762e4596696796c393bc"> 1337</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t CR3; </div>
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<div class="line"><a name="l01338"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga6ac527c7428ad8807a7740c1f33f0351"> 1338</a></span>  uint16_t RESERVED5; </div>
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<div class="line"><a name="l01339"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga2b9d1df38cb1d745305c8190a8707a0f"> 1339</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint16_t GTPR; </div>
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<div class="line"><a name="l01340"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaa893512291681dfbecc5baa899cfafbf"> 1340</a></span>  uint16_t RESERVED6; </div>
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<div class="line"><a name="l01341"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gabe51502097b1fd281d0a2a1b157d769e"> 1341</a></span> } <a class="code" href="struct_u_s_a_r_t___type_def.html">USART_TypeDef</a>;</div>
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<div class="line"><a name="l01342"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gacd89bb1cba0381c2be8a551e6d14e9f7"> 1342</a></span> </div>
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<div class="line"><a name="l01347"></a><span class="lineno"> 1347</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l01348"></a><span class="lineno"> 1348</span> {</div>
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<div class="line"><a name="l01349"></a><span class="lineno"><a class="line" href="struct_w_w_d_g___type_def.html"> 1349</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CR; </div>
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<div class="line"><a name="l01350"></a><span class="lineno"> 1350</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CFR; </div>
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<div class="line"><a name="l01351"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga4caf530d45f7428c9700d9c0057135f8"> 1351</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SR; </div>
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<div class="line"><a name="l01352"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gadcd6a7e5d75022e46ce60291f4b8544c"> 1352</a></span> } <a class="code" href="struct_w_w_d_g___type_def.html">WWDG_TypeDef</a>;</div>
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<div class="line"><a name="l01353"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga15655cda4854cc794db1f27b3c0bba38"> 1353</a></span> </div>
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<div class="line"><a name="l01358"></a><span class="lineno"> 1358</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l01359"></a><span class="lineno"> 1359</span> {</div>
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<div class="line"><a name="l01360"></a><span class="lineno"><a class="line" href="struct_c_r_y_p___type_def.html"> 1360</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CR; </div>
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<div class="line"><a name="l01361"></a><span class="lineno"> 1361</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SR; </div>
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<div class="line"><a name="l01362"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga65da2a40a06c5c391cbe346dbaa5380c"> 1362</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DR; </div>
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<div class="line"><a name="l01363"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga1d5cabaf9aea97e1b6f08352bc249094"> 1363</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DOUT; </div>
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<div class="line"><a name="l01364"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gab478a4717a3fa209b9c060ecaf70c9a1"> 1364</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DMACR; </div>
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<div class="line"><a name="l01365"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga0b3e1f1551d11a01f7b2356e91281e7d"> 1365</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t IMSCR; </div>
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<div class="line"><a name="l01366"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gad525241894427fc83a16e3370bb5b1d8"> 1366</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RISR; </div>
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<div class="line"><a name="l01367"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga3ee13f960f6631c574b1018c97f95925"> 1367</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t MISR; </div>
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<div class="line"><a name="l01368"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga04be1b2f14a37aed1deff4d57e6261dd"> 1368</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t K0LR; </div>
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<div class="line"><a name="l01369"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaa807ff93c7ce98e9d13cbc52d245770f"> 1369</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t K0RR; </div>
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<div class="line"><a name="l01370"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga9dc2c37bda5dd59196c295be21c1f88b"> 1370</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t K1LR; </div>
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<div class="line"><a name="l01371"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga2a1fdc979620667cc9c40c5caa5cd6ba"> 1371</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t K1RR; </div>
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<div class="line"><a name="l01372"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga816fc42432d8064efbf944430e45050d"> 1372</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t K2LR; </div>
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<div class="line"><a name="l01373"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga496e0b1dee706ce76274ae74ee4e8095"> 1373</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t K2RR; </div>
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<div class="line"><a name="l01374"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaa0dc0e8f97e7b7333083c1429c41bca8"> 1374</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t K3LR; </div>
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<div class="line"><a name="l01375"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga96ef270d5244bd331fb8db5b0deffb4a"> 1375</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t K3RR; </div>
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<div class="line"><a name="l01376"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga39e099c27b2be81a03c09810f390454b"> 1376</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t IV0LR; </div>
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<div class="line"><a name="l01377"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga1c3230419aed39ab61263b87547cbc3e"> 1377</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t IV0RR; </div>
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<div class="line"><a name="l01378"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga3b9c6cf4e4ef58624504b08a5fc2242d"> 1378</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t IV1LR; </div>
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<div class="line"><a name="l01379"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga4d6479478d84d3b85dcebb667ad963de"> 1379</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t IV1RR; </div>
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|
<div class="line"><a name="l01380"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga8d837d2677d8ca1d8ed8bc018d6bb176"> 1380</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CSGCMCCM0R; </div>
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<div class="line"><a name="l01381"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaca99392151eb711971f5260ca675c81b"> 1381</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CSGCMCCM1R; </div>
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<div class="line"><a name="l01382"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga926db5a8be35fdd38102fb4b9d3a12ed"> 1382</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CSGCMCCM2R; </div>
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<div class="line"><a name="l01383"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga4851d377da2a935b55cb832befef6b4e"> 1383</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CSGCMCCM3R; </div>
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<div class="line"><a name="l01384"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gad79968d5d5f78b8092c4de4e2c2c667b"> 1384</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CSGCMCCM4R; </div>
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<div class="line"><a name="l01385"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga4b7a644727bdc5f4c18d546968a61012"> 1385</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CSGCMCCM5R; </div>
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<div class="line"><a name="l01386"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gae78c4644295e025c55630d78f11e4b1f"> 1386</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CSGCMCCM6R; </div>
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<div class="line"><a name="l01387"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga4ec4296951d313a1cf46367832752701"> 1387</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CSGCMCCM7R; </div>
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<div class="line"><a name="l01388"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga2f9c622eea7f715471d37025beed5a46"> 1388</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CSGCM0R; </div>
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<div class="line"><a name="l01389"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga2798980d0154fe0dfadc7419655f8c49"> 1389</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CSGCM1R; </div>
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<div class="line"><a name="l01390"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gac981185bb8c7a4c3cf75e25b06741ac3"> 1390</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CSGCM2R; </div>
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<div class="line"><a name="l01391"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga6b3c0b0492c1941412dbe5abd1f64566"> 1391</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CSGCM3R; </div>
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<div class="line"><a name="l01392"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga3b14b272307919449e84c96247e92dff"> 1392</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CSGCM4R; </div>
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<div class="line"><a name="l01393"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga040ae185cd8181a78b40d0115466405b"> 1393</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CSGCM5R; </div>
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<div class="line"><a name="l01394"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gab656f3f8c56857eb0b6ac5a3897254c5"> 1394</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CSGCM6R; </div>
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<div class="line"><a name="l01395"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga064e623ceccfdb07a7857aa20273dd33"> 1395</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CSGCM7R; </div>
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<div class="line"><a name="l01396"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gaf4b7c440d7156226fd2788c366b9eaba"> 1396</a></span> } <a class="code" href="struct_c_r_y_p___type_def.html">CRYP_TypeDef</a>;</div>
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<div class="line"><a name="l01397"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gadc9500a1222f448f5598e39a5998883f"> 1397</a></span> </div>
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<div class="line"><a name="l01402"></a><span class="lineno"> 1402</span> <span class="keyword">typedef</span> <span class="keyword">struct </span></div>
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<div class="line"><a name="l01403"></a><span class="lineno"> 1403</span> {</div>
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<div class="line"><a name="l01404"></a><span class="lineno"><a class="line" href="struct_h_a_s_h___type_def.html"> 1404</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CR; </div>
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<div class="line"><a name="l01405"></a><span class="lineno"> 1405</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DIN; </div>
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<div class="line"><a name="l01406"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gadba940f3265121b77f9304b1843010ea"> 1406</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t STR; </div>
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<div class="line"><a name="l01407"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gac4f283960465f7a1d318ed66d4b88f74"> 1407</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t HR[5]; </div>
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<div class="line"><a name="l01408"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga4b07bc8eb36129062d3f331921316d66"> 1408</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t IMR; </div>
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<div class="line"><a name="l01409"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gacb0d3ac4cdf8c478ca0ffeebadc04840"> 1409</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SR; </div>
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<div class="line"><a name="l01410"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga01011d00eb28b8798af8c5dfedf6f35d"> 1410</a></span>  uint32_t RESERVED[52]; </div>
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<div class="line"><a name="l01411"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga8af8c27ac134cbeb13af4e4e856de537"> 1411</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CSR[54]; </div>
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<div class="line"><a name="l01412"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga9f95e7cb8f85cae58cc429e14e96f663"> 1412</a></span> } <a class="code" href="struct_h_a_s_h___type_def.html">HASH_TypeDef</a>;</div>
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<div class="line"><a name="l01413"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga4a5c1f1632eefa894a966313663e9337"> 1413</a></span> </div>
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<div class="line"><a name="l01418"></a><span class="lineno"> 1418</span> <span class="keyword">typedef</span> <span class="keyword">struct </span></div>
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<div class="line"><a name="l01419"></a><span class="lineno"> 1419</span> {</div>
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<div class="line"><a name="l01420"></a><span class="lineno"><a class="line" href="struct_h_a_s_h___d_i_g_e_s_t___type_def.html"> 1420</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t HR[8]; </div>
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<div class="line"><a name="l01421"></a><span class="lineno"> 1421</span> } <a class="code" href="struct_h_a_s_h___d_i_g_e_s_t___type_def.html">HASH_DIGEST_TypeDef</a>;</div>
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<div class="line"><a name="l01422"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga13ebb694ffb07e21fb7869e4006f41c5"> 1422</a></span> </div>
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<div class="line"><a name="l01427"></a><span class="lineno"> 1427</span> <span class="keyword">typedef</span> <span class="keyword">struct </span></div>
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<div class="line"><a name="l01428"></a><span class="lineno"> 1428</span> {</div>
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<div class="line"><a name="l01429"></a><span class="lineno"><a class="line" href="struct_r_n_g___type_def.html"> 1429</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CR; </div>
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<div class="line"><a name="l01430"></a><span class="lineno"> 1430</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SR; </div>
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<div class="line"><a name="l01431"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#gab422a7aeea33d29d0f8b841bb461e3a8"> 1431</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DR; </div>
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<div class="line"><a name="l01432"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga4e4c38cd6a078fea5f9fa5e31bc0d326"> 1432</a></span> } <a class="code" href="struct_r_n_g___type_def.html">RNG_TypeDef</a>;</div>
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<div class="line"><a name="l01433"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s.html#ga89f3352fb11cca430aaecc0c9b49c6d3"> 1433</a></span> </div>
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<div class="line"><a name="l01441"></a><span class="lineno"> 1441</span> <span class="preprocessor">#define FLASH_BASE ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l01442"></a><span class="lineno"> 1442</span> <span class="preprocessor">#define CCMDATARAM_BASE ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l01443"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga23a9099a5f8fc9c6e253c0eecb2be8db"> 1443</a></span> <span class="preprocessor">#define SRAM1_BASE ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l01444"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gabea1f1810ebeac402164b42ab54bcdf9"> 1444</a></span> <span class="preprocessor">#define SRAM2_BASE ((uint32_t)0x2001C000) </span></div>
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<div class="line"><a name="l01445"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga7d0fbfb8894012dbbb96754b95e562cd"> 1445</a></span> <span class="preprocessor">#define SRAM3_BASE ((uint32_t)0x20020000) </span></div>
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<div class="line"><a name="l01446"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gadbb42a3d0a8a90a79d2146e4014241b1"> 1446</a></span> <span class="preprocessor">#define PERIPH_BASE ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l01447"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gadb41012a2428a526d7ee5ff0f61d2344"> 1447</a></span> <span class="preprocessor">#define BKPSRAM_BASE ((uint32_t)0x40024000) </span></div>
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<div class="line"><a name="l01449"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#ga52e57051bdf8909222b36e5408a48f32"> 1449</a></span> <span class="preprocessor">#if defined (STM32F40_41xxx)</span></div>
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<div class="line"><a name="l01450"></a><span class="lineno"> 1450</span> <span class="preprocessor">#define FSMC_R_BASE ((uint32_t)0xA0000000) </span></div>
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<div class="line"><a name="l01451"></a><span class="lineno"> 1451</span> <span class="preprocessor">#endif </span><span class="comment">/* STM32F40_41xxx */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l01452"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaddf0e199dccba83272b20c9fb4d3aaed"> 1452</a></span> </div>
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<div class="line"><a name="l01453"></a><span class="lineno"> 1453</span> <span class="preprocessor">#if defined (STM32F427_437xx) || defined (STM32F429_439xx)</span></div>
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<div class="line"><a name="l01454"></a><span class="lineno"> 1454</span> <span class="preprocessor">#define FMC_R_BASE ((uint32_t)0xA0000000) </span></div>
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<div class="line"><a name="l01455"></a><span class="lineno"> 1455</span> <span class="preprocessor">#endif </span><span class="comment">/* STM32F427_437xx || STM32F429_439xx */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l01456"></a><span class="lineno"> 1456</span> </div>
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<div class="line"><a name="l01457"></a><span class="lineno"> 1457</span> <span class="preprocessor">#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) </span></div>
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<div class="line"><a name="l01458"></a><span class="lineno"> 1458</span> <span class="preprocessor">#define SRAM1_BB_BASE ((uint32_t)0x22000000) </span></div>
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<div class="line"><a name="l01459"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaf98d1f99ecd952ee59e80b345d835bb0"> 1459</a></span> <span class="preprocessor">#define SRAM2_BB_BASE ((uint32_t)0x2201C000) </span></div>
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<div class="line"><a name="l01460"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gac4c4f61082e4b168f29d9cf97dc3ca5c"> 1460</a></span> <span class="preprocessor">#define SRAM3_BB_BASE ((uint32_t)0x22400000) </span></div>
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<div class="line"><a name="l01461"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gac33cb6edadf184ab9860d77089503922"> 1461</a></span> <span class="preprocessor">#define PERIPH_BB_BASE ((uint32_t)0x42000000) </span></div>
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<div class="line"><a name="l01462"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaebfa4db60f9ac39c7c7f3fed98090410"> 1462</a></span> <span class="preprocessor">#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) </span></div>
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<div class="line"><a name="l01464"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gaee19a30c9fa326bb10b547e4eaf4e250"> 1464</a></span> <span class="preprocessor"></span><span class="comment">/* Legacy defines */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l01465"></a><span class="lineno"> 1465</span> <span class="preprocessor">#define SRAM_BASE SRAM1_BASE</span></div>
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|
<div class="line"><a name="l01466"></a><span class="lineno"> 1466</span> <span class="preprocessor">#define SRAM_BB_BASE SRAM1_BB_BASE</span></div>
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|
<div class="line"><a name="l01467"></a><span class="lineno"> 1467</span> </div>
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<div class="line"><a name="l01468"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gad3548b6e2f017f39d399358f3ac98454"> 1468</a></span> </div>
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|
<div class="line"><a name="l01470"></a><span class="lineno"> 1470</span> <span class="preprocessor">#define APB1PERIPH_BASE PERIPH_BASE</span></div>
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|
<div class="line"><a name="l01471"></a><span class="lineno"> 1471</span> <span class="preprocessor">#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)</span></div>
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|
<div class="line"><a name="l01472"></a><span class="lineno"> 1472</span> <span class="preprocessor">#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)</span></div>
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|
<div class="line"><a name="l01473"></a><span class="lineno"> 1473</span> <span class="preprocessor">#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)</span></div>
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|
<div class="line"><a name="l01474"></a><span class="lineno"> 1474</span> </div>
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|
<div class="line"><a name="l01476"></a><span class="lineno"> 1476</span> <span class="preprocessor">#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)</span></div>
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|
<div class="line"><a name="l01477"></a><span class="lineno"> 1477</span> <span class="preprocessor">#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)</span></div>
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|
<div class="line"><a name="l01478"></a><span class="lineno"> 1478</span> <span class="preprocessor">#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)</span></div>
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|
<div class="line"><a name="l01479"></a><span class="lineno"> 1479</span> <span class="preprocessor">#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)</span></div>
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|
<div class="line"><a name="l01480"></a><span class="lineno"> 1480</span> <span class="preprocessor">#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)</span></div>
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|
<div class="line"><a name="l01481"></a><span class="lineno"> 1481</span> <span class="preprocessor">#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)</span></div>
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|
<div class="line"><a name="l01482"></a><span class="lineno"> 1482</span> <span class="preprocessor">#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)</span></div>
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|
<div class="line"><a name="l01483"></a><span class="lineno"> 1483</span> <span class="preprocessor">#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)</span></div>
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|
<div class="line"><a name="l01484"></a><span class="lineno"> 1484</span> <span class="preprocessor">#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)</span></div>
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|
<div class="line"><a name="l01485"></a><span class="lineno"> 1485</span> <span class="preprocessor">#define RTC_BASE (APB1PERIPH_BASE + 0x2800)</span></div>
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|
<div class="line"><a name="l01486"></a><span class="lineno"> 1486</span> <span class="preprocessor">#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)</span></div>
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|
<div class="line"><a name="l01487"></a><span class="lineno"> 1487</span> <span class="preprocessor">#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)</span></div>
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|
<div class="line"><a name="l01488"></a><span class="lineno"> 1488</span> <span class="preprocessor">#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)</span></div>
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|
<div class="line"><a name="l01489"></a><span class="lineno"> 1489</span> <span class="preprocessor">#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)</span></div>
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|
<div class="line"><a name="l01490"></a><span class="lineno"> 1490</span> <span class="preprocessor">#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)</span></div>
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|
<div class="line"><a name="l01491"></a><span class="lineno"> 1491</span> <span class="preprocessor">#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)</span></div>
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|
<div class="line"><a name="l01492"></a><span class="lineno"> 1492</span> <span class="preprocessor">#define USART2_BASE (APB1PERIPH_BASE + 0x4400)</span></div>
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|
<div class="line"><a name="l01493"></a><span class="lineno"> 1493</span> <span class="preprocessor">#define USART3_BASE (APB1PERIPH_BASE + 0x4800)</span></div>
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|
<div class="line"><a name="l01494"></a><span class="lineno"> 1494</span> <span class="preprocessor">#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)</span></div>
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|
<div class="line"><a name="l01495"></a><span class="lineno"> 1495</span> <span class="preprocessor">#define UART5_BASE (APB1PERIPH_BASE + 0x5000)</span></div>
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|
<div class="line"><a name="l01496"></a><span class="lineno"> 1496</span> <span class="preprocessor">#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)</span></div>
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|
<div class="line"><a name="l01497"></a><span class="lineno"> 1497</span> <span class="preprocessor">#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)</span></div>
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|
<div class="line"><a name="l01498"></a><span class="lineno"> 1498</span> <span class="preprocessor">#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)</span></div>
|
|
<div class="line"><a name="l01499"></a><span class="lineno"> 1499</span> <span class="preprocessor">#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)</span></div>
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|
<div class="line"><a name="l01500"></a><span class="lineno"> 1500</span> <span class="preprocessor">#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)</span></div>
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|
<div class="line"><a name="l01501"></a><span class="lineno"> 1501</span> <span class="preprocessor">#define PWR_BASE (APB1PERIPH_BASE + 0x7000)</span></div>
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|
<div class="line"><a name="l01502"></a><span class="lineno"> 1502</span> <span class="preprocessor">#define DAC_BASE (APB1PERIPH_BASE + 0x7400)</span></div>
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|
<div class="line"><a name="l01503"></a><span class="lineno"> 1503</span> <span class="preprocessor">#define UART7_BASE (APB1PERIPH_BASE + 0x7800)</span></div>
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|
<div class="line"><a name="l01504"></a><span class="lineno"> 1504</span> <span class="preprocessor">#define UART8_BASE (APB1PERIPH_BASE + 0x7C00)</span></div>
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|
<div class="line"><a name="l01505"></a><span class="lineno"> 1505</span> </div>
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|
<div class="line"><a name="l01507"></a><span class="lineno"> 1507</span> <span class="preprocessor">#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)</span></div>
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|
<div class="line"><a name="l01508"></a><span class="lineno"> 1508</span> <span class="preprocessor">#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)</span></div>
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|
<div class="line"><a name="l01509"></a><span class="lineno"> 1509</span> <span class="preprocessor">#define USART1_BASE (APB2PERIPH_BASE + 0x1000)</span></div>
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|
<div class="line"><a name="l01510"></a><span class="lineno"> 1510</span> <span class="preprocessor">#define USART6_BASE (APB2PERIPH_BASE + 0x1400)</span></div>
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|
<div class="line"><a name="l01511"></a><span class="lineno"> 1511</span> <span class="preprocessor">#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)</span></div>
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|
<div class="line"><a name="l01512"></a><span class="lineno"> 1512</span> <span class="preprocessor">#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)</span></div>
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|
<div class="line"><a name="l01513"></a><span class="lineno"> 1513</span> <span class="preprocessor">#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)</span></div>
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|
<div class="line"><a name="l01514"></a><span class="lineno"> 1514</span> <span class="preprocessor">#define ADC_BASE (APB2PERIPH_BASE + 0x2300)</span></div>
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|
<div class="line"><a name="l01515"></a><span class="lineno"> 1515</span> <span class="preprocessor">#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)</span></div>
|
|
<div class="line"><a name="l01516"></a><span class="lineno"> 1516</span> <span class="preprocessor">#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)</span></div>
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|
<div class="line"><a name="l01517"></a><span class="lineno"> 1517</span> <span class="preprocessor">#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)</span></div>
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|
<div class="line"><a name="l01518"></a><span class="lineno"> 1518</span> <span class="preprocessor">#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)</span></div>
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|
<div class="line"><a name="l01519"></a><span class="lineno"> 1519</span> <span class="preprocessor">#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)</span></div>
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|
<div class="line"><a name="l01520"></a><span class="lineno"> 1520</span> <span class="preprocessor">#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)</span></div>
|
|
<div class="line"><a name="l01521"></a><span class="lineno"> 1521</span> <span class="preprocessor">#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)</span></div>
|
|
<div class="line"><a name="l01522"></a><span class="lineno"> 1522</span> <span class="preprocessor">#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)</span></div>
|
|
<div class="line"><a name="l01523"></a><span class="lineno"> 1523</span> <span class="preprocessor">#define SPI5_BASE (APB2PERIPH_BASE + 0x5000)</span></div>
|
|
<div class="line"><a name="l01524"></a><span class="lineno"> 1524</span> <span class="preprocessor">#define SPI6_BASE (APB2PERIPH_BASE + 0x5400)</span></div>
|
|
<div class="line"><a name="l01525"></a><span class="lineno"> 1525</span> <span class="preprocessor">#define SAI1_BASE (APB2PERIPH_BASE + 0x5800)</span></div>
|
|
<div class="line"><a name="l01526"></a><span class="lineno"> 1526</span> <span class="preprocessor">#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)</span></div>
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|
<div class="line"><a name="l01527"></a><span class="lineno"> 1527</span> <span class="preprocessor">#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)</span></div>
|
|
<div class="line"><a name="l01528"></a><span class="lineno"> 1528</span> <span class="preprocessor">#define LTDC_BASE (APB2PERIPH_BASE + 0x6800)</span></div>
|
|
<div class="line"><a name="l01529"></a><span class="lineno"> 1529</span> <span class="preprocessor">#define LTDC_Layer1_BASE (LTDC_BASE + 0x84)</span></div>
|
|
<div class="line"><a name="l01530"></a><span class="lineno"> 1530</span> <span class="preprocessor">#define LTDC_Layer2_BASE (LTDC_BASE + 0x104) </span></div>
|
|
<div class="line"><a name="l01531"></a><span class="lineno"> 1531</span> </div>
|
|
<div class="line"><a name="l01533"></a><span class="lineno"> 1533</span> <span class="preprocessor">#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)</span></div>
|
|
<div class="line"><a name="l01534"></a><span class="lineno"> 1534</span> <span class="preprocessor">#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)</span></div>
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|
<div class="line"><a name="l01535"></a><span class="lineno"> 1535</span> <span class="preprocessor">#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)</span></div>
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|
<div class="line"><a name="l01536"></a><span class="lineno"> 1536</span> <span class="preprocessor">#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)</span></div>
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|
<div class="line"><a name="l01537"></a><span class="lineno"> 1537</span> <span class="preprocessor">#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)</span></div>
|
|
<div class="line"><a name="l01538"></a><span class="lineno"> 1538</span> <span class="preprocessor">#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)</span></div>
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|
<div class="line"><a name="l01539"></a><span class="lineno"> 1539</span> <span class="preprocessor">#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)</span></div>
|
|
<div class="line"><a name="l01540"></a><span class="lineno"> 1540</span> <span class="preprocessor">#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)</span></div>
|
|
<div class="line"><a name="l01541"></a><span class="lineno"> 1541</span> <span class="preprocessor">#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)</span></div>
|
|
<div class="line"><a name="l01542"></a><span class="lineno"> 1542</span> <span class="preprocessor">#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)</span></div>
|
|
<div class="line"><a name="l01543"></a><span class="lineno"> 1543</span> <span class="preprocessor">#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)</span></div>
|
|
<div class="line"><a name="l01544"></a><span class="lineno"> 1544</span> <span class="preprocessor">#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)</span></div>
|
|
<div class="line"><a name="l01545"></a><span class="lineno"> 1545</span> <span class="preprocessor">#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)</span></div>
|
|
<div class="line"><a name="l01546"></a><span class="lineno"> 1546</span> <span class="preprocessor">#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)</span></div>
|
|
<div class="line"><a name="l01547"></a><span class="lineno"> 1547</span> <span class="preprocessor">#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)</span></div>
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|
<div class="line"><a name="l01548"></a><span class="lineno"> 1548</span> <span class="preprocessor">#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)</span></div>
|
|
<div class="line"><a name="l01549"></a><span class="lineno"> 1549</span> <span class="preprocessor">#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)</span></div>
|
|
<div class="line"><a name="l01550"></a><span class="lineno"> 1550</span> <span class="preprocessor">#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)</span></div>
|
|
<div class="line"><a name="l01551"></a><span class="lineno"> 1551</span> <span class="preprocessor">#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)</span></div>
|
|
<div class="line"><a name="l01552"></a><span class="lineno"> 1552</span> <span class="preprocessor">#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)</span></div>
|
|
<div class="line"><a name="l01553"></a><span class="lineno"> 1553</span> <span class="preprocessor">#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)</span></div>
|
|
<div class="line"><a name="l01554"></a><span class="lineno"> 1554</span> <span class="preprocessor">#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)</span></div>
|
|
<div class="line"><a name="l01555"></a><span class="lineno"> 1555</span> <span class="preprocessor">#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)</span></div>
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|
<div class="line"><a name="l01556"></a><span class="lineno"> 1556</span> <span class="preprocessor">#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)</span></div>
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|
<div class="line"><a name="l01557"></a><span class="lineno"> 1557</span> <span class="preprocessor">#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)</span></div>
|
|
<div class="line"><a name="l01558"></a><span class="lineno"> 1558</span> <span class="preprocessor">#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)</span></div>
|
|
<div class="line"><a name="l01559"></a><span class="lineno"> 1559</span> <span class="preprocessor">#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)</span></div>
|
|
<div class="line"><a name="l01560"></a><span class="lineno"> 1560</span> <span class="preprocessor">#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)</span></div>
|
|
<div class="line"><a name="l01561"></a><span class="lineno"> 1561</span> <span class="preprocessor">#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)</span></div>
|
|
<div class="line"><a name="l01562"></a><span class="lineno"> 1562</span> <span class="preprocessor">#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)</span></div>
|
|
<div class="line"><a name="l01563"></a><span class="lineno"> 1563</span> <span class="preprocessor">#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)</span></div>
|
|
<div class="line"><a name="l01564"></a><span class="lineno"> 1564</span> <span class="preprocessor">#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)</span></div>
|
|
<div class="line"><a name="l01565"></a><span class="lineno"> 1565</span> <span class="preprocessor">#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)</span></div>
|
|
<div class="line"><a name="l01566"></a><span class="lineno"> 1566</span> <span class="preprocessor">#define ETH_MAC_BASE (ETH_BASE)</span></div>
|
|
<div class="line"><a name="l01567"></a><span class="lineno"> 1567</span> <span class="preprocessor">#define ETH_MMC_BASE (ETH_BASE + 0x0100)</span></div>
|
|
<div class="line"><a name="l01568"></a><span class="lineno"> 1568</span> <span class="preprocessor">#define ETH_PTP_BASE (ETH_BASE + 0x0700)</span></div>
|
|
<div class="line"><a name="l01569"></a><span class="lineno"> 1569</span> <span class="preprocessor">#define ETH_DMA_BASE (ETH_BASE + 0x1000)</span></div>
|
|
<div class="line"><a name="l01570"></a><span class="lineno"> 1570</span> <span class="preprocessor">#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)</span></div>
|
|
<div class="line"><a name="l01571"></a><span class="lineno"> 1571</span> </div>
|
|
<div class="line"><a name="l01573"></a><span class="lineno"> 1573</span> <span class="preprocessor">#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)</span></div>
|
|
<div class="line"><a name="l01574"></a><span class="lineno"> 1574</span> <span class="preprocessor">#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)</span></div>
|
|
<div class="line"><a name="l01575"></a><span class="lineno"> 1575</span> <span class="preprocessor">#define HASH_BASE (AHB2PERIPH_BASE + 0x60400)</span></div>
|
|
<div class="line"><a name="l01576"></a><span class="lineno"> 1576</span> <span class="preprocessor">#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710)</span></div>
|
|
<div class="line"><a name="l01577"></a><span class="lineno"> 1577</span> <span class="preprocessor">#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)</span></div>
|
|
<div class="line"><a name="l01578"></a><span class="lineno"> 1578</span> </div>
|
|
<div class="line"><a name="l01579"></a><span class="lineno"><a class="line" href="group___peripheral__memory__map.html#gab92662976cfe62457141e5b4f83d541c"> 1579</a></span> <span class="preprocessor">#if defined (STM32F40_41xxx)</span></div>
|
|
<div class="line"><a name="l01580"></a><span class="lineno"> 1580</span> </div>
|
|
<div class="line"><a name="l01581"></a><span class="lineno"> 1581</span> <span class="preprocessor">#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)</span></div>
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|
<div class="line"><a name="l01582"></a><span class="lineno"> 1582</span> <span class="preprocessor">#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)</span></div>
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|
<div class="line"><a name="l01583"></a><span class="lineno"> 1583</span> <span class="preprocessor">#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)</span></div>
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|
<div class="line"><a name="l01584"></a><span class="lineno"> 1584</span> <span class="preprocessor">#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)</span></div>
|
|
<div class="line"><a name="l01585"></a><span class="lineno"> 1585</span> <span class="preprocessor">#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)</span></div>
|
|
<div class="line"><a name="l01586"></a><span class="lineno"> 1586</span> <span class="preprocessor">#endif </span><span class="comment">/* STM32F40_41xxx */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l01587"></a><span class="lineno"> 1587</span> </div>
|
|
<div class="line"><a name="l01588"></a><span class="lineno"> 1588</span> <span class="preprocessor">#if defined (STM32F427_437xx) || defined (STM32F429_439xx)</span></div>
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|
<div class="line"><a name="l01589"></a><span class="lineno"> 1589</span> </div>
|
|
<div class="line"><a name="l01590"></a><span class="lineno"> 1590</span> <span class="preprocessor">#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)</span></div>
|
|
<div class="line"><a name="l01591"></a><span class="lineno"> 1591</span> <span class="preprocessor">#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)</span></div>
|
|
<div class="line"><a name="l01592"></a><span class="lineno"> 1592</span> <span class="preprocessor">#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060)</span></div>
|
|
<div class="line"><a name="l01593"></a><span class="lineno"> 1593</span> <span class="preprocessor">#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)</span></div>
|
|
<div class="line"><a name="l01594"></a><span class="lineno"> 1594</span> <span class="preprocessor">#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)</span></div>
|
|
<div class="line"><a name="l01595"></a><span class="lineno"> 1595</span> <span class="preprocessor">#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)</span></div>
|
|
<div class="line"><a name="l01596"></a><span class="lineno"> 1596</span> <span class="preprocessor">#endif </span><span class="comment">/* STM32F427_437xx || STM32F429_439xx */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l01597"></a><span class="lineno"> 1597</span> </div>
|
|
<div class="line"><a name="l01598"></a><span class="lineno"> 1598</span> <span class="comment">/* Debug MCU registers base address */</span></div>
|
|
<div class="line"><a name="l01599"></a><span class="lineno"> 1599</span> <span class="preprocessor">#define DBGMCU_BASE ((uint32_t )0xE0042000)</span></div>
|
|
<div class="line"><a name="l01600"></a><span class="lineno"> 1600</span> </div>
|
|
<div class="line"><a name="l01608"></a><span class="lineno"> 1608</span> <span class="preprocessor">#define TIM2 ((TIM_TypeDef *) TIM2_BASE)</span></div>
|
|
<div class="line"><a name="l01609"></a><span class="lineno"> 1609</span> <span class="preprocessor">#define TIM3 ((TIM_TypeDef *) TIM3_BASE)</span></div>
|
|
<div class="line"><a name="l01610"></a><span class="lineno"> 1610</span> <span class="preprocessor">#define TIM4 ((TIM_TypeDef *) TIM4_BASE)</span></div>
|
|
<div class="line"><a name="l01611"></a><span class="lineno"> 1611</span> <span class="preprocessor">#define TIM5 ((TIM_TypeDef *) TIM5_BASE)</span></div>
|
|
<div class="line"><a name="l01612"></a><span class="lineno"> 1612</span> <span class="preprocessor">#define TIM6 ((TIM_TypeDef *) TIM6_BASE)</span></div>
|
|
<div class="line"><a name="l01613"></a><span class="lineno"> 1613</span> <span class="preprocessor">#define TIM7 ((TIM_TypeDef *) TIM7_BASE)</span></div>
|
|
<div class="line"><a name="l01614"></a><span class="lineno"> 1614</span> <span class="preprocessor">#define TIM12 ((TIM_TypeDef *) TIM12_BASE)</span></div>
|
|
<div class="line"><a name="l01615"></a><span class="lineno"> 1615</span> <span class="preprocessor">#define TIM13 ((TIM_TypeDef *) TIM13_BASE)</span></div>
|
|
<div class="line"><a name="l01616"></a><span class="lineno"> 1616</span> <span class="preprocessor">#define TIM14 ((TIM_TypeDef *) TIM14_BASE)</span></div>
|
|
<div class="line"><a name="l01617"></a><span class="lineno"> 1617</span> <span class="preprocessor">#define RTC ((RTC_TypeDef *) RTC_BASE)</span></div>
|
|
<div class="line"><a name="l01618"></a><span class="lineno"> 1618</span> <span class="preprocessor">#define WWDG ((WWDG_TypeDef *) WWDG_BASE)</span></div>
|
|
<div class="line"><a name="l01619"></a><span class="lineno"> 1619</span> <span class="preprocessor">#define IWDG ((IWDG_TypeDef *) IWDG_BASE)</span></div>
|
|
<div class="line"><a name="l01620"></a><span class="lineno"> 1620</span> <span class="preprocessor">#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)</span></div>
|
|
<div class="line"><a name="l01621"></a><span class="lineno"> 1621</span> <span class="preprocessor">#define SPI2 ((SPI_TypeDef *) SPI2_BASE)</span></div>
|
|
<div class="line"><a name="l01622"></a><span class="lineno"> 1622</span> <span class="preprocessor">#define SPI3 ((SPI_TypeDef *) SPI3_BASE)</span></div>
|
|
<div class="line"><a name="l01623"></a><span class="lineno"> 1623</span> <span class="preprocessor">#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)</span></div>
|
|
<div class="line"><a name="l01624"></a><span class="lineno"> 1624</span> <span class="preprocessor">#define USART2 ((USART_TypeDef *) USART2_BASE)</span></div>
|
|
<div class="line"><a name="l01625"></a><span class="lineno"> 1625</span> <span class="preprocessor">#define USART3 ((USART_TypeDef *) USART3_BASE)</span></div>
|
|
<div class="line"><a name="l01626"></a><span class="lineno"> 1626</span> <span class="preprocessor">#define UART4 ((USART_TypeDef *) UART4_BASE)</span></div>
|
|
<div class="line"><a name="l01627"></a><span class="lineno"> 1627</span> <span class="preprocessor">#define UART5 ((USART_TypeDef *) UART5_BASE)</span></div>
|
|
<div class="line"><a name="l01628"></a><span class="lineno"> 1628</span> <span class="preprocessor">#define I2C1 ((I2C_TypeDef *) I2C1_BASE)</span></div>
|
|
<div class="line"><a name="l01629"></a><span class="lineno"> 1629</span> <span class="preprocessor">#define I2C2 ((I2C_TypeDef *) I2C2_BASE)</span></div>
|
|
<div class="line"><a name="l01630"></a><span class="lineno"> 1630</span> <span class="preprocessor">#define I2C3 ((I2C_TypeDef *) I2C3_BASE)</span></div>
|
|
<div class="line"><a name="l01631"></a><span class="lineno"> 1631</span> <span class="preprocessor">#define CAN1 ((CAN_TypeDef *) CAN1_BASE)</span></div>
|
|
<div class="line"><a name="l01632"></a><span class="lineno"> 1632</span> <span class="preprocessor">#define CAN2 ((CAN_TypeDef *) CAN2_BASE)</span></div>
|
|
<div class="line"><a name="l01633"></a><span class="lineno"> 1633</span> <span class="preprocessor">#define PWR ((PWR_TypeDef *) PWR_BASE)</span></div>
|
|
<div class="line"><a name="l01634"></a><span class="lineno"> 1634</span> <span class="preprocessor">#define DAC ((DAC_TypeDef *) DAC_BASE)</span></div>
|
|
<div class="line"><a name="l01635"></a><span class="lineno"> 1635</span> <span class="preprocessor">#define UART7 ((USART_TypeDef *) UART7_BASE)</span></div>
|
|
<div class="line"><a name="l01636"></a><span class="lineno"> 1636</span> <span class="preprocessor">#define UART8 ((USART_TypeDef *) UART8_BASE)</span></div>
|
|
<div class="line"><a name="l01637"></a><span class="lineno"> 1637</span> <span class="preprocessor">#define TIM1 ((TIM_TypeDef *) TIM1_BASE)</span></div>
|
|
<div class="line"><a name="l01638"></a><span class="lineno"> 1638</span> <span class="preprocessor">#define TIM8 ((TIM_TypeDef *) TIM8_BASE)</span></div>
|
|
<div class="line"><a name="l01639"></a><span class="lineno"> 1639</span> <span class="preprocessor">#define USART1 ((USART_TypeDef *) USART1_BASE)</span></div>
|
|
<div class="line"><a name="l01640"></a><span class="lineno"> 1640</span> <span class="preprocessor">#define USART6 ((USART_TypeDef *) USART6_BASE)</span></div>
|
|
<div class="line"><a name="l01641"></a><span class="lineno"> 1641</span> <span class="preprocessor">#define ADC ((ADC_Common_TypeDef *) ADC_BASE)</span></div>
|
|
<div class="line"><a name="l01642"></a><span class="lineno"> 1642</span> <span class="preprocessor">#define ADC1 ((ADC_TypeDef *) ADC1_BASE)</span></div>
|
|
<div class="line"><a name="l01643"></a><span class="lineno"> 1643</span> <span class="preprocessor">#define ADC2 ((ADC_TypeDef *) ADC2_BASE)</span></div>
|
|
<div class="line"><a name="l01644"></a><span class="lineno"> 1644</span> <span class="preprocessor">#define ADC3 ((ADC_TypeDef *) ADC3_BASE)</span></div>
|
|
<div class="line"><a name="l01645"></a><span class="lineno"> 1645</span> <span class="preprocessor">#define SDIO ((SDIO_TypeDef *) SDIO_BASE)</span></div>
|
|
<div class="line"><a name="l01646"></a><span class="lineno"> 1646</span> <span class="preprocessor">#define SPI1 ((SPI_TypeDef *) SPI1_BASE) </span></div>
|
|
<div class="line"><a name="l01647"></a><span class="lineno"> 1647</span> <span class="preprocessor">#define SPI4 ((SPI_TypeDef *) SPI4_BASE)</span></div>
|
|
<div class="line"><a name="l01648"></a><span class="lineno"> 1648</span> <span class="preprocessor">#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)</span></div>
|
|
<div class="line"><a name="l01649"></a><span class="lineno"> 1649</span> <span class="preprocessor">#define EXTI ((EXTI_TypeDef *) EXTI_BASE)</span></div>
|
|
<div class="line"><a name="l01650"></a><span class="lineno"> 1650</span> <span class="preprocessor">#define TIM9 ((TIM_TypeDef *) TIM9_BASE)</span></div>
|
|
<div class="line"><a name="l01651"></a><span class="lineno"> 1651</span> <span class="preprocessor">#define TIM10 ((TIM_TypeDef *) TIM10_BASE)</span></div>
|
|
<div class="line"><a name="l01652"></a><span class="lineno"> 1652</span> <span class="preprocessor">#define TIM11 ((TIM_TypeDef *) TIM11_BASE)</span></div>
|
|
<div class="line"><a name="l01653"></a><span class="lineno"> 1653</span> <span class="preprocessor">#define SPI5 ((SPI_TypeDef *) SPI5_BASE)</span></div>
|
|
<div class="line"><a name="l01654"></a><span class="lineno"> 1654</span> <span class="preprocessor">#define SPI6 ((SPI_TypeDef *) SPI6_BASE)</span></div>
|
|
<div class="line"><a name="l01655"></a><span class="lineno"> 1655</span> <span class="preprocessor">#define SAI1 ((SAI_TypeDef *) SAI1_BASE)</span></div>
|
|
<div class="line"><a name="l01656"></a><span class="lineno"> 1656</span> <span class="preprocessor">#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)</span></div>
|
|
<div class="line"><a name="l01657"></a><span class="lineno"> 1657</span> <span class="preprocessor">#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)</span></div>
|
|
<div class="line"><a name="l01658"></a><span class="lineno"> 1658</span> <span class="preprocessor">#define LTDC ((LTDC_TypeDef *)LTDC_BASE)</span></div>
|
|
<div class="line"><a name="l01659"></a><span class="lineno"> 1659</span> <span class="preprocessor">#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)</span></div>
|
|
<div class="line"><a name="l01660"></a><span class="lineno"> 1660</span> <span class="preprocessor">#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)</span></div>
|
|
<div class="line"><a name="l01661"></a><span class="lineno"> 1661</span> <span class="preprocessor">#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)</span></div>
|
|
<div class="line"><a name="l01662"></a><span class="lineno"> 1662</span> <span class="preprocessor">#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)</span></div>
|
|
<div class="line"><a name="l01663"></a><span class="lineno"> 1663</span> <span class="preprocessor">#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)</span></div>
|
|
<div class="line"><a name="l01664"></a><span class="lineno"> 1664</span> <span class="preprocessor">#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)</span></div>
|
|
<div class="line"><a name="l01665"></a><span class="lineno"> 1665</span> <span class="preprocessor">#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)</span></div>
|
|
<div class="line"><a name="l01666"></a><span class="lineno"> 1666</span> <span class="preprocessor">#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)</span></div>
|
|
<div class="line"><a name="l01667"></a><span class="lineno"> 1667</span> <span class="preprocessor">#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)</span></div>
|
|
<div class="line"><a name="l01668"></a><span class="lineno"> 1668</span> <span class="preprocessor">#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)</span></div>
|
|
<div class="line"><a name="l01669"></a><span class="lineno"> 1669</span> <span class="preprocessor">#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)</span></div>
|
|
<div class="line"><a name="l01670"></a><span class="lineno"> 1670</span> <span class="preprocessor">#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)</span></div>
|
|
<div class="line"><a name="l01671"></a><span class="lineno"> 1671</span> <span class="preprocessor">#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)</span></div>
|
|
<div class="line"><a name="l01672"></a><span class="lineno"> 1672</span> <span class="preprocessor">#define CRC ((CRC_TypeDef *) CRC_BASE)</span></div>
|
|
<div class="line"><a name="l01673"></a><span class="lineno"> 1673</span> <span class="preprocessor">#define RCC ((RCC_TypeDef *) RCC_BASE)</span></div>
|
|
<div class="line"><a name="l01674"></a><span class="lineno"> 1674</span> <span class="preprocessor">#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)</span></div>
|
|
<div class="line"><a name="l01675"></a><span class="lineno"> 1675</span> <span class="preprocessor">#define DMA1 ((DMA_TypeDef *) DMA1_BASE)</span></div>
|
|
<div class="line"><a name="l01676"></a><span class="lineno"> 1676</span> <span class="preprocessor">#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)</span></div>
|
|
<div class="line"><a name="l01677"></a><span class="lineno"> 1677</span> <span class="preprocessor">#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)</span></div>
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<div class="line"><a name="l01678"></a><span class="lineno"> 1678</span> <span class="preprocessor">#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)</span></div>
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|
<div class="line"><a name="l01679"></a><span class="lineno"> 1679</span> <span class="preprocessor">#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)</span></div>
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<div class="line"><a name="l01680"></a><span class="lineno"> 1680</span> <span class="preprocessor">#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)</span></div>
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<div class="line"><a name="l01681"></a><span class="lineno"> 1681</span> <span class="preprocessor">#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)</span></div>
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<div class="line"><a name="l01682"></a><span class="lineno"> 1682</span> <span class="preprocessor">#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)</span></div>
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<div class="line"><a name="l01683"></a><span class="lineno"> 1683</span> <span class="preprocessor">#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)</span></div>
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<div class="line"><a name="l01684"></a><span class="lineno"> 1684</span> <span class="preprocessor">#define DMA2 ((DMA_TypeDef *) DMA2_BASE)</span></div>
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<div class="line"><a name="l01685"></a><span class="lineno"> 1685</span> <span class="preprocessor">#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)</span></div>
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<div class="line"><a name="l01686"></a><span class="lineno"> 1686</span> <span class="preprocessor">#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)</span></div>
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<div class="line"><a name="l01687"></a><span class="lineno"> 1687</span> <span class="preprocessor">#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)</span></div>
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<div class="line"><a name="l01688"></a><span class="lineno"> 1688</span> <span class="preprocessor">#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)</span></div>
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<div class="line"><a name="l01689"></a><span class="lineno"> 1689</span> <span class="preprocessor">#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)</span></div>
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<div class="line"><a name="l01690"></a><span class="lineno"> 1690</span> <span class="preprocessor">#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)</span></div>
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<div class="line"><a name="l01691"></a><span class="lineno"> 1691</span> <span class="preprocessor">#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)</span></div>
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<div class="line"><a name="l01692"></a><span class="lineno"> 1692</span> <span class="preprocessor">#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)</span></div>
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<div class="line"><a name="l01693"></a><span class="lineno"> 1693</span> <span class="preprocessor">#define ETH ((ETH_TypeDef *) ETH_BASE) </span></div>
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<div class="line"><a name="l01694"></a><span class="lineno"> 1694</span> <span class="preprocessor">#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)</span></div>
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<div class="line"><a name="l01695"></a><span class="lineno"> 1695</span> <span class="preprocessor">#define DCMI ((DCMI_TypeDef *) DCMI_BASE)</span></div>
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<div class="line"><a name="l01696"></a><span class="lineno"> 1696</span> <span class="preprocessor">#define CRYP ((CRYP_TypeDef *) CRYP_BASE)</span></div>
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|
<div class="line"><a name="l01697"></a><span class="lineno"> 1697</span> <span class="preprocessor">#define HASH ((HASH_TypeDef *) HASH_BASE)</span></div>
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<div class="line"><a name="l01698"></a><span class="lineno"> 1698</span> <span class="preprocessor">#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)</span></div>
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|
<div class="line"><a name="l01699"></a><span class="lineno"> 1699</span> <span class="preprocessor">#define RNG ((RNG_TypeDef *) RNG_BASE)</span></div>
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|
<div class="line"><a name="l01700"></a><span class="lineno"> 1700</span> </div>
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<div class="line"><a name="l01701"></a><span class="lineno"> 1701</span> <span class="preprocessor">#if defined (STM32F40_41xxx)</span></div>
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<div class="line"><a name="l01702"></a><span class="lineno"> 1702</span> <span class="preprocessor">#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)</span></div>
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|
<div class="line"><a name="l01703"></a><span class="lineno"> 1703</span> <span class="preprocessor">#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)</span></div>
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|
<div class="line"><a name="l01704"></a><span class="lineno"> 1704</span> <span class="preprocessor">#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)</span></div>
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|
<div class="line"><a name="l01705"></a><span class="lineno"> 1705</span> <span class="preprocessor">#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)</span></div>
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|
<div class="line"><a name="l01706"></a><span class="lineno"> 1706</span> <span class="preprocessor">#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)</span></div>
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|
<div class="line"><a name="l01707"></a><span class="lineno"> 1707</span> <span class="preprocessor">#endif </span><span class="comment">/* STM32F40_41xxx */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l01708"></a><span class="lineno"> 1708</span> </div>
|
|
<div class="line"><a name="l01709"></a><span class="lineno"> 1709</span> <span class="preprocessor">#if defined (STM32F427_437xx) || defined (STM32F429_439xx)</span></div>
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|
<div class="line"><a name="l01710"></a><span class="lineno"> 1710</span> <span class="preprocessor">#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)</span></div>
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|
<div class="line"><a name="l01711"></a><span class="lineno"> 1711</span> <span class="preprocessor">#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)</span></div>
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|
<div class="line"><a name="l01712"></a><span class="lineno"> 1712</span> <span class="preprocessor">#define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)</span></div>
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|
<div class="line"><a name="l01713"></a><span class="lineno"> 1713</span> <span class="preprocessor">#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)</span></div>
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|
<div class="line"><a name="l01714"></a><span class="lineno"> 1714</span> <span class="preprocessor">#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)</span></div>
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|
<div class="line"><a name="l01715"></a><span class="lineno"> 1715</span> <span class="preprocessor">#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)</span></div>
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|
<div class="line"><a name="l01716"></a><span class="lineno"> 1716</span> <span class="preprocessor">#endif </span><span class="comment">/* STM32F427_437xx || STM32F429_439xx */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l01717"></a><span class="lineno"> 1717</span> </div>
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|
<div class="line"><a name="l01718"></a><span class="lineno"> 1718</span> <span class="preprocessor">#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)</span></div>
|
|
<div class="line"><a name="l01719"></a><span class="lineno"> 1719</span> </div>
|
|
<div class="line"><a name="l01732"></a><span class="lineno"> 1732</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l01733"></a><span class="lineno"> 1733</span> <span class="comment">/* Peripheral Registers_Bits_Definition */</span></div>
|
|
<div class="line"><a name="l01734"></a><span class="lineno"> 1734</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l01735"></a><span class="lineno"> 1735</span> </div>
|
|
<div class="line"><a name="l01736"></a><span class="lineno"> 1736</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l01737"></a><span class="lineno"> 1737</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l01738"></a><span class="lineno"> 1738</span> <span class="comment">/* Analog to Digital Converter */</span></div>
|
|
<div class="line"><a name="l01739"></a><span class="lineno"> 1739</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l01740"></a><span class="lineno"> 1740</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l01741"></a><span class="lineno"> 1741</span> <span class="comment">/******************** Bit definition for ADC_SR register ********************/</span></div>
|
|
<div class="line"><a name="l01742"></a><span class="lineno"> 1742</span> <span class="preprocessor">#define ADC_SR_AWD ((uint8_t)0x01) </span></div>
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|
<div class="line"><a name="l01743"></a><span class="lineno"> 1743</span> <span class="preprocessor">#define ADC_SR_EOC ((uint8_t)0x02) </span></div>
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|
<div class="line"><a name="l01744"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b7f27694281e4cad956da567e5583b2"> 1744</a></span> <span class="preprocessor">#define ADC_SR_JEOC ((uint8_t)0x04) </span></div>
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|
<div class="line"><a name="l01745"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3dc295c5253743aeb2cda582953b7b53"> 1745</a></span> <span class="preprocessor">#define ADC_SR_JSTRT ((uint8_t)0x08) </span></div>
|
|
<div class="line"><a name="l01746"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc9f07589bb1a4e398781df372389b56"> 1746</a></span> <span class="preprocessor">#define ADC_SR_STRT ((uint8_t)0x10) </span></div>
|
|
<div class="line"><a name="l01747"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7340a01ffec051c06e80a037eee58a14"> 1747</a></span> <span class="preprocessor">#define ADC_SR_OVR ((uint8_t)0x20) </span></div>
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|
<div class="line"><a name="l01749"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e5211d5e3e53cdedf4d9d6fe4ce2a45"> 1749</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for ADC_CR1 register ********************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l01750"></a><span class="lineno"> 1750</span> <span class="preprocessor">#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) </span></div>
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|
<div class="line"><a name="l01751"></a><span class="lineno"> 1751</span> <span class="preprocessor">#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) </span></div>
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|
<div class="line"><a name="l01752"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8bb755c7059bb2d4f5e2e999d2a2677"> 1752</a></span> <span class="preprocessor">#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) </span></div>
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|
<div class="line"><a name="l01753"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga18725d77c35c173cdb5bdab658d9dace"> 1753</a></span> <span class="preprocessor">#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) </span></div>
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|
<div class="line"><a name="l01754"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafcd37244d74db7c9a34a4f08b94301ae"> 1754</a></span> <span class="preprocessor">#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) </span></div>
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|
<div class="line"><a name="l01755"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga625eebdc95937325cad90a151853f5a0"> 1755</a></span> <span class="preprocessor">#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) </span></div>
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|
<div class="line"><a name="l01756"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb768d4aafbabc114d4650cf962392ec"> 1756</a></span> <span class="preprocessor">#define ADC_CR1_EOCIE ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l01757"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf37f3c0d7c72192803d0772e076cf8ee"> 1757</a></span> <span class="preprocessor">#define ADC_CR1_AWDIE ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l01758"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa39fee2e812a7ca45998cccf32e90aea"> 1758</a></span> <span class="preprocessor">#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) </span></div>
|
|
<div class="line"><a name="l01759"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd44f86b189696d5a3780342516de722"> 1759</a></span> <span class="preprocessor">#define ADC_CR1_SCAN ((uint32_t)0x00000100) </span></div>
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|
<div class="line"><a name="l01760"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c46fc1dc6c63acf88821f46a8f6d5e7"> 1760</a></span> <span class="preprocessor">#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l01761"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaeab75ece0c73dd97e8f21911ed22d06"> 1761</a></span> <span class="preprocessor">#define ADC_CR1_JAUTO ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l01762"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c9fc31f19c04033dfa98e982519c451"> 1762</a></span> <span class="preprocessor">#define ADC_CR1_DISCEN ((uint32_t)0x00000800) </span></div>
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|
<div class="line"><a name="l01763"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6353cb0d564410358b3a086dd0241f8c"> 1763</a></span> <span class="preprocessor">#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) </span></div>
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|
<div class="line"><a name="l01764"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd690297fc73fca40d797f4c90800b9a"> 1764</a></span> <span class="preprocessor">#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) </span></div>
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|
<div class="line"><a name="l01765"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd06a2840346bf45ff335707db0b6e30"> 1765</a></span> <span class="preprocessor">#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) </span></div>
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|
<div class="line"><a name="l01766"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeaa416a291023449ae82e7ef39844075"> 1766</a></span> <span class="preprocessor">#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) </span></div>
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|
<div class="line"><a name="l01767"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga59ff81db7def261f0e84d5dbb6cca1ce"> 1767</a></span> <span class="preprocessor">#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) </span></div>
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|
<div class="line"><a name="l01768"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39940d3611126052f4f748934c629ebf"> 1768</a></span> <span class="preprocessor">#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) </span></div>
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|
<div class="line"><a name="l01769"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab73d5fdf276f5ef3965afdda78ac9e1e"> 1769</a></span> <span class="preprocessor">#define ADC_CR1_AWDEN ((uint32_t)0x00800000) </span></div>
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|
<div class="line"><a name="l01770"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4886de74bcd3a1e545094089f76fd0b3"> 1770</a></span> <span class="preprocessor">#define ADC_CR1_RES ((uint32_t)0x03000000) </span></div>
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|
<div class="line"><a name="l01771"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e006d43fcb9fe1306745c95a1bdd651"> 1771</a></span> <span class="preprocessor">#define ADC_CR1_RES_0 ((uint32_t)0x01000000) </span></div>
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|
<div class="line"><a name="l01772"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71e4a4c233895a2e7b6dd3ca6ca849e5"> 1772</a></span> <span class="preprocessor">#define ADC_CR1_RES_1 ((uint32_t)0x02000000) </span></div>
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|
<div class="line"><a name="l01773"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacfc432ddbd2140a92d877f6d9dc52417"> 1773</a></span> <span class="preprocessor">#define ADC_CR1_OVRIE ((uint32_t)0x04000000) </span></div>
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|
<div class="line"><a name="l01775"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa892fda7c204bf18a33a059f28be0fba"> 1775</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for ADC_CR2 register ********************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l01776"></a><span class="lineno"> 1776</span> <span class="preprocessor">#define ADC_CR2_ADON ((uint32_t)0x00000001) </span></div>
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|
<div class="line"><a name="l01777"></a><span class="lineno"> 1777</span> <span class="preprocessor">#define ADC_CR2_CONT ((uint32_t)0x00000002) </span></div>
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|
<div class="line"><a name="l01778"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89b646f092b052d8488d2016f6290f0e"> 1778</a></span> <span class="preprocessor">#define ADC_CR2_DMA ((uint32_t)0x00000100) </span></div>
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|
<div class="line"><a name="l01779"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49bb71a868c9d88a0f7bbe48918b2140"> 1779</a></span> <span class="preprocessor">#define ADC_CR2_DDS ((uint32_t)0x00000200) </span></div>
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|
<div class="line"><a name="l01780"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga017309ac4b532bc8c607388f4e2cbbec"> 1780</a></span> <span class="preprocessor">#define ADC_CR2_EOCS ((uint32_t)0x00000400) </span></div>
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|
<div class="line"><a name="l01781"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d7d75f0c4c8fa190fbf9f86fbe6dfc8"> 1781</a></span> <span class="preprocessor">#define ADC_CR2_ALIGN ((uint32_t)0x00000800) </span></div>
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|
<div class="line"><a name="l01782"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf9dac2004ab20295e04012060ab24aeb"> 1782</a></span> <span class="preprocessor">#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) </span></div>
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|
<div class="line"><a name="l01783"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5950b5a7438a447584f6dd86c343362"> 1783</a></span> <span class="preprocessor">#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) </span></div>
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|
<div class="line"><a name="l01784"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab3aa5d0e2a4b77960ec8f3b425a3eac"> 1784</a></span> <span class="preprocessor">#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) </span></div>
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|
<div class="line"><a name="l01785"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa70c1f30e2101e2177ce564440203ba3"> 1785</a></span> <span class="preprocessor">#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) </span></div>
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|
<div class="line"><a name="l01786"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99fa4a240d34ce231d6d0543bac7fd9b"> 1786</a></span> <span class="preprocessor">#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) </span></div>
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|
<div class="line"><a name="l01787"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga571bb97f950181fedbc0d4756482713d"> 1787</a></span> <span class="preprocessor">#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) </span></div>
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|
<div class="line"><a name="l01788"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae34f5dda7a153ffd927c9cd38999f822"> 1788</a></span> <span class="preprocessor">#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l01789"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07330f702208792faca3a563dc4fd9c6"> 1789</a></span> <span class="preprocessor">#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l01790"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b3c99510de210ff3137ff8de328889b"> 1790</a></span> <span class="preprocessor">#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l01791"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga949c70fdf36a32a6afcbf44fec123832"> 1791</a></span> <span class="preprocessor">#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) </span></div>
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<div class="line"><a name="l01792"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac12fe8a6cc24eef2ed2e1f1525855678"> 1792</a></span> <span class="preprocessor">#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l01793"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d1054d6cd017e305cf6e8a864ce96c8"> 1793</a></span> <span class="preprocessor">#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l01794"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9410c7fd93f6d0b157ede745ee269d7b"> 1794</a></span> <span class="preprocessor">#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l01795"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a6725419743a8d01b4a223609952893"> 1795</a></span> <span class="preprocessor">#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l01796"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c2322988b5fff19d012d9179d412ad0"> 1796</a></span> <span class="preprocessor">#define ADC_CR2_EXTEN ((uint32_t)0x30000000) </span></div>
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<div class="line"><a name="l01797"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga387de6160834197888efa43e164c2db9"> 1797</a></span> <span class="preprocessor">#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l01798"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga574b4d8e90655d0432882d620e629234"> 1798</a></span> <span class="preprocessor">#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l01799"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3519da0cc6fbd31444a16244c70232e6"> 1799</a></span> <span class="preprocessor">#define ADC_CR2_SWSTART ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l01801"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5eae65bad1a6c975e1911eb5ba117468"> 1801</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for ADC_SMPR1 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l01802"></a><span class="lineno"> 1802</span> <span class="preprocessor">#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) </span></div>
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<div class="line"><a name="l01803"></a><span class="lineno"> 1803</span> <span class="preprocessor">#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l01804"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga32242a2c2156a012a7343bcb43d490d0"> 1804</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l01805"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a8996c53042759f01e966fb00351ebf"> 1805</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l01806"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42b96f058436c8bdcfabe1e08c7edd61"> 1806</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) </span></div>
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<div class="line"><a name="l01807"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga289d89b4d92d7f685a8e44aeb9ddcded"> 1807</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l01808"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c74d559f2a70a2e8c807b7bcaccd800"> 1808</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l01809"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60780d613953f48a2dfc8debce72fb28"> 1809</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l01810"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa61e1dbafcae3e1c8eae4320a6e5ec5d"> 1810</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) </span></div>
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<div class="line"><a name="l01811"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93a876a9a6d90cd30456433b7e38c3f2"> 1811</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l01812"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga433b5a7d944666fb7abed3b107c352fc"> 1812</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l01813"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaaac6ae97c00276d7472bc92a9edd6e2"> 1813</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l01814"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6020f9d742e15650ad919aaccaf2ff6c"> 1814</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) </span></div>
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<div class="line"><a name="l01815"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb59adb544d416e91ea0c12d4f39ccc9"> 1815</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l01816"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2df120cd93a177ea17946a656259129e"> 1816</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l01817"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49e7444d6cf630eccfd52fb4155bd553"> 1817</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l01818"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5d5ad9d8d08feaee18d1f2d8d6787a1"> 1818</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) </span></div>
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<div class="line"><a name="l01819"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4cd285d46485136deb6223377d0b17c"> 1819</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l01820"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab1574fc02a40f22fc751073e02ebb781"> 1820</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l01821"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9243898272b1d27018c971eecfa57f78"> 1821</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l01822"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1016b8ca359247491a2a0a5d77aa1c22"> 1822</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) </span></div>
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<div class="line"><a name="l01823"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e658a8b72bac244bf919a874690e49e"> 1823</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l01824"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ae0043ad863f7710834217bc82c8ecf"> 1824</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l01825"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5f8e555f5ece2ee632dd9d6c60d9584"> 1825</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l01826"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab978e10b7dcfe6c1b88dd4fef50498ac"> 1826</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) </span></div>
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<div class="line"><a name="l01827"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga045285e1c5ab9ae570e37fe627b0e117"> 1827</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l01828"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2925d05347e46e9c6a970214fa76bbec"> 1828</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l01829"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1a7d0ef695bd2017bcda3949f0134be"> 1829</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l01830"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga793ff2f46f51e1d485a9bd728687bf15"> 1830</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) </span></div>
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<div class="line"><a name="l01831"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade321fdbf74f830e54951ccfca285686"> 1831</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l01832"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9867370ecef7b99c32b8ecb44ad9e581"> 1832</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l01833"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42b004d74f288cb191bfc6a327f94480"> 1833</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l01834"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ac4c21586d6a353c208a5175906ecc1"> 1834</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) </span></div>
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<div class="line"><a name="l01835"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac81ceec799a7da2def4f33339bd5e273"> 1835</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l01836"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3c7d84a92899d950de236fe9d14df2c"> 1836</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l01837"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6862168bb7688638764defc72120716b"> 1837</a></span> <span class="preprocessor">#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l01839"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec1addc9c417b4b7693768817b058059"> 1839</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for ADC_SMPR2 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l01840"></a><span class="lineno"> 1840</span> <span class="preprocessor">#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) </span></div>
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<div class="line"><a name="l01841"></a><span class="lineno"> 1841</span> <span class="preprocessor">#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l01842"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a13b3c652e5759e2d8bc7e38889bc5e"> 1842</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l01843"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1bde59fce56980a59a3dfdb0da7ebe0c"> 1843</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l01844"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d5b6e025d8e70767914c144793b93e6"> 1844</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) </span></div>
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<div class="line"><a name="l01845"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga361de56c56c45834fc837df349f155dc"> 1845</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l01846"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b85dd0b1708cdf1bf403b07ad51da36"> 1846</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l01847"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa99de1a2d2bbe8921353114d03cb7f6"> 1847</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l01848"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6ceb41e5e3cb6ae7da28070bc0b07d2"> 1848</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) </span></div>
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<div class="line"><a name="l01849"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b9efc8f9488d389301c4a6f9ef4427a"> 1849</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l01850"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea6e1e298372596bcdcdf93e763b3683"> 1850</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l01851"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97e2ac0d4d8afb3aa0b4c09c8fa1d018"> 1851</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l01852"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83fe79e3e10b689a209dc5a724f89199"> 1852</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) </span></div>
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<div class="line"><a name="l01853"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad580d376e0a0bcb34183a6d6735b3122"> 1853</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l01854"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga081c3d61e5311a11cb046d56630e1fd0"> 1854</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l01855"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1679a42f67ca4b9b9496dd6000fec01"> 1855</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l01856"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1bf92b0a67dcec9b3c325d58e7e517b0"> 1856</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) </span></div>
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<div class="line"><a name="l01857"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40682268fa8534bd369eb64a329bdf46"> 1857</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l01858"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeab838fcf0aace87b2163b96d208bb64"> 1858</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l01859"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4123bce64dc4f1831f992b09d6db4f2"> 1859</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l01860"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3edf57b459804d17d5a588dd446c763"> 1860</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) </span></div>
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<div class="line"><a name="l01861"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2a2fd74311c4ffcaed4a8d1a3be2245"> 1861</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l01862"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9500281fa740994b9cfa6a7df8227849"> 1862</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l01863"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22dd2b1695a4e7a4b1d4ec2b8e244ffc"> 1863</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l01864"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab4de4f6c62646be62d0710dc46eb5e88"> 1864</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) </span></div>
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<div class="line"><a name="l01865"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c19081d82f2c6478c6aefc207778e1e"> 1865</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l01866"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64cd99c27d07298913541dbdc31aa8ae"> 1866</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l01867"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbebc0a7f368e5846408d768603d9b44"> 1867</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l01868"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27f59166864f7cd0a5e8e6b4450e72d3"> 1868</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) </span></div>
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<div class="line"><a name="l01869"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4139fac7e8ba3e604e35ba906880f909"> 1869</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l01870"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ec6ee971fc8b2d1890858df94a5c500"> 1870</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l01871"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f30003c59ab6c232d73aa446c77651a"> 1871</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l01872"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c8708fc97082257b43fa4534c721068"> 1872</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) </span></div>
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<div class="line"><a name="l01873"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e42897bdc25951a73bac060a7a065ca"> 1873</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l01874"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0695c289e658b772070a7f29797e9cc3"> 1874</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l01875"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5f1d2290107eda2dfee33810779b0f6"> 1875</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l01876"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb9ce9d71f989bad0ed686caf4dd5250"> 1876</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) </span></div>
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<div class="line"><a name="l01877"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3756c6141f55c60da0bcd4d599e7d60d"> 1877</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l01878"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5348f83daaa38060702d7b9cfe2e4005"> 1878</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l01879"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga892f18c89fbaafc74b7d67db74b41423"> 1879</a></span> <span class="preprocessor">#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l01881"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga070135017850599b1e19766c6aa31cd1"> 1881</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for ADC_JOFR1 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l01882"></a><span class="lineno"> 1882</span> <span class="preprocessor">#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) </span></div>
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<div class="line"><a name="l01884"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad76f97130b391455094605a6c803026c"> 1884</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for ADC_JOFR2 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l01885"></a><span class="lineno"> 1885</span> <span class="preprocessor">#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) </span></div>
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<div class="line"><a name="l01887"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b15a9e9ce10303e233059c1de6d956c"> 1887</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for ADC_JOFR3 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l01888"></a><span class="lineno"> 1888</span> <span class="preprocessor">#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) </span></div>
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<div class="line"><a name="l01890"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga743e4c3a7cefc1a193146e77791c3985"> 1890</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for ADC_JOFR4 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l01891"></a><span class="lineno"> 1891</span> <span class="preprocessor">#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) </span></div>
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<div class="line"><a name="l01893"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada0937f2f6a64bd6b7531ad553471b8d"> 1893</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for ADC_HTR register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l01894"></a><span class="lineno"> 1894</span> <span class="preprocessor">#define ADC_HTR_HT ((uint16_t)0x0FFF) </span></div>
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<div class="line"><a name="l01896"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad685f031174465e636ef75a5bd7b637d"> 1896</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for ADC_LTR register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l01897"></a><span class="lineno"> 1897</span> <span class="preprocessor">#define ADC_LTR_LT ((uint16_t)0x0FFF) </span></div>
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<div class="line"><a name="l01899"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac7ac18b970378acf726f04ae68232c24"> 1899</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for ADC_SQR1 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l01900"></a><span class="lineno"> 1900</span> <span class="preprocessor">#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) </span></div>
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<div class="line"><a name="l01901"></a><span class="lineno"> 1901</span> <span class="preprocessor">#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l01902"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ae1998c0dd11275958e7347a92852fc"> 1902</a></span> <span class="preprocessor">#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l01903"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40d24ddd458198e7731d5abf9d15fc08"> 1903</a></span> <span class="preprocessor">#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l01904"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaccdca8b0f3cab9f62ae2ffbb9c30546f"> 1904</a></span> <span class="preprocessor">#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l01905"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37e8723bfdc43da0b86e40a49b78c9ad"> 1905</a></span> <span class="preprocessor">#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l01906"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga412374f7ce1f62ee187c819391898778"> 1906</a></span> <span class="preprocessor">#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) </span></div>
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<div class="line"><a name="l01907"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05ca5e303f844f512c9a9cb5df9a1028"> 1907</a></span> <span class="preprocessor">#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l01908"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab0251199146cb3d0d2c1c0608fbca585"> 1908</a></span> <span class="preprocessor">#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l01909"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacde3a6d9e94aa1c2399e335911fd6212"> 1909</a></span> <span class="preprocessor">#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l01910"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1bc61e4d3ea200e1fc3e9d621ebbd2b4"> 1910</a></span> <span class="preprocessor">#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l01911"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeea616e444521cd58c5d8d574c47ccf0"> 1911</a></span> <span class="preprocessor">#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l01912"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e0c9439633fb5c67c8f2138c9d2efae"> 1912</a></span> <span class="preprocessor">#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) </span></div>
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<div class="line"><a name="l01913"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea22b4dd0fbb26d2a0babbc483778b0e"> 1913</a></span> <span class="preprocessor">#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l01914"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23222c591c6d926f7a741bc9346f1d8f"> 1914</a></span> <span class="preprocessor">#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l01915"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacbfbc70f67ce1d8f227e17a7f19c123b"> 1915</a></span> <span class="preprocessor">#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l01916"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac00e343ff0dd8f1f29e897148e3e070a"> 1916</a></span> <span class="preprocessor">#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l01917"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab63443b0c5a2eca60a8c9714f6f31c03"> 1917</a></span> <span class="preprocessor">#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l01918"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf676d45ba227a2dc641b2afadfa7852"> 1918</a></span> <span class="preprocessor">#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) </span></div>
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<div class="line"><a name="l01919"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7dbc07d0904f60abcc15827ccab1a8c2"> 1919</a></span> <span class="preprocessor">#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l01920"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafecb33099669a080cede6ce0236389e7"> 1920</a></span> <span class="preprocessor">#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l01921"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3404d0bf04b8561bf93455d968b77ea9"> 1921</a></span> <span class="preprocessor">#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l01922"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ea6af777051f14be5cf166dd4ae69d1"> 1922</a></span> <span class="preprocessor">#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l01923"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf59e4a113346ac3daf6829c3321444f5"> 1923</a></span> <span class="preprocessor">#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l01924"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6052517e5fcab3f58c42b59fb3ffee55"> 1924</a></span> <span class="preprocessor">#define ADC_SQR1_L ((uint32_t)0x00F00000) </span></div>
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<div class="line"><a name="l01925"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7af851b5898b4421958e7a100602c8cd"> 1925</a></span> <span class="preprocessor">#define ADC_SQR1_L_0 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l01926"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae68a19a18d72f6d87c6f2b8cc8bfc6dc"> 1926</a></span> <span class="preprocessor">#define ADC_SQR1_L_1 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l01927"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00ec56fbf232492ec12c954e27d03c6c"> 1927</a></span> <span class="preprocessor">#define ADC_SQR1_L_2 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l01928"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52708c6570da08c295603e5b52461ecd"> 1928</a></span> <span class="preprocessor">#define ADC_SQR1_L_3 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l01930"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaffdd34daa55da53d18055417ae895c47"> 1930</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for ADC_SQR2 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l01931"></a><span class="lineno"> 1931</span> <span class="preprocessor">#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) </span></div>
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<div class="line"><a name="l01932"></a><span class="lineno"> 1932</span> <span class="preprocessor">#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l01933"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa9f66f702fc124040956117f20ef8df4"> 1933</a></span> <span class="preprocessor">#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l01934"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga12bbc822c10582a80f7e20a11038ce96"> 1934</a></span> <span class="preprocessor">#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l01935"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d0d7daf3b6db6ff4fa382495f6127c6"> 1935</a></span> <span class="preprocessor">#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l01936"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74bda24f18a95261661a944cecf45a52"> 1936</a></span> <span class="preprocessor">#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l01937"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2697675d008dda4e6a4905fc0f8d22af"> 1937</a></span> <span class="preprocessor">#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) </span></div>
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<div class="line"><a name="l01938"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c46dd0f30ef85094ca0cde2e8c00dac"> 1938</a></span> <span class="preprocessor">#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l01939"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga308ec58a8d20dcb3a348c30c332a0a8e"> 1939</a></span> <span class="preprocessor">#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l01940"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga858717a28d6c26612ad4ced46863ba13"> 1940</a></span> <span class="preprocessor">#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l01941"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d06168a43b4845409f2fb9193ee474a"> 1941</a></span> <span class="preprocessor">#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l01942"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa5eaea65d6719a8199639ec30bb8a07b"> 1942</a></span> <span class="preprocessor">#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l01943"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23e22da18926dd107adc69282a445412"> 1943</a></span> <span class="preprocessor">#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) </span></div>
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<div class="line"><a name="l01944"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacadd092f31f37bb129065be175673c63"> 1944</a></span> <span class="preprocessor">#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l01945"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5d91ecfc3d40cc6b1960544e526eb91"> 1945</a></span> <span class="preprocessor">#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l01946"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace032949b436d9af8a20ea10a349d55b"> 1946</a></span> <span class="preprocessor">#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l01947"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5cf43f1c5de0e73d6159fabc3681b891"> 1947</a></span> <span class="preprocessor">#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l01948"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3389c07a9de242151ffa434908fee39d"> 1948</a></span> <span class="preprocessor">#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l01949"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13f30540b9f2d33640ea7d9652dc3c71"> 1949</a></span> <span class="preprocessor">#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) </span></div>
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<div class="line"><a name="l01950"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga910e5bda9852d49117b76b0d9f420ef2"> 1950</a></span> <span class="preprocessor">#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l01951"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22e474b65f217ac21137b1d3f3cbb6bb"> 1951</a></span> <span class="preprocessor">#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l01952"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5a36056dbfce703d22387432ac12262"> 1952</a></span> <span class="preprocessor">#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l01953"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09a1de734fe67156af26edf3b8a61044"> 1953</a></span> <span class="preprocessor">#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l01954"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b1d6ad0a40e7171d40a964b361d1eb9"> 1954</a></span> <span class="preprocessor">#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l01955"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24d63e60eabad897aa9b19dbe56da71e"> 1955</a></span> <span class="preprocessor">#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) </span></div>
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<div class="line"><a name="l01956"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7df899f74116e6cb3205af2767840cfb"> 1956</a></span> <span class="preprocessor">#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l01957"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7bf491b9c1542fb0d0b83fc96166362e"> 1957</a></span> <span class="preprocessor">#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l01958"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5bc91fec2ef468c5d39d19beda9ecd3e"> 1958</a></span> <span class="preprocessor">#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l01959"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e142789d2bd0584480e923754544ff5"> 1959</a></span> <span class="preprocessor">#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l01960"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6b844fe698c16437e91c9e05a367a4c"> 1960</a></span> <span class="preprocessor">#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l01961"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a8127191e3c48f4e0952bdb5e196225"> 1961</a></span> <span class="preprocessor">#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) </span></div>
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<div class="line"><a name="l01962"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e8a39f645505ef84cb94bbc8d21b8e0"> 1962</a></span> <span class="preprocessor">#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l01963"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8731660b1710e63d5423cd31c11be184"> 1963</a></span> <span class="preprocessor">#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l01964"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b2da909e54f8f6f61bf2bd2cd3e93e0"> 1964</a></span> <span class="preprocessor">#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l01965"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5930c4a07d594aa23bc868526b42601"> 1965</a></span> <span class="preprocessor">#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l01966"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga377805a21e7da2a66a3913a77bcc1e66"> 1966</a></span> <span class="preprocessor">#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l01968"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6043d31a6cb9bd7c1542c3d41eb296c7"> 1968</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for ADC_SQR3 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l01969"></a><span class="lineno"> 1969</span> <span class="preprocessor">#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) </span></div>
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<div class="line"><a name="l01970"></a><span class="lineno"> 1970</span> <span class="preprocessor">#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l01971"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52491114e8394648559004f3bae718d9"> 1971</a></span> <span class="preprocessor">#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l01972"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53d3bb1c8bb48c7bcb0f7409db69f7b4"> 1972</a></span> <span class="preprocessor">#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l01973"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaddb9af3a3b23a103fbc34c4f422fd2af"> 1973</a></span> <span class="preprocessor">#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l01974"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf591f43a15c0c2c5afae2598b8f2afc"> 1974</a></span> <span class="preprocessor">#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l01975"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05cfde0ef0e6a8dd6311f5cd7a806556"> 1975</a></span> <span class="preprocessor">#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) </span></div>
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<div class="line"><a name="l01976"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9981512f99a6c41ce107a9428d9cfdd0"> 1976</a></span> <span class="preprocessor">#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l01977"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60637fb25c099f8da72a8a36211f7a8c"> 1977</a></span> <span class="preprocessor">#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l01978"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaede0302eb64f023913c7a9e588d77937"> 1978</a></span> <span class="preprocessor">#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l01979"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga158ab7429a864634a46c81fdb51d7508"> 1979</a></span> <span class="preprocessor">#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l01980"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae729e21d590271c59c0d653300d5581c"> 1980</a></span> <span class="preprocessor">#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l01981"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf65c33275178a8777fa8fed8a01f7389"> 1981</a></span> <span class="preprocessor">#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) </span></div>
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<div class="line"><a name="l01982"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga990aeb689b7cc8f0bebb3dd6af7b27a6"> 1982</a></span> <span class="preprocessor">#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l01983"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga601f21b7c1e571fb8c5ff310aca021e1"> 1983</a></span> <span class="preprocessor">#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l01984"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7fd2c154b5852cb08ce60b4adfa36313"> 1984</a></span> <span class="preprocessor">#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l01985"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga214580377dd3a424ad819f14f6b025d4"> 1985</a></span> <span class="preprocessor">#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l01986"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabae2353b109c9cda2a176ea1f44db4fe"> 1986</a></span> <span class="preprocessor">#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l01987"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d2f00d3372bd1d64bf4eb2271277ab0"> 1987</a></span> <span class="preprocessor">#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) </span></div>
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<div class="line"><a name="l01988"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5279e505b1a59b223f30e5be139d5042"> 1988</a></span> <span class="preprocessor">#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l01989"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3fc43f70bb3c67c639678b91d852390b"> 1989</a></span> <span class="preprocessor">#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l01990"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2a501b20cf758a7353efcb3f95a3a93"> 1990</a></span> <span class="preprocessor">#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l01991"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaffafa27fd561e4c7d419e3f665d80f2c"> 1991</a></span> <span class="preprocessor">#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l01992"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0251fa70e400ee74f442d8fba2b1afb"> 1992</a></span> <span class="preprocessor">#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l01993"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3dc48c3c6b304517261486d8a63637ae"> 1993</a></span> <span class="preprocessor">#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) </span></div>
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<div class="line"><a name="l01994"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe23b9e640df96ca84eab4b6b4f44083"> 1994</a></span> <span class="preprocessor">#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l01995"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae841d68049442e4568b86322ed4be6f"> 1995</a></span> <span class="preprocessor">#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l01996"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1de9fc24755b715c700c6442f4a396b"> 1996</a></span> <span class="preprocessor">#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l01997"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f704feb58eecb39bc7f199577064172"> 1997</a></span> <span class="preprocessor">#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l01998"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88a7994f637a75d105cc5975b154c373"> 1998</a></span> <span class="preprocessor">#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l01999"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31c6fce8f01e75c68124124061f67f0e"> 1999</a></span> <span class="preprocessor">#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) </span></div>
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<div class="line"><a name="l02000"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b0cad694c068ea8874b6504bd6ae885"> 2000</a></span> <span class="preprocessor">#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l02001"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga723792274b16b342d16d6a02fce74ba6"> 2001</a></span> <span class="preprocessor">#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l02002"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91b8b5293abd0601c543c13a0b53b335"> 2002</a></span> <span class="preprocessor">#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l02003"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab29847362a613b43eeeda6db758d781e"> 2003</a></span> <span class="preprocessor">#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l02004"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa92c8ea1bfb42ed80622770ae2dc41ab"> 2004</a></span> <span class="preprocessor">#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l02006"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78f9e51811549a6797ecfe1468def4ff"> 2006</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for ADC_JSQR register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02007"></a><span class="lineno"> 2007</span> <span class="preprocessor">#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) </span></div>
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<div class="line"><a name="l02008"></a><span class="lineno"> 2008</span> <span class="preprocessor">#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l02009"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7fa15dfe51b084b36cb5df2fbf44bb2"> 2009</a></span> <span class="preprocessor">#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02010"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3ea38b080462c4571524b5fcbfed292"> 2010</a></span> <span class="preprocessor">#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02011"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabae36d7655fb1dce11e60ffa8e57b509"> 2011</a></span> <span class="preprocessor">#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l02012"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3e7a96d33f640444b40b70e9ee28671"> 2012</a></span> <span class="preprocessor">#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l02013"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6066a6aef47f317a5df0c9bbf59121fb"> 2013</a></span> <span class="preprocessor">#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) </span></div>
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<div class="line"><a name="l02014"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2c4baf98380a477cebb01be3e8f0594"> 2014</a></span> <span class="preprocessor">#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l02015"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e8446a5857e5379cff8cadf822e15d4"> 2015</a></span> <span class="preprocessor">#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l02016"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaabf0889d056b56e4a113142b3694166d"> 2016</a></span> <span class="preprocessor">#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l02017"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga048f97e9e332adb21eca27b647af1378"> 2017</a></span> <span class="preprocessor">#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l02018"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga18bee187ed94e73b16eeea7501394581"> 2018</a></span> <span class="preprocessor">#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l02019"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78b031d11b56e49b2c28c1a79136b48a"> 2019</a></span> <span class="preprocessor">#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) </span></div>
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<div class="line"><a name="l02020"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga064d6ccde30a22430c658b8efc431e59"> 2020</a></span> <span class="preprocessor">#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l02021"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2fbdc1b854a54c4288402c2d3a7fca9"> 2021</a></span> <span class="preprocessor">#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l02022"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga12fbc27c3543f23125f632dfa60fdc98"> 2022</a></span> <span class="preprocessor">#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l02023"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga169ec7d371e3ee897b73c3ad84b6ed32"> 2023</a></span> <span class="preprocessor">#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l02024"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga693542d5a536304f364476589ba0bec9"> 2024</a></span> <span class="preprocessor">#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l02025"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga139ddd01c0faf219dca844477453149e"> 2025</a></span> <span class="preprocessor">#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) </span></div>
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<div class="line"><a name="l02026"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1452b8cf4acc90fb522d90751043aac"> 2026</a></span> <span class="preprocessor">#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l02027"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39a279051ef198ee34cad73743b996f4"> 2027</a></span> <span class="preprocessor">#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l02028"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13e250d329673c02f7a0d24d25e83649"> 2028</a></span> <span class="preprocessor">#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l02029"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30dad81d708c35136e2da4e96cfe07b7"> 2029</a></span> <span class="preprocessor">#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l02030"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ceab97acb95b31cb7448c9da38fc11a"> 2030</a></span> <span class="preprocessor">#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l02031"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52f6571e7efed6a0f72df19c66d3c917"> 2031</a></span> <span class="preprocessor">#define ADC_JSQR_JL ((uint32_t)0x00300000) </span></div>
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<div class="line"><a name="l02032"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaede3a17ef541039943d9dcd85df223ca"> 2032</a></span> <span class="preprocessor">#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l02033"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa624d1fe34014b88873e2dfa91f79232"> 2033</a></span> <span class="preprocessor">#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l02035"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f82ef3b6e6350b9e52e622daeaa3e6e"> 2035</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for ADC_JDR1 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02036"></a><span class="lineno"> 2036</span> <span class="preprocessor">#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) </span></div>
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<div class="line"><a name="l02038"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad02fcd8fd97b2f7d70a5a04fed60b558"> 2038</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for ADC_JDR2 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02039"></a><span class="lineno"> 2039</span> <span class="preprocessor">#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) </span></div>
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<div class="line"><a name="l02041"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9fbd8801b9c60269ca477062985a08e8"> 2041</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for ADC_JDR3 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02042"></a><span class="lineno"> 2042</span> <span class="preprocessor">#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) </span></div>
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<div class="line"><a name="l02044"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae84e9e5928bb9ed1aef6c83089fb5ef"> 2044</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for ADC_JDR4 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02045"></a><span class="lineno"> 2045</span> <span class="preprocessor">#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) </span></div>
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<div class="line"><a name="l02047"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga48d8fafdad1fb1bb0f761fd833e7b0c1"> 2047</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for ADC_DR register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02048"></a><span class="lineno"> 2048</span> <span class="preprocessor">#define ADC_DR_DATA ((uint32_t)0x0000FFFF) </span></div>
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<div class="line"><a name="l02049"></a><span class="lineno"> 2049</span> <span class="preprocessor">#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) </span></div>
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<div class="line"><a name="l02051"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67c396288ac97bfab2d37017bd536b98"> 2051</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for ADC_CSR register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02052"></a><span class="lineno"> 2052</span> <span class="preprocessor">#define ADC_CSR_AWD1 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l02053"></a><span class="lineno"> 2053</span> <span class="preprocessor">#define ADC_CSR_EOC1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02054"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e640f7443f14d01a37e29cff004223f"> 2054</a></span> <span class="preprocessor">#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02055"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga715bcb019d713187aacd46f4482fa5f9"> 2055</a></span> <span class="preprocessor">#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l02056"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a8a134d8b946f3549390294ef94b8d6"> 2056</a></span> <span class="preprocessor">#define ADC_CSR_STRT1 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l02057"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f1e6578b14d71c6d972c6d6f6d48eaa"> 2057</a></span> <span class="preprocessor">#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l02058"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78ff468cfaa299ef62ab7b8b9910e142"> 2058</a></span> <span class="preprocessor">#define ADC_CSR_AWD2 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l02059"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga321ed2ccdf98d3a3307947056a8c401a"> 2059</a></span> <span class="preprocessor">#define ADC_CSR_EOC2 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l02060"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80d8090a99ec65807ed831fea0d5524c"> 2060</a></span> <span class="preprocessor">#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l02061"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga411d79254769bbb4eeb14964abad497a"> 2061</a></span> <span class="preprocessor">#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l02062"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf24dbb77fadc6f928b8e38199a08abc7"> 2062</a></span> <span class="preprocessor">#define ADC_CSR_STRT2 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l02063"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ca65d6d580299518fb7491e1cebac1d"> 2063</a></span> <span class="preprocessor">#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l02064"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9e79005049b17d08c28aeca86677655"> 2064</a></span> <span class="preprocessor">#define ADC_CSR_AWD3 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l02065"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00e2a30df5568b5663e9f016743b3a35"> 2065</a></span> <span class="preprocessor">#define ADC_CSR_EOC3 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l02066"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8883de33c5a7b30c611db11340fec6d"> 2066</a></span> <span class="preprocessor">#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l02067"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a94c410343ba459146b2bb17833a795"> 2067</a></span> <span class="preprocessor">#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l02068"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae7d3c36f449ef1ee9ee20c5686b4e974"> 2068</a></span> <span class="preprocessor">#define ADC_CSR_STRT3 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l02069"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga94140d21b4c83d9f401cc459a7ec6060"> 2069</a></span> <span class="preprocessor">#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l02071"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga396513974cf26f2a4aa0f36e755e227c"> 2071</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for ADC_CCR register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02072"></a><span class="lineno"> 2072</span> <span class="preprocessor">#define ADC_CCR_MULTI ((uint32_t)0x0000001F) </span></div>
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<div class="line"><a name="l02073"></a><span class="lineno"> 2073</span> <span class="preprocessor">#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l02074"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf70ab04667c7c7da0f29c0e5a6c48e68"> 2074</a></span> <span class="preprocessor">#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02075"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4e7104ce01e3a79b8f6138d87dc3684"> 2075</a></span> <span class="preprocessor">#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02076"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8781dec7f076b475b85f8470aee94d06"> 2076</a></span> <span class="preprocessor">#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l02077"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae6a5be6cff1227431b8d54dffcc1ce88"> 2077</a></span> <span class="preprocessor">#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l02078"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae55be7b911b4c0272543f98a0dba5f20"> 2078</a></span> <span class="preprocessor">#define ADC_CCR_DELAY ((uint32_t)0x00000F00) </span></div>
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<div class="line"><a name="l02079"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5087b3cb0d4570b80b3138c277bcbf6c"> 2079</a></span> <span class="preprocessor">#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l02080"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c13aa04949ed520cf92613d3a619198"> 2080</a></span> <span class="preprocessor">#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l02081"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22b71e9df8b1fca93802ad602341eb0b"> 2081</a></span> <span class="preprocessor">#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l02082"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d0d5785cb6c75e700517e88af188573"> 2082</a></span> <span class="preprocessor">#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l02083"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17f85cbda5dcf9a392a29befb73c6ceb"> 2083</a></span> <span class="preprocessor">#define ADC_CCR_DDS ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l02084"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0216de7d6fcfa507c9aa1400972d862"> 2084</a></span> <span class="preprocessor">#define ADC_CCR_DMA ((uint32_t)0x0000C000) </span></div>
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<div class="line"><a name="l02085"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e745513bbc2e5e5a76ae999d5d535af"> 2085</a></span> <span class="preprocessor">#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l02086"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e346b21afcaeced784e6c80b3aa1fb4"> 2086</a></span> <span class="preprocessor">#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l02087"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a42ee6ec5115244aef8f60d35abcc47"> 2087</a></span> <span class="preprocessor">#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) </span></div>
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<div class="line"><a name="l02088"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacdc9d29cafdd54e5c0dd752c358e1bc8"> 2088</a></span> <span class="preprocessor">#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l02089"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a2ee019aef4c64fffc72141f7aaab2c"> 2089</a></span> <span class="preprocessor">#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l02090"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3108cc8fb81f6efd1e93fa5f82ac313"> 2090</a></span> <span class="preprocessor">#define ADC_CCR_VBATE ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l02091"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa090830d2d359db04f365d46c6644d5"> 2091</a></span> <span class="preprocessor">#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l02093"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc020d85a8740491ce3f218a0706f1dc"> 2093</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for ADC_CDR register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02094"></a><span class="lineno"> 2094</span> <span class="preprocessor">#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) </span></div>
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<div class="line"><a name="l02095"></a><span class="lineno"> 2095</span> <span class="preprocessor">#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) </span></div>
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<div class="line"><a name="l02097"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55f0776b9bf2612c194c1ab478d8a371"> 2097</a></span> <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02098"></a><span class="lineno"> 2098</span> <span class="comment">/* */</span></div>
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<div class="line"><a name="l02099"></a><span class="lineno"> 2099</span> <span class="comment">/* Controller Area Network */</span></div>
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<div class="line"><a name="l02100"></a><span class="lineno"> 2100</span> <span class="comment">/* */</span></div>
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<div class="line"><a name="l02101"></a><span class="lineno"> 2101</span> <span class="comment">/******************************************************************************/</span></div>
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<div class="line"><a name="l02103"></a><span class="lineno"> 2103</span> <span class="comment">/******************* Bit definition for CAN_MCR register ********************/</span></div>
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<div class="line"><a name="l02104"></a><span class="lineno"> 2104</span> <span class="preprocessor">#define CAN_MCR_INRQ ((uint16_t)0x0001) </span></div>
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<div class="line"><a name="l02105"></a><span class="lineno"> 2105</span> <span class="preprocessor">#define CAN_MCR_SLEEP ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l02106"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0cf12be5661908dbe38aa14cd4c3a356"> 2106</a></span> <span class="preprocessor">#define CAN_MCR_TXFP ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l02107"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf9602dfb2f95b481b6e642b95991176"> 2107</a></span> <span class="preprocessor">#define CAN_MCR_RFLM ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l02108"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga35e7e66f9cd8cb6efa6a80367d2294a9"> 2108</a></span> <span class="preprocessor">#define CAN_MCR_NART ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l02109"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga501125ff257a7d02c35a0d6dcbaa2ba8"> 2109</a></span> <span class="preprocessor">#define CAN_MCR_AWUM ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l02110"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2774f04e286942d36a5b6135c8028049"> 2110</a></span> <span class="preprocessor">#define CAN_MCR_ABOM ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l02111"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa2745f1a565c3f2ec5b16612d1fd66e0"> 2111</a></span> <span class="preprocessor">#define CAN_MCR_TTCM ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l02112"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7aff5c0a3ead7f937849ab66eba7490"> 2112</a></span> <span class="preprocessor">#define CAN_MCR_RESET ((uint16_t)0x8000) </span></div>
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<div class="line"><a name="l02114"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga410fdbad37a9dbda508b8c437277e79f"> 2114</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_MSR register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02115"></a><span class="lineno"> 2115</span> <span class="preprocessor">#define CAN_MSR_INAK ((uint16_t)0x0001) </span></div>
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<div class="line"><a name="l02116"></a><span class="lineno"> 2116</span> <span class="preprocessor">#define CAN_MSR_SLAK ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l02117"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2871cee90ebecb760bab16e9c039b682"> 2117</a></span> <span class="preprocessor">#define CAN_MSR_ERRI ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l02118"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1611badb362f0fd9047af965509f074"> 2118</a></span> <span class="preprocessor">#define CAN_MSR_WKUI ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l02119"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c424768e9e963402f37cb95ae87a1ae"> 2119</a></span> <span class="preprocessor">#define CAN_MSR_SLAKI ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l02120"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f4c753b96d21c5001b39ad5b08519fc"> 2120</a></span> <span class="preprocessor">#define CAN_MSR_TXM ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l02121"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47ab62ae123c791de27ad05dde5bee91"> 2121</a></span> <span class="preprocessor">#define CAN_MSR_RXM ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l02122"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga651580d35b658e90ea831cb13b8a8988"> 2122</a></span> <span class="preprocessor">#define CAN_MSR_SAMP ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l02123"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67f8e1140b0304930d5b4f2a041a7884"> 2123</a></span> <span class="preprocessor">#define CAN_MSR_RX ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l02125"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6564a1d2f23f246053188a454264eb4b"> 2125</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_TSR register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02126"></a><span class="lineno"> 2126</span> <span class="preprocessor">#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l02127"></a><span class="lineno"> 2127</span> <span class="preprocessor">#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02128"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a4809b8908618df57e6393cc7fe0f52"> 2128</a></span> <span class="preprocessor">#define CAN_TSR_ALST0 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02129"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaacedb237b31d29aef7f38475e9a6b297"> 2129</a></span> <span class="preprocessor">#define CAN_TSR_TERR0 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l02130"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b94ea5001d70a26ec32d9dc6ff76e47"> 2130</a></span> <span class="preprocessor">#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l02131"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga805d2dab5b1d4618492b1cf2a3f5e1e0"> 2131</a></span> <span class="preprocessor">#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l02132"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafdac6b87a303b0d0ec9b0d94a54ae31f"> 2132</a></span> <span class="preprocessor">#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l02133"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd3118dec59c3a45d2f262b090699538"> 2133</a></span> <span class="preprocessor">#define CAN_TSR_ALST1 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l02134"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea918e510c5471b1ac797350b7950151"> 2134</a></span> <span class="preprocessor">#define CAN_TSR_TERR1 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l02135"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a34d996177f23148c9b4cd6b0a80529"> 2135</a></span> <span class="preprocessor">#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l02136"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b01eca562bdb60e5416840fca47fff6"> 2136</a></span> <span class="preprocessor">#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l02137"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c44a4e585b3ab1c37a6c2c28c90d6cd"> 2137</a></span> <span class="preprocessor">#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l02138"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3cf9e83cec96164f1dadf4e43411ebf0"> 2138</a></span> <span class="preprocessor">#define CAN_TSR_ALST2 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l02139"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga782c591bb204d751b470dd53a37d240e"> 2139</a></span> <span class="preprocessor">#define CAN_TSR_TERR2 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l02140"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga75db1172038ebd72db1ed2fedc6108ff"> 2140</a></span> <span class="preprocessor">#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l02141"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26a85626eb26bf99413ba80c676d0af8"> 2141</a></span> <span class="preprocessor">#define CAN_TSR_CODE ((uint32_t)0x03000000) </span></div>
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<div class="line"><a name="l02143"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac00145ea43822f362f3d473bba62fa13"> 2143</a></span> <span class="preprocessor">#define CAN_TSR_TME ((uint32_t)0x1C000000) </span></div>
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<div class="line"><a name="l02144"></a><span class="lineno"> 2144</span> <span class="preprocessor">#define CAN_TSR_TME0 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l02145"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga61ab11e97b42c5210109516e30af9b05"> 2145</a></span> <span class="preprocessor">#define CAN_TSR_TME1 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l02146"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7500e491fe82e67ed5d40759e8a50f0"> 2146</a></span> <span class="preprocessor">#define CAN_TSR_TME2 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l02148"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6523fac51d3aed2e36de4c2f07c2a21"> 2148</a></span> <span class="preprocessor">#define CAN_TSR_LOW ((uint32_t)0xE0000000) </span></div>
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<div class="line"><a name="l02149"></a><span class="lineno"> 2149</span> <span class="preprocessor">#define CAN_TSR_LOW0 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l02150"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96c6453caa447cc4a9961d6ee5dea74e"> 2150</a></span> <span class="preprocessor">#define CAN_TSR_LOW1 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l02151"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79ff582efea1d7be2d1de7a1fd1a2b65"> 2151</a></span> <span class="preprocessor">#define CAN_TSR_LOW2 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l02153"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd1db2c2ce76b732fdb71df65fb8124f"> 2153</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_RF0R register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02154"></a><span class="lineno"> 2154</span> <span class="preprocessor">#define CAN_RF0R_FMP0 ((uint8_t)0x03) </span></div>
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<div class="line"><a name="l02155"></a><span class="lineno"> 2155</span> <span class="preprocessor">#define CAN_RF0R_FULL0 ((uint8_t)0x08) </span></div>
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<div class="line"><a name="l02156"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e23f3d7947e58531524d77b5c4741cc"> 2156</a></span> <span class="preprocessor">#define CAN_RF0R_FOVR0 ((uint8_t)0x10) </span></div>
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<div class="line"><a name="l02157"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae934674f6e22a758e430f32cfc386d70"> 2157</a></span> <span class="preprocessor">#define CAN_RF0R_RFOM0 ((uint8_t)0x20) </span></div>
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<div class="line"><a name="l02159"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74d2db4b9b7d52712e47557dcc61964d"> 2159</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_RF1R register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02160"></a><span class="lineno"> 2160</span> <span class="preprocessor">#define CAN_RF1R_FMP1 ((uint8_t)0x03) </span></div>
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<div class="line"><a name="l02161"></a><span class="lineno"> 2161</span> <span class="preprocessor">#define CAN_RF1R_FULL1 ((uint8_t)0x08) </span></div>
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<div class="line"><a name="l02162"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f9254d05043df6f21bf96234a03f72f"> 2162</a></span> <span class="preprocessor">#define CAN_RF1R_FOVR1 ((uint8_t)0x10) </span></div>
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<div class="line"><a name="l02163"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabdaa12fe4d14254cc4a6a4de749a7d0a"> 2163</a></span> <span class="preprocessor">#define CAN_RF1R_RFOM1 ((uint8_t)0x20) </span></div>
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<div class="line"><a name="l02165"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6930f860de4a90e3344e63fbc209b9ab"> 2165</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for CAN_IER register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02166"></a><span class="lineno"> 2166</span> <span class="preprocessor">#define CAN_IER_TMEIE ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l02167"></a><span class="lineno"> 2167</span> <span class="preprocessor">#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02168"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe027af7acd051f5a52db78608a36e26"> 2168</a></span> <span class="preprocessor">#define CAN_IER_FFIE0 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02169"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga59eecd1bb7d1d0e17422a26ae89cf39d"> 2169</a></span> <span class="preprocessor">#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l02170"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf926ae29d98a8b72ef48f001fda07fc3"> 2170</a></span> <span class="preprocessor">#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l02171"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c423699fdcd2ddddb3046a368505679"> 2171</a></span> <span class="preprocessor">#define CAN_IER_FFIE1 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l02172"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b8492d1b8ce13fead7869a0e4ef39ed"> 2172</a></span> <span class="preprocessor">#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l02173"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5a7e9d13e8d96bef2ac1972520b1c4f"> 2173</a></span> <span class="preprocessor">#define CAN_IER_EWGIE ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l02174"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3734d9bf5cd08ff219b2d8c2f8300dbf"> 2174</a></span> <span class="preprocessor">#define CAN_IER_EPVIE ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l02175"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa80103eca53d74a2b047f761336918e3"> 2175</a></span> <span class="preprocessor">#define CAN_IER_BOFIE ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l02176"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e3307992cabee858287305a64e5031b"> 2176</a></span> <span class="preprocessor">#define CAN_IER_LECIE ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l02177"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d953fd5b625af04f95f5414259769ef"> 2177</a></span> <span class="preprocessor">#define CAN_IER_ERRIE ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l02178"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81514ecf1b6596e9930906779c4bdf39"> 2178</a></span> <span class="preprocessor">#define CAN_IER_WKUIE ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l02179"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga962968c3ee1f70c714a5b12442369d9a"> 2179</a></span> <span class="preprocessor">#define CAN_IER_SLKIE ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l02181"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga82389b79f21410f5d5f6bef38d192812"> 2181</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for CAN_ESR register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02182"></a><span class="lineno"> 2182</span> <span class="preprocessor">#define CAN_ESR_EWGF ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l02183"></a><span class="lineno"> 2183</span> <span class="preprocessor">#define CAN_ESR_EPVF ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02184"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c0c02829fb41ac2a1b1852c19931de8"> 2184</a></span> <span class="preprocessor">#define CAN_ESR_BOFF ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02186"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga619d49f67f1835a7efc457205fea1225"> 2186</a></span> <span class="preprocessor">#define CAN_ESR_LEC ((uint32_t)0x00000070) </span></div>
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<div class="line"><a name="l02187"></a><span class="lineno"> 2187</span> <span class="preprocessor">#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l02188"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9f86741dd89034900e300499ae2272e"> 2188</a></span> <span class="preprocessor">#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l02189"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga054ebb41578d890d4d9dffb4828f02e7"> 2189</a></span> <span class="preprocessor">#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l02191"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4998e7bfd002999413c68107911c6e8c"> 2191</a></span> <span class="preprocessor">#define CAN_ESR_TEC ((uint32_t)0x00FF0000) </span></div>
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<div class="line"><a name="l02192"></a><span class="lineno"> 2192</span> <span class="preprocessor">#define CAN_ESR_REC ((uint32_t)0xFF000000) </span></div>
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<div class="line"><a name="l02194"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0df5b2ea3f419182e9bd885f55ee5dc9"> 2194</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_BTR register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02195"></a><span class="lineno"> 2195</span> <span class="preprocessor">#define CAN_BTR_BRP ((uint32_t)0x000003FF) </span></div>
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<div class="line"><a name="l02196"></a><span class="lineno"> 2196</span> <span class="preprocessor">#define CAN_BTR_TS1 ((uint32_t)0x000F0000) </span></div>
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<div class="line"><a name="l02197"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96a5522b4c06551856f7185bdd448b02"> 2197</a></span> <span class="preprocessor">#define CAN_BTR_TS2 ((uint32_t)0x00700000) </span></div>
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<div class="line"><a name="l02198"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d7ae8f06f8fbbf5dcfbbbb887057be9"> 2198</a></span> <span class="preprocessor">#define CAN_BTR_SJW ((uint32_t)0x03000000) </span></div>
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<div class="line"><a name="l02199"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac006aa2ab26c50227ccaa18e0a79bff3"> 2199</a></span> <span class="preprocessor">#define CAN_BTR_LBKM ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l02200"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04c8b91ddacdcbb779bae42398c94cf2"> 2200</a></span> <span class="preprocessor">#define CAN_BTR_SILM ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l02203"></a><span class="lineno"> 2203</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for CAN_TI0R register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02204"></a><span class="lineno"> 2204</span> <span class="preprocessor">#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l02205"></a><span class="lineno"> 2205</span> <span class="preprocessor">#define CAN_TI0R_RTR ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02206"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b79cbb7ebb7f3419aa6ac04bd76899a"> 2206</a></span> <span class="preprocessor">#define CAN_TI0R_IDE ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02207"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5556f2ceb5b71b8afa76a18a31cbb6a"> 2207</a></span> <span class="preprocessor">#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) </span></div>
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<div class="line"><a name="l02208"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06f761a877f8ad39f878284f69119c0b"> 2208</a></span> <span class="preprocessor">#define CAN_TI0R_STID ((uint32_t)0xFFE00000) </span></div>
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<div class="line"><a name="l02210"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d3b5882e1f9f76f5cfebffb5bc2f717"> 2210</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for CAN_TDT0R register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02211"></a><span class="lineno"> 2211</span> <span class="preprocessor">#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) </span></div>
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<div class="line"><a name="l02212"></a><span class="lineno"> 2212</span> <span class="preprocessor">#define CAN_TDT0R_TGT ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l02213"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf812eaee11f12863773b3f8e95ae6e2"> 2213</a></span> <span class="preprocessor">#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) </span></div>
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<div class="line"><a name="l02215"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga104ba91151bf88edd44593b1690b879a"> 2215</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for CAN_TDL0R register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02216"></a><span class="lineno"> 2216</span> <span class="preprocessor">#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) </span></div>
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<div class="line"><a name="l02217"></a><span class="lineno"> 2217</span> <span class="preprocessor">#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) </span></div>
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<div class="line"><a name="l02218"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadec3350607b41410ddb6e00a71a4384e"> 2218</a></span> <span class="preprocessor">#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) </span></div>
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<div class="line"><a name="l02219"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1cd20d218027e7432178c67414475830"> 2219</a></span> <span class="preprocessor">#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) </span></div>
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<div class="line"><a name="l02221"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga283a1bfa52851ea4ee45f45817985752"> 2221</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for CAN_TDH0R register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02222"></a><span class="lineno"> 2222</span> <span class="preprocessor">#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) </span></div>
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<div class="line"><a name="l02223"></a><span class="lineno"> 2223</span> <span class="preprocessor">#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) </span></div>
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<div class="line"><a name="l02224"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0114ae75b33f978ca7825f7bcd836982"> 2224</a></span> <span class="preprocessor">#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) </span></div>
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<div class="line"><a name="l02225"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5b6a0742ac1bcd5ef0408cb0f92ef75"> 2225</a></span> <span class="preprocessor">#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) </span></div>
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<div class="line"><a name="l02227"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6021a4045fbfd71817bf9aec6cbc731c"> 2227</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_TI1R register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02228"></a><span class="lineno"> 2228</span> <span class="preprocessor">#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l02229"></a><span class="lineno"> 2229</span> <span class="preprocessor">#define CAN_TI1R_RTR ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02230"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0adf4a08415673753fafedf463f93bee"> 2230</a></span> <span class="preprocessor">#define CAN_TI1R_IDE ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02231"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga476cde56b1a2a13cde8477d5178ba34b"> 2231</a></span> <span class="preprocessor">#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) </span></div>
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<div class="line"><a name="l02232"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f338f3e295b7b512ed865b3f9a8d6de"> 2232</a></span> <span class="preprocessor">#define CAN_TI1R_STID ((uint32_t)0xFFE00000) </span></div>
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<div class="line"><a name="l02234"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga842071768c2f8f5eae11a764a77dd0dd"> 2234</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_TDT1R register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02235"></a><span class="lineno"> 2235</span> <span class="preprocessor">#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) </span></div>
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<div class="line"><a name="l02236"></a><span class="lineno"> 2236</span> <span class="preprocessor">#define CAN_TDT1R_TGT ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l02237"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68ef8b6cb43a80d29c5fc318a67acd3b"> 2237</a></span> <span class="preprocessor">#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) </span></div>
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<div class="line"><a name="l02239"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad28ac334a59a6679c362611d65666910"> 2239</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_TDL1R register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02240"></a><span class="lineno"> 2240</span> <span class="preprocessor">#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) </span></div>
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<div class="line"><a name="l02241"></a><span class="lineno"> 2241</span> <span class="preprocessor">#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) </span></div>
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<div class="line"><a name="l02242"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga21abc05257bcdfa47fc824b4d806a105"> 2242</a></span> <span class="preprocessor">#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) </span></div>
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<div class="line"><a name="l02243"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0bf459dee1be706b38141722be67e4ab"> 2243</a></span> <span class="preprocessor">#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) </span></div>
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<div class="line"><a name="l02245"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga482506faa59360c6a48aa9bc55a024c4"> 2245</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_TDH1R register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02246"></a><span class="lineno"> 2246</span> <span class="preprocessor">#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) </span></div>
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<div class="line"><a name="l02247"></a><span class="lineno"> 2247</span> <span class="preprocessor">#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) </span></div>
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|
<div class="line"><a name="l02248"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41c3f19eea0d63211f643833da984c90"> 2248</a></span> <span class="preprocessor">#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) </span></div>
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<div class="line"><a name="l02249"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga35cbe73d2ce87b6aaf19510818610d16"> 2249</a></span> <span class="preprocessor">#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) </span></div>
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<div class="line"><a name="l02251"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec56ce4aba46e836d44e2c034a9ed817"> 2251</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_TI2R register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02252"></a><span class="lineno"> 2252</span> <span class="preprocessor">#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l02253"></a><span class="lineno"> 2253</span> <span class="preprocessor">#define CAN_TI2R_RTR ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02254"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab4edd8438a684e353c497f80cb37365f"> 2254</a></span> <span class="preprocessor">#define CAN_TI2R_IDE ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02255"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga980cfab3daebb05da35b6166a051385d"> 2255</a></span> <span class="preprocessor">#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) </span></div>
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<div class="line"><a name="l02256"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1d888a2225c77452f73bf66fb0e1b78"> 2256</a></span> <span class="preprocessor">#define CAN_TI2R_STID ((uint32_t)0xFFE00000) </span></div>
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<div class="line"><a name="l02258"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41c8bd734dd29caa40d34ced3981443a"> 2258</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_TDT2R register ******************/</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l02259"></a><span class="lineno"> 2259</span> <span class="preprocessor">#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) </span></div>
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<div class="line"><a name="l02260"></a><span class="lineno"> 2260</span> <span class="preprocessor">#define CAN_TDT2R_TGT ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l02261"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52898eb9fa3bcf0b8086220971af49f5"> 2261</a></span> <span class="preprocessor">#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) </span></div>
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<div class="line"><a name="l02263"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga508aea584f7c81700b485916a13431fa"> 2263</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_TDL2R register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02264"></a><span class="lineno"> 2264</span> <span class="preprocessor">#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) </span></div>
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<div class="line"><a name="l02265"></a><span class="lineno"> 2265</span> <span class="preprocessor">#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) </span></div>
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<div class="line"><a name="l02266"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a9852d0f6058c19f0e678228ea14a21"> 2266</a></span> <span class="preprocessor">#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) </span></div>
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<div class="line"><a name="l02267"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5be1bcda68f562be669184b30727be1"> 2267</a></span> <span class="preprocessor">#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) </span></div>
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<div class="line"><a name="l02269"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d76ed3982f13fb34a54d62f0caa3fa2"> 2269</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_TDH2R register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02270"></a><span class="lineno"> 2270</span> <span class="preprocessor">#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) </span></div>
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<div class="line"><a name="l02271"></a><span class="lineno"> 2271</span> <span class="preprocessor">#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) </span></div>
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<div class="line"><a name="l02272"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23a93a13da2f302ecd2f0c462065428d"> 2272</a></span> <span class="preprocessor">#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) </span></div>
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<div class="line"><a name="l02273"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9f372328c8d1e4fe2503d45aed50fb6"> 2273</a></span> <span class="preprocessor">#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) </span></div>
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<div class="line"><a name="l02275"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga895341b943e4b01938857b84a0b0dbda"> 2275</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_RI0R register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02276"></a><span class="lineno"> 2276</span> <span class="preprocessor">#define CAN_RI0R_RTR ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02277"></a><span class="lineno"> 2277</span> <span class="preprocessor">#define CAN_RI0R_IDE ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02278"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41f4780b822a42834bf1927eb92b4fba"> 2278</a></span> <span class="preprocessor">#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) </span></div>
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<div class="line"><a name="l02279"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga688074182caafff289c921548bc9afca"> 2279</a></span> <span class="preprocessor">#define CAN_RI0R_STID ((uint32_t)0xFFE00000) </span></div>
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<div class="line"><a name="l02281"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga101aa355c83b8c7d068f02b7dcc5b98f"> 2281</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_RDT0R register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02282"></a><span class="lineno"> 2282</span> <span class="preprocessor">#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) </span></div>
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<div class="line"><a name="l02283"></a><span class="lineno"> 2283</span> <span class="preprocessor">#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) </span></div>
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<div class="line"><a name="l02284"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17ca0af4afd89e6a1c43ffd1430359b7"> 2284</a></span> <span class="preprocessor">#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) </span></div>
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<div class="line"><a name="l02286"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae20b7a72690033591eeda7a511ac4a2e"> 2286</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_RDL0R register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02287"></a><span class="lineno"> 2287</span> <span class="preprocessor">#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) </span></div>
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<div class="line"><a name="l02288"></a><span class="lineno"> 2288</span> <span class="preprocessor">#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) </span></div>
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<div class="line"><a name="l02289"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44313106efc3a5a65633168a2ad1928d"> 2289</a></span> <span class="preprocessor">#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) </span></div>
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<div class="line"><a name="l02290"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga73d4025ce501af78db93761e8b8c3b9e"> 2290</a></span> <span class="preprocessor">#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) </span></div>
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<div class="line"><a name="l02292"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad637a53ae780998f95f2bb570d5cd05a"> 2292</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_RDH0R register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02293"></a><span class="lineno"> 2293</span> <span class="preprocessor">#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) </span></div>
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<div class="line"><a name="l02294"></a><span class="lineno"> 2294</span> <span class="preprocessor">#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) </span></div>
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<div class="line"><a name="l02295"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4dc7309c31cda93d05bb1fe1c923646c"> 2295</a></span> <span class="preprocessor">#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) </span></div>
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<div class="line"><a name="l02296"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga577eba5ab3a66283f5c0837e91f1776a"> 2296</a></span> <span class="preprocessor">#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) </span></div>
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<div class="line"><a name="l02298"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga243b8a3632812b2f8c7b447ed635ce5f"> 2298</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_RI1R register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02299"></a><span class="lineno"> 2299</span> <span class="preprocessor">#define CAN_RI1R_RTR ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02300"></a><span class="lineno"> 2300</span> <span class="preprocessor">#define CAN_RI1R_IDE ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02301"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafbd0ecd9579a339bffb95ea3b7c9f1e8"> 2301</a></span> <span class="preprocessor">#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) </span></div>
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<div class="line"><a name="l02302"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8dcedeb4250767a66a4d60c67e367cf8"> 2302</a></span> <span class="preprocessor">#define CAN_RI1R_STID ((uint32_t)0xFFE00000) </span></div>
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<div class="line"><a name="l02304"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f3c3aab0f24533821188d14901b3980"> 2304</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_RDT1R register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02305"></a><span class="lineno"> 2305</span> <span class="preprocessor">#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) </span></div>
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<div class="line"><a name="l02306"></a><span class="lineno"> 2306</span> <span class="preprocessor">#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) </span></div>
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<div class="line"><a name="l02307"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga964b0fa7c70a24a74165c57b3486aae8"> 2307</a></span> <span class="preprocessor">#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) </span></div>
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<div class="line"><a name="l02309"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac112cba5a4cd0b541c1150263132c68a"> 2309</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_RDL1R register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02310"></a><span class="lineno"> 2310</span> <span class="preprocessor">#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) </span></div>
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<div class="line"><a name="l02311"></a><span class="lineno"> 2311</span> <span class="preprocessor">#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) </span></div>
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<div class="line"><a name="l02312"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e399fed282a5aac0b25b059fcf04020"> 2312</a></span> <span class="preprocessor">#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) </span></div>
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<div class="line"><a name="l02313"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27ec34e08f87e8836f32bbfed52e860a"> 2313</a></span> <span class="preprocessor">#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) </span></div>
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<div class="line"><a name="l02315"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80bfe3e724b28e8d2a5b7ac4393212cf"> 2315</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_RDH1R register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02316"></a><span class="lineno"> 2316</span> <span class="preprocessor">#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) </span></div>
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<div class="line"><a name="l02317"></a><span class="lineno"> 2317</span> <span class="preprocessor">#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) </span></div>
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<div class="line"><a name="l02318"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc2a55c1b5195cf043ef33e79d736255"> 2318</a></span> <span class="preprocessor">#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) </span></div>
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<div class="line"><a name="l02319"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81d25a1ea5ad28e7db4a2adbb8a651ad"> 2319</a></span> <span class="preprocessor">#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) </span></div>
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<div class="line"><a name="l02322"></a><span class="lineno"> 2322</span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_FMR register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02323"></a><span class="lineno"> 2323</span> <span class="preprocessor">#define CAN_FMR_FINIT ((uint8_t)0x01) </span></div>
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<div class="line"><a name="l02325"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5eb5b835ee11a78bd391b9d1049f2549"> 2325</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_FM1R register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02326"></a><span class="lineno"> 2326</span> <span class="preprocessor">#define CAN_FM1R_FBM ((uint16_t)0x3FFF) </span></div>
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<div class="line"><a name="l02327"></a><span class="lineno"> 2327</span> <span class="preprocessor">#define CAN_FM1R_FBM0 ((uint16_t)0x0001) </span></div>
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<div class="line"><a name="l02328"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga481099e17a895e92cfbcfca617d52860"> 2328</a></span> <span class="preprocessor">#define CAN_FM1R_FBM1 ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l02329"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d95ff05ed6ef9a38e9af9c0d3db3687"> 2329</a></span> <span class="preprocessor">#define CAN_FM1R_FBM2 ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l02330"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2839d73344a7601aa22b5ed3fc0e5d1"> 2330</a></span> <span class="preprocessor">#define CAN_FM1R_FBM3 ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l02331"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ba7963ac4eb5b936c444258c13f8940"> 2331</a></span> <span class="preprocessor">#define CAN_FM1R_FBM4 ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l02332"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d129b27c2af41ae39e606e802a53386"> 2332</a></span> <span class="preprocessor">#define CAN_FM1R_FBM5 ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l02333"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0c94e5f4dcceea510fc72b86128aff3"> 2333</a></span> <span class="preprocessor">#define CAN_FM1R_FBM6 ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l02334"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d7fb7c366544a1ef7a85481d3e6325d"> 2334</a></span> <span class="preprocessor">#define CAN_FM1R_FBM7 ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l02335"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ff70e74447679a0d1cde1aa69ea2db1"> 2335</a></span> <span class="preprocessor">#define CAN_FM1R_FBM8 ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l02336"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga657fc12fd334bc626b2eb53fb03457b0"> 2336</a></span> <span class="preprocessor">#define CAN_FM1R_FBM9 ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l02337"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab6bc390ed9a658014fd09fd1073e3037"> 2337</a></span> <span class="preprocessor">#define CAN_FM1R_FBM10 ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l02338"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga375758246b99234dda725b7c64daff32"> 2338</a></span> <span class="preprocessor">#define CAN_FM1R_FBM11 ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l02339"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a98c6bde07c570463b6c0e32c0f6805"> 2339</a></span> <span class="preprocessor">#define CAN_FM1R_FBM12 ((uint16_t)0x1000) </span></div>
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<div class="line"><a name="l02340"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab88796333c19954176ef77208cae4964"> 2340</a></span> <span class="preprocessor">#define CAN_FM1R_FBM13 ((uint16_t)0x2000) </span></div>
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<div class="line"><a name="l02342"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf03b553802edd3ae23b70e97228b6dcc"> 2342</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_FS1R register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02343"></a><span class="lineno"> 2343</span> <span class="preprocessor">#define CAN_FS1R_FSC ((uint16_t)0x3FFF) </span></div>
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<div class="line"><a name="l02344"></a><span class="lineno"> 2344</span> <span class="preprocessor">#define CAN_FS1R_FSC0 ((uint16_t)0x0001) </span></div>
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<div class="line"><a name="l02345"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab41471f35878bcdff72d9cd05acf4714"> 2345</a></span> <span class="preprocessor">#define CAN_FS1R_FSC1 ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l02346"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab5ea9e0ed17df35894fff7828c89cad"> 2346</a></span> <span class="preprocessor">#define CAN_FS1R_FSC2 ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l02347"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83304e93d2e75c1cd8bfe7c2ec30c1c8"> 2347</a></span> <span class="preprocessor">#define CAN_FS1R_FSC3 ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l02348"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ba1fa61fcf851188a6f16323dda1358"> 2348</a></span> <span class="preprocessor">#define CAN_FS1R_FSC4 ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l02349"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2175f52f4308c088458f9e54a1f1354"> 2349</a></span> <span class="preprocessor">#define CAN_FS1R_FSC5 ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l02350"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga791ac090d6a8f2c79cd72f9072aef30f"> 2350</a></span> <span class="preprocessor">#define CAN_FS1R_FSC6 ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l02351"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb4ef2030ec70a4635ca4ac38cca76cb"> 2351</a></span> <span class="preprocessor">#define CAN_FS1R_FSC7 ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l02352"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf015be41f803007b9d0b2f3371e3621b"> 2352</a></span> <span class="preprocessor">#define CAN_FS1R_FSC8 ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l02353"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga206d175417e2c787b44b0734708a5c9a"> 2353</a></span> <span class="preprocessor">#define CAN_FS1R_FSC9 ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l02354"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7209f008874dadf147cb5357ee46c226"> 2354</a></span> <span class="preprocessor">#define CAN_FS1R_FSC10 ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l02355"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga58b4d8fa56d898ad6bf66ba8a4e098eb"> 2355</a></span> <span class="preprocessor">#define CAN_FS1R_FSC11 ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l02356"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93162a66091ffd4829ed8265f53fe977"> 2356</a></span> <span class="preprocessor">#define CAN_FS1R_FSC12 ((uint16_t)0x1000) </span></div>
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<div class="line"><a name="l02357"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2e0bf399ea9175123c95c7010ef527d"> 2357</a></span> <span class="preprocessor">#define CAN_FS1R_FSC13 ((uint16_t)0x2000) </span></div>
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<div class="line"><a name="l02359"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2df1f2a554fc014529da34620739bc4"> 2359</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for CAN_FFA1R register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02360"></a><span class="lineno"> 2360</span> <span class="preprocessor">#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) </span></div>
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<div class="line"><a name="l02361"></a><span class="lineno"> 2361</span> <span class="preprocessor">#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) </span></div>
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<div class="line"><a name="l02362"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16fa4bf13579d29b57f7602489d043fe"> 2362</a></span> <span class="preprocessor">#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l02363"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b1a0f95bac4fed1a801da0cdbf2a833"> 2363</a></span> <span class="preprocessor">#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l02364"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba35e135e17431de861e57b550421386"> 2364</a></span> <span class="preprocessor">#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l02365"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b64393197f5cd0bd6e4853828a98065"> 2365</a></span> <span class="preprocessor">#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l02366"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga111ce1e4500e2c0f543128dddbe941e9"> 2366</a></span> <span class="preprocessor">#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l02367"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a824c777e7fea25f580bc313ed2ece6"> 2367</a></span> <span class="preprocessor">#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l02368"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd571c9c746225e9b856ce3a46c3bb2f"> 2368</a></span> <span class="preprocessor">#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l02369"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2afec157fe9684f1fa4b4401500f035"> 2369</a></span> <span class="preprocessor">#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l02370"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d70e150cfd4866ea6b0a264ad45f51b"> 2370</a></span> <span class="preprocessor">#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l02371"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa802583aa70aadeb46366ff98eccaf1"> 2371</a></span> <span class="preprocessor">#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l02372"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ee7da4c7e42fa7576d965c4bf94c089"> 2372</a></span> <span class="preprocessor">#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l02373"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ac0384eab9b0cfdb491a960279fc438"> 2373</a></span> <span class="preprocessor">#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) </span></div>
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<div class="line"><a name="l02374"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaacd7e79ab503ec5143b5848edac71817"> 2374</a></span> <span class="preprocessor">#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) </span></div>
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<div class="line"><a name="l02376"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac74339b69a2e6f67df9b6e136089c0ee"> 2376</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_FA1R register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02377"></a><span class="lineno"> 2377</span> <span class="preprocessor">#define CAN_FA1R_FACT ((uint16_t)0x3FFF) </span></div>
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<div class="line"><a name="l02378"></a><span class="lineno"> 2378</span> <span class="preprocessor">#define CAN_FA1R_FACT0 ((uint16_t)0x0001) </span></div>
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<div class="line"><a name="l02379"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa571445875b08a9514e1d1b410a93ebd"> 2379</a></span> <span class="preprocessor">#define CAN_FA1R_FACT1 ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l02380"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3ec1e2f9b9ccf2b4869cdf7c7328e60"> 2380</a></span> <span class="preprocessor">#define CAN_FA1R_FACT2 ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l02381"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2457026460aecb52dba7ea17237b4dbe"> 2381</a></span> <span class="preprocessor">#define CAN_FA1R_FACT3 ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l02382"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66354c26d0252cc86729365b315a69ee"> 2382</a></span> <span class="preprocessor">#define CAN_FA1R_FACT4 ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l02383"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga087dc5f2bdfe084eb98d2a0d06a29f1d"> 2383</a></span> <span class="preprocessor">#define CAN_FA1R_FACT5 ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l02384"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c46367b7e5ea831e34ba4cf824a63da"> 2384</a></span> <span class="preprocessor">#define CAN_FA1R_FACT6 ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l02385"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga548238c7babf34116fdb44b4575e2664"> 2385</a></span> <span class="preprocessor">#define CAN_FA1R_FACT7 ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l02386"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae403370a70f9ea2b6f9b449cafa6a91c"> 2386</a></span> <span class="preprocessor">#define CAN_FA1R_FACT8 ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l02387"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33e9f4334cf3bf9e7e30d5edf278a02b"> 2387</a></span> <span class="preprocessor">#define CAN_FA1R_FACT9 ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l02388"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ccbdd2932828bfa1d68777cb595f12e"> 2388</a></span> <span class="preprocessor">#define CAN_FA1R_FACT10 ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l02389"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf8e4011791e551feeae33c47ef2b6a6a"> 2389</a></span> <span class="preprocessor">#define CAN_FA1R_FACT11 ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l02390"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19696d8b702b33eafe7f18aa0c6c1955"> 2390</a></span> <span class="preprocessor">#define CAN_FA1R_FACT12 ((uint16_t)0x1000) </span></div>
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<div class="line"><a name="l02391"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89e5e3ccd4250ad2360b91ef51248a66"> 2391</a></span> <span class="preprocessor">#define CAN_FA1R_FACT13 ((uint16_t)0x2000) </span></div>
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<div class="line"><a name="l02393"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa722eeef87f8a3f58ebfcb531645cc05"> 2393</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F0R1 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02394"></a><span class="lineno"> 2394</span> <span class="preprocessor">#define CAN_F0R1_FB0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l02395"></a><span class="lineno"> 2395</span> <span class="preprocessor">#define CAN_F0R1_FB1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02396"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga38014ea45b62975627f8e222390f6819"> 2396</a></span> <span class="preprocessor">#define CAN_F0R1_FB2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02397"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e01c05df79304035c7aab1c7295bf3f"> 2397</a></span> <span class="preprocessor">#define CAN_F0R1_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l02398"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga083282146d4db7f757fef86cf302eded"> 2398</a></span> <span class="preprocessor">#define CAN_F0R1_FB4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l02399"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4a1adc2e4e550a38649a2bfd3662680"> 2399</a></span> <span class="preprocessor">#define CAN_F0R1_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l02400"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0bfa15bf30fefb21f351228cde87981"> 2400</a></span> <span class="preprocessor">#define CAN_F0R1_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l02401"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5381c154ba89611bf4381657305ecb85"> 2401</a></span> <span class="preprocessor">#define CAN_F0R1_FB7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l02402"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae224160853946732608f00ad008a6b1a"> 2402</a></span> <span class="preprocessor">#define CAN_F0R1_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l02403"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0c44034b5f42fa8250dbb8e46bc83eb"> 2403</a></span> <span class="preprocessor">#define CAN_F0R1_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l02404"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga465e092af3e73882f9eaffad13f36dea"> 2404</a></span> <span class="preprocessor">#define CAN_F0R1_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l02405"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1cb7ff6d513fec365eb5a830c3746f0"> 2405</a></span> <span class="preprocessor">#define CAN_F0R1_FB11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l02406"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b8a688856ca6b53417948f79932534d"> 2406</a></span> <span class="preprocessor">#define CAN_F0R1_FB12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l02407"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga72b81011a2d626ac398a387c89055935"> 2407</a></span> <span class="preprocessor">#define CAN_F0R1_FB13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l02408"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac178a6710aeb6c58f725dd7f00af5d5a"> 2408</a></span> <span class="preprocessor">#define CAN_F0R1_FB14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l02409"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8aee1182bef65da056242c4ed49dd0ef"> 2409</a></span> <span class="preprocessor">#define CAN_F0R1_FB15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l02410"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe16c95f454da44949977e4225590658"> 2410</a></span> <span class="preprocessor">#define CAN_F0R1_FB16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l02411"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb07dca9fddf64a3476f25f227e33e1f"> 2411</a></span> <span class="preprocessor">#define CAN_F0R1_FB17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l02412"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf019423a4b07e564dfe917b859e68e80"> 2412</a></span> <span class="preprocessor">#define CAN_F0R1_FB18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l02413"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ee508d40637a9d558d2ab85753395bd"> 2413</a></span> <span class="preprocessor">#define CAN_F0R1_FB19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l02414"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga827a459cd51a193d571a16e1d38fac22"> 2414</a></span> <span class="preprocessor">#define CAN_F0R1_FB20 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l02415"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ecfbfd6f5e129d690f1cb62ee344d78"> 2415</a></span> <span class="preprocessor">#define CAN_F0R1_FB21 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l02416"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a0568e276f245e1f167e673a1f5b92e"> 2416</a></span> <span class="preprocessor">#define CAN_F0R1_FB22 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l02417"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb71599bae1e35e750524708ac5824f1"> 2417</a></span> <span class="preprocessor">#define CAN_F0R1_FB23 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l02418"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7589f9a62f9f5406934266820a265f3a"> 2418</a></span> <span class="preprocessor">#define CAN_F0R1_FB24 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l02419"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a0db2ff3fcf3ecd929d61e548905685"> 2419</a></span> <span class="preprocessor">#define CAN_F0R1_FB25 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l02420"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2161321c3b0857a9ca07bc45ac9cd1be"> 2420</a></span> <span class="preprocessor">#define CAN_F0R1_FB26 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l02421"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa85c1d5ccfd6241059822a3aadc1053d"> 2421</a></span> <span class="preprocessor">#define CAN_F0R1_FB27 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l02422"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d82ba565f065b4dec733d002c02498b"> 2422</a></span> <span class="preprocessor">#define CAN_F0R1_FB28 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l02423"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga199d63d7155cb5212982d4902e31e70c"> 2423</a></span> <span class="preprocessor">#define CAN_F0R1_FB29 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l02424"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac82d92ad6fb51b340e8a52da903e1009"> 2424</a></span> <span class="preprocessor">#define CAN_F0R1_FB30 ((uint32_t)0x40000000) </span></div>
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|
<div class="line"><a name="l02425"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa0a651933135336bc14baa3e0a56ab1"> 2425</a></span> <span class="preprocessor">#define CAN_F0R1_FB31 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l02427"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c9745bc78a65538cbe0fb0d09911554"> 2427</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F1R1 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02428"></a><span class="lineno"> 2428</span> <span class="preprocessor">#define CAN_F1R1_FB0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l02429"></a><span class="lineno"> 2429</span> <span class="preprocessor">#define CAN_F1R1_FB1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02430"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf74bbd84aff2eb3891f6f6d0c418793c"> 2430</a></span> <span class="preprocessor">#define CAN_F1R1_FB2 ((uint32_t)0x00000004) </span></div>
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|
<div class="line"><a name="l02431"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa2cb33663f4220e5a0d416cbddcec193"> 2431</a></span> <span class="preprocessor">#define CAN_F1R1_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l02432"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86d75200e9ead1afbe88add086ac4bb4"> 2432</a></span> <span class="preprocessor">#define CAN_F1R1_FB4 ((uint32_t)0x00000010) </span></div>
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|
<div class="line"><a name="l02433"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4dbe3b567fca94f5d5e4c877e0383d4"> 2433</a></span> <span class="preprocessor">#define CAN_F1R1_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l02434"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab74c1e5fba0af06b783289d56a8d743a"> 2434</a></span> <span class="preprocessor">#define CAN_F1R1_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l02435"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga163dda15630c6f057bac420a8cb393d8"> 2435</a></span> <span class="preprocessor">#define CAN_F1R1_FB7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l02436"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd27041e24d500c940abed9aaa53910d"> 2436</a></span> <span class="preprocessor">#define CAN_F1R1_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l02437"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaadfffc15f309b85cc3abd7439ea4b8c6"> 2437</a></span> <span class="preprocessor">#define CAN_F1R1_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l02438"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf2588b13464de27f12768d33a75d2ba"> 2438</a></span> <span class="preprocessor">#define CAN_F1R1_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l02439"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga979839e5c63f94eb294a09b74f5c09bf"> 2439</a></span> <span class="preprocessor">#define CAN_F1R1_FB11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l02440"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f049fa606d557a8a468747c6d285357"> 2440</a></span> <span class="preprocessor">#define CAN_F1R1_FB12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l02441"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43409866ee9e6ea1712f50679a4bb212"> 2441</a></span> <span class="preprocessor">#define CAN_F1R1_FB13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l02442"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f86fb2f2080f513d8392d389cdaa1fd"> 2442</a></span> <span class="preprocessor">#define CAN_F1R1_FB14 ((uint32_t)0x00004000) </span></div>
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|
<div class="line"><a name="l02443"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c1b7aeeb196a6564b2b3f049590520e"> 2443</a></span> <span class="preprocessor">#define CAN_F1R1_FB15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l02444"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45bad406315318f9cecb0c783ac7218d"> 2444</a></span> <span class="preprocessor">#define CAN_F1R1_FB16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l02445"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b105deaf668c0e04950be0de975bcde"> 2445</a></span> <span class="preprocessor">#define CAN_F1R1_FB17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l02446"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84fabcf9736d7ef78587ff63cb6b1373"> 2446</a></span> <span class="preprocessor">#define CAN_F1R1_FB18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l02447"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga966d41aca2269fd8cb6830dbbd176140"> 2447</a></span> <span class="preprocessor">#define CAN_F1R1_FB19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l02448"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a53cd0cf8722dc63b8ff26d4b0fa0f7"> 2448</a></span> <span class="preprocessor">#define CAN_F1R1_FB20 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l02449"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3fb64b2b59f73045b3ead12ab1211b4b"> 2449</a></span> <span class="preprocessor">#define CAN_F1R1_FB21 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l02450"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad558faeeeaf748bdface31d4bd3ed5b6"> 2450</a></span> <span class="preprocessor">#define CAN_F1R1_FB22 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l02451"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab16bc53f206b1f318e5fe8c248294fec"> 2451</a></span> <span class="preprocessor">#define CAN_F1R1_FB23 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l02452"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42841c82744146dc70e8e679b5904e02"> 2452</a></span> <span class="preprocessor">#define CAN_F1R1_FB24 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l02453"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1f961b642e42faaaf495c9ec099c128"> 2453</a></span> <span class="preprocessor">#define CAN_F1R1_FB25 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l02454"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96670686c71a15631ec2f772973dd7d5"> 2454</a></span> <span class="preprocessor">#define CAN_F1R1_FB26 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l02455"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa2d8b1a30c3a6ae1f75369abc445ab7d"> 2455</a></span> <span class="preprocessor">#define CAN_F1R1_FB27 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l02456"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf027c958889ab93acfb1b86988269874"> 2456</a></span> <span class="preprocessor">#define CAN_F1R1_FB28 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l02457"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga32400e283bc0037da21f0c913bb860b6"> 2457</a></span> <span class="preprocessor">#define CAN_F1R1_FB29 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l02458"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb0467d664f27b3ca8ef4ad220593c46"> 2458</a></span> <span class="preprocessor">#define CAN_F1R1_FB30 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l02459"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c3e3090ab67a54830be208a628efd8f"> 2459</a></span> <span class="preprocessor">#define CAN_F1R1_FB31 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l02461"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ddfc083d58a190057fb67e4eb31136b"> 2461</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F2R1 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02462"></a><span class="lineno"> 2462</span> <span class="preprocessor">#define CAN_F2R1_FB0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l02463"></a><span class="lineno"> 2463</span> <span class="preprocessor">#define CAN_F2R1_FB1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02464"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf17f4c3e553020ee893415796bd29d84"> 2464</a></span> <span class="preprocessor">#define CAN_F2R1_FB2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02465"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae97de172023462e5f40d4b420209809b"> 2465</a></span> <span class="preprocessor">#define CAN_F2R1_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l02466"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23008ac61893eb6a65ab9041c53a84ee"> 2466</a></span> <span class="preprocessor">#define CAN_F2R1_FB4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l02467"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad559580b386d0c621a6bf7292c706e36"> 2467</a></span> <span class="preprocessor">#define CAN_F2R1_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l02468"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e52ca421788d68f3edb9a52434374dd"> 2468</a></span> <span class="preprocessor">#define CAN_F2R1_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l02469"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96a97a9711a0a53a7ee18907e95d8887"> 2469</a></span> <span class="preprocessor">#define CAN_F2R1_FB7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l02470"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f73f1bd0d3246f27d7a91a620fb3cc7"> 2470</a></span> <span class="preprocessor">#define CAN_F2R1_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l02471"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga72bf4a6050af614eb1ac85c76feb95cc"> 2471</a></span> <span class="preprocessor">#define CAN_F2R1_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l02472"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad484c083bc2023deda5840facc549908"> 2472</a></span> <span class="preprocessor">#define CAN_F2R1_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l02473"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d0e05e4824f05e2cf12b3d0a0b7f319"> 2473</a></span> <span class="preprocessor">#define CAN_F2R1_FB11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l02474"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga022da7a86e8174aff1054eb1aef2c73c"> 2474</a></span> <span class="preprocessor">#define CAN_F2R1_FB12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l02475"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaedf715fa1ef43c8461408944e4aecec7"> 2475</a></span> <span class="preprocessor">#define CAN_F2R1_FB13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l02476"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47960a79c582cbc9bfef85c411a2be94"> 2476</a></span> <span class="preprocessor">#define CAN_F2R1_FB14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l02477"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8c6e3cf3a4d1e9d722e820a3a0c1b6a"> 2477</a></span> <span class="preprocessor">#define CAN_F2R1_FB15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l02478"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga421a366074fb422686461a92abd1259e"> 2478</a></span> <span class="preprocessor">#define CAN_F2R1_FB16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l02479"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga178a0308db954b97818401be1f28a990"> 2479</a></span> <span class="preprocessor">#define CAN_F2R1_FB17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l02480"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab60aef7e45f8d12777032321a33cdb38"> 2480</a></span> <span class="preprocessor">#define CAN_F2R1_FB18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l02481"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0483dac5b6986246a3ba106fbeb8e3bd"> 2481</a></span> <span class="preprocessor">#define CAN_F2R1_FB19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l02482"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga259b472c9c9f158e1701c8b8d5a940b9"> 2482</a></span> <span class="preprocessor">#define CAN_F2R1_FB20 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l02483"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23db612c79422bee815e437d6aaf5a6c"> 2483</a></span> <span class="preprocessor">#define CAN_F2R1_FB21 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l02484"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef9a469e877bfa29f4edb66730c43d43"> 2484</a></span> <span class="preprocessor">#define CAN_F2R1_FB22 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l02485"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4edc4a54cc13f63afe8dbe3aa37776a5"> 2485</a></span> <span class="preprocessor">#define CAN_F2R1_FB23 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l02486"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga169f5fb3dd35ae2b048c8c05c3e202d7"> 2486</a></span> <span class="preprocessor">#define CAN_F2R1_FB24 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l02487"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0073b206235b3c33a9b831e5027e3bf0"> 2487</a></span> <span class="preprocessor">#define CAN_F2R1_FB25 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l02488"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga459caea38417d17c042e52ba38eb3c1b"> 2488</a></span> <span class="preprocessor">#define CAN_F2R1_FB26 ((uint32_t)0x04000000) </span></div>
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|
<div class="line"><a name="l02489"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0da8cd8657f6e67f1d86fc9f695bb4e"> 2489</a></span> <span class="preprocessor">#define CAN_F2R1_FB27 ((uint32_t)0x08000000) </span></div>
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|
<div class="line"><a name="l02490"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80c9ae7f2eca3db813737c49d49f2b08"> 2490</a></span> <span class="preprocessor">#define CAN_F2R1_FB28 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l02491"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d6b6c109e359e3d2a07e6626c2b4aff"> 2491</a></span> <span class="preprocessor">#define CAN_F2R1_FB29 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l02492"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c4d05997d8930291c8ab2bb19545714"> 2492</a></span> <span class="preprocessor">#define CAN_F2R1_FB30 ((uint32_t)0x40000000) </span></div>
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|
<div class="line"><a name="l02493"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5431f98aafd2a7f8158a335d65ebea1"> 2493</a></span> <span class="preprocessor">#define CAN_F2R1_FB31 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l02495"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaada8442f47c1fffb00c13e404d036122"> 2495</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F3R1 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02496"></a><span class="lineno"> 2496</span> <span class="preprocessor">#define CAN_F3R1_FB0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l02497"></a><span class="lineno"> 2497</span> <span class="preprocessor">#define CAN_F3R1_FB1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02498"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6bc065319a9862c1f5ca7326b790ef53"> 2498</a></span> <span class="preprocessor">#define CAN_F3R1_FB2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02499"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42e636521c72a20aa8380fe4fe150b91"> 2499</a></span> <span class="preprocessor">#define CAN_F3R1_FB3 ((uint32_t)0x00000008) </span></div>
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|
<div class="line"><a name="l02500"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga217f5b77e4fefb2d1135187ee2b5bbf2"> 2500</a></span> <span class="preprocessor">#define CAN_F3R1_FB4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l02501"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7693dcf6c0011bbeb19e0413a5ce1f56"> 2501</a></span> <span class="preprocessor">#define CAN_F3R1_FB5 ((uint32_t)0x00000020) </span></div>
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|
<div class="line"><a name="l02502"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0bffde5d3e1e2e75f4facc98903620f7"> 2502</a></span> <span class="preprocessor">#define CAN_F3R1_FB6 ((uint32_t)0x00000040) </span></div>
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|
<div class="line"><a name="l02503"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30ccdfd3676f314e749cc205ffcfe1cf"> 2503</a></span> <span class="preprocessor">#define CAN_F3R1_FB7 ((uint32_t)0x00000080) </span></div>
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|
<div class="line"><a name="l02504"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b2aa80397b4961a33b41303aa348ea1"> 2504</a></span> <span class="preprocessor">#define CAN_F3R1_FB8 ((uint32_t)0x00000100) </span></div>
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|
<div class="line"><a name="l02505"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b7072c9b829c7df660eb2dea05ee8d8"> 2505</a></span> <span class="preprocessor">#define CAN_F3R1_FB9 ((uint32_t)0x00000200) </span></div>
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|
<div class="line"><a name="l02506"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad016208d1aa9008aaba9a887a1e8b6fa"> 2506</a></span> <span class="preprocessor">#define CAN_F3R1_FB10 ((uint32_t)0x00000400) </span></div>
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|
<div class="line"><a name="l02507"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4f4f0d2b56860e36f7777ab397e8609"> 2507</a></span> <span class="preprocessor">#define CAN_F3R1_FB11 ((uint32_t)0x00000800) </span></div>
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|
<div class="line"><a name="l02508"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadcfc2559b456c3af3804a22e0fb5c50d"> 2508</a></span> <span class="preprocessor">#define CAN_F3R1_FB12 ((uint32_t)0x00001000) </span></div>
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|
<div class="line"><a name="l02509"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7df8031e3a2f661b45fdbde58a26c6b6"> 2509</a></span> <span class="preprocessor">#define CAN_F3R1_FB13 ((uint32_t)0x00002000) </span></div>
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|
<div class="line"><a name="l02510"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c6baa9ac6a1cdd55c2d51ee40cf8f2d"> 2510</a></span> <span class="preprocessor">#define CAN_F3R1_FB14 ((uint32_t)0x00004000) </span></div>
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|
<div class="line"><a name="l02511"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95fc8c778ffa6deac5a202985fdd98ae"> 2511</a></span> <span class="preprocessor">#define CAN_F3R1_FB15 ((uint32_t)0x00008000) </span></div>
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|
<div class="line"><a name="l02512"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c4a4998f2ddc12771da116b1c20d765"> 2512</a></span> <span class="preprocessor">#define CAN_F3R1_FB16 ((uint32_t)0x00010000) </span></div>
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|
<div class="line"><a name="l02513"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5fb6157fc48147e6c74ed348d156bfa1"> 2513</a></span> <span class="preprocessor">#define CAN_F3R1_FB17 ((uint32_t)0x00020000) </span></div>
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|
<div class="line"><a name="l02514"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaadcf2a14e752519bf8a90129fb9d42b1"> 2514</a></span> <span class="preprocessor">#define CAN_F3R1_FB18 ((uint32_t)0x00040000) </span></div>
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|
<div class="line"><a name="l02515"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47c5296c991b481548302478df85e477"> 2515</a></span> <span class="preprocessor">#define CAN_F3R1_FB19 ((uint32_t)0x00080000) </span></div>
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|
<div class="line"><a name="l02516"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga657b8cda94fd736a4831ab4086ae746f"> 2516</a></span> <span class="preprocessor">#define CAN_F3R1_FB20 ((uint32_t)0x00100000) </span></div>
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|
<div class="line"><a name="l02517"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga435edc4b2055ac2d1c3ce616a9c1b236"> 2517</a></span> <span class="preprocessor">#define CAN_F3R1_FB21 ((uint32_t)0x00200000) </span></div>
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|
<div class="line"><a name="l02518"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa508de7087eb832ecaf353a4b6821ef"> 2518</a></span> <span class="preprocessor">#define CAN_F3R1_FB22 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l02519"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga643ceb9293665b8307e63ae0e1700d91"> 2519</a></span> <span class="preprocessor">#define CAN_F3R1_FB23 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l02520"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91f5887e884fcf423d680798f4e372bb"> 2520</a></span> <span class="preprocessor">#define CAN_F3R1_FB24 ((uint32_t)0x01000000) </span></div>
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|
<div class="line"><a name="l02521"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6adc9c7706f39f7c33760fe6b8c5d17e"> 2521</a></span> <span class="preprocessor">#define CAN_F3R1_FB25 ((uint32_t)0x02000000) </span></div>
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|
<div class="line"><a name="l02522"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7581186f0241f6db9f63a0a0db22919"> 2522</a></span> <span class="preprocessor">#define CAN_F3R1_FB26 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l02523"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43b4c084e802398ad265ceb69cfd7519"> 2523</a></span> <span class="preprocessor">#define CAN_F3R1_FB27 ((uint32_t)0x08000000) </span></div>
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|
<div class="line"><a name="l02524"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade732503a8d41e3f1bb338a2a8103bd2"> 2524</a></span> <span class="preprocessor">#define CAN_F3R1_FB28 ((uint32_t)0x10000000) </span></div>
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|
<div class="line"><a name="l02525"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7539a7f651425a757a549205544e508c"> 2525</a></span> <span class="preprocessor">#define CAN_F3R1_FB29 ((uint32_t)0x20000000) </span></div>
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|
<div class="line"><a name="l02526"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ec25e4ba3ebaf53780e2b8da63e4a3b"> 2526</a></span> <span class="preprocessor">#define CAN_F3R1_FB30 ((uint32_t)0x40000000) </span></div>
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|
<div class="line"><a name="l02527"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8268be8b5477f813c165e851acd41a2"> 2527</a></span> <span class="preprocessor">#define CAN_F3R1_FB31 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l02529"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15bbe0d2d24dc95e10156c2541feb4c4"> 2529</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F4R1 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02530"></a><span class="lineno"> 2530</span> <span class="preprocessor">#define CAN_F4R1_FB0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l02531"></a><span class="lineno"> 2531</span> <span class="preprocessor">#define CAN_F4R1_FB1 ((uint32_t)0x00000002) </span></div>
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|
<div class="line"><a name="l02532"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0eb0d4d21c082c8381271ab146431993"> 2532</a></span> <span class="preprocessor">#define CAN_F4R1_FB2 ((uint32_t)0x00000004) </span></div>
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|
<div class="line"><a name="l02533"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91922c78bf92f051b8e8abbf9cc1f6e9"> 2533</a></span> <span class="preprocessor">#define CAN_F4R1_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l02534"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae56f77f869114e69525353f96004f955"> 2534</a></span> <span class="preprocessor">#define CAN_F4R1_FB4 ((uint32_t)0x00000010) </span></div>
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|
<div class="line"><a name="l02535"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga951a8213e55b01ecedcef870c85841e7"> 2535</a></span> <span class="preprocessor">#define CAN_F4R1_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l02536"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga453f90cdd0b520b7d65e19af3868d4ec"> 2536</a></span> <span class="preprocessor">#define CAN_F4R1_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l02537"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace348ba56c1f9676e5b605a6fe0cd52e"> 2537</a></span> <span class="preprocessor">#define CAN_F4R1_FB7 ((uint32_t)0x00000080) </span></div>
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|
<div class="line"><a name="l02538"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae99d36b50a16c38b2006fdba4683ddd9"> 2538</a></span> <span class="preprocessor">#define CAN_F4R1_FB8 ((uint32_t)0x00000100) </span></div>
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|
<div class="line"><a name="l02539"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5d61ae4af9acc61476493b640cfb4745"> 2539</a></span> <span class="preprocessor">#define CAN_F4R1_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l02540"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89ded00ec0b6c0918b019457d6cf43f5"> 2540</a></span> <span class="preprocessor">#define CAN_F4R1_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l02541"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac658a1ced873fd9dff54833d8c413536"> 2541</a></span> <span class="preprocessor">#define CAN_F4R1_FB11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l02542"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad06bc748776a78f008895be9e0cc7a1d"> 2542</a></span> <span class="preprocessor">#define CAN_F4R1_FB12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l02543"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf612f239dcf45bd933136a5c8c5909f9"> 2543</a></span> <span class="preprocessor">#define CAN_F4R1_FB13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l02544"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6dc611a52acf6dfa1df7ebf867bc7e2f"> 2544</a></span> <span class="preprocessor">#define CAN_F4R1_FB14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l02545"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1736bc2808a37aa82358fe1c36c963a6"> 2545</a></span> <span class="preprocessor">#define CAN_F4R1_FB15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l02546"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d7ec466bbf196a41f6da2a7b506675d"> 2546</a></span> <span class="preprocessor">#define CAN_F4R1_FB16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l02547"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad30ff7e7b0c0f7e56821ecbcd6fcc23c"> 2547</a></span> <span class="preprocessor">#define CAN_F4R1_FB17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l02548"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga199bd29b6f3ff56150a9dcd71c8ea13f"> 2548</a></span> <span class="preprocessor">#define CAN_F4R1_FB18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l02549"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga893837534cbc7a043fa995de4619e2da"> 2549</a></span> <span class="preprocessor">#define CAN_F4R1_FB19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l02550"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga551e80c41958417cbcf1d0c53e4947a3"> 2550</a></span> <span class="preprocessor">#define CAN_F4R1_FB20 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l02551"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80d9a946bd39dae4b0a862cf21f262ed"> 2551</a></span> <span class="preprocessor">#define CAN_F4R1_FB21 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l02552"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5646609987ce174cf3b94bb4538172f4"> 2552</a></span> <span class="preprocessor">#define CAN_F4R1_FB22 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l02553"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga356faa77de97c61e9b5f6b763173a987"> 2553</a></span> <span class="preprocessor">#define CAN_F4R1_FB23 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l02554"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac6b246b3df35cc1db06e8c809137562f"> 2554</a></span> <span class="preprocessor">#define CAN_F4R1_FB24 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l02555"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4882da3ee5be3aed3d5eb46923859674"> 2555</a></span> <span class="preprocessor">#define CAN_F4R1_FB25 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l02556"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e178aa8c6f98a866aaae511b9da86c8"> 2556</a></span> <span class="preprocessor">#define CAN_F4R1_FB26 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l02557"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a5ca327060530761d71362d39b2d364"> 2557</a></span> <span class="preprocessor">#define CAN_F4R1_FB27 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l02558"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeabe4836aed74af4adba72b2c7684a6e"> 2558</a></span> <span class="preprocessor">#define CAN_F4R1_FB28 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l02559"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa8e7d74919e74723f7df71357cc994a"> 2559</a></span> <span class="preprocessor">#define CAN_F4R1_FB29 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l02560"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e2b2b9bd5b397e58d57fb379546110b"> 2560</a></span> <span class="preprocessor">#define CAN_F4R1_FB30 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l02561"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb165ede225dc35a825647e5efcab437"> 2561</a></span> <span class="preprocessor">#define CAN_F4R1_FB31 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l02563"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga92d7e6a44e87911e9cc14f6bff854fa2"> 2563</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F5R1 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02564"></a><span class="lineno"> 2564</span> <span class="preprocessor">#define CAN_F5R1_FB0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l02565"></a><span class="lineno"> 2565</span> <span class="preprocessor">#define CAN_F5R1_FB1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02566"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5cdf98e317662e286ad2a3344ee516df"> 2566</a></span> <span class="preprocessor">#define CAN_F5R1_FB2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02567"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac814c424ed2ccc11645da6e62f3fb81"> 2567</a></span> <span class="preprocessor">#define CAN_F5R1_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l02568"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b0af1936dd43bd319614e3298fd28d1"> 2568</a></span> <span class="preprocessor">#define CAN_F5R1_FB4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l02569"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga013f84e3f3f0e148d3a9a071ccbf6738"> 2569</a></span> <span class="preprocessor">#define CAN_F5R1_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l02570"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7cfc330921811d76ed6476d6935e84e7"> 2570</a></span> <span class="preprocessor">#define CAN_F5R1_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l02571"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf9aebaa8e61198240c1564ce73acb1d2"> 2571</a></span> <span class="preprocessor">#define CAN_F5R1_FB7 ((uint32_t)0x00000080) </span></div>
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|
<div class="line"><a name="l02572"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadea331fb6273fda80a8f5a3dc8eaf6f4"> 2572</a></span> <span class="preprocessor">#define CAN_F5R1_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l02573"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc7dfaacfba6a42a17b16281f690f952"> 2573</a></span> <span class="preprocessor">#define CAN_F5R1_FB9 ((uint32_t)0x00000200) </span></div>
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|
<div class="line"><a name="l02574"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba0938e0f55773406fd59c2a0bd7c46e"> 2574</a></span> <span class="preprocessor">#define CAN_F5R1_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l02575"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9715c4445159d0068172309092e574e3"> 2575</a></span> <span class="preprocessor">#define CAN_F5R1_FB11 ((uint32_t)0x00000800) </span></div>
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|
<div class="line"><a name="l02576"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae7de15e73395473569a447023dae53c4"> 2576</a></span> <span class="preprocessor">#define CAN_F5R1_FB12 ((uint32_t)0x00001000) </span></div>
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|
<div class="line"><a name="l02577"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39b60e0befdf681694bc4123b4b7f7bd"> 2577</a></span> <span class="preprocessor">#define CAN_F5R1_FB13 ((uint32_t)0x00002000) </span></div>
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|
<div class="line"><a name="l02578"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0bc4598d0d603c802b7140f967d84e5c"> 2578</a></span> <span class="preprocessor">#define CAN_F5R1_FB14 ((uint32_t)0x00004000) </span></div>
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|
<div class="line"><a name="l02579"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8b4439ac4bc79ff74d21060ff533b12"> 2579</a></span> <span class="preprocessor">#define CAN_F5R1_FB15 ((uint32_t)0x00008000) </span></div>
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|
<div class="line"><a name="l02580"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d117ee64d9c1673f22f12f24bd481a4"> 2580</a></span> <span class="preprocessor">#define CAN_F5R1_FB16 ((uint32_t)0x00010000) </span></div>
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|
<div class="line"><a name="l02581"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf761c448bf29c4d93f4c2a75981fa049"> 2581</a></span> <span class="preprocessor">#define CAN_F5R1_FB17 ((uint32_t)0x00020000) </span></div>
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|
<div class="line"><a name="l02582"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga87543e5b7c48580ca9925402ab6ca5a7"> 2582</a></span> <span class="preprocessor">#define CAN_F5R1_FB18 ((uint32_t)0x00040000) </span></div>
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|
<div class="line"><a name="l02583"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b9c39ec4649cd68a540c88c3c64d506"> 2583</a></span> <span class="preprocessor">#define CAN_F5R1_FB19 ((uint32_t)0x00080000) </span></div>
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|
<div class="line"><a name="l02584"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4992301536d388de215273769708b843"> 2584</a></span> <span class="preprocessor">#define CAN_F5R1_FB20 ((uint32_t)0x00100000) </span></div>
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|
<div class="line"><a name="l02585"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab21c0b793d7aff03497a95d5c6528ab2"> 2585</a></span> <span class="preprocessor">#define CAN_F5R1_FB21 ((uint32_t)0x00200000) </span></div>
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|
<div class="line"><a name="l02586"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1c4c5d06a9da5f853aaede3470b07f4"> 2586</a></span> <span class="preprocessor">#define CAN_F5R1_FB22 ((uint32_t)0x00400000) </span></div>
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|
<div class="line"><a name="l02587"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91214f1f7dbb4b75b0c425624640fd76"> 2587</a></span> <span class="preprocessor">#define CAN_F5R1_FB23 ((uint32_t)0x00800000) </span></div>
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|
<div class="line"><a name="l02588"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b24151a68c59fe0f3aa15e498fdc739"> 2588</a></span> <span class="preprocessor">#define CAN_F5R1_FB24 ((uint32_t)0x01000000) </span></div>
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|
<div class="line"><a name="l02589"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadea89ef2e5c3dafae174b671c8e083d2"> 2589</a></span> <span class="preprocessor">#define CAN_F5R1_FB25 ((uint32_t)0x02000000) </span></div>
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|
<div class="line"><a name="l02590"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2acccf9ab5708116cd888f2d65da54cc"> 2590</a></span> <span class="preprocessor">#define CAN_F5R1_FB26 ((uint32_t)0x04000000) </span></div>
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|
<div class="line"><a name="l02591"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c0b9425117a2409b61032a9c746c2b5"> 2591</a></span> <span class="preprocessor">#define CAN_F5R1_FB27 ((uint32_t)0x08000000) </span></div>
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|
<div class="line"><a name="l02592"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a0d31d96e75ea32299e78845f584632"> 2592</a></span> <span class="preprocessor">#define CAN_F5R1_FB28 ((uint32_t)0x10000000) </span></div>
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|
<div class="line"><a name="l02593"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade5db4ad8b19580b895356fff66bb6be"> 2593</a></span> <span class="preprocessor">#define CAN_F5R1_FB29 ((uint32_t)0x20000000) </span></div>
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|
<div class="line"><a name="l02594"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4acec834c3eaf55af5e745d6988ddc1e"> 2594</a></span> <span class="preprocessor">#define CAN_F5R1_FB30 ((uint32_t)0x40000000) </span></div>
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|
<div class="line"><a name="l02595"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga923a0086ada8e09a9202338b588f27d1"> 2595</a></span> <span class="preprocessor">#define CAN_F5R1_FB31 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l02597"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8d28066798958e5730a95353690bcd0"> 2597</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F6R1 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02598"></a><span class="lineno"> 2598</span> <span class="preprocessor">#define CAN_F6R1_FB0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l02599"></a><span class="lineno"> 2599</span> <span class="preprocessor">#define CAN_F6R1_FB1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02600"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacb57fe42259bd37deffe11eded640c76"> 2600</a></span> <span class="preprocessor">#define CAN_F6R1_FB2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02601"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1de288e28d5547106645ecc5b0c47f2a"> 2601</a></span> <span class="preprocessor">#define CAN_F6R1_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l02602"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa8662caaa28aee37b2689f55400b75c"> 2602</a></span> <span class="preprocessor">#define CAN_F6R1_FB4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l02603"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4ccedde67989fcbaa84cae9cae4b1eb"> 2603</a></span> <span class="preprocessor">#define CAN_F6R1_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l02604"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45b063b3c14fd27bd63c03f878ac6cfc"> 2604</a></span> <span class="preprocessor">#define CAN_F6R1_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l02605"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga32f8566fab72dec6d52ad7262e67cbcc"> 2605</a></span> <span class="preprocessor">#define CAN_F6R1_FB7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l02606"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8636ecdacc3ca05d69e66737b7f2e7cf"> 2606</a></span> <span class="preprocessor">#define CAN_F6R1_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l02607"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb555ddab4853625c9b48b24e88d0dd8"> 2607</a></span> <span class="preprocessor">#define CAN_F6R1_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l02608"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1e7ca2d014d77152ff0e6bbb8d5fb63"> 2608</a></span> <span class="preprocessor">#define CAN_F6R1_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l02609"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe4dc5e57c209eb4d3c5ed94b3a2e897"> 2609</a></span> <span class="preprocessor">#define CAN_F6R1_FB11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l02610"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa63ca9ec114f553d68e0b0d38ae57ff0"> 2610</a></span> <span class="preprocessor">#define CAN_F6R1_FB12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l02611"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf3394a2675a7cb30556a40cc5b77c08"> 2611</a></span> <span class="preprocessor">#define CAN_F6R1_FB13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l02612"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9c9c04edb492e48619de926196ab695"> 2612</a></span> <span class="preprocessor">#define CAN_F6R1_FB14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l02613"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga070e91897e07ae11a9d2f60ff31e196a"> 2613</a></span> <span class="preprocessor">#define CAN_F6R1_FB15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l02614"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3479321a85f1f55e24a1b56d13226a22"> 2614</a></span> <span class="preprocessor">#define CAN_F6R1_FB16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l02615"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a998a2b37fde5207b286a58c115a9e8"> 2615</a></span> <span class="preprocessor">#define CAN_F6R1_FB17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l02616"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga891ad3d341cee397d49fc982c509f7d5"> 2616</a></span> <span class="preprocessor">#define CAN_F6R1_FB18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l02617"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4a70606f1b07a6bbb5ae4fe8ad374e5"> 2617</a></span> <span class="preprocessor">#define CAN_F6R1_FB19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l02618"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1542ea54030e3052c8991b249cd0e504"> 2618</a></span> <span class="preprocessor">#define CAN_F6R1_FB20 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l02619"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e1a7c680bcfc57c6cc521cbaa0749d6"> 2619</a></span> <span class="preprocessor">#define CAN_F6R1_FB21 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l02620"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6fba31d938ab3492c8855c26bebfbef2"> 2620</a></span> <span class="preprocessor">#define CAN_F6R1_FB22 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l02621"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga556f3b08cee839e038109e604e5bba4c"> 2621</a></span> <span class="preprocessor">#define CAN_F6R1_FB23 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l02622"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafdc41162219ed6f5be1b5ae7ba328754"> 2622</a></span> <span class="preprocessor">#define CAN_F6R1_FB24 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l02623"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89f4fd5c28d2fd7475081b39b2b358c6"> 2623</a></span> <span class="preprocessor">#define CAN_F6R1_FB25 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l02624"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5eb9d0f3cad0eeea398f2ba5fd83cf2"> 2624</a></span> <span class="preprocessor">#define CAN_F6R1_FB26 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l02625"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3fa46e9d1fafcb3eb1189d6d43692cd"> 2625</a></span> <span class="preprocessor">#define CAN_F6R1_FB27 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l02626"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9168b4d12ddb654b397ce3ffb66af4c"> 2626</a></span> <span class="preprocessor">#define CAN_F6R1_FB28 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l02627"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga610fdf301fb1cff5af38f83b4e0c81b1"> 2627</a></span> <span class="preprocessor">#define CAN_F6R1_FB29 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l02628"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a3e033aae51ff31b75fb801599232f5"> 2628</a></span> <span class="preprocessor">#define CAN_F6R1_FB30 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l02629"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga868ae6fc3bbe273b44d250791a80df58"> 2629</a></span> <span class="preprocessor">#define CAN_F6R1_FB31 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l02631"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69b2dffd9969ff8658b45a7a2bb1c5ee"> 2631</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F7R1 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02632"></a><span class="lineno"> 2632</span> <span class="preprocessor">#define CAN_F7R1_FB0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l02633"></a><span class="lineno"> 2633</span> <span class="preprocessor">#define CAN_F7R1_FB1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02634"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2217bcc5b82de25751d3984884b0e0c1"> 2634</a></span> <span class="preprocessor">#define CAN_F7R1_FB2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02635"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf71cbdd5cbe109fde119adb86d64f0a7"> 2635</a></span> <span class="preprocessor">#define CAN_F7R1_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l02636"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0a7a004058a6b10b5cb3374eb82dd1d"> 2636</a></span> <span class="preprocessor">#define CAN_F7R1_FB4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l02637"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2224329373b490c8dd4f0c148ef58997"> 2637</a></span> <span class="preprocessor">#define CAN_F7R1_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l02638"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3574ea4882319ac08e0df065bdd3566"> 2638</a></span> <span class="preprocessor">#define CAN_F7R1_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l02639"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76f63e712a9a57dacab2874dd695254d"> 2639</a></span> <span class="preprocessor">#define CAN_F7R1_FB7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l02640"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22d969f17f8a25a63cb056ee2cb622d3"> 2640</a></span> <span class="preprocessor">#define CAN_F7R1_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l02641"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae89ec51b51c83c108880e361caf17ac"> 2641</a></span> <span class="preprocessor">#define CAN_F7R1_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l02642"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67fca99c67cab6713605e14d96a9df62"> 2642</a></span> <span class="preprocessor">#define CAN_F7R1_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l02643"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaacd1ef8f0870bc5a5422a6bedbb61d40"> 2643</a></span> <span class="preprocessor">#define CAN_F7R1_FB11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l02644"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf56408d9914f566396d64609830e2d4f"> 2644</a></span> <span class="preprocessor">#define CAN_F7R1_FB12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l02645"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65947100832111c7fb427d1982f801eb"> 2645</a></span> <span class="preprocessor">#define CAN_F7R1_FB13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l02646"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga175ed9cdbbf756ec76b9c6fb1f69adff"> 2646</a></span> <span class="preprocessor">#define CAN_F7R1_FB14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l02647"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91af48b8cd11f119d257311dcf2cc291"> 2647</a></span> <span class="preprocessor">#define CAN_F7R1_FB15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l02648"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7108bc449a6e328748dd8d2209b83753"> 2648</a></span> <span class="preprocessor">#define CAN_F7R1_FB16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l02649"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc47acac1bb59603f58d9aef661d9334"> 2649</a></span> <span class="preprocessor">#define CAN_F7R1_FB17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l02650"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b07b4ebfaac9e60d6042b1bff98ec33"> 2650</a></span> <span class="preprocessor">#define CAN_F7R1_FB18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l02651"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3328e95d8ae911adc0e5dd4128f8161"> 2651</a></span> <span class="preprocessor">#define CAN_F7R1_FB19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l02652"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga473e4917f35772cd08b06e166d6e475e"> 2652</a></span> <span class="preprocessor">#define CAN_F7R1_FB20 ((uint32_t)0x00100000) </span></div>
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|
<div class="line"><a name="l02653"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf40a4dd0979fb7ffba4b4192fe6dde5f"> 2653</a></span> <span class="preprocessor">#define CAN_F7R1_FB21 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l02654"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5854aa102655334a6242e43c0b25aede"> 2654</a></span> <span class="preprocessor">#define CAN_F7R1_FB22 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l02655"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga505dbdeaf89d103795046fb689b81664"> 2655</a></span> <span class="preprocessor">#define CAN_F7R1_FB23 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l02656"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga692f7a0bbc73be14e9d554394dceb176"> 2656</a></span> <span class="preprocessor">#define CAN_F7R1_FB24 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l02657"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a93f243e7acf3f749f2b6ec8ae7bc5f"> 2657</a></span> <span class="preprocessor">#define CAN_F7R1_FB25 ((uint32_t)0x02000000) </span></div>
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|
<div class="line"><a name="l02658"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68815c969c231268a63c8809a55bc866"> 2658</a></span> <span class="preprocessor">#define CAN_F7R1_FB26 ((uint32_t)0x04000000) </span></div>
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|
<div class="line"><a name="l02659"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7055881b4a6d9fe51e8dcfb99a546139"> 2659</a></span> <span class="preprocessor">#define CAN_F7R1_FB27 ((uint32_t)0x08000000) </span></div>
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|
<div class="line"><a name="l02660"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19ab918d9499635e8199a143833c6fdb"> 2660</a></span> <span class="preprocessor">#define CAN_F7R1_FB28 ((uint32_t)0x10000000) </span></div>
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|
<div class="line"><a name="l02661"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8360f2a2ba21a1b2f361d4330026edfd"> 2661</a></span> <span class="preprocessor">#define CAN_F7R1_FB29 ((uint32_t)0x20000000) </span></div>
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|
<div class="line"><a name="l02662"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga681e922052442801310265bab7356fc4"> 2662</a></span> <span class="preprocessor">#define CAN_F7R1_FB30 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l02663"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab12aa3a716a85bf96a1496ecaeae0cec"> 2663</a></span> <span class="preprocessor">#define CAN_F7R1_FB31 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l02665"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9990b9fd20bbe0ff114acace0cb47ad7"> 2665</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F8R1 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02666"></a><span class="lineno"> 2666</span> <span class="preprocessor">#define CAN_F8R1_FB0 ((uint32_t)0x00000001) </span></div>
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|
<div class="line"><a name="l02667"></a><span class="lineno"> 2667</span> <span class="preprocessor">#define CAN_F8R1_FB1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02668"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13cd870005a4712c3a8b9675a962c642"> 2668</a></span> <span class="preprocessor">#define CAN_F8R1_FB2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02669"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49082d55960382ded8b2f7235dd3b33d"> 2669</a></span> <span class="preprocessor">#define CAN_F8R1_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l02670"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafdb99f376b40d3933ce6a28ad31f496a"> 2670</a></span> <span class="preprocessor">#define CAN_F8R1_FB4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l02671"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2cd97fc37fa6ffadbb7af4f9ddf1d014"> 2671</a></span> <span class="preprocessor">#define CAN_F8R1_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l02672"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5842614b55172086992fc085955168d7"> 2672</a></span> <span class="preprocessor">#define CAN_F8R1_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l02673"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga373c77cab88912e816a6e12195bd3205"> 2673</a></span> <span class="preprocessor">#define CAN_F8R1_FB7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l02674"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5937607627dd44c4fb79f9063534e2b1"> 2674</a></span> <span class="preprocessor">#define CAN_F8R1_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l02675"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b6765194a47f1a6d7dfbf78e0b4139c"> 2675</a></span> <span class="preprocessor">#define CAN_F8R1_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l02676"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa79159b413994d12b593cc4f1b23d1fa"> 2676</a></span> <span class="preprocessor">#define CAN_F8R1_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l02677"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b959e903cdac33f5da71aa5c7477a0d"> 2677</a></span> <span class="preprocessor">#define CAN_F8R1_FB11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l02678"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5de7f304ca7bfcb9e78c9c2d346d300"> 2678</a></span> <span class="preprocessor">#define CAN_F8R1_FB12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l02679"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d5a19fa7032ef2b68e2feebd0db15e6"> 2679</a></span> <span class="preprocessor">#define CAN_F8R1_FB13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l02680"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga943a685663474ed7aa509eaccbda2ffb"> 2680</a></span> <span class="preprocessor">#define CAN_F8R1_FB14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l02681"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga668cb8a75c4166b5287a09ba98c8ec70"> 2681</a></span> <span class="preprocessor">#define CAN_F8R1_FB15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l02682"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga84727d6a0fdcb2870529d7a371a0b660"> 2682</a></span> <span class="preprocessor">#define CAN_F8R1_FB16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l02683"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9eb9c851eb03c49bc02f686aee490a28"> 2683</a></span> <span class="preprocessor">#define CAN_F8R1_FB17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l02684"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ccc46770c70da8546bbbcf492bcdd95"> 2684</a></span> <span class="preprocessor">#define CAN_F8R1_FB18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l02685"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf24b0628e89b2c27cb9e13b0492876eb"> 2685</a></span> <span class="preprocessor">#define CAN_F8R1_FB19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l02686"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36b946c123c3c3f1cdbd1272db24c58b"> 2686</a></span> <span class="preprocessor">#define CAN_F8R1_FB20 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l02687"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab91129b8b7746111a31a968c1f1a8b19"> 2687</a></span> <span class="preprocessor">#define CAN_F8R1_FB21 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l02688"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19663b29868ae926896961451768d748"> 2688</a></span> <span class="preprocessor">#define CAN_F8R1_FB22 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l02689"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19d8c89621a78de5177481d217bb5033"> 2689</a></span> <span class="preprocessor">#define CAN_F8R1_FB23 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l02690"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab265fadfeb8674b869264ad25bedcac4"> 2690</a></span> <span class="preprocessor">#define CAN_F8R1_FB24 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l02691"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga102fdb92fecd6aa86e5dbd2fea2b2e79"> 2691</a></span> <span class="preprocessor">#define CAN_F8R1_FB25 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l02692"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b73f4ab4941e6d920e75f7197ed025b"> 2692</a></span> <span class="preprocessor">#define CAN_F8R1_FB26 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l02693"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d72a1b4728fa13d4a2a3f7478f8398b"> 2693</a></span> <span class="preprocessor">#define CAN_F8R1_FB27 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l02694"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5826d272442cf9b69336172a039bc439"> 2694</a></span> <span class="preprocessor">#define CAN_F8R1_FB28 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l02695"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacdb656881f89c0da122383403a816ce1"> 2695</a></span> <span class="preprocessor">#define CAN_F8R1_FB29 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l02696"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d8c536aab73553ff1913ba806be351c"> 2696</a></span> <span class="preprocessor">#define CAN_F8R1_FB30 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l02697"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8fb8328cdbf23c9982b769bd39a24113"> 2697</a></span> <span class="preprocessor">#define CAN_F8R1_FB31 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l02699"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b2fa38175302b2d91f2b45ae16c5db7"> 2699</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F9R1 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02700"></a><span class="lineno"> 2700</span> <span class="preprocessor">#define CAN_F9R1_FB0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l02701"></a><span class="lineno"> 2701</span> <span class="preprocessor">#define CAN_F9R1_FB1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02702"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga930a17d830cb9a95a79531dac2220785"> 2702</a></span> <span class="preprocessor">#define CAN_F9R1_FB2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02703"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8671eac978ebea75e6345adbcdf78026"> 2703</a></span> <span class="preprocessor">#define CAN_F9R1_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l02704"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee3585fb5ee4081dffeb2a2dda1ce72f"> 2704</a></span> <span class="preprocessor">#define CAN_F9R1_FB4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l02705"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga807e831fafa69e9df65618de855ea186"> 2705</a></span> <span class="preprocessor">#define CAN_F9R1_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l02706"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaddce646e28626a508b2f98c4f35148b3"> 2706</a></span> <span class="preprocessor">#define CAN_F9R1_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l02707"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ea72662e0243714ace5c0b48e7912f6"> 2707</a></span> <span class="preprocessor">#define CAN_F9R1_FB7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l02708"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b08ddbc0bed91c6a1933e6485ded5e2"> 2708</a></span> <span class="preprocessor">#define CAN_F9R1_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l02709"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae21fd9c8c790d4bc229c7ccb6d99dd36"> 2709</a></span> <span class="preprocessor">#define CAN_F9R1_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l02710"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf1a8f02576caccfddc12f2ead734762"> 2710</a></span> <span class="preprocessor">#define CAN_F9R1_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l02711"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80a2594aaa275fd88225927e7115085b"> 2711</a></span> <span class="preprocessor">#define CAN_F9R1_FB11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l02712"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3db445a3214057317d84269116c9a3de"> 2712</a></span> <span class="preprocessor">#define CAN_F9R1_FB12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l02713"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf09c1d038af593122315a878c15f608"> 2713</a></span> <span class="preprocessor">#define CAN_F9R1_FB13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l02714"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga12b2a29143ddf47eb1eddf76f9289cb9"> 2714</a></span> <span class="preprocessor">#define CAN_F9R1_FB14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l02715"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga691bc907b71c30dffdf246c95240ac9b"> 2715</a></span> <span class="preprocessor">#define CAN_F9R1_FB15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l02716"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf8669ceaa46f5aecada88accedfb4dbb"> 2716</a></span> <span class="preprocessor">#define CAN_F9R1_FB16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l02717"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga35e8769a1e21c4cf3714667e07201804"> 2717</a></span> <span class="preprocessor">#define CAN_F9R1_FB17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l02718"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7060a1863aa5b08ce8469001d46c630"> 2718</a></span> <span class="preprocessor">#define CAN_F9R1_FB18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l02719"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf015fb7231bd315f82948019dcfc725"> 2719</a></span> <span class="preprocessor">#define CAN_F9R1_FB19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l02720"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02c06b01abb3414394747a7cf8eac888"> 2720</a></span> <span class="preprocessor">#define CAN_F9R1_FB20 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l02721"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99a1a20417252e33a4817c0530745239"> 2721</a></span> <span class="preprocessor">#define CAN_F9R1_FB21 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l02722"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09c0f503e2ef85b3b6332ccbca7b0251"> 2722</a></span> <span class="preprocessor">#define CAN_F9R1_FB22 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l02723"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacab12d06dee3d6dad5fd7c56c23c70d1"> 2723</a></span> <span class="preprocessor">#define CAN_F9R1_FB23 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l02724"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c72a8d17db1de69086f19579b169c04"> 2724</a></span> <span class="preprocessor">#define CAN_F9R1_FB24 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l02725"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4bb3ba674ec6c82ed108f6c0bfb2f854"> 2725</a></span> <span class="preprocessor">#define CAN_F9R1_FB25 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l02726"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba13bd7fa1e4c2eaef3de31d933cbc10"> 2726</a></span> <span class="preprocessor">#define CAN_F9R1_FB26 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l02727"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa72247fe16d8f777c26726063fa43536"> 2727</a></span> <span class="preprocessor">#define CAN_F9R1_FB27 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l02728"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga32d7c1678449ff8f4e4b6f548ba85be4"> 2728</a></span> <span class="preprocessor">#define CAN_F9R1_FB28 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l02729"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga678d4a0a39b379db5c2e0285782c686f"> 2729</a></span> <span class="preprocessor">#define CAN_F9R1_FB29 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l02730"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6033aa5f4d140dc48ddb4a777583163c"> 2730</a></span> <span class="preprocessor">#define CAN_F9R1_FB30 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l02731"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9fda159c684d7361094da1883473b544"> 2731</a></span> <span class="preprocessor">#define CAN_F9R1_FB31 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l02733"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga127c155bc5c5236f04cfdcf96ff66cc5"> 2733</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F10R1 register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02734"></a><span class="lineno"> 2734</span> <span class="preprocessor">#define CAN_F10R1_FB0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l02735"></a><span class="lineno"> 2735</span> <span class="preprocessor">#define CAN_F10R1_FB1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02736"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d5b5b7bc147da430d9c8fbe03679ca3"> 2736</a></span> <span class="preprocessor">#define CAN_F10R1_FB2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02737"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ed7be0180fd7096f10cfde27261ecc9"> 2737</a></span> <span class="preprocessor">#define CAN_F10R1_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l02738"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad099442eb6b71912a81d1f6fccbaec0a"> 2738</a></span> <span class="preprocessor">#define CAN_F10R1_FB4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l02739"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4024c53b7b0cec550baed99ae92e3465"> 2739</a></span> <span class="preprocessor">#define CAN_F10R1_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l02740"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1859eaac9ae1220c752218e5ad526179"> 2740</a></span> <span class="preprocessor">#define CAN_F10R1_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l02741"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5683dc25f0aae9a802a5f57c88bec856"> 2741</a></span> <span class="preprocessor">#define CAN_F10R1_FB7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l02742"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae83dd9ce8a2c7917e278ce4755f8f43e"> 2742</a></span> <span class="preprocessor">#define CAN_F10R1_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l02743"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93ad070c9f5abca3c9b9095e3a13db9c"> 2743</a></span> <span class="preprocessor">#define CAN_F10R1_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l02744"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd32db3ffec3536cd842e17c34c210d9"> 2744</a></span> <span class="preprocessor">#define CAN_F10R1_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l02745"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga85673ce7a92ae8ca9a13ed2fb5574a76"> 2745</a></span> <span class="preprocessor">#define CAN_F10R1_FB11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l02746"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d525825fe4bfc1d4ffccc21ab89a3fa"> 2746</a></span> <span class="preprocessor">#define CAN_F10R1_FB12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l02747"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33336e283eeee9b77f1f289d77f2304e"> 2747</a></span> <span class="preprocessor">#define CAN_F10R1_FB13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l02748"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf74ee01e72b3de69d6e8fcc092f7461"> 2748</a></span> <span class="preprocessor">#define CAN_F10R1_FB14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l02749"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ee416ff22b47bb289bab34afbc74f19"> 2749</a></span> <span class="preprocessor">#define CAN_F10R1_FB15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l02750"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97a8d8586c64910b0f6c09fef44c4ea7"> 2750</a></span> <span class="preprocessor">#define CAN_F10R1_FB16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l02751"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9e8e43adc56ba1e593b97e062c79075"> 2751</a></span> <span class="preprocessor">#define CAN_F10R1_FB17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l02752"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa64a0b16c073b51cb5e90b94c638fd95"> 2752</a></span> <span class="preprocessor">#define CAN_F10R1_FB18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l02753"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65f5cc396cfcf3bad71a71326e64f7d9"> 2753</a></span> <span class="preprocessor">#define CAN_F10R1_FB19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l02754"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga424940f535aa9a1520e25df53673d01f"> 2754</a></span> <span class="preprocessor">#define CAN_F10R1_FB20 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l02755"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga166a4035770c58147d583c3dc571d10a"> 2755</a></span> <span class="preprocessor">#define CAN_F10R1_FB21 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l02756"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga302214ece439e8913b47949bd07d118a"> 2756</a></span> <span class="preprocessor">#define CAN_F10R1_FB22 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l02757"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9abe6ae1dcb2bd140e7e28d37fd8abb"> 2757</a></span> <span class="preprocessor">#define CAN_F10R1_FB23 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l02758"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99063956b41c4dcf6c78cc29305b1cd1"> 2758</a></span> <span class="preprocessor">#define CAN_F10R1_FB24 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l02759"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81ae64786c3a83bdd21cf72c560c7c1e"> 2759</a></span> <span class="preprocessor">#define CAN_F10R1_FB25 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l02760"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f9083faf8395701c892814694b45d2c"> 2760</a></span> <span class="preprocessor">#define CAN_F10R1_FB26 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l02761"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaeb6942affe306b407940fdf01534e4a"> 2761</a></span> <span class="preprocessor">#define CAN_F10R1_FB27 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l02762"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e4ee946a9614316f666852bc266c1f7"> 2762</a></span> <span class="preprocessor">#define CAN_F10R1_FB28 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l02763"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99153cddc8fc7e846fcc44383936541f"> 2763</a></span> <span class="preprocessor">#define CAN_F10R1_FB29 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l02764"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e2ba1740577246368e60d94fd3d7c69"> 2764</a></span> <span class="preprocessor">#define CAN_F10R1_FB30 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l02765"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca062686821fba26a0e5e5b0a6c5b855"> 2765</a></span> <span class="preprocessor">#define CAN_F10R1_FB31 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l02767"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0424bf38917058b166a8bfd861d22b40"> 2767</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F11R1 register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02768"></a><span class="lineno"> 2768</span> <span class="preprocessor">#define CAN_F11R1_FB0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l02769"></a><span class="lineno"> 2769</span> <span class="preprocessor">#define CAN_F11R1_FB1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02770"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad059cc9b2fe5634b9330b44c37dadf06"> 2770</a></span> <span class="preprocessor">#define CAN_F11R1_FB2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02771"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad74b116cda63fcd1a662c4de835616e7"> 2771</a></span> <span class="preprocessor">#define CAN_F11R1_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l02772"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e05bb0c2a5bdcebb974f7dd409724bc"> 2772</a></span> <span class="preprocessor">#define CAN_F11R1_FB4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l02773"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa17242aed4365034dc660ef9e8b9f1bf"> 2773</a></span> <span class="preprocessor">#define CAN_F11R1_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l02774"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga450dbed19882423d70ed7606aada2453"> 2774</a></span> <span class="preprocessor">#define CAN_F11R1_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l02775"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7ace73f2d3db1e2a1e55257d210fa04"> 2775</a></span> <span class="preprocessor">#define CAN_F11R1_FB7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l02776"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1459d395a3b08a948c3f5002e0914516"> 2776</a></span> <span class="preprocessor">#define CAN_F11R1_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l02777"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30fc2236c2a18b7cb6e493fad36d8efe"> 2777</a></span> <span class="preprocessor">#define CAN_F11R1_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l02778"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74ab4a6f6b5a751acda410e0c39b87af"> 2778</a></span> <span class="preprocessor">#define CAN_F11R1_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l02779"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e69f7001534264fd027371fa188ac52"> 2779</a></span> <span class="preprocessor">#define CAN_F11R1_FB11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l02780"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e858dd29f741910c8ed8c512cae81b1"> 2780</a></span> <span class="preprocessor">#define CAN_F11R1_FB12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l02781"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6ba167c6cd5bc080065430e24c3a866"> 2781</a></span> <span class="preprocessor">#define CAN_F11R1_FB13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l02782"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4629ab1e8632c82f3fb2648a574963b1"> 2782</a></span> <span class="preprocessor">#define CAN_F11R1_FB14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l02783"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga833c408a165cc4ac87a242c08d4ba9b9"> 2783</a></span> <span class="preprocessor">#define CAN_F11R1_FB15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l02784"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabfecd6bbe1a15cd341942d1840b476cc"> 2784</a></span> <span class="preprocessor">#define CAN_F11R1_FB16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l02785"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf50e1747d1d9369b7b22c5d591ae82b9"> 2785</a></span> <span class="preprocessor">#define CAN_F11R1_FB17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l02786"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga603d63333a621594a15696cb03f59eeb"> 2786</a></span> <span class="preprocessor">#define CAN_F11R1_FB18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l02787"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb361a00177e6aa2ee19aa5a2d1781aa"> 2787</a></span> <span class="preprocessor">#define CAN_F11R1_FB19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l02788"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf111110e0f5dbda31962f7732e3480c7"> 2788</a></span> <span class="preprocessor">#define CAN_F11R1_FB20 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l02789"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf2c4828b07b2b315d27b382818de285"> 2789</a></span> <span class="preprocessor">#define CAN_F11R1_FB21 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l02790"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5afa52941bb68a03ec9804b817d5a90e"> 2790</a></span> <span class="preprocessor">#define CAN_F11R1_FB22 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l02791"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac042471dbcb1a32ce161f38a144ac5aa"> 2791</a></span> <span class="preprocessor">#define CAN_F11R1_FB23 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l02792"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac46f233c9692cb2a2e246daf6547a38"> 2792</a></span> <span class="preprocessor">#define CAN_F11R1_FB24 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l02793"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8b379e3832482f2b18f01713d3338d5"> 2793</a></span> <span class="preprocessor">#define CAN_F11R1_FB25 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l02794"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60eabd8db9ec6b439d60dbc2374ce84d"> 2794</a></span> <span class="preprocessor">#define CAN_F11R1_FB26 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l02795"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga351a183cfab10d3daab415c85cc16203"> 2795</a></span> <span class="preprocessor">#define CAN_F11R1_FB27 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l02796"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb854a85c7a575a45cdade37efb4edee"> 2796</a></span> <span class="preprocessor">#define CAN_F11R1_FB28 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l02797"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga131776c359f81500d3d2a97535d7e718"> 2797</a></span> <span class="preprocessor">#define CAN_F11R1_FB29 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l02798"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga680d7e4c7ebc431a8c72c00e9f110563"> 2798</a></span> <span class="preprocessor">#define CAN_F11R1_FB30 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l02799"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c1fa00ee18804c169541d18995dc3c1"> 2799</a></span> <span class="preprocessor">#define CAN_F11R1_FB31 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l02801"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga96180b8c64aabd33f016fb97ba152f07"> 2801</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F12R1 register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02802"></a><span class="lineno"> 2802</span> <span class="preprocessor">#define CAN_F12R1_FB0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l02803"></a><span class="lineno"> 2803</span> <span class="preprocessor">#define CAN_F12R1_FB1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02804"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaccbe3637fb55f28496ca7f692a69f6ca"> 2804</a></span> <span class="preprocessor">#define CAN_F12R1_FB2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02805"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae625d21947ae82cc3509b06363ad0635"> 2805</a></span> <span class="preprocessor">#define CAN_F12R1_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l02806"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9de7cc313f2b6b16a564b13b1bc30157"> 2806</a></span> <span class="preprocessor">#define CAN_F12R1_FB4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l02807"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac039cc1ce2281cf10be62cbc44748f5f"> 2807</a></span> <span class="preprocessor">#define CAN_F12R1_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l02808"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc3a35b6f6b3a46c176398ec322fd6fb"> 2808</a></span> <span class="preprocessor">#define CAN_F12R1_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l02809"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d005c10fe75169336104c3155294000"> 2809</a></span> <span class="preprocessor">#define CAN_F12R1_FB7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l02810"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51256bfed734a95da3e7880e279432bf"> 2810</a></span> <span class="preprocessor">#define CAN_F12R1_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l02811"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c967f124b03968372d801e1393fa209"> 2811</a></span> <span class="preprocessor">#define CAN_F12R1_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l02812"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga592f9953deeb56888144c72060d04e24"> 2812</a></span> <span class="preprocessor">#define CAN_F12R1_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l02813"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d1613eac2aaeafda711cf3308ccd44c"> 2813</a></span> <span class="preprocessor">#define CAN_F12R1_FB11 ((uint32_t)0x00000800) </span></div>
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|
<div class="line"><a name="l02814"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b8594ab0c5d9124accd2d6ca85cf4bd"> 2814</a></span> <span class="preprocessor">#define CAN_F12R1_FB12 ((uint32_t)0x00001000) </span></div>
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|
<div class="line"><a name="l02815"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4025ed76892f23e5a63d0d8ac6a2be5f"> 2815</a></span> <span class="preprocessor">#define CAN_F12R1_FB13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l02816"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e2e318cc14828c118bd40d982922e14"> 2816</a></span> <span class="preprocessor">#define CAN_F12R1_FB14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l02817"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e0ff698b5e9f3f99a421166611b041d"> 2817</a></span> <span class="preprocessor">#define CAN_F12R1_FB15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l02818"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b0666538a7646ddc0fcd882a261f5d9"> 2818</a></span> <span class="preprocessor">#define CAN_F12R1_FB16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l02819"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga846d84b3d53e305b093198379f442528"> 2819</a></span> <span class="preprocessor">#define CAN_F12R1_FB17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l02820"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7940c0898c2ef1d9f829bf1b6b5fcf3"> 2820</a></span> <span class="preprocessor">#define CAN_F12R1_FB18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l02821"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6bdc7bd4dbad1f8e3bb622343bd7c522"> 2821</a></span> <span class="preprocessor">#define CAN_F12R1_FB19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l02822"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c870a6fbae41b4f1c6d66ab690789d6"> 2822</a></span> <span class="preprocessor">#define CAN_F12R1_FB20 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l02823"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09e179b38460e47b81616c46a5f356f8"> 2823</a></span> <span class="preprocessor">#define CAN_F12R1_FB21 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l02824"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad42e298d4d97c98cc5149bc552a598fa"> 2824</a></span> <span class="preprocessor">#define CAN_F12R1_FB22 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l02825"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga318e2a6ae62d5172dcdb45e011d5e0c4"> 2825</a></span> <span class="preprocessor">#define CAN_F12R1_FB23 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l02826"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90e95cb0020289335acd5d7f4b62a880"> 2826</a></span> <span class="preprocessor">#define CAN_F12R1_FB24 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l02827"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e2720e18fdff00c9fb75d5136e485dc"> 2827</a></span> <span class="preprocessor">#define CAN_F12R1_FB25 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l02828"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae4a87123ae5ff76992162152fbb4c92a"> 2828</a></span> <span class="preprocessor">#define CAN_F12R1_FB26 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l02829"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9582717e16455f97c7dff65f7beadd6e"> 2829</a></span> <span class="preprocessor">#define CAN_F12R1_FB27 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l02830"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf15e362beb5a3b733c08c8c2ab81efcb"> 2830</a></span> <span class="preprocessor">#define CAN_F12R1_FB28 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l02831"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d600a7a39c7069c216db511d3a5d866"> 2831</a></span> <span class="preprocessor">#define CAN_F12R1_FB29 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l02832"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9a6addc248c6db2118d1ce6e049d331"> 2832</a></span> <span class="preprocessor">#define CAN_F12R1_FB30 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l02833"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31d3a46845cd9ca6670472aae2aa2ebe"> 2833</a></span> <span class="preprocessor">#define CAN_F12R1_FB31 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l02835"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac441b11b1be9b3608b9a09c2b8069722"> 2835</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F13R1 register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02836"></a><span class="lineno"> 2836</span> <span class="preprocessor">#define CAN_F13R1_FB0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l02837"></a><span class="lineno"> 2837</span> <span class="preprocessor">#define CAN_F13R1_FB1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02838"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa20d063950ad122a1965527a17d93c37"> 2838</a></span> <span class="preprocessor">#define CAN_F13R1_FB2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02839"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf60decd61c8a8dc9e4342de8ad67ea76"> 2839</a></span> <span class="preprocessor">#define CAN_F13R1_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l02840"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7863b3af06385d0e9037c57a5d2091e2"> 2840</a></span> <span class="preprocessor">#define CAN_F13R1_FB4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l02841"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga043282b30813ce88dbdb320936ff6aca"> 2841</a></span> <span class="preprocessor">#define CAN_F13R1_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l02842"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3bbc9e9866f20d9d2f3cea1c6777c673"> 2842</a></span> <span class="preprocessor">#define CAN_F13R1_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l02843"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga885b36e017b013ab6deedd91d9ac2c66"> 2843</a></span> <span class="preprocessor">#define CAN_F13R1_FB7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l02844"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa389b53582e5cacf326fff4512626d68"> 2844</a></span> <span class="preprocessor">#define CAN_F13R1_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l02845"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad09b75feeda08b16962db7da6a32dc9b"> 2845</a></span> <span class="preprocessor">#define CAN_F13R1_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l02846"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaba75675c019979882ecd8c6ef82d7a4"> 2846</a></span> <span class="preprocessor">#define CAN_F13R1_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l02847"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac579473f666edec0e0fcce278b642a9d"> 2847</a></span> <span class="preprocessor">#define CAN_F13R1_FB11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l02848"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14640c225c434428ef1870f462eb9bbd"> 2848</a></span> <span class="preprocessor">#define CAN_F13R1_FB12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l02849"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d8c9f5879cc4e31fe2e63f82febbc69"> 2849</a></span> <span class="preprocessor">#define CAN_F13R1_FB13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l02850"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e0e3cfe033bb34f62312cfe47d1b84a"> 2850</a></span> <span class="preprocessor">#define CAN_F13R1_FB14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l02851"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93d91a28c1ffca3f72f10e0b44040791"> 2851</a></span> <span class="preprocessor">#define CAN_F13R1_FB15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l02852"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga355b438a5abccec89e13bdd00206b36f"> 2852</a></span> <span class="preprocessor">#define CAN_F13R1_FB16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l02853"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89b23d147d2c040eb2317633b3ef46da"> 2853</a></span> <span class="preprocessor">#define CAN_F13R1_FB17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l02854"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81d184cd46306fe24b46087a90e8f8f2"> 2854</a></span> <span class="preprocessor">#define CAN_F13R1_FB18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l02855"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga151a0e903046edc92bddcd0ef4a23449"> 2855</a></span> <span class="preprocessor">#define CAN_F13R1_FB19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l02856"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e95e6d0d060fb2cfdf31e1b5fdfe3de"> 2856</a></span> <span class="preprocessor">#define CAN_F13R1_FB20 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l02857"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e0fb1cf032c57f954dd2679a05f8115"> 2857</a></span> <span class="preprocessor">#define CAN_F13R1_FB21 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l02858"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb775bb1ded6a8f55f2a0849bec2eeac"> 2858</a></span> <span class="preprocessor">#define CAN_F13R1_FB22 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l02859"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8743dfb60255d98911ea66605efd3b2f"> 2859</a></span> <span class="preprocessor">#define CAN_F13R1_FB23 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l02860"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga54b067c38f3be3ad6041ea12fec15700"> 2860</a></span> <span class="preprocessor">#define CAN_F13R1_FB24 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l02861"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00fe1942d9a8767a76f139bd74eafea0"> 2861</a></span> <span class="preprocessor">#define CAN_F13R1_FB25 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l02862"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05db1c0a2e6e051d616b59f386dc7b1e"> 2862</a></span> <span class="preprocessor">#define CAN_F13R1_FB26 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l02863"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66dd0da9fd8ef27b30f1ad56a9982caf"> 2863</a></span> <span class="preprocessor">#define CAN_F13R1_FB27 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l02864"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3b8381bc6ce5ab107cc1a92e565387a"> 2864</a></span> <span class="preprocessor">#define CAN_F13R1_FB28 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l02865"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91c99de5ae099ecdee50ebd62e552df5"> 2865</a></span> <span class="preprocessor">#define CAN_F13R1_FB29 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l02866"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83713f9e2c3c90f001ab378d9ca1f488"> 2866</a></span> <span class="preprocessor">#define CAN_F13R1_FB30 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l02867"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga050fb1e9555d0d24f81682e194677684"> 2867</a></span> <span class="preprocessor">#define CAN_F13R1_FB31 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l02869"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a750d71e94876d2f6e73a0e8b7217b2"> 2869</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F0R2 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02870"></a><span class="lineno"> 2870</span> <span class="preprocessor">#define CAN_F0R2_FB0 ((uint32_t)0x00000001) </span></div>
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|
<div class="line"><a name="l02871"></a><span class="lineno"> 2871</span> <span class="preprocessor">#define CAN_F0R2_FB1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02872"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34282ddec559ecea4b613f2430334237"> 2872</a></span> <span class="preprocessor">#define CAN_F0R2_FB2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02873"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f23fc3814e0eb6af35c01e22c5dc6a7"> 2873</a></span> <span class="preprocessor">#define CAN_F0R2_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l02874"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga82ee32b6ec44d763b4364fa032d3439c"> 2874</a></span> <span class="preprocessor">#define CAN_F0R2_FB4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l02875"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7867b1d377088c63cdcc615932101997"> 2875</a></span> <span class="preprocessor">#define CAN_F0R2_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l02876"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37fc5c9115eb669f1ac493b1c7296250"> 2876</a></span> <span class="preprocessor">#define CAN_F0R2_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l02877"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae04b27aad09a3027f20a4eb48884c463"> 2877</a></span> <span class="preprocessor">#define CAN_F0R2_FB7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l02878"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae58d87c9513c11593041c3d43b955e8b"> 2878</a></span> <span class="preprocessor">#define CAN_F0R2_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l02879"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga03a6328d408b8015bb472c76f96a4dd8"> 2879</a></span> <span class="preprocessor">#define CAN_F0R2_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l02880"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga92fd1acf48665f966b670a0457456deb"> 2880</a></span> <span class="preprocessor">#define CAN_F0R2_FB10 ((uint32_t)0x00000400) </span></div>
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|
<div class="line"><a name="l02881"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa853cff5493c4e857b7bb1ad28678ed4"> 2881</a></span> <span class="preprocessor">#define CAN_F0R2_FB11 ((uint32_t)0x00000800) </span></div>
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|
<div class="line"><a name="l02882"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa43bba65dd777c71e07130fde3fa6216"> 2882</a></span> <span class="preprocessor">#define CAN_F0R2_FB12 ((uint32_t)0x00001000) </span></div>
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|
<div class="line"><a name="l02883"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9077b9c35c6721d2a0e090a42af0eaaf"> 2883</a></span> <span class="preprocessor">#define CAN_F0R2_FB13 ((uint32_t)0x00002000) </span></div>
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|
<div class="line"><a name="l02884"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23af8df7d4e843a6e196b1542421ef45"> 2884</a></span> <span class="preprocessor">#define CAN_F0R2_FB14 ((uint32_t)0x00004000) </span></div>
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|
<div class="line"><a name="l02885"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0fe7776af3adce7d203aeb16d55d86d4"> 2885</a></span> <span class="preprocessor">#define CAN_F0R2_FB15 ((uint32_t)0x00008000) </span></div>
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|
<div class="line"><a name="l02886"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81168efb90a776e44a96d1fe5e3b88c3"> 2886</a></span> <span class="preprocessor">#define CAN_F0R2_FB16 ((uint32_t)0x00010000) </span></div>
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|
<div class="line"><a name="l02887"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9708e7cde70a19e8e8fa33291e1b9d5"> 2887</a></span> <span class="preprocessor">#define CAN_F0R2_FB17 ((uint32_t)0x00020000) </span></div>
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|
<div class="line"><a name="l02888"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2f2154c3030cebcfc3f1e4aed74fbf1"> 2888</a></span> <span class="preprocessor">#define CAN_F0R2_FB18 ((uint32_t)0x00040000) </span></div>
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|
<div class="line"><a name="l02889"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae87c14b75911aa0a9d0349d02d342711"> 2889</a></span> <span class="preprocessor">#define CAN_F0R2_FB19 ((uint32_t)0x00080000) </span></div>
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|
<div class="line"><a name="l02890"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6fd7859cfc05300f68b175f520ddc31e"> 2890</a></span> <span class="preprocessor">#define CAN_F0R2_FB20 ((uint32_t)0x00100000) </span></div>
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|
<div class="line"><a name="l02891"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaea36db8fcada46357137efeea256457"> 2891</a></span> <span class="preprocessor">#define CAN_F0R2_FB21 ((uint32_t)0x00200000) </span></div>
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|
<div class="line"><a name="l02892"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57872dcfea1f8a56170640842edf9c1a"> 2892</a></span> <span class="preprocessor">#define CAN_F0R2_FB22 ((uint32_t)0x00400000) </span></div>
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|
<div class="line"><a name="l02893"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc01e7f26d0e85da93ca78d0d71a4fed"> 2893</a></span> <span class="preprocessor">#define CAN_F0R2_FB23 ((uint32_t)0x00800000) </span></div>
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|
<div class="line"><a name="l02894"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07d8c3c8c3eb3c97b5979388c548e2fc"> 2894</a></span> <span class="preprocessor">#define CAN_F0R2_FB24 ((uint32_t)0x01000000) </span></div>
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|
<div class="line"><a name="l02895"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade31bd75624afeaef9b5ab45a5057db9"> 2895</a></span> <span class="preprocessor">#define CAN_F0R2_FB25 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l02896"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa78ff8fcfe0f14655aaf94ecc92d7532"> 2896</a></span> <span class="preprocessor">#define CAN_F0R2_FB26 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l02897"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad577ebd9a8cedd1b8b13d5a41d2fbab"> 2897</a></span> <span class="preprocessor">#define CAN_F0R2_FB27 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l02898"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab814105bcd2a2c636c26197b21ead2b0"> 2898</a></span> <span class="preprocessor">#define CAN_F0R2_FB28 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l02899"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea82daeaa71ecddb187613df9517e51c"> 2899</a></span> <span class="preprocessor">#define CAN_F0R2_FB29 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l02900"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef5036edf5bd310e5e06f3ea5cb818a2"> 2900</a></span> <span class="preprocessor">#define CAN_F0R2_FB30 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l02901"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0c2db96ddbcfa1b838c283e20ca554b"> 2901</a></span> <span class="preprocessor">#define CAN_F0R2_FB31 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l02903"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ace83e798931f35c123507e1ef59fbb"> 2903</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F1R2 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02904"></a><span class="lineno"> 2904</span> <span class="preprocessor">#define CAN_F1R2_FB0 ((uint32_t)0x00000001) </span></div>
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|
<div class="line"><a name="l02905"></a><span class="lineno"> 2905</span> <span class="preprocessor">#define CAN_F1R2_FB1 ((uint32_t)0x00000002) </span></div>
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|
<div class="line"><a name="l02906"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ea3c5d8ab8962d9cd0e2b067167d3d4"> 2906</a></span> <span class="preprocessor">#define CAN_F1R2_FB2 ((uint32_t)0x00000004) </span></div>
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|
<div class="line"><a name="l02907"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacfa5449488e7330d8f11f75fcf3e75cd"> 2907</a></span> <span class="preprocessor">#define CAN_F1R2_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l02908"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe49a3e224459f1bd9b3279ebfa8803b"> 2908</a></span> <span class="preprocessor">#define CAN_F1R2_FB4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l02909"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga77cf2217ec29e2043bada827249dedd5"> 2909</a></span> <span class="preprocessor">#define CAN_F1R2_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l02910"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf35643f0148ed0f93e3ba52e95a4cf6b"> 2910</a></span> <span class="preprocessor">#define CAN_F1R2_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l02911"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae08798adabd9cc0fb2b07eaff6444878"> 2911</a></span> <span class="preprocessor">#define CAN_F1R2_FB7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l02912"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06659c9a418d7f4a8729d87bc397be23"> 2912</a></span> <span class="preprocessor">#define CAN_F1R2_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l02913"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36bb9ca8dadd6714052f8d31cb01cb7b"> 2913</a></span> <span class="preprocessor">#define CAN_F1R2_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l02914"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d400044261146be3deb722d9cf3d5c1"> 2914</a></span> <span class="preprocessor">#define CAN_F1R2_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l02915"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3e5769ea8faaed16c6cb2ce979d28a9"> 2915</a></span> <span class="preprocessor">#define CAN_F1R2_FB11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l02916"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga915236a6b5081c2c30bd4d49144bc463"> 2916</a></span> <span class="preprocessor">#define CAN_F1R2_FB12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l02917"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf1aa2e62d4eede199196f81795d309c"> 2917</a></span> <span class="preprocessor">#define CAN_F1R2_FB13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l02918"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7db0ae3dcaab35e4c496c8a800b5c994"> 2918</a></span> <span class="preprocessor">#define CAN_F1R2_FB14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l02919"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga02cdb71c56a5d9994ecd2dee668c7184"> 2919</a></span> <span class="preprocessor">#define CAN_F1R2_FB15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l02920"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac66691ca840db6c861460d311a942a87"> 2920</a></span> <span class="preprocessor">#define CAN_F1R2_FB16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l02921"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabcdd57022e26859db1f81f2df08c8725"> 2921</a></span> <span class="preprocessor">#define CAN_F1R2_FB17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l02922"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga211795b36769a0b87044f0d82a7a72b1"> 2922</a></span> <span class="preprocessor">#define CAN_F1R2_FB18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l02923"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc8c427731f33c76fad0873bb29a4b4c"> 2923</a></span> <span class="preprocessor">#define CAN_F1R2_FB19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l02924"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga10a3e6be9968b8007562e7afe6b3b342"> 2924</a></span> <span class="preprocessor">#define CAN_F1R2_FB20 ((uint32_t)0x00100000) </span></div>
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|
<div class="line"><a name="l02925"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4aac6ab4bd4cdeecbe621adf1d11b95a"> 2925</a></span> <span class="preprocessor">#define CAN_F1R2_FB21 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l02926"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30140ced3da0d0a526c4f4f5881987c1"> 2926</a></span> <span class="preprocessor">#define CAN_F1R2_FB22 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l02927"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49f36aec2e851ed18c5a382a0708bbcb"> 2927</a></span> <span class="preprocessor">#define CAN_F1R2_FB23 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l02928"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99ccab06a8a97616a2fc3e026f36351d"> 2928</a></span> <span class="preprocessor">#define CAN_F1R2_FB24 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l02929"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa408889ff6478d6558d4c53c9114bde"> 2929</a></span> <span class="preprocessor">#define CAN_F1R2_FB25 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l02930"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga032dd8dc11aa9013cc0e824e31932951"> 2930</a></span> <span class="preprocessor">#define CAN_F1R2_FB26 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l02931"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76f29020524ec6403a40de4e260a2ea8"> 2931</a></span> <span class="preprocessor">#define CAN_F1R2_FB27 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l02932"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0bb51cd27fea671be51a59ce7a83008e"> 2932</a></span> <span class="preprocessor">#define CAN_F1R2_FB28 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l02933"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga085c38b511aa4895b6c939a06070c916"> 2933</a></span> <span class="preprocessor">#define CAN_F1R2_FB29 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l02934"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe299378c771da8d7d8e72a6f6e41f7f"> 2934</a></span> <span class="preprocessor">#define CAN_F1R2_FB30 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l02935"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaabc8bef79b09bcfcb0df6ba467ed906b"> 2935</a></span> <span class="preprocessor">#define CAN_F1R2_FB31 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l02937"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga21cbfc217d67062d265753964c871065"> 2937</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F2R2 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l02938"></a><span class="lineno"> 2938</span> <span class="preprocessor">#define CAN_F2R2_FB0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l02939"></a><span class="lineno"> 2939</span> <span class="preprocessor">#define CAN_F2R2_FB1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02940"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36964e4bf6aa10467b3d95781da56814"> 2940</a></span> <span class="preprocessor">#define CAN_F2R2_FB2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02941"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d0541eb1a4f8ae0afe429ac0757de6a"> 2941</a></span> <span class="preprocessor">#define CAN_F2R2_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l02942"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14fd5aff8767df509b396190ddf7fa28"> 2942</a></span> <span class="preprocessor">#define CAN_F2R2_FB4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l02943"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7283e2a71983078144fa9a8e5ae563a9"> 2943</a></span> <span class="preprocessor">#define CAN_F2R2_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l02944"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeba1324d32b084c477a0ece7b904a4cd"> 2944</a></span> <span class="preprocessor">#define CAN_F2R2_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l02945"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a367cf9f2f7e604e9f5e30b5ed30779"> 2945</a></span> <span class="preprocessor">#define CAN_F2R2_FB7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l02946"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b92ac9785e2f7c890130e9b7d792c79"> 2946</a></span> <span class="preprocessor">#define CAN_F2R2_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l02947"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac969a33d20353d5cd7fb317f5fa71138"> 2947</a></span> <span class="preprocessor">#define CAN_F2R2_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l02948"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafeaac84fa5eec0173c531e9940327f86"> 2948</a></span> <span class="preprocessor">#define CAN_F2R2_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l02949"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga532413ea309fa031e65397a5b31ac92c"> 2949</a></span> <span class="preprocessor">#define CAN_F2R2_FB11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l02950"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga360e02860472400a9000ef2fc8ba7bb1"> 2950</a></span> <span class="preprocessor">#define CAN_F2R2_FB12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l02951"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c917a5b5e1a010229caaa5b3a41d7a6"> 2951</a></span> <span class="preprocessor">#define CAN_F2R2_FB13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l02952"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0956873246e63b41c0a640bc8d117319"> 2952</a></span> <span class="preprocessor">#define CAN_F2R2_FB14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l02953"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53202218de27d073d577c27427fe0cbe"> 2953</a></span> <span class="preprocessor">#define CAN_F2R2_FB15 ((uint32_t)0x00008000) </span></div>
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|
<div class="line"><a name="l02954"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga960a1ffd4b153168494d91df69e30742"> 2954</a></span> <span class="preprocessor">#define CAN_F2R2_FB16 ((uint32_t)0x00010000) </span></div>
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|
<div class="line"><a name="l02955"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc81e9ab9ab926d1ca30c5b6060a126b"> 2955</a></span> <span class="preprocessor">#define CAN_F2R2_FB17 ((uint32_t)0x00020000) </span></div>
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|
<div class="line"><a name="l02956"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa5f9a5279398454a3a2493b3e1783f52"> 2956</a></span> <span class="preprocessor">#define CAN_F2R2_FB18 ((uint32_t)0x00040000) </span></div>
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|
<div class="line"><a name="l02957"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0275ec7527a223a33289118f9e0a2edd"> 2957</a></span> <span class="preprocessor">#define CAN_F2R2_FB19 ((uint32_t)0x00080000) </span></div>
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|
<div class="line"><a name="l02958"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34028a240868ca7dd365ce98e31e84ca"> 2958</a></span> <span class="preprocessor">#define CAN_F2R2_FB20 ((uint32_t)0x00100000) </span></div>
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|
<div class="line"><a name="l02959"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga807cfa122b6c74d85fdab233dd9ed502"> 2959</a></span> <span class="preprocessor">#define CAN_F2R2_FB21 ((uint32_t)0x00200000) </span></div>
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|
<div class="line"><a name="l02960"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1187f1ab7514c90af34b44eff80858fa"> 2960</a></span> <span class="preprocessor">#define CAN_F2R2_FB22 ((uint32_t)0x00400000) </span></div>
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|
<div class="line"><a name="l02961"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacecb18e779a44989b724901f6c2af84f"> 2961</a></span> <span class="preprocessor">#define CAN_F2R2_FB23 ((uint32_t)0x00800000) </span></div>
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|
<div class="line"><a name="l02962"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f2a6017895d8d139dcbc3d0e6e69e69"> 2962</a></span> <span class="preprocessor">#define CAN_F2R2_FB24 ((uint32_t)0x01000000) </span></div>
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|
<div class="line"><a name="l02963"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaceff2f283cbd4935ec5d45ceaa18efe0"> 2963</a></span> <span class="preprocessor">#define CAN_F2R2_FB25 ((uint32_t)0x02000000) </span></div>
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|
<div class="line"><a name="l02964"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3086667a209f91ed6d6b496b83111044"> 2964</a></span> <span class="preprocessor">#define CAN_F2R2_FB26 ((uint32_t)0x04000000) </span></div>
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|
<div class="line"><a name="l02965"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c8c7b240bb0dd2a3ec8b6c4c25af7ba"> 2965</a></span> <span class="preprocessor">#define CAN_F2R2_FB27 ((uint32_t)0x08000000) </span></div>
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|
<div class="line"><a name="l02966"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51498379a1e3b81a83bf8d164c4f7e5e"> 2966</a></span> <span class="preprocessor">#define CAN_F2R2_FB28 ((uint32_t)0x10000000) </span></div>
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|
<div class="line"><a name="l02967"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1f78e7c530a3ef26d44b9353fa9ee36"> 2967</a></span> <span class="preprocessor">#define CAN_F2R2_FB29 ((uint32_t)0x20000000) </span></div>
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|
<div class="line"><a name="l02968"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e30d0e50fca346ca8cb427a6c85f9dc"> 2968</a></span> <span class="preprocessor">#define CAN_F2R2_FB30 ((uint32_t)0x40000000) </span></div>
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|
<div class="line"><a name="l02969"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga77586d252cad5a0a866b1d9deb6835ba"> 2969</a></span> <span class="preprocessor">#define CAN_F2R2_FB31 ((uint32_t)0x80000000) </span></div>
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|
<div class="line"><a name="l02971"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac34bca92730b6f7cd0de8af1a2d0014f"> 2971</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F3R2 register *******************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l02972"></a><span class="lineno"> 2972</span> <span class="preprocessor">#define CAN_F3R2_FB0 ((uint32_t)0x00000001) </span></div>
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|
<div class="line"><a name="l02973"></a><span class="lineno"> 2973</span> <span class="preprocessor">#define CAN_F3R2_FB1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l02974"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga46730b7e64aa771087b6c9d5deb273e1"> 2974</a></span> <span class="preprocessor">#define CAN_F3R2_FB2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l02975"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb12b61624912b90382a4ad95281e7f4"> 2975</a></span> <span class="preprocessor">#define CAN_F3R2_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l02976"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6621759dddc575c01f5bbaab43d1f04e"> 2976</a></span> <span class="preprocessor">#define CAN_F3R2_FB4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l02977"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga29d052fc2597171767d8cf5d72388ad5"> 2977</a></span> <span class="preprocessor">#define CAN_F3R2_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l02978"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga731e9949d77054ba176340652083ad46"> 2978</a></span> <span class="preprocessor">#define CAN_F3R2_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l02979"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93c52f51fe9eefe7f0cf094522a592b6"> 2979</a></span> <span class="preprocessor">#define CAN_F3R2_FB7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l02980"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad675c2d3f72d8bc42e0f3088ddbcc3c9"> 2980</a></span> <span class="preprocessor">#define CAN_F3R2_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l02981"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1734cf6a5a72d403cd043eb704246c85"> 2981</a></span> <span class="preprocessor">#define CAN_F3R2_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l02982"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97d82554ce38567e44cd87ed99175928"> 2982</a></span> <span class="preprocessor">#define CAN_F3R2_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l02983"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga505f85fadba4397e6d9a241bbc9229bc"> 2983</a></span> <span class="preprocessor">#define CAN_F3R2_FB11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l02984"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb635843951fb42ffeb776d8564d7e14"> 2984</a></span> <span class="preprocessor">#define CAN_F3R2_FB12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l02985"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5db557239646008004286de15847ced4"> 2985</a></span> <span class="preprocessor">#define CAN_F3R2_FB13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l02986"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga118b2044dae4c93c66aaa4f28c5b695c"> 2986</a></span> <span class="preprocessor">#define CAN_F3R2_FB14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l02987"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8c041a2b8162a8055a1894d0a0b3d682"> 2987</a></span> <span class="preprocessor">#define CAN_F3R2_FB15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l02988"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb6e0947fcb7594d12dcbca38d60c9f8"> 2988</a></span> <span class="preprocessor">#define CAN_F3R2_FB16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l02989"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1dae8addc6fa59e824e1a67fc8c91ddd"> 2989</a></span> <span class="preprocessor">#define CAN_F3R2_FB17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l02990"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga992795c5e0b3b8a8c5d4d6e9eceb7366"> 2990</a></span> <span class="preprocessor">#define CAN_F3R2_FB18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l02991"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1637eff70416eb85d5d2a54e1f5d412e"> 2991</a></span> <span class="preprocessor">#define CAN_F3R2_FB19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l02992"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7bbfdfa29b84ea60e67d41f775c6ffc6"> 2992</a></span> <span class="preprocessor">#define CAN_F3R2_FB20 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l02993"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga827747e8cc66e4dcd22498c59e45c776"> 2993</a></span> <span class="preprocessor">#define CAN_F3R2_FB21 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l02994"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe0bb6919615ec6311e8c39f62bca618"> 2994</a></span> <span class="preprocessor">#define CAN_F3R2_FB22 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l02995"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c3e4716d3e52ec99451a942dceb59de"> 2995</a></span> <span class="preprocessor">#define CAN_F3R2_FB23 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l02996"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaffefb44a948d36dcd94248f63aa68d2b"> 2996</a></span> <span class="preprocessor">#define CAN_F3R2_FB24 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l02997"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79ce25d44a38f520b4a93384d6f5ac40"> 2997</a></span> <span class="preprocessor">#define CAN_F3R2_FB25 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l02998"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3fe1ced752dc811f9418181275c8c3fe"> 2998</a></span> <span class="preprocessor">#define CAN_F3R2_FB26 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l02999"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9fb2f469246193f6fc9e4ade42192d28"> 2999</a></span> <span class="preprocessor">#define CAN_F3R2_FB27 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l03000"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae85be7f7d7a9ddb8a60edb30d2a5727"> 3000</a></span> <span class="preprocessor">#define CAN_F3R2_FB28 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l03001"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga850c21b26100c68b9cb57608c0249543"> 3001</a></span> <span class="preprocessor">#define CAN_F3R2_FB29 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l03002"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga82ec6ad2ad1b6115496adcb3e66fae25"> 3002</a></span> <span class="preprocessor">#define CAN_F3R2_FB30 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l03003"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4fa34cc998edfdd1b3db93395ee6500"> 3003</a></span> <span class="preprocessor">#define CAN_F3R2_FB31 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l03005"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga58a154f4d0cb787f23429b3f7cf70fd6"> 3005</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F4R2 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l03006"></a><span class="lineno"> 3006</span> <span class="preprocessor">#define CAN_F4R2_FB0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l03007"></a><span class="lineno"> 3007</span> <span class="preprocessor">#define CAN_F4R2_FB1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l03008"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97250d3eed2504846f39c50dce71c9d0"> 3008</a></span> <span class="preprocessor">#define CAN_F4R2_FB2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l03009"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga145e11678ee6062df5164894ad8f80b1"> 3009</a></span> <span class="preprocessor">#define CAN_F4R2_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l03010"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d19193baf5412ec2e38822d062196b8"> 3010</a></span> <span class="preprocessor">#define CAN_F4R2_FB4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l03011"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga94b8b1428b640932aced6446f8b41f83"> 3011</a></span> <span class="preprocessor">#define CAN_F4R2_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l03012"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93164ec00412eb5eed168e8a30557f25"> 3012</a></span> <span class="preprocessor">#define CAN_F4R2_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l03013"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04e44c5a14e44c20f3b81044a915db13"> 3013</a></span> <span class="preprocessor">#define CAN_F4R2_FB7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l03014"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37e57dec99c33f462a2dbb6273df2f57"> 3014</a></span> <span class="preprocessor">#define CAN_F4R2_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l03015"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6c7d3ec0375e356192583142f7fccca"> 3015</a></span> <span class="preprocessor">#define CAN_F4R2_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l03016"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad33f7d788aea161826a86bc2c5567450"> 3016</a></span> <span class="preprocessor">#define CAN_F4R2_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l03017"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab998448b0bd20ff6384c26ad9e6baaf"> 3017</a></span> <span class="preprocessor">#define CAN_F4R2_FB11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l03018"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8794112fcbb0dca0c7d0316ac8725e8"> 3018</a></span> <span class="preprocessor">#define CAN_F4R2_FB12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l03019"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d22e782a9ca087f99ab9f53b2626aed"> 3019</a></span> <span class="preprocessor">#define CAN_F4R2_FB13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l03020"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa8d5c2635a62bdfa6e3a5a12b127fc8"> 3020</a></span> <span class="preprocessor">#define CAN_F4R2_FB14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l03021"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad491689799985f0c8f17b270cd8873c4"> 3021</a></span> <span class="preprocessor">#define CAN_F4R2_FB15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l03022"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab1b80d40d87204de4687735de852f47f"> 3022</a></span> <span class="preprocessor">#define CAN_F4R2_FB16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l03023"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0994b341ba8a73b950f01d83d012780d"> 3023</a></span> <span class="preprocessor">#define CAN_F4R2_FB17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l03024"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ae8b77d791ba7403618989a77e62922"> 3024</a></span> <span class="preprocessor">#define CAN_F4R2_FB18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l03025"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc116988117a7e7fabc722855351d257"> 3025</a></span> <span class="preprocessor">#define CAN_F4R2_FB19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l03026"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07b1fc6ee0dc4cc892d69ed496b59007"> 3026</a></span> <span class="preprocessor">#define CAN_F4R2_FB20 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l03027"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa58785812f0d3e73a657426b81f0b78b"> 3027</a></span> <span class="preprocessor">#define CAN_F4R2_FB21 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l03028"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga363da353073d7ee6421cf171688ef52b"> 3028</a></span> <span class="preprocessor">#define CAN_F4R2_FB22 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l03029"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f22695359aa9a1b07763aef44a9a1c4"> 3029</a></span> <span class="preprocessor">#define CAN_F4R2_FB23 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l03030"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac0f8c1ef382225198407474f2b7fa073"> 3030</a></span> <span class="preprocessor">#define CAN_F4R2_FB24 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l03031"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9476c54044db3182ee789e9df1d1aa19"> 3031</a></span> <span class="preprocessor">#define CAN_F4R2_FB25 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l03032"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga73158a3669d2ef96db84e4f196d040bf"> 3032</a></span> <span class="preprocessor">#define CAN_F4R2_FB26 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l03033"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17d36fcf8e08c76597a7b2c05e831f98"> 3033</a></span> <span class="preprocessor">#define CAN_F4R2_FB27 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l03034"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa683635426f418ead45032c25e0179ee"> 3034</a></span> <span class="preprocessor">#define CAN_F4R2_FB28 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l03035"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23c77145ea84805a785b49c0a7f31774"> 3035</a></span> <span class="preprocessor">#define CAN_F4R2_FB29 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l03036"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga18492e954ec07174a1b140104062f941"> 3036</a></span> <span class="preprocessor">#define CAN_F4R2_FB30 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l03037"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf94626a8450c20e241ad6298660ec23"> 3037</a></span> <span class="preprocessor">#define CAN_F4R2_FB31 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l03039"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70293ff8a71e353d84a3da134eb427d9"> 3039</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F5R2 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l03040"></a><span class="lineno"> 3040</span> <span class="preprocessor">#define CAN_F5R2_FB0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l03041"></a><span class="lineno"> 3041</span> <span class="preprocessor">#define CAN_F5R2_FB1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l03042"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17b264aaa84a3c6ab5a35014eb5dfb09"> 3042</a></span> <span class="preprocessor">#define CAN_F5R2_FB2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l03043"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa871f5bc692996efc8c1bad1d08b43c5"> 3043</a></span> <span class="preprocessor">#define CAN_F5R2_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l03044"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf44a72156023a5889a1c22d77e188e2e"> 3044</a></span> <span class="preprocessor">#define CAN_F5R2_FB4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l03045"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3d8828885a79299bc65c2011f71240e2"> 3045</a></span> <span class="preprocessor">#define CAN_F5R2_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l03046"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadfa978108927c827e3021499a20d0372"> 3046</a></span> <span class="preprocessor">#define CAN_F5R2_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l03047"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3b3c48011935170a9bd120b724030fe"> 3047</a></span> <span class="preprocessor">#define CAN_F5R2_FB7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l03048"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56cf7f6d0bf48847f3d8f72777774e58"> 3048</a></span> <span class="preprocessor">#define CAN_F5R2_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l03049"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2cb8a5551d90c8d79b09b4d82f3f59c2"> 3049</a></span> <span class="preprocessor">#define CAN_F5R2_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l03050"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga423b7b77bfd5dd6791f1b1dd16e9807a"> 3050</a></span> <span class="preprocessor">#define CAN_F5R2_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l03051"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c50420a128a70341e63ad23b0bedba5"> 3051</a></span> <span class="preprocessor">#define CAN_F5R2_FB11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l03052"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga392844657c800d2e16e7916ed5fb9891"> 3052</a></span> <span class="preprocessor">#define CAN_F5R2_FB12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l03053"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb35a3bbc447c46929643115490e250d"> 3053</a></span> <span class="preprocessor">#define CAN_F5R2_FB13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l03054"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga974bae58f9819eee0377d709c985bcbe"> 3054</a></span> <span class="preprocessor">#define CAN_F5R2_FB14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l03055"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2823bb25e138cc52d11b154456947ab7"> 3055</a></span> <span class="preprocessor">#define CAN_F5R2_FB15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l03056"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98cf223bdcc1a106f7573b57f836f9ed"> 3056</a></span> <span class="preprocessor">#define CAN_F5R2_FB16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l03057"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26bfd14720495dd180f1524f2fdb3743"> 3057</a></span> <span class="preprocessor">#define CAN_F5R2_FB17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l03058"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41b457c721dc855d05b2f353c22a83a7"> 3058</a></span> <span class="preprocessor">#define CAN_F5R2_FB18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l03059"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1bc89534aaf3f810a2151b04b0086717"> 3059</a></span> <span class="preprocessor">#define CAN_F5R2_FB19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l03060"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga070940536728fad3c0e5336926131b4b"> 3060</a></span> <span class="preprocessor">#define CAN_F5R2_FB20 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l03061"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaddf2e4aa8107150a86d37ce03a0e1c0e"> 3061</a></span> <span class="preprocessor">#define CAN_F5R2_FB21 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l03062"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1788704faad47f1d45017df41a35f053"> 3062</a></span> <span class="preprocessor">#define CAN_F5R2_FB22 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l03063"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11c4aeffb6646643c412e19e6f5cc015"> 3063</a></span> <span class="preprocessor">#define CAN_F5R2_FB23 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l03064"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef348c2d37f96f5e5324368f90c80d42"> 3064</a></span> <span class="preprocessor">#define CAN_F5R2_FB24 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l03065"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga398d842cfcb2d441d999e1407fc54f83"> 3065</a></span> <span class="preprocessor">#define CAN_F5R2_FB25 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l03066"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6575f8d4d154e2e8342b3f88352a9d52"> 3066</a></span> <span class="preprocessor">#define CAN_F5R2_FB26 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l03067"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9e6ad77b1d8ac7303e920658aceb354"> 3067</a></span> <span class="preprocessor">#define CAN_F5R2_FB27 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l03068"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga911ade78e30d1a037d35dda5eb7cbd4b"> 3068</a></span> <span class="preprocessor">#define CAN_F5R2_FB28 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l03069"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49542b9334bc4917e25d6808c78787d1"> 3069</a></span> <span class="preprocessor">#define CAN_F5R2_FB29 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l03070"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga255da64f4a66ff888f6633d6e51658c6"> 3070</a></span> <span class="preprocessor">#define CAN_F5R2_FB30 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l03071"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8335d23f9fd156f40dc7fd63ba6783cb"> 3071</a></span> <span class="preprocessor">#define CAN_F5R2_FB31 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l03073"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f7122b0ad8cb4fc1797d0dbecbb4a05"> 3073</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F6R2 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l03074"></a><span class="lineno"> 3074</span> <span class="preprocessor">#define CAN_F6R2_FB0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l03075"></a><span class="lineno"> 3075</span> <span class="preprocessor">#define CAN_F6R2_FB1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l03076"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71ad6452660daed3d6c436533a25efc2"> 3076</a></span> <span class="preprocessor">#define CAN_F6R2_FB2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l03077"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9e24abd8d2f0775661415b6565f4f6d"> 3077</a></span> <span class="preprocessor">#define CAN_F6R2_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l03078"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6dc3f6ce4dde435743aadbe17cc78b9"> 3078</a></span> <span class="preprocessor">#define CAN_F6R2_FB4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l03079"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1f5163490dffe1f4d7c635458359c2f"> 3079</a></span> <span class="preprocessor">#define CAN_F6R2_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l03080"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89e9191d214d05f4d90fbcd38daa73e1"> 3080</a></span> <span class="preprocessor">#define CAN_F6R2_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l03081"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97d29588281c546d98e09760cc5ef593"> 3081</a></span> <span class="preprocessor">#define CAN_F6R2_FB7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l03082"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53f5717aca9932255049b133661765bf"> 3082</a></span> <span class="preprocessor">#define CAN_F6R2_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l03083"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ec93958e936379d891bc3450dba3d1d"> 3083</a></span> <span class="preprocessor">#define CAN_F6R2_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l03084"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f97c7eb9d6e69d589db38d745ae321c"> 3084</a></span> <span class="preprocessor">#define CAN_F6R2_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l03085"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga372ebb5d42d147d41688f7c0fcf467d2"> 3085</a></span> <span class="preprocessor">#define CAN_F6R2_FB11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l03086"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47baa2c9c05c7c422a49994b8f80016f"> 3086</a></span> <span class="preprocessor">#define CAN_F6R2_FB12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l03087"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55d7665b118e98586c2a9b1900ce7292"> 3087</a></span> <span class="preprocessor">#define CAN_F6R2_FB13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l03088"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5095a203d07244e75dd6deca125b4468"> 3088</a></span> <span class="preprocessor">#define CAN_F6R2_FB14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l03089"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga533dbb10e8fce9aa6ec23573fb49c339"> 3089</a></span> <span class="preprocessor">#define CAN_F6R2_FB15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l03090"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b95be922291e534609302c0c833f1f7"> 3090</a></span> <span class="preprocessor">#define CAN_F6R2_FB16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l03091"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17301d50c7b6ad30ffc05ee2c63f6171"> 3091</a></span> <span class="preprocessor">#define CAN_F6R2_FB17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l03092"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf23dfb03247544122ed01472b8a31b4d"> 3092</a></span> <span class="preprocessor">#define CAN_F6R2_FB18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l03093"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf8d35fbfa677fc446da68f4043b633e"> 3093</a></span> <span class="preprocessor">#define CAN_F6R2_FB19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l03094"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c81a1972ec8d87421c6113bb9747c3e"> 3094</a></span> <span class="preprocessor">#define CAN_F6R2_FB20 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l03095"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11ea1bd4bae8b27a5fd73d210eb83d39"> 3095</a></span> <span class="preprocessor">#define CAN_F6R2_FB21 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l03096"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c48dcd1ac5e23827813ed695bdff0d1"> 3096</a></span> <span class="preprocessor">#define CAN_F6R2_FB22 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l03097"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd115d29d9f0a8fddc13a32c013af26b"> 3097</a></span> <span class="preprocessor">#define CAN_F6R2_FB23 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l03098"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3f116b2e31dd40bcdd6617fee83907e"> 3098</a></span> <span class="preprocessor">#define CAN_F6R2_FB24 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l03099"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga090da76d2d9379dbfc54f7c3fcf69fe4"> 3099</a></span> <span class="preprocessor">#define CAN_F6R2_FB25 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l03100"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9c8a59a8065400f4a75be49a78e2a9e"> 3100</a></span> <span class="preprocessor">#define CAN_F6R2_FB26 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l03101"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3854a1a11c72e64d3c4722494f463421"> 3101</a></span> <span class="preprocessor">#define CAN_F6R2_FB27 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l03102"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b5ceb9d7ae0c6e34490b8d8659919c9"> 3102</a></span> <span class="preprocessor">#define CAN_F6R2_FB28 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l03103"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac01a4accedd624ceccf8f8976a043177"> 3103</a></span> <span class="preprocessor">#define CAN_F6R2_FB29 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l03104"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc2d754207055a5a87696eb1bb7d8cae"> 3104</a></span> <span class="preprocessor">#define CAN_F6R2_FB30 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l03105"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga471631ee112af3bde77d848c22d743ef"> 3105</a></span> <span class="preprocessor">#define CAN_F6R2_FB31 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l03107"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64bcb159347ad8e2a2609ce89ed030df"> 3107</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F7R2 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l03108"></a><span class="lineno"> 3108</span> <span class="preprocessor">#define CAN_F7R2_FB0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l03109"></a><span class="lineno"> 3109</span> <span class="preprocessor">#define CAN_F7R2_FB1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l03110"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec0803330590bf9aba9d09342034b2c1"> 3110</a></span> <span class="preprocessor">#define CAN_F7R2_FB2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l03111"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8c633d4cbfdf79f09ae1df5e75c98439"> 3111</a></span> <span class="preprocessor">#define CAN_F7R2_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l03112"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31a0c4ece8b73760ad295344b8558ddb"> 3112</a></span> <span class="preprocessor">#define CAN_F7R2_FB4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l03113"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe2fc15309540b87538ea3e8460d8d11"> 3113</a></span> <span class="preprocessor">#define CAN_F7R2_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l03114"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac81d4c021f4579021ddf9485472a84f5"> 3114</a></span> <span class="preprocessor">#define CAN_F7R2_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l03115"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5dd6a00bb403a3e19e66c68f5ee308e2"> 3115</a></span> <span class="preprocessor">#define CAN_F7R2_FB7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l03116"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b5eaf37458d0426fd7f847775fd41e9"> 3116</a></span> <span class="preprocessor">#define CAN_F7R2_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l03117"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga780440ce173cde12fd117b519419424c"> 3117</a></span> <span class="preprocessor">#define CAN_F7R2_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l03118"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99ae0e27d14b42fef4551d83ee88b4ac"> 3118</a></span> <span class="preprocessor">#define CAN_F7R2_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l03119"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace90c0624446480421fac233739413dc"> 3119</a></span> <span class="preprocessor">#define CAN_F7R2_FB11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l03120"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae60d566699df87580584ed496681562"> 3120</a></span> <span class="preprocessor">#define CAN_F7R2_FB12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l03121"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6325b37cc369b92b2334e482dbe3bf06"> 3121</a></span> <span class="preprocessor">#define CAN_F7R2_FB13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l03122"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace846d293ac11d535ee2aad17cf099bc"> 3122</a></span> <span class="preprocessor">#define CAN_F7R2_FB14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l03123"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91b26397a75fc4c0124e84903d31221e"> 3123</a></span> <span class="preprocessor">#define CAN_F7R2_FB15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l03124"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada2e01c05c216ba6ff4756d043297c0e"> 3124</a></span> <span class="preprocessor">#define CAN_F7R2_FB16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l03125"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeef08aa6565ff24bd9863b4b8a9c2ff5"> 3125</a></span> <span class="preprocessor">#define CAN_F7R2_FB17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l03126"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16c3ccb033b9541b57c338b9737f18dd"> 3126</a></span> <span class="preprocessor">#define CAN_F7R2_FB18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l03127"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad898ca382f57efb1842884d46217245c"> 3127</a></span> <span class="preprocessor">#define CAN_F7R2_FB19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l03128"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf419938e132cc1a0bf59a6c058e2c7c5"> 3128</a></span> <span class="preprocessor">#define CAN_F7R2_FB20 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l03129"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae991abb6f2e64443be7e39633f192aba"> 3129</a></span> <span class="preprocessor">#define CAN_F7R2_FB21 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l03130"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3738a42e2767c928de21a2f784ce6bce"> 3130</a></span> <span class="preprocessor">#define CAN_F7R2_FB22 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l03131"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5cb252582e6b7bd706b37447f71d6cd"> 3131</a></span> <span class="preprocessor">#define CAN_F7R2_FB23 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l03132"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae616e53b9d961571eea4ff2df31f8399"> 3132</a></span> <span class="preprocessor">#define CAN_F7R2_FB24 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l03133"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2049c9bb27af3cde01334b1901aa417"> 3133</a></span> <span class="preprocessor">#define CAN_F7R2_FB25 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l03134"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e69c2fd32e2c523c9e939df825fc605"> 3134</a></span> <span class="preprocessor">#define CAN_F7R2_FB26 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l03135"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga659cc84b9186e279c37e88b94e1c9829"> 3135</a></span> <span class="preprocessor">#define CAN_F7R2_FB27 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l03136"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43c9da5ad4c2d261858f73b779cc3dae"> 3136</a></span> <span class="preprocessor">#define CAN_F7R2_FB28 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l03137"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a1ea8d66ada6cea7268fba151c00d91"> 3137</a></span> <span class="preprocessor">#define CAN_F7R2_FB29 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l03138"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabbd6032652515423412ad73b8a004bbb"> 3138</a></span> <span class="preprocessor">#define CAN_F7R2_FB30 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l03139"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a991a0bb5a81748b091d6b96c59fc37"> 3139</a></span> <span class="preprocessor">#define CAN_F7R2_FB31 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l03141"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f88a239b8a39ff3343b1cfe70b06139"> 3141</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F8R2 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l03142"></a><span class="lineno"> 3142</span> <span class="preprocessor">#define CAN_F8R2_FB0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l03143"></a><span class="lineno"> 3143</span> <span class="preprocessor">#define CAN_F8R2_FB1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l03144"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3cfe399fb494ff6ab1d5b91258c42764"> 3144</a></span> <span class="preprocessor">#define CAN_F8R2_FB2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l03145"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ca04b514b4d6a3b19619932513b8953"> 3145</a></span> <span class="preprocessor">#define CAN_F8R2_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l03146"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4c3c099bf7db702b7bf5f71cddaaec2"> 3146</a></span> <span class="preprocessor">#define CAN_F8R2_FB4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l03147"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1e53037e7f7171d8a7358590f0e7420"> 3147</a></span> <span class="preprocessor">#define CAN_F8R2_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l03148"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51e2af45725e06538c4d09ad07296316"> 3148</a></span> <span class="preprocessor">#define CAN_F8R2_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l03149"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ee5e9d68190f0d41a5b8603d1933922"> 3149</a></span> <span class="preprocessor">#define CAN_F8R2_FB7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l03150"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66c636150cfad43a32652dba3ded8383"> 3150</a></span> <span class="preprocessor">#define CAN_F8R2_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l03151"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0fc81a4ee32f76ce3a6fdbb3fc49425c"> 3151</a></span> <span class="preprocessor">#define CAN_F8R2_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l03152"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68a36336242e8259c779f1c8f4544737"> 3152</a></span> <span class="preprocessor">#define CAN_F8R2_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l03153"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0014717b3c4c65afb7542308980803d"> 3153</a></span> <span class="preprocessor">#define CAN_F8R2_FB11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l03154"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga315a7e30b95c05db01b7f56f4d825e62"> 3154</a></span> <span class="preprocessor">#define CAN_F8R2_FB12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l03155"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga353aad2279bf6b72bd861f6c79253635"> 3155</a></span> <span class="preprocessor">#define CAN_F8R2_FB13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l03156"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25193c4b44d05db08ba40f0e0f2c45e1"> 3156</a></span> <span class="preprocessor">#define CAN_F8R2_FB14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l03157"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4469bfc90525f84d9d04d3a4996997e6"> 3157</a></span> <span class="preprocessor">#define CAN_F8R2_FB15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l03158"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b17ebf3dd1e53d8417f955ebcf743b3"> 3158</a></span> <span class="preprocessor">#define CAN_F8R2_FB16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l03159"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6db6c2262434fc76213a441d8ce2edf1"> 3159</a></span> <span class="preprocessor">#define CAN_F8R2_FB17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l03160"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a1e1e9aa84af36845402d19236c1214"> 3160</a></span> <span class="preprocessor">#define CAN_F8R2_FB18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l03161"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0a9ee665444a6b42e98e0f988d1ba7a"> 3161</a></span> <span class="preprocessor">#define CAN_F8R2_FB19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l03162"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16cde37565a3d3ec3a8c41013df6f6f1"> 3162</a></span> <span class="preprocessor">#define CAN_F8R2_FB20 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l03163"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57ca000fea3be225ddf5f295437b6e36"> 3163</a></span> <span class="preprocessor">#define CAN_F8R2_FB21 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l03164"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad60ee9ebdce23be6d2adca113ca918e8"> 3164</a></span> <span class="preprocessor">#define CAN_F8R2_FB22 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l03165"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae186c9794783eb47b460532801afe43a"> 3165</a></span> <span class="preprocessor">#define CAN_F8R2_FB23 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l03166"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga106a5e5b8ae8d683fcec85b076688f34"> 3166</a></span> <span class="preprocessor">#define CAN_F8R2_FB24 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l03167"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1643a77c219a9b2706f438c5123bccc8"> 3167</a></span> <span class="preprocessor">#define CAN_F8R2_FB25 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l03168"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab21aa6ed09bed09347e07dbcbd0e9e93"> 3168</a></span> <span class="preprocessor">#define CAN_F8R2_FB26 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l03169"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8267e4cdc484abd75634469f9b255c5"> 3169</a></span> <span class="preprocessor">#define CAN_F8R2_FB27 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l03170"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga697d286473e81666c91f28e853aab4ad"> 3170</a></span> <span class="preprocessor">#define CAN_F8R2_FB28 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l03171"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga295c26638700a849ee3c6504caf6ceab"> 3171</a></span> <span class="preprocessor">#define CAN_F8R2_FB29 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l03172"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f8469008983b405bfc5855258f4f6e6"> 3172</a></span> <span class="preprocessor">#define CAN_F8R2_FB30 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l03173"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad18d894a75ebe73c0185d905cfb81dbf"> 3173</a></span> <span class="preprocessor">#define CAN_F8R2_FB31 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l03175"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0636c9c9fd84e5e8d12e78f236f2a56c"> 3175</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F9R2 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l03176"></a><span class="lineno"> 3176</span> <span class="preprocessor">#define CAN_F9R2_FB0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l03177"></a><span class="lineno"> 3177</span> <span class="preprocessor">#define CAN_F9R2_FB1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l03178"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1209cec0d1199b7f74bb2e2b1cca424"> 3178</a></span> <span class="preprocessor">#define CAN_F9R2_FB2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l03179"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9fd983be0f74b7f183261f21cd2f6910"> 3179</a></span> <span class="preprocessor">#define CAN_F9R2_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l03180"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e363da951c1191e733a8bc603cda3f5"> 3180</a></span> <span class="preprocessor">#define CAN_F9R2_FB4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l03181"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabab5a59d405ae1684853988e95ab9844"> 3181</a></span> <span class="preprocessor">#define CAN_F9R2_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l03182"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b5b46878001f43618c726b3429e4b50"> 3182</a></span> <span class="preprocessor">#define CAN_F9R2_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l03183"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga582895a48cfeb8d7ecf6c9757ba0aa39"> 3183</a></span> <span class="preprocessor">#define CAN_F9R2_FB7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l03184"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe18a44ac1a9c4cf2a6e94bb946af17f"> 3184</a></span> <span class="preprocessor">#define CAN_F9R2_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l03185"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae497ffa0ef246a52e57a394fa57e616d"> 3185</a></span> <span class="preprocessor">#define CAN_F9R2_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l03186"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4eedc431183ceae7240d11afc05bacfa"> 3186</a></span> <span class="preprocessor">#define CAN_F9R2_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l03187"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71d1294050a77f52ecd4b00568cd7477"> 3187</a></span> <span class="preprocessor">#define CAN_F9R2_FB11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l03188"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5adc0ffeba391461d887f5d176a9b5bd"> 3188</a></span> <span class="preprocessor">#define CAN_F9R2_FB12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l03189"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga989f1dea5a35e78b08649ac699955563"> 3189</a></span> <span class="preprocessor">#define CAN_F9R2_FB13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l03190"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b71e1b7db02ef8c5853534921b33aee"> 3190</a></span> <span class="preprocessor">#define CAN_F9R2_FB14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l03191"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga48cff2713910823bbf9c8aeb399d6695"> 3191</a></span> <span class="preprocessor">#define CAN_F9R2_FB15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l03192"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9e0057c4eb0f7238d2ec98ae0702ff3"> 3192</a></span> <span class="preprocessor">#define CAN_F9R2_FB16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l03193"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc16f71c9ee3bc56be17f7488c1df807"> 3193</a></span> <span class="preprocessor">#define CAN_F9R2_FB17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l03194"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3909a33262113171b7d4dc11fcf8c3b1"> 3194</a></span> <span class="preprocessor">#define CAN_F9R2_FB18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l03195"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8cead3f8d10075aa34c9446859356e2d"> 3195</a></span> <span class="preprocessor">#define CAN_F9R2_FB19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l03196"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf7730d43a2cf07a1568ed738a4f69692"> 3196</a></span> <span class="preprocessor">#define CAN_F9R2_FB20 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l03197"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b2f5ba8403cbd679694cf9665e2690f"> 3197</a></span> <span class="preprocessor">#define CAN_F9R2_FB21 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l03198"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca5a17ed59696ed0572b80767c4bef81"> 3198</a></span> <span class="preprocessor">#define CAN_F9R2_FB22 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l03199"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac318672024cefb98843d473cbb2d46b2"> 3199</a></span> <span class="preprocessor">#define CAN_F9R2_FB23 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l03200"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3523d55c8cf0a308fea4837b00f89abb"> 3200</a></span> <span class="preprocessor">#define CAN_F9R2_FB24 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l03201"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga21d8d812323030dd39f417318c36b8dc"> 3201</a></span> <span class="preprocessor">#define CAN_F9R2_FB25 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l03202"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga065bba6dde8a5b81b42c2618204bf0be"> 3202</a></span> <span class="preprocessor">#define CAN_F9R2_FB26 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l03203"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade5290535026c192f7e94a4cb98e48b4"> 3203</a></span> <span class="preprocessor">#define CAN_F9R2_FB27 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l03204"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac7e7544d60c3084da344ee20ab6a760"> 3204</a></span> <span class="preprocessor">#define CAN_F9R2_FB28 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l03205"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae965845f1e45d1f45831be60829e63bc"> 3205</a></span> <span class="preprocessor">#define CAN_F9R2_FB29 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l03206"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63bbecf009bf6bd61dc9e8fe0603da73"> 3206</a></span> <span class="preprocessor">#define CAN_F9R2_FB30 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l03207"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga834cf606ef4b69b0c459b8cb9e836a9b"> 3207</a></span> <span class="preprocessor">#define CAN_F9R2_FB31 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l03209"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga18ef7c7bae75406a267e6a333c549a9f"> 3209</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F10R2 register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l03210"></a><span class="lineno"> 3210</span> <span class="preprocessor">#define CAN_F10R2_FB0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l03211"></a><span class="lineno"> 3211</span> <span class="preprocessor">#define CAN_F10R2_FB1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l03212"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga616898121d5befed0eb5ab61492872f2"> 3212</a></span> <span class="preprocessor">#define CAN_F10R2_FB2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l03213"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa24b6ba1e723098e55e4affc793558c5"> 3213</a></span> <span class="preprocessor">#define CAN_F10R2_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l03214"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b7fc9db4e77e216f37bf088d7b7703c"> 3214</a></span> <span class="preprocessor">#define CAN_F10R2_FB4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l03215"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2348cdfff622628147e2c1df0a35363c"> 3215</a></span> <span class="preprocessor">#define CAN_F10R2_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l03216"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaebde0ea1e0aaf38fdcf1584e9c9b2063"> 3216</a></span> <span class="preprocessor">#define CAN_F10R2_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l03217"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b5b32b71c86c6dc7040b3044be61af7"> 3217</a></span> <span class="preprocessor">#define CAN_F10R2_FB7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l03218"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9df7daa799c7c73d9a56de5f92285aca"> 3218</a></span> <span class="preprocessor">#define CAN_F10R2_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l03219"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed755173b9d4375b40d73cab90396adc"> 3219</a></span> <span class="preprocessor">#define CAN_F10R2_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l03220"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a8d08fea6e7307f6d1d602e113a6d27"> 3220</a></span> <span class="preprocessor">#define CAN_F10R2_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l03221"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6aecdda55a484aa0e96c89f5d0f42aba"> 3221</a></span> <span class="preprocessor">#define CAN_F10R2_FB11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l03222"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4da658bf0a044b327c5efcc592e0ebe1"> 3222</a></span> <span class="preprocessor">#define CAN_F10R2_FB12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l03223"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae6ec91db97da763ae1da98ef3a3f7fea"> 3223</a></span> <span class="preprocessor">#define CAN_F10R2_FB13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l03224"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62bba82d177602a29448acf481a7f691"> 3224</a></span> <span class="preprocessor">#define CAN_F10R2_FB14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l03225"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ce79aa37f7a175695fb910f986b7d81"> 3225</a></span> <span class="preprocessor">#define CAN_F10R2_FB15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l03226"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf31488587e33ea32b60a5c21f3e3aff"> 3226</a></span> <span class="preprocessor">#define CAN_F10R2_FB16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l03227"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8c7c289c07afb023bb3eedfe4d5a9b1"> 3227</a></span> <span class="preprocessor">#define CAN_F10R2_FB17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l03228"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74258ab493246fefc21ddc475dcfda4a"> 3228</a></span> <span class="preprocessor">#define CAN_F10R2_FB18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l03229"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabcf9f2daaa27f340a8cd4e64533f5caf"> 3229</a></span> <span class="preprocessor">#define CAN_F10R2_FB19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l03230"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b8ad53931f4cb3bebb3f557d8686066"> 3230</a></span> <span class="preprocessor">#define CAN_F10R2_FB20 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l03231"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9f0b00c508bddf59fd290091e738a340"> 3231</a></span> <span class="preprocessor">#define CAN_F10R2_FB21 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l03232"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb9db852d4bf1332f748a0cfc0063364"> 3232</a></span> <span class="preprocessor">#define CAN_F10R2_FB22 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l03233"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga616164fcd20341e4eed5b10a8fd2837c"> 3233</a></span> <span class="preprocessor">#define CAN_F10R2_FB23 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l03234"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae70893925ea53547e9ce780c0480587b"> 3234</a></span> <span class="preprocessor">#define CAN_F10R2_FB24 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l03235"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed74e80c74c6c5e12d26abbc0d923787"> 3235</a></span> <span class="preprocessor">#define CAN_F10R2_FB25 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l03236"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaecb5b90d073107f3c5612379aaffa7ce"> 3236</a></span> <span class="preprocessor">#define CAN_F10R2_FB26 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l03237"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga678702522f87f63edfcad21194be3c53"> 3237</a></span> <span class="preprocessor">#define CAN_F10R2_FB27 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l03238"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4523c34e7f333636fade643b895b8f5"> 3238</a></span> <span class="preprocessor">#define CAN_F10R2_FB28 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l03239"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf0e55fcb496970abe8fea481561f886"> 3239</a></span> <span class="preprocessor">#define CAN_F10R2_FB29 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l03240"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e4683223d46d60897b2c46b02addec5"> 3240</a></span> <span class="preprocessor">#define CAN_F10R2_FB30 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l03241"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6df50371abf968f0638faf7e0bf76cc8"> 3241</a></span> <span class="preprocessor">#define CAN_F10R2_FB31 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l03243"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2de1906dc4119b37b29bbe25e3e6dbe0"> 3243</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F11R2 register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l03244"></a><span class="lineno"> 3244</span> <span class="preprocessor">#define CAN_F11R2_FB0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l03245"></a><span class="lineno"> 3245</span> <span class="preprocessor">#define CAN_F11R2_FB1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l03246"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacad6560088b586891d446952bbd8fbbe"> 3246</a></span> <span class="preprocessor">#define CAN_F11R2_FB2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l03247"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac81bc667cb0c63aa0448f6e0eb1d105d"> 3247</a></span> <span class="preprocessor">#define CAN_F11R2_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l03248"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8dab8868637d6d6fb707b6a37a5989b5"> 3248</a></span> <span class="preprocessor">#define CAN_F11R2_FB4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l03249"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga559246cfa4658a5adaa282e4a3b35dd5"> 3249</a></span> <span class="preprocessor">#define CAN_F11R2_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l03250"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga499aebdfc0c14b9c399698e28fde3e50"> 3250</a></span> <span class="preprocessor">#define CAN_F11R2_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l03251"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1613d097fe5b7107ff36f97a9263bd38"> 3251</a></span> <span class="preprocessor">#define CAN_F11R2_FB7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l03252"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9db1830185822d66619059a644d86ffe"> 3252</a></span> <span class="preprocessor">#define CAN_F11R2_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l03253"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab35bedade0c9f71455abfbbac2edee14"> 3253</a></span> <span class="preprocessor">#define CAN_F11R2_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l03254"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac79ac007ffed536eedddffdd2615c5f7"> 3254</a></span> <span class="preprocessor">#define CAN_F11R2_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l03255"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5900c2273c405ce35b9bd52b189c102"> 3255</a></span> <span class="preprocessor">#define CAN_F11R2_FB11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l03256"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9dad5ea347a6a928997a0a1c149369ce"> 3256</a></span> <span class="preprocessor">#define CAN_F11R2_FB12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l03257"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9285109080a523012f27b3bdbabc6949"> 3257</a></span> <span class="preprocessor">#define CAN_F11R2_FB13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l03258"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65cdf759738f8b0cb8c4c3231453aad8"> 3258</a></span> <span class="preprocessor">#define CAN_F11R2_FB14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l03259"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24a40efa6debcdcfef0f7ab6d8b3eb04"> 3259</a></span> <span class="preprocessor">#define CAN_F11R2_FB15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l03260"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa923634a3432436c4c84e65be1fd39d6"> 3260</a></span> <span class="preprocessor">#define CAN_F11R2_FB16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l03261"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65bae4ee01f83fe051acee8ee4c8a10e"> 3261</a></span> <span class="preprocessor">#define CAN_F11R2_FB17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l03262"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b6762f3642ce7a06fff58270ac9f53f"> 3262</a></span> <span class="preprocessor">#define CAN_F11R2_FB18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l03263"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69c7d6a41708543278980035b64bd31b"> 3263</a></span> <span class="preprocessor">#define CAN_F11R2_FB19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l03264"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88d6d67020cbc5a4d5f0b7c5dc488aa6"> 3264</a></span> <span class="preprocessor">#define CAN_F11R2_FB20 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l03265"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07f4a8d606f2063be35b52e1fc5e4b58"> 3265</a></span> <span class="preprocessor">#define CAN_F11R2_FB21 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l03266"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga58c6e5b0076c31b7bee1c9aea94e11fb"> 3266</a></span> <span class="preprocessor">#define CAN_F11R2_FB22 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l03267"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93bf815d462dc3a40725f73e107e11f5"> 3267</a></span> <span class="preprocessor">#define CAN_F11R2_FB23 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l03268"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeebe934727476f5fde11c888c424c417"> 3268</a></span> <span class="preprocessor">#define CAN_F11R2_FB24 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l03269"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8324877e56a61c15119f2ebf929894cc"> 3269</a></span> <span class="preprocessor">#define CAN_F11R2_FB25 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l03270"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadfd994c36da11529ac494df973b5759c"> 3270</a></span> <span class="preprocessor">#define CAN_F11R2_FB26 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l03271"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f3e9d272b625f7d6269057aee5d7761"> 3271</a></span> <span class="preprocessor">#define CAN_F11R2_FB27 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l03272"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5da4d794a9797d14536197679b7b2b14"> 3272</a></span> <span class="preprocessor">#define CAN_F11R2_FB28 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l03273"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9b9a815f36e7c2929f4313ca424c83a"> 3273</a></span> <span class="preprocessor">#define CAN_F11R2_FB29 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l03274"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf162471f4c070d13fa409d44467373fc"> 3274</a></span> <span class="preprocessor">#define CAN_F11R2_FB30 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l03275"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c301fd37e3fa27d3bd28a1f3f553e77"> 3275</a></span> <span class="preprocessor">#define CAN_F11R2_FB31 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l03277"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6525c1ff364a229c9ea1b353b11be8c3"> 3277</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F12R2 register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l03278"></a><span class="lineno"> 3278</span> <span class="preprocessor">#define CAN_F12R2_FB0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l03279"></a><span class="lineno"> 3279</span> <span class="preprocessor">#define CAN_F12R2_FB1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l03280"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5fd095552b3108c685514e78e43e52d"> 3280</a></span> <span class="preprocessor">#define CAN_F12R2_FB2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l03281"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga450e88e19b2e478e73cbc5eef74a72d2"> 3281</a></span> <span class="preprocessor">#define CAN_F12R2_FB3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l03282"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17875db304b98c38e627f7d7db339136"> 3282</a></span> <span class="preprocessor">#define CAN_F12R2_FB4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l03283"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2960fee8bc56574e1b51975da7d2f041"> 3283</a></span> <span class="preprocessor">#define CAN_F12R2_FB5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l03284"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b3b6f518fae0cb1123aa187138d90b6"> 3284</a></span> <span class="preprocessor">#define CAN_F12R2_FB6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l03285"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39cedc414fa80ef987825daf32e11ac4"> 3285</a></span> <span class="preprocessor">#define CAN_F12R2_FB7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l03286"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga10aa07474c2e7cf7f2845d0d2b2bd383"> 3286</a></span> <span class="preprocessor">#define CAN_F12R2_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l03287"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga227ef5f36f6e03969cd952d62a3bc0a9"> 3287</a></span> <span class="preprocessor">#define CAN_F12R2_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l03288"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a946c991cee617b322ff9a372af3512"> 3288</a></span> <span class="preprocessor">#define CAN_F12R2_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l03289"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0ab582743e96fcd36662a9434b875bd"> 3289</a></span> <span class="preprocessor">#define CAN_F12R2_FB11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l03290"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga854c2b7108e33d263cc8269648f8bbbe"> 3290</a></span> <span class="preprocessor">#define CAN_F12R2_FB12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l03291"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ed3de0039e458bac5530d08c2e9af51"> 3291</a></span> <span class="preprocessor">#define CAN_F12R2_FB13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l03292"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadad0db6fe916794156f773e98b524b07"> 3292</a></span> <span class="preprocessor">#define CAN_F12R2_FB14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l03293"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7a50bd0de8b4e85d9e90c1f48ef7bc8"> 3293</a></span> <span class="preprocessor">#define CAN_F12R2_FB15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l03294"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c5558cc37c62c5570a5e2716e30ed99"> 3294</a></span> <span class="preprocessor">#define CAN_F12R2_FB16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l03295"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9fa511d56f90a2ee10e44e56e378f7ed"> 3295</a></span> <span class="preprocessor">#define CAN_F12R2_FB17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l03296"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga77ae08ea078773a1aecbf74e89dc2a5d"> 3296</a></span> <span class="preprocessor">#define CAN_F12R2_FB18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l03297"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a94ac3d4ba5c16a98fc04144ae3bb86"> 3297</a></span> <span class="preprocessor">#define CAN_F12R2_FB19 ((uint32_t)0x00080000) </span></div>
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|
<div class="line"><a name="l03298"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9070c9b9eec5dea6b5c4cdbaa1d5918"> 3298</a></span> <span class="preprocessor">#define CAN_F12R2_FB20 ((uint32_t)0x00100000) </span></div>
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|
<div class="line"><a name="l03299"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga758cacc8b96577bb3663da1fae36040b"> 3299</a></span> <span class="preprocessor">#define CAN_F12R2_FB21 ((uint32_t)0x00200000) </span></div>
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|
<div class="line"><a name="l03300"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80db4704807d6df4aaee2eebfcf5210a"> 3300</a></span> <span class="preprocessor">#define CAN_F12R2_FB22 ((uint32_t)0x00400000) </span></div>
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|
<div class="line"><a name="l03301"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3d3fb3a9b4b6b90139024bef933bc3d"> 3301</a></span> <span class="preprocessor">#define CAN_F12R2_FB23 ((uint32_t)0x00800000) </span></div>
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|
<div class="line"><a name="l03302"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24e87973f51235e81195d84f78489cb0"> 3302</a></span> <span class="preprocessor">#define CAN_F12R2_FB24 ((uint32_t)0x01000000) </span></div>
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|
<div class="line"><a name="l03303"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e917f2a362569d86a75a34eddce636c"> 3303</a></span> <span class="preprocessor">#define CAN_F12R2_FB25 ((uint32_t)0x02000000) </span></div>
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|
<div class="line"><a name="l03304"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6e5f2c5de8981fbfc152926fc8fb057"> 3304</a></span> <span class="preprocessor">#define CAN_F12R2_FB26 ((uint32_t)0x04000000) </span></div>
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|
<div class="line"><a name="l03305"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaad1149501e8f926a247aa532405c0b9"> 3305</a></span> <span class="preprocessor">#define CAN_F12R2_FB27 ((uint32_t)0x08000000) </span></div>
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|
<div class="line"><a name="l03306"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53538969afd7e43cc7fed4c400ab6f5a"> 3306</a></span> <span class="preprocessor">#define CAN_F12R2_FB28 ((uint32_t)0x10000000) </span></div>
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|
<div class="line"><a name="l03307"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74e04fa5d17a7cc7687c0ca40dd571ce"> 3307</a></span> <span class="preprocessor">#define CAN_F12R2_FB29 ((uint32_t)0x20000000) </span></div>
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|
<div class="line"><a name="l03308"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc1d97354c1649fa5ddc46f4271297d9"> 3308</a></span> <span class="preprocessor">#define CAN_F12R2_FB30 ((uint32_t)0x40000000) </span></div>
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|
<div class="line"><a name="l03309"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71b870003e469dcb24979e835a2f81a4"> 3309</a></span> <span class="preprocessor">#define CAN_F12R2_FB31 ((uint32_t)0x80000000) </span></div>
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|
<div class="line"><a name="l03311"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab11cddebcb4e1ab70b7222a999d0c58a"> 3311</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CAN_F13R2 register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l03312"></a><span class="lineno"> 3312</span> <span class="preprocessor">#define CAN_F13R2_FB0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l03313"></a><span class="lineno"> 3313</span> <span class="preprocessor">#define CAN_F13R2_FB1 ((uint32_t)0x00000002) </span></div>
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|
<div class="line"><a name="l03314"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b6865be0c757b49a250a537d73ae85e"> 3314</a></span> <span class="preprocessor">#define CAN_F13R2_FB2 ((uint32_t)0x00000004) </span></div>
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|
<div class="line"><a name="l03315"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf18df9b2fd549b8991fdd9f8f94e7cbb"> 3315</a></span> <span class="preprocessor">#define CAN_F13R2_FB3 ((uint32_t)0x00000008) </span></div>
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|
<div class="line"><a name="l03316"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga034e8f5b7675ce34eb2792531c7e174d"> 3316</a></span> <span class="preprocessor">#define CAN_F13R2_FB4 ((uint32_t)0x00000010) </span></div>
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|
<div class="line"><a name="l03317"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf19767c0892dffb6eff8c5a3b0e254f5"> 3317</a></span> <span class="preprocessor">#define CAN_F13R2_FB5 ((uint32_t)0x00000020) </span></div>
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|
<div class="line"><a name="l03318"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad03b0ab4d686a1ad858f1ba4b679fff9"> 3318</a></span> <span class="preprocessor">#define CAN_F13R2_FB6 ((uint32_t)0x00000040) </span></div>
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|
<div class="line"><a name="l03319"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e37522978ae2e88c27f5604c5517d42"> 3319</a></span> <span class="preprocessor">#define CAN_F13R2_FB7 ((uint32_t)0x00000080) </span></div>
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|
<div class="line"><a name="l03320"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2bf6fff2ca4adf6e093a13b2db77adbb"> 3320</a></span> <span class="preprocessor">#define CAN_F13R2_FB8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l03321"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabca970c306c9c9b576ef3424f686f324"> 3321</a></span> <span class="preprocessor">#define CAN_F13R2_FB9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l03322"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae44e1d120c773c9dc26f418acf3cb6de"> 3322</a></span> <span class="preprocessor">#define CAN_F13R2_FB10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l03323"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga891d1d97e1a57c4cfa1a714b61b083eb"> 3323</a></span> <span class="preprocessor">#define CAN_F13R2_FB11 ((uint32_t)0x00000800) </span></div>
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|
<div class="line"><a name="l03324"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb4be9c1da46b251c43c0aafe7b04497"> 3324</a></span> <span class="preprocessor">#define CAN_F13R2_FB12 ((uint32_t)0x00001000) </span></div>
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|
<div class="line"><a name="l03325"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47f5215de00574378a489f90eb11eff4"> 3325</a></span> <span class="preprocessor">#define CAN_F13R2_FB13 ((uint32_t)0x00002000) </span></div>
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|
<div class="line"><a name="l03326"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3bbd5350aeb18966e2a40e2dc4223e3"> 3326</a></span> <span class="preprocessor">#define CAN_F13R2_FB14 ((uint32_t)0x00004000) </span></div>
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|
<div class="line"><a name="l03327"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2d97199e363dd56cd9a455aec75ef1c"> 3327</a></span> <span class="preprocessor">#define CAN_F13R2_FB15 ((uint32_t)0x00008000) </span></div>
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|
<div class="line"><a name="l03328"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0731f4e60125130bebf88d33fd4ae3ca"> 3328</a></span> <span class="preprocessor">#define CAN_F13R2_FB16 ((uint32_t)0x00010000) </span></div>
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|
<div class="line"><a name="l03329"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1683c0cc3b3143a919f4dd59243eba9f"> 3329</a></span> <span class="preprocessor">#define CAN_F13R2_FB17 ((uint32_t)0x00020000) </span></div>
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|
<div class="line"><a name="l03330"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2ed74a0929c6d397c14f49f114f13bf"> 3330</a></span> <span class="preprocessor">#define CAN_F13R2_FB18 ((uint32_t)0x00040000) </span></div>
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|
<div class="line"><a name="l03331"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafde6cdff22bf29d31b5be1b309fe4dde"> 3331</a></span> <span class="preprocessor">#define CAN_F13R2_FB19 ((uint32_t)0x00080000) </span></div>
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|
<div class="line"><a name="l03332"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb873fa1c32fbf6c5a2f3be93ba2f2e6"> 3332</a></span> <span class="preprocessor">#define CAN_F13R2_FB20 ((uint32_t)0x00100000) </span></div>
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|
<div class="line"><a name="l03333"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf82a4dfd4d3c7a13232479be997ed1f9"> 3333</a></span> <span class="preprocessor">#define CAN_F13R2_FB21 ((uint32_t)0x00200000) </span></div>
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|
<div class="line"><a name="l03334"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7bf4384e44f002392339a71bc9c912c"> 3334</a></span> <span class="preprocessor">#define CAN_F13R2_FB22 ((uint32_t)0x00400000) </span></div>
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|
<div class="line"><a name="l03335"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7023986be02dd8f736e04e658844061"> 3335</a></span> <span class="preprocessor">#define CAN_F13R2_FB23 ((uint32_t)0x00800000) </span></div>
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|
<div class="line"><a name="l03336"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd059121f2a882342a409ebef8a96999"> 3336</a></span> <span class="preprocessor">#define CAN_F13R2_FB24 ((uint32_t)0x01000000) </span></div>
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|
<div class="line"><a name="l03337"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ef57f88bf1e6e34b0096013278926c0"> 3337</a></span> <span class="preprocessor">#define CAN_F13R2_FB25 ((uint32_t)0x02000000) </span></div>
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|
<div class="line"><a name="l03338"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4847de9f5b54fc5ce00e0fba69564d2d"> 3338</a></span> <span class="preprocessor">#define CAN_F13R2_FB26 ((uint32_t)0x04000000) </span></div>
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|
<div class="line"><a name="l03339"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c415fa87c556bd8a4fc0f680d25f160"> 3339</a></span> <span class="preprocessor">#define CAN_F13R2_FB27 ((uint32_t)0x08000000) </span></div>
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|
<div class="line"><a name="l03340"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20487222c41a08fe68b9ce58dfd52fff"> 3340</a></span> <span class="preprocessor">#define CAN_F13R2_FB28 ((uint32_t)0x10000000) </span></div>
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|
<div class="line"><a name="l03341"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0d5ca021778a6e84fd3c0ad8981255d"> 3341</a></span> <span class="preprocessor">#define CAN_F13R2_FB29 ((uint32_t)0x20000000) </span></div>
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|
<div class="line"><a name="l03342"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f0c8c09be20a14f29ab46d53dd712ba"> 3342</a></span> <span class="preprocessor">#define CAN_F13R2_FB30 ((uint32_t)0x40000000) </span></div>
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|
<div class="line"><a name="l03343"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26161b84a5fc507f959b620c8e380703"> 3343</a></span> <span class="preprocessor">#define CAN_F13R2_FB31 ((uint32_t)0x80000000) </span></div>
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|
<div class="line"><a name="l03345"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga305ac04b1c5198a4f82c78c570ce7f97"> 3345</a></span> <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l03346"></a><span class="lineno"> 3346</span> <span class="comment">/* */</span></div>
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|
<div class="line"><a name="l03347"></a><span class="lineno"> 3347</span> <span class="comment">/* CRC calculation unit */</span></div>
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|
<div class="line"><a name="l03348"></a><span class="lineno"> 3348</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l03349"></a><span class="lineno"> 3349</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l03350"></a><span class="lineno"> 3350</span> <span class="comment">/******************* Bit definition for CRC_DR register *********************/</span></div>
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|
<div class="line"><a name="l03351"></a><span class="lineno"> 3351</span> <span class="preprocessor">#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) </span></div>
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|
<div class="line"><a name="l03354"></a><span class="lineno"> 3354</span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for CRC_IDR register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l03355"></a><span class="lineno"> 3355</span> <span class="preprocessor">#define CRC_IDR_IDR ((uint8_t)0xFF) </span></div>
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<div class="line"><a name="l03358"></a><span class="lineno"> 3358</span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for CRC_CR register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l03359"></a><span class="lineno"> 3359</span> <span class="preprocessor">#define CRC_CR_RESET ((uint8_t)0x01) </span></div>
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<div class="line"><a name="l03361"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d57481fb891a0964b40f721354c56d7"> 3361</a></span> <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l03362"></a><span class="lineno"> 3362</span> <span class="comment">/* */</span></div>
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|
<div class="line"><a name="l03363"></a><span class="lineno"> 3363</span> <span class="comment">/* Crypto Processor */</span></div>
|
|
<div class="line"><a name="l03364"></a><span class="lineno"> 3364</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l03365"></a><span class="lineno"> 3365</span> <span class="comment">/******************************************************************************/</span></div>
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|
<div class="line"><a name="l03366"></a><span class="lineno"> 3366</span> <span class="comment">/******************* Bits definition for CRYP_CR register ********************/</span></div>
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|
<div class="line"><a name="l03367"></a><span class="lineno"> 3367</span> <span class="preprocessor">#define CRYP_CR_ALGODIR ((uint32_t)0x00000004)</span></div>
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<div class="line"><a name="l03368"></a><span class="lineno"> 3368</span> </div>
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<div class="line"><a name="l03369"></a><span class="lineno"> 3369</span> <span class="preprocessor">#define CRYP_CR_ALGOMODE ((uint32_t)0x00080038)</span></div>
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<div class="line"><a name="l03370"></a><span class="lineno"> 3370</span> <span class="preprocessor">#define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008)</span></div>
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<div class="line"><a name="l03371"></a><span class="lineno"> 3371</span> <span class="preprocessor">#define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010)</span></div>
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<div class="line"><a name="l03372"></a><span class="lineno"> 3372</span> <span class="preprocessor">#define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020)</span></div>
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<div class="line"><a name="l03373"></a><span class="lineno"> 3373</span> <span class="preprocessor">#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)</span></div>
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<div class="line"><a name="l03374"></a><span class="lineno"> 3374</span> <span class="preprocessor">#define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008)</span></div>
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<div class="line"><a name="l03375"></a><span class="lineno"> 3375</span> <span class="preprocessor">#define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010)</span></div>
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<div class="line"><a name="l03376"></a><span class="lineno"> 3376</span> <span class="preprocessor">#define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018)</span></div>
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<div class="line"><a name="l03377"></a><span class="lineno"> 3377</span> <span class="preprocessor">#define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020)</span></div>
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<div class="line"><a name="l03378"></a><span class="lineno"> 3378</span> <span class="preprocessor">#define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028)</span></div>
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<div class="line"><a name="l03379"></a><span class="lineno"> 3379</span> <span class="preprocessor">#define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030)</span></div>
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<div class="line"><a name="l03380"></a><span class="lineno"> 3380</span> <span class="preprocessor">#define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038)</span></div>
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|
<div class="line"><a name="l03381"></a><span class="lineno"> 3381</span> </div>
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|
<div class="line"><a name="l03382"></a><span class="lineno"> 3382</span> <span class="preprocessor">#define CRYP_CR_DATATYPE ((uint32_t)0x000000C0)</span></div>
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<div class="line"><a name="l03383"></a><span class="lineno"> 3383</span> <span class="preprocessor">#define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040)</span></div>
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<div class="line"><a name="l03384"></a><span class="lineno"> 3384</span> <span class="preprocessor">#define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080)</span></div>
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<div class="line"><a name="l03385"></a><span class="lineno"> 3385</span> <span class="preprocessor">#define CRYP_CR_KEYSIZE ((uint32_t)0x00000300)</span></div>
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<div class="line"><a name="l03386"></a><span class="lineno"> 3386</span> <span class="preprocessor">#define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100)</span></div>
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<div class="line"><a name="l03387"></a><span class="lineno"> 3387</span> <span class="preprocessor">#define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200)</span></div>
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<div class="line"><a name="l03388"></a><span class="lineno"> 3388</span> <span class="preprocessor">#define CRYP_CR_FFLUSH ((uint32_t)0x00004000)</span></div>
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<div class="line"><a name="l03389"></a><span class="lineno"> 3389</span> <span class="preprocessor">#define CRYP_CR_CRYPEN ((uint32_t)0x00008000)</span></div>
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<div class="line"><a name="l03390"></a><span class="lineno"> 3390</span> </div>
|
|
<div class="line"><a name="l03391"></a><span class="lineno"> 3391</span> <span class="preprocessor">#define CRYP_CR_GCM_CCMPH ((uint32_t)0x00030000)</span></div>
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<div class="line"><a name="l03392"></a><span class="lineno"> 3392</span> <span class="preprocessor">#define CRYP_CR_GCM_CCMPH_0 ((uint32_t)0x00010000)</span></div>
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<div class="line"><a name="l03393"></a><span class="lineno"> 3393</span> <span class="preprocessor">#define CRYP_CR_GCM_CCMPH_1 ((uint32_t)0x00020000)</span></div>
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<div class="line"><a name="l03394"></a><span class="lineno"> 3394</span> <span class="preprocessor">#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l03395"></a><span class="lineno"> 3395</span> </div>
|
|
<div class="line"><a name="l03396"></a><span class="lineno"> 3396</span> <span class="comment">/****************** Bits definition for CRYP_SR register *********************/</span></div>
|
|
<div class="line"><a name="l03397"></a><span class="lineno"> 3397</span> <span class="preprocessor">#define CRYP_SR_IFEM ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l03398"></a><span class="lineno"> 3398</span> <span class="preprocessor">#define CRYP_SR_IFNF ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l03399"></a><span class="lineno"> 3399</span> <span class="preprocessor">#define CRYP_SR_OFNE ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l03400"></a><span class="lineno"> 3400</span> <span class="preprocessor">#define CRYP_SR_OFFU ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l03401"></a><span class="lineno"> 3401</span> <span class="preprocessor">#define CRYP_SR_BUSY ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l03402"></a><span class="lineno"> 3402</span> <span class="comment">/****************** Bits definition for CRYP_DMACR register ******************/</span></div>
|
|
<div class="line"><a name="l03403"></a><span class="lineno"> 3403</span> <span class="preprocessor">#define CRYP_DMACR_DIEN ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l03404"></a><span class="lineno"> 3404</span> <span class="preprocessor">#define CRYP_DMACR_DOEN ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l03405"></a><span class="lineno"> 3405</span> <span class="comment">/***************** Bits definition for CRYP_IMSCR register ******************/</span></div>
|
|
<div class="line"><a name="l03406"></a><span class="lineno"> 3406</span> <span class="preprocessor">#define CRYP_IMSCR_INIM ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l03407"></a><span class="lineno"> 3407</span> <span class="preprocessor">#define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l03408"></a><span class="lineno"> 3408</span> <span class="comment">/****************** Bits definition for CRYP_RISR register *******************/</span></div>
|
|
<div class="line"><a name="l03409"></a><span class="lineno"> 3409</span> <span class="preprocessor">#define CRYP_RISR_OUTRIS ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l03410"></a><span class="lineno"> 3410</span> <span class="preprocessor">#define CRYP_RISR_INRIS ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l03411"></a><span class="lineno"> 3411</span> <span class="comment">/****************** Bits definition for CRYP_MISR register *******************/</span></div>
|
|
<div class="line"><a name="l03412"></a><span class="lineno"> 3412</span> <span class="preprocessor">#define CRYP_MISR_INMIS ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l03413"></a><span class="lineno"> 3413</span> <span class="preprocessor">#define CRYP_MISR_OUTMIS ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l03414"></a><span class="lineno"> 3414</span> </div>
|
|
<div class="line"><a name="l03415"></a><span class="lineno"> 3415</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l03416"></a><span class="lineno"> 3416</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l03417"></a><span class="lineno"> 3417</span> <span class="comment">/* Digital to Analog Converter */</span></div>
|
|
<div class="line"><a name="l03418"></a><span class="lineno"> 3418</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l03419"></a><span class="lineno"> 3419</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l03420"></a><span class="lineno"> 3420</span> <span class="comment">/******************** Bit definition for DAC_CR register ********************/</span></div>
|
|
<div class="line"><a name="l03421"></a><span class="lineno"> 3421</span> <span class="preprocessor">#define DAC_CR_EN1 ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l03422"></a><span class="lineno"> 3422</span> <span class="preprocessor">#define DAC_CR_BOFF1 ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l03423"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd8cedbb3dda03d56ac0ba92d2d9cefd"> 3423</a></span> <span class="preprocessor">#define DAC_CR_TEN1 ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l03425"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga998aa4fd791ea2f4626df6ddc8fc7109"> 3425</a></span> <span class="preprocessor">#define DAC_CR_TSEL1 ((uint32_t)0x00000038) </span></div>
|
|
<div class="line"><a name="l03426"></a><span class="lineno"> 3426</span> <span class="preprocessor">#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l03427"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf951c1a57a1a19e356df57d908f09c6c"> 3427</a></span> <span class="preprocessor">#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l03428"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8dfa13ec123c583136e24b7890add45b"> 3428</a></span> <span class="preprocessor">#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l03430"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa625d7638422e90a616ac93edd4bf408"> 3430</a></span> <span class="preprocessor">#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) </span></div>
|
|
<div class="line"><a name="l03431"></a><span class="lineno"> 3431</span> <span class="preprocessor">#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l03432"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90491f31219d07175629eecdcdc9271e"> 3432</a></span> <span class="preprocessor">#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) </span></div>
|
|
<div class="line"><a name="l03434"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga48e167ae02d2ad5bc9fd30c2f8ea5b37"> 3434</a></span> <span class="preprocessor">#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) </span></div>
|
|
<div class="line"><a name="l03435"></a><span class="lineno"> 3435</span> <span class="preprocessor">#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l03436"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3bcf611b2f0b975513325895bf16e085"> 3436</a></span> <span class="preprocessor">#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l03437"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4225dcce22b440fcd3a8ad96c5f2baec"> 3437</a></span> <span class="preprocessor">#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l03438"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6cc15817842cb7992d449c448684f68d"> 3438</a></span> <span class="preprocessor">#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l03440"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafdc83b4feb742c632ba66f55d102432b"> 3440</a></span> <span class="preprocessor">#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l03441"></a><span class="lineno"> 3441</span> <span class="preprocessor">#define DAC_CR_EN2 ((uint32_t)0x00010000) </span></div>
|
|
<div class="line"><a name="l03442"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga995c19d8c8de9ee09057ec6151154e17"> 3442</a></span> <span class="preprocessor">#define DAC_CR_BOFF2 ((uint32_t)0x00020000) </span></div>
|
|
<div class="line"><a name="l03443"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa65db2420e02fc6813842f57134d898f"> 3443</a></span> <span class="preprocessor">#define DAC_CR_TEN2 ((uint32_t)0x00040000) </span></div>
|
|
<div class="line"><a name="l03445"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8fc527f6ddb787123da09d2085b772f"> 3445</a></span> <span class="preprocessor">#define DAC_CR_TSEL2 ((uint32_t)0x00380000) </span></div>
|
|
<div class="line"><a name="l03446"></a><span class="lineno"> 3446</span> <span class="preprocessor">#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) </span></div>
|
|
<div class="line"><a name="l03447"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga73b4d0ccff78f7c3862903e7b0e66302"> 3447</a></span> <span class="preprocessor">#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) </span></div>
|
|
<div class="line"><a name="l03448"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9753b87f31e7106ecf77b2f01a99b237"> 3448</a></span> <span class="preprocessor">#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) </span></div>
|
|
<div class="line"><a name="l03450"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ad3da8a9c5fe9566d8ffe38916caaff"> 3450</a></span> <span class="preprocessor">#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) </span></div>
|
|
<div class="line"><a name="l03451"></a><span class="lineno"> 3451</span> <span class="preprocessor">#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) </span></div>
|
|
<div class="line"><a name="l03452"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf24e48cf288db4a4643057dd09e3a7b"> 3452</a></span> <span class="preprocessor">#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) </span></div>
|
|
<div class="line"><a name="l03454"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4798bf254010b442b4ac4288c2f1b65f"> 3454</a></span> <span class="preprocessor">#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) </span></div>
|
|
<div class="line"><a name="l03455"></a><span class="lineno"> 3455</span> <span class="preprocessor">#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) </span></div>
|
|
<div class="line"><a name="l03456"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7cf03fe2359cb0f11c33f793c2e92bdd"> 3456</a></span> <span class="preprocessor">#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) </span></div>
|
|
<div class="line"><a name="l03457"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8d952192721dbdcea8d707d43096454"> 3457</a></span> <span class="preprocessor">#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) </span></div>
|
|
<div class="line"><a name="l03458"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga860032e8196838cd36a655c1749139d6"> 3458</a></span> <span class="preprocessor">#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) </span></div>
|
|
<div class="line"><a name="l03460"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0fe77a2029873111cbe723a5cba9c57"> 3460</a></span> <span class="preprocessor">#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) </span></div>
|
|
<div class="line"><a name="l03462"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f905c2ac89f976df6c4beffdde58b53"> 3462</a></span> <span class="preprocessor"></span><span class="comment">/***************** Bit definition for DAC_SWTRIGR register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03463"></a><span class="lineno"> 3463</span> <span class="preprocessor">#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) </span></div>
|
|
<div class="line"><a name="l03464"></a><span class="lineno"> 3464</span> <span class="preprocessor">#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) </span></div>
|
|
<div class="line"><a name="l03466"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0e53585b505d21f5c457476bd5a18f8"> 3466</a></span> <span class="preprocessor"></span><span class="comment">/***************** Bit definition for DAC_DHR12R1 register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03467"></a><span class="lineno"> 3467</span> <span class="preprocessor">#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) </span></div>
|
|
<div class="line"><a name="l03469"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5295b5cb7f5d71ed2e8a310deb00013d"> 3469</a></span> <span class="preprocessor"></span><span class="comment">/***************** Bit definition for DAC_DHR12L1 register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03470"></a><span class="lineno"> 3470</span> <span class="preprocessor">#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) </span></div>
|
|
<div class="line"><a name="l03472"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d34667f8f4b753689c8c936c28471c5"> 3472</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for DAC_DHR8R1 register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03473"></a><span class="lineno"> 3473</span> <span class="preprocessor">#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) </span></div>
|
|
<div class="line"><a name="l03475"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1fc9f022fe4a08f67c51646177b26cb"> 3475</a></span> <span class="preprocessor"></span><span class="comment">/***************** Bit definition for DAC_DHR12R2 register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03476"></a><span class="lineno"> 3476</span> <span class="preprocessor">#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) </span></div>
|
|
<div class="line"><a name="l03478"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7506e369b37d55826042b540b10e44c7"> 3478</a></span> <span class="preprocessor"></span><span class="comment">/***************** Bit definition for DAC_DHR12L2 register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03479"></a><span class="lineno"> 3479</span> <span class="preprocessor">#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) </span></div>
|
|
<div class="line"><a name="l03481"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f66bd794202221e1a55547673b7abab"> 3481</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for DAC_DHR8R2 register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03482"></a><span class="lineno"> 3482</span> <span class="preprocessor">#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) </span></div>
|
|
<div class="line"><a name="l03484"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7da94dc053e6637efb9ccb57b7ae481c"> 3484</a></span> <span class="preprocessor"></span><span class="comment">/***************** Bit definition for DAC_DHR12RD register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03485"></a><span class="lineno"> 3485</span> <span class="preprocessor">#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) </span></div>
|
|
<div class="line"><a name="l03486"></a><span class="lineno"> 3486</span> <span class="preprocessor">#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) </span></div>
|
|
<div class="line"><a name="l03488"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3edd68db1697af93027e05f6b764c540"> 3488</a></span> <span class="preprocessor"></span><span class="comment">/***************** Bit definition for DAC_DHR12LD register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03489"></a><span class="lineno"> 3489</span> <span class="preprocessor">#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) </span></div>
|
|
<div class="line"><a name="l03490"></a><span class="lineno"> 3490</span> <span class="preprocessor">#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) </span></div>
|
|
<div class="line"><a name="l03492"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8421d613b182aab8d6c58592bcda6c17"> 3492</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for DAC_DHR8RD register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03493"></a><span class="lineno"> 3493</span> <span class="preprocessor">#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) </span></div>
|
|
<div class="line"><a name="l03494"></a><span class="lineno"> 3494</span> <span class="preprocessor">#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) </span></div>
|
|
<div class="line"><a name="l03496"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae31631eaac76ebecb059918c351ef3c9"> 3496</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for DAC_DOR1 register *******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03497"></a><span class="lineno"> 3497</span> <span class="preprocessor">#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) </span></div>
|
|
<div class="line"><a name="l03499"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b4192938e039dc25a7df8fcc5f3932a"> 3499</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for DAC_DOR2 register *******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03500"></a><span class="lineno"> 3500</span> <span class="preprocessor">#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) </span></div>
|
|
<div class="line"><a name="l03502"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacaaa39c1e82279918918b072fd56db04"> 3502</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for DAC_SR register ********************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03503"></a><span class="lineno"> 3503</span> <span class="preprocessor">#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l03504"></a><span class="lineno"> 3504</span> <span class="preprocessor">#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) </span></div>
|
|
<div class="line"><a name="l03506"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf16e48ab85d9261c5b599c56b14aea5d"> 3506</a></span> <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03507"></a><span class="lineno"> 3507</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l03508"></a><span class="lineno"> 3508</span> <span class="comment">/* Debug MCU */</span></div>
|
|
<div class="line"><a name="l03509"></a><span class="lineno"> 3509</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l03510"></a><span class="lineno"> 3510</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l03511"></a><span class="lineno"> 3511</span> </div>
|
|
<div class="line"><a name="l03512"></a><span class="lineno"> 3512</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l03513"></a><span class="lineno"> 3513</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l03514"></a><span class="lineno"> 3514</span> <span class="comment">/* DCMI */</span></div>
|
|
<div class="line"><a name="l03515"></a><span class="lineno"> 3515</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l03516"></a><span class="lineno"> 3516</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l03517"></a><span class="lineno"> 3517</span> <span class="comment">/******************** Bits definition for DCMI_CR register ******************/</span></div>
|
|
<div class="line"><a name="l03518"></a><span class="lineno"> 3518</span> <span class="preprocessor">#define DCMI_CR_CAPTURE ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l03519"></a><span class="lineno"> 3519</span> <span class="preprocessor">#define DCMI_CR_CM ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l03520"></a><span class="lineno"> 3520</span> <span class="preprocessor">#define DCMI_CR_CROP ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l03521"></a><span class="lineno"> 3521</span> <span class="preprocessor">#define DCMI_CR_JPEG ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l03522"></a><span class="lineno"> 3522</span> <span class="preprocessor">#define DCMI_CR_ESS ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l03523"></a><span class="lineno"> 3523</span> <span class="preprocessor">#define DCMI_CR_PCKPOL ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l03524"></a><span class="lineno"> 3524</span> <span class="preprocessor">#define DCMI_CR_HSPOL ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l03525"></a><span class="lineno"> 3525</span> <span class="preprocessor">#define DCMI_CR_VSPOL ((uint32_t)0x00000080)</span></div>
|
|
<div class="line"><a name="l03526"></a><span class="lineno"> 3526</span> <span class="preprocessor">#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l03527"></a><span class="lineno"> 3527</span> <span class="preprocessor">#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l03528"></a><span class="lineno"> 3528</span> <span class="preprocessor">#define DCMI_CR_EDM_0 ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l03529"></a><span class="lineno"> 3529</span> <span class="preprocessor">#define DCMI_CR_EDM_1 ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l03530"></a><span class="lineno"> 3530</span> <span class="preprocessor">#define DCMI_CR_CRE ((uint32_t)0x00001000)</span></div>
|
|
<div class="line"><a name="l03531"></a><span class="lineno"> 3531</span> <span class="preprocessor">#define DCMI_CR_ENABLE ((uint32_t)0x00004000)</span></div>
|
|
<div class="line"><a name="l03532"></a><span class="lineno"> 3532</span> </div>
|
|
<div class="line"><a name="l03533"></a><span class="lineno"> 3533</span> <span class="comment">/******************** Bits definition for DCMI_SR register ******************/</span></div>
|
|
<div class="line"><a name="l03534"></a><span class="lineno"> 3534</span> <span class="preprocessor">#define DCMI_SR_HSYNC ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l03535"></a><span class="lineno"> 3535</span> <span class="preprocessor">#define DCMI_SR_VSYNC ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l03536"></a><span class="lineno"> 3536</span> <span class="preprocessor">#define DCMI_SR_FNE ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l03537"></a><span class="lineno"> 3537</span> </div>
|
|
<div class="line"><a name="l03538"></a><span class="lineno"> 3538</span> <span class="comment">/******************** Bits definition for DCMI_RISR register ****************/</span></div>
|
|
<div class="line"><a name="l03539"></a><span class="lineno"> 3539</span> <span class="preprocessor">#define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l03540"></a><span class="lineno"> 3540</span> <span class="preprocessor">#define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l03541"></a><span class="lineno"> 3541</span> <span class="preprocessor">#define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l03542"></a><span class="lineno"> 3542</span> <span class="preprocessor">#define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l03543"></a><span class="lineno"> 3543</span> <span class="preprocessor">#define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l03544"></a><span class="lineno"> 3544</span> </div>
|
|
<div class="line"><a name="l03545"></a><span class="lineno"> 3545</span> <span class="comment">/******************** Bits definition for DCMI_IER register *****************/</span></div>
|
|
<div class="line"><a name="l03546"></a><span class="lineno"> 3546</span> <span class="preprocessor">#define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l03547"></a><span class="lineno"> 3547</span> <span class="preprocessor">#define DCMI_IER_OVF_IE ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l03548"></a><span class="lineno"> 3548</span> <span class="preprocessor">#define DCMI_IER_ERR_IE ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l03549"></a><span class="lineno"> 3549</span> <span class="preprocessor">#define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l03550"></a><span class="lineno"> 3550</span> <span class="preprocessor">#define DCMI_IER_LINE_IE ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l03551"></a><span class="lineno"> 3551</span> </div>
|
|
<div class="line"><a name="l03552"></a><span class="lineno"> 3552</span> <span class="comment">/******************** Bits definition for DCMI_MISR register ****************/</span></div>
|
|
<div class="line"><a name="l03553"></a><span class="lineno"> 3553</span> <span class="preprocessor">#define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l03554"></a><span class="lineno"> 3554</span> <span class="preprocessor">#define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l03555"></a><span class="lineno"> 3555</span> <span class="preprocessor">#define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l03556"></a><span class="lineno"> 3556</span> <span class="preprocessor">#define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l03557"></a><span class="lineno"> 3557</span> <span class="preprocessor">#define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l03558"></a><span class="lineno"> 3558</span> </div>
|
|
<div class="line"><a name="l03559"></a><span class="lineno"> 3559</span> <span class="comment">/******************** Bits definition for DCMI_ICR register *****************/</span></div>
|
|
<div class="line"><a name="l03560"></a><span class="lineno"> 3560</span> <span class="preprocessor">#define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l03561"></a><span class="lineno"> 3561</span> <span class="preprocessor">#define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l03562"></a><span class="lineno"> 3562</span> <span class="preprocessor">#define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l03563"></a><span class="lineno"> 3563</span> <span class="preprocessor">#define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l03564"></a><span class="lineno"> 3564</span> <span class="preprocessor">#define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l03565"></a><span class="lineno"> 3565</span> </div>
|
|
<div class="line"><a name="l03566"></a><span class="lineno"> 3566</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l03567"></a><span class="lineno"> 3567</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l03568"></a><span class="lineno"> 3568</span> <span class="comment">/* DMA Controller */</span></div>
|
|
<div class="line"><a name="l03569"></a><span class="lineno"> 3569</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l03570"></a><span class="lineno"> 3570</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l03571"></a><span class="lineno"> 3571</span> <span class="comment">/******************** Bits definition for DMA_SxCR register *****************/</span> </div>
|
|
<div class="line"><a name="l03572"></a><span class="lineno"> 3572</span> <span class="preprocessor">#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)</span></div>
|
|
<div class="line"><a name="l03573"></a><span class="lineno"> 3573</span> <span class="preprocessor">#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)</span></div>
|
|
<div class="line"><a name="l03574"></a><span class="lineno"> 3574</span> <span class="preprocessor">#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)</span></div>
|
|
<div class="line"><a name="l03575"></a><span class="lineno"> 3575</span> <span class="preprocessor">#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000) </span></div>
|
|
<div class="line"><a name="l03576"></a><span class="lineno"> 3576</span> <span class="preprocessor">#define DMA_SxCR_MBURST ((uint32_t)0x01800000)</span></div>
|
|
<div class="line"><a name="l03577"></a><span class="lineno"> 3577</span> <span class="preprocessor">#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)</span></div>
|
|
<div class="line"><a name="l03578"></a><span class="lineno"> 3578</span> <span class="preprocessor">#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)</span></div>
|
|
<div class="line"><a name="l03579"></a><span class="lineno"> 3579</span> <span class="preprocessor">#define DMA_SxCR_PBURST ((uint32_t)0x00600000)</span></div>
|
|
<div class="line"><a name="l03580"></a><span class="lineno"> 3580</span> <span class="preprocessor">#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)</span></div>
|
|
<div class="line"><a name="l03581"></a><span class="lineno"> 3581</span> <span class="preprocessor">#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)</span></div>
|
|
<div class="line"><a name="l03582"></a><span class="lineno"> 3582</span> <span class="preprocessor">#define DMA_SxCR_ACK ((uint32_t)0x00100000)</span></div>
|
|
<div class="line"><a name="l03583"></a><span class="lineno"> 3583</span> <span class="preprocessor">#define DMA_SxCR_CT ((uint32_t)0x00080000) </span></div>
|
|
<div class="line"><a name="l03584"></a><span class="lineno"> 3584</span> <span class="preprocessor">#define DMA_SxCR_DBM ((uint32_t)0x00040000)</span></div>
|
|
<div class="line"><a name="l03585"></a><span class="lineno"> 3585</span> <span class="preprocessor">#define DMA_SxCR_PL ((uint32_t)0x00030000)</span></div>
|
|
<div class="line"><a name="l03586"></a><span class="lineno"> 3586</span> <span class="preprocessor">#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)</span></div>
|
|
<div class="line"><a name="l03587"></a><span class="lineno"> 3587</span> <span class="preprocessor">#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)</span></div>
|
|
<div class="line"><a name="l03588"></a><span class="lineno"> 3588</span> <span class="preprocessor">#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)</span></div>
|
|
<div class="line"><a name="l03589"></a><span class="lineno"> 3589</span> <span class="preprocessor">#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)</span></div>
|
|
<div class="line"><a name="l03590"></a><span class="lineno"> 3590</span> <span class="preprocessor">#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)</span></div>
|
|
<div class="line"><a name="l03591"></a><span class="lineno"> 3591</span> <span class="preprocessor">#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)</span></div>
|
|
<div class="line"><a name="l03592"></a><span class="lineno"> 3592</span> <span class="preprocessor">#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)</span></div>
|
|
<div class="line"><a name="l03593"></a><span class="lineno"> 3593</span> <span class="preprocessor">#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l03594"></a><span class="lineno"> 3594</span> <span class="preprocessor">#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)</span></div>
|
|
<div class="line"><a name="l03595"></a><span class="lineno"> 3595</span> <span class="preprocessor">#define DMA_SxCR_MINC ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l03596"></a><span class="lineno"> 3596</span> <span class="preprocessor">#define DMA_SxCR_PINC ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l03597"></a><span class="lineno"> 3597</span> <span class="preprocessor">#define DMA_SxCR_CIRC ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l03598"></a><span class="lineno"> 3598</span> <span class="preprocessor">#define DMA_SxCR_DIR ((uint32_t)0x000000C0)</span></div>
|
|
<div class="line"><a name="l03599"></a><span class="lineno"> 3599</span> <span class="preprocessor">#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l03600"></a><span class="lineno"> 3600</span> <span class="preprocessor">#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)</span></div>
|
|
<div class="line"><a name="l03601"></a><span class="lineno"> 3601</span> <span class="preprocessor">#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l03602"></a><span class="lineno"> 3602</span> <span class="preprocessor">#define DMA_SxCR_TCIE ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l03603"></a><span class="lineno"> 3603</span> <span class="preprocessor">#define DMA_SxCR_HTIE ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l03604"></a><span class="lineno"> 3604</span> <span class="preprocessor">#define DMA_SxCR_TEIE ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l03605"></a><span class="lineno"> 3605</span> <span class="preprocessor">#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l03606"></a><span class="lineno"> 3606</span> <span class="preprocessor">#define DMA_SxCR_EN ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l03607"></a><span class="lineno"> 3607</span> </div>
|
|
<div class="line"><a name="l03608"></a><span class="lineno"> 3608</span> <span class="comment">/******************** Bits definition for DMA_SxCNDTR register **************/</span></div>
|
|
<div class="line"><a name="l03609"></a><span class="lineno"> 3609</span> <span class="preprocessor">#define DMA_SxNDT ((uint32_t)0x0000FFFF)</span></div>
|
|
<div class="line"><a name="l03610"></a><span class="lineno"> 3610</span> <span class="preprocessor">#define DMA_SxNDT_0 ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l03611"></a><span class="lineno"> 3611</span> <span class="preprocessor">#define DMA_SxNDT_1 ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l03612"></a><span class="lineno"> 3612</span> <span class="preprocessor">#define DMA_SxNDT_2 ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l03613"></a><span class="lineno"> 3613</span> <span class="preprocessor">#define DMA_SxNDT_3 ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l03614"></a><span class="lineno"> 3614</span> <span class="preprocessor">#define DMA_SxNDT_4 ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l03615"></a><span class="lineno"> 3615</span> <span class="preprocessor">#define DMA_SxNDT_5 ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l03616"></a><span class="lineno"> 3616</span> <span class="preprocessor">#define DMA_SxNDT_6 ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l03617"></a><span class="lineno"> 3617</span> <span class="preprocessor">#define DMA_SxNDT_7 ((uint32_t)0x00000080)</span></div>
|
|
<div class="line"><a name="l03618"></a><span class="lineno"> 3618</span> <span class="preprocessor">#define DMA_SxNDT_8 ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l03619"></a><span class="lineno"> 3619</span> <span class="preprocessor">#define DMA_SxNDT_9 ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l03620"></a><span class="lineno"> 3620</span> <span class="preprocessor">#define DMA_SxNDT_10 ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l03621"></a><span class="lineno"> 3621</span> <span class="preprocessor">#define DMA_SxNDT_11 ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l03622"></a><span class="lineno"> 3622</span> <span class="preprocessor">#define DMA_SxNDT_12 ((uint32_t)0x00001000)</span></div>
|
|
<div class="line"><a name="l03623"></a><span class="lineno"> 3623</span> <span class="preprocessor">#define DMA_SxNDT_13 ((uint32_t)0x00002000)</span></div>
|
|
<div class="line"><a name="l03624"></a><span class="lineno"> 3624</span> <span class="preprocessor">#define DMA_SxNDT_14 ((uint32_t)0x00004000)</span></div>
|
|
<div class="line"><a name="l03625"></a><span class="lineno"> 3625</span> <span class="preprocessor">#define DMA_SxNDT_15 ((uint32_t)0x00008000)</span></div>
|
|
<div class="line"><a name="l03626"></a><span class="lineno"> 3626</span> </div>
|
|
<div class="line"><a name="l03627"></a><span class="lineno"> 3627</span> <span class="comment">/******************** Bits definition for DMA_SxFCR register ****************/</span> </div>
|
|
<div class="line"><a name="l03628"></a><span class="lineno"> 3628</span> <span class="preprocessor">#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)</span></div>
|
|
<div class="line"><a name="l03629"></a><span class="lineno"> 3629</span> <span class="preprocessor">#define DMA_SxFCR_FS ((uint32_t)0x00000038)</span></div>
|
|
<div class="line"><a name="l03630"></a><span class="lineno"> 3630</span> <span class="preprocessor">#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l03631"></a><span class="lineno"> 3631</span> <span class="preprocessor">#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l03632"></a><span class="lineno"> 3632</span> <span class="preprocessor">#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l03633"></a><span class="lineno"> 3633</span> <span class="preprocessor">#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l03634"></a><span class="lineno"> 3634</span> <span class="preprocessor">#define DMA_SxFCR_FTH ((uint32_t)0x00000003)</span></div>
|
|
<div class="line"><a name="l03635"></a><span class="lineno"> 3635</span> <span class="preprocessor">#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l03636"></a><span class="lineno"> 3636</span> <span class="preprocessor">#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l03637"></a><span class="lineno"> 3637</span> </div>
|
|
<div class="line"><a name="l03638"></a><span class="lineno"> 3638</span> <span class="comment">/******************** Bits definition for DMA_LISR register *****************/</span> </div>
|
|
<div class="line"><a name="l03639"></a><span class="lineno"> 3639</span> <span class="preprocessor">#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)</span></div>
|
|
<div class="line"><a name="l03640"></a><span class="lineno"> 3640</span> <span class="preprocessor">#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)</span></div>
|
|
<div class="line"><a name="l03641"></a><span class="lineno"> 3641</span> <span class="preprocessor">#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)</span></div>
|
|
<div class="line"><a name="l03642"></a><span class="lineno"> 3642</span> <span class="preprocessor">#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)</span></div>
|
|
<div class="line"><a name="l03643"></a><span class="lineno"> 3643</span> <span class="preprocessor">#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)</span></div>
|
|
<div class="line"><a name="l03644"></a><span class="lineno"> 3644</span> <span class="preprocessor">#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)</span></div>
|
|
<div class="line"><a name="l03645"></a><span class="lineno"> 3645</span> <span class="preprocessor">#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)</span></div>
|
|
<div class="line"><a name="l03646"></a><span class="lineno"> 3646</span> <span class="preprocessor">#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)</span></div>
|
|
<div class="line"><a name="l03647"></a><span class="lineno"> 3647</span> <span class="preprocessor">#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)</span></div>
|
|
<div class="line"><a name="l03648"></a><span class="lineno"> 3648</span> <span class="preprocessor">#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)</span></div>
|
|
<div class="line"><a name="l03649"></a><span class="lineno"> 3649</span> <span class="preprocessor">#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l03650"></a><span class="lineno"> 3650</span> <span class="preprocessor">#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l03651"></a><span class="lineno"> 3651</span> <span class="preprocessor">#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l03652"></a><span class="lineno"> 3652</span> <span class="preprocessor">#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l03653"></a><span class="lineno"> 3653</span> <span class="preprocessor">#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l03654"></a><span class="lineno"> 3654</span> <span class="preprocessor">#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l03655"></a><span class="lineno"> 3655</span> <span class="preprocessor">#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l03656"></a><span class="lineno"> 3656</span> <span class="preprocessor">#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l03657"></a><span class="lineno"> 3657</span> <span class="preprocessor">#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l03658"></a><span class="lineno"> 3658</span> <span class="preprocessor">#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l03659"></a><span class="lineno"> 3659</span> </div>
|
|
<div class="line"><a name="l03660"></a><span class="lineno"> 3660</span> <span class="comment">/******************** Bits definition for DMA_HISR register *****************/</span> </div>
|
|
<div class="line"><a name="l03661"></a><span class="lineno"> 3661</span> <span class="preprocessor">#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)</span></div>
|
|
<div class="line"><a name="l03662"></a><span class="lineno"> 3662</span> <span class="preprocessor">#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)</span></div>
|
|
<div class="line"><a name="l03663"></a><span class="lineno"> 3663</span> <span class="preprocessor">#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)</span></div>
|
|
<div class="line"><a name="l03664"></a><span class="lineno"> 3664</span> <span class="preprocessor">#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)</span></div>
|
|
<div class="line"><a name="l03665"></a><span class="lineno"> 3665</span> <span class="preprocessor">#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)</span></div>
|
|
<div class="line"><a name="l03666"></a><span class="lineno"> 3666</span> <span class="preprocessor">#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)</span></div>
|
|
<div class="line"><a name="l03667"></a><span class="lineno"> 3667</span> <span class="preprocessor">#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)</span></div>
|
|
<div class="line"><a name="l03668"></a><span class="lineno"> 3668</span> <span class="preprocessor">#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)</span></div>
|
|
<div class="line"><a name="l03669"></a><span class="lineno"> 3669</span> <span class="preprocessor">#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)</span></div>
|
|
<div class="line"><a name="l03670"></a><span class="lineno"> 3670</span> <span class="preprocessor">#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)</span></div>
|
|
<div class="line"><a name="l03671"></a><span class="lineno"> 3671</span> <span class="preprocessor">#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l03672"></a><span class="lineno"> 3672</span> <span class="preprocessor">#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l03673"></a><span class="lineno"> 3673</span> <span class="preprocessor">#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l03674"></a><span class="lineno"> 3674</span> <span class="preprocessor">#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l03675"></a><span class="lineno"> 3675</span> <span class="preprocessor">#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l03676"></a><span class="lineno"> 3676</span> <span class="preprocessor">#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l03677"></a><span class="lineno"> 3677</span> <span class="preprocessor">#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l03678"></a><span class="lineno"> 3678</span> <span class="preprocessor">#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l03679"></a><span class="lineno"> 3679</span> <span class="preprocessor">#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l03680"></a><span class="lineno"> 3680</span> <span class="preprocessor">#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l03681"></a><span class="lineno"> 3681</span> </div>
|
|
<div class="line"><a name="l03682"></a><span class="lineno"> 3682</span> <span class="comment">/******************** Bits definition for DMA_LIFCR register ****************/</span> </div>
|
|
<div class="line"><a name="l03683"></a><span class="lineno"> 3683</span> <span class="preprocessor">#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)</span></div>
|
|
<div class="line"><a name="l03684"></a><span class="lineno"> 3684</span> <span class="preprocessor">#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)</span></div>
|
|
<div class="line"><a name="l03685"></a><span class="lineno"> 3685</span> <span class="preprocessor">#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)</span></div>
|
|
<div class="line"><a name="l03686"></a><span class="lineno"> 3686</span> <span class="preprocessor">#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)</span></div>
|
|
<div class="line"><a name="l03687"></a><span class="lineno"> 3687</span> <span class="preprocessor">#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)</span></div>
|
|
<div class="line"><a name="l03688"></a><span class="lineno"> 3688</span> <span class="preprocessor">#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)</span></div>
|
|
<div class="line"><a name="l03689"></a><span class="lineno"> 3689</span> <span class="preprocessor">#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)</span></div>
|
|
<div class="line"><a name="l03690"></a><span class="lineno"> 3690</span> <span class="preprocessor">#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)</span></div>
|
|
<div class="line"><a name="l03691"></a><span class="lineno"> 3691</span> <span class="preprocessor">#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)</span></div>
|
|
<div class="line"><a name="l03692"></a><span class="lineno"> 3692</span> <span class="preprocessor">#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)</span></div>
|
|
<div class="line"><a name="l03693"></a><span class="lineno"> 3693</span> <span class="preprocessor">#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l03694"></a><span class="lineno"> 3694</span> <span class="preprocessor">#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l03695"></a><span class="lineno"> 3695</span> <span class="preprocessor">#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l03696"></a><span class="lineno"> 3696</span> <span class="preprocessor">#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l03697"></a><span class="lineno"> 3697</span> <span class="preprocessor">#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l03698"></a><span class="lineno"> 3698</span> <span class="preprocessor">#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l03699"></a><span class="lineno"> 3699</span> <span class="preprocessor">#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l03700"></a><span class="lineno"> 3700</span> <span class="preprocessor">#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l03701"></a><span class="lineno"> 3701</span> <span class="preprocessor">#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l03702"></a><span class="lineno"> 3702</span> <span class="preprocessor">#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l03703"></a><span class="lineno"> 3703</span> </div>
|
|
<div class="line"><a name="l03704"></a><span class="lineno"> 3704</span> <span class="comment">/******************** Bits definition for DMA_HIFCR register ****************/</span> </div>
|
|
<div class="line"><a name="l03705"></a><span class="lineno"> 3705</span> <span class="preprocessor">#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)</span></div>
|
|
<div class="line"><a name="l03706"></a><span class="lineno"> 3706</span> <span class="preprocessor">#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)</span></div>
|
|
<div class="line"><a name="l03707"></a><span class="lineno"> 3707</span> <span class="preprocessor">#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)</span></div>
|
|
<div class="line"><a name="l03708"></a><span class="lineno"> 3708</span> <span class="preprocessor">#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)</span></div>
|
|
<div class="line"><a name="l03709"></a><span class="lineno"> 3709</span> <span class="preprocessor">#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)</span></div>
|
|
<div class="line"><a name="l03710"></a><span class="lineno"> 3710</span> <span class="preprocessor">#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)</span></div>
|
|
<div class="line"><a name="l03711"></a><span class="lineno"> 3711</span> <span class="preprocessor">#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)</span></div>
|
|
<div class="line"><a name="l03712"></a><span class="lineno"> 3712</span> <span class="preprocessor">#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)</span></div>
|
|
<div class="line"><a name="l03713"></a><span class="lineno"> 3713</span> <span class="preprocessor">#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)</span></div>
|
|
<div class="line"><a name="l03714"></a><span class="lineno"> 3714</span> <span class="preprocessor">#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)</span></div>
|
|
<div class="line"><a name="l03715"></a><span class="lineno"> 3715</span> <span class="preprocessor">#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l03716"></a><span class="lineno"> 3716</span> <span class="preprocessor">#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l03717"></a><span class="lineno"> 3717</span> <span class="preprocessor">#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l03718"></a><span class="lineno"> 3718</span> <span class="preprocessor">#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l03719"></a><span class="lineno"> 3719</span> <span class="preprocessor">#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l03720"></a><span class="lineno"> 3720</span> <span class="preprocessor">#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l03721"></a><span class="lineno"> 3721</span> <span class="preprocessor">#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l03722"></a><span class="lineno"> 3722</span> <span class="preprocessor">#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l03723"></a><span class="lineno"> 3723</span> <span class="preprocessor">#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l03724"></a><span class="lineno"> 3724</span> <span class="preprocessor">#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l03725"></a><span class="lineno"> 3725</span> </div>
|
|
<div class="line"><a name="l03726"></a><span class="lineno"> 3726</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l03727"></a><span class="lineno"> 3727</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l03728"></a><span class="lineno"> 3728</span> <span class="comment">/* AHB Master DMA2D Controller (DMA2D) */</span></div>
|
|
<div class="line"><a name="l03729"></a><span class="lineno"> 3729</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l03730"></a><span class="lineno"> 3730</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l03731"></a><span class="lineno"> 3731</span> </div>
|
|
<div class="line"><a name="l03732"></a><span class="lineno"> 3732</span> <span class="comment">/******************** Bit definition for DMA2D_CR register ******************/</span></div>
|
|
<div class="line"><a name="l03733"></a><span class="lineno"> 3733</span> </div>
|
|
<div class="line"><a name="l03734"></a><span class="lineno"> 3734</span> <span class="preprocessor">#define DMA2D_CR_START ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l03735"></a><span class="lineno"> 3735</span> <span class="preprocessor">#define DMA2D_CR_SUSP ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l03736"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga21ef0ff3efbf1ac68d1221fef8f05371"> 3736</a></span> <span class="preprocessor">#define DMA2D_CR_ABORT ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l03737"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga64fa2b2fd936575f41106f14e3e0292a"> 3737</a></span> <span class="preprocessor">#define DMA2D_CR_TEIE ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l03738"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad12973bf311ed4aa10e3f97766d589ca"> 3738</a></span> <span class="preprocessor">#define DMA2D_CR_TCIE ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l03739"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga615079079a7f8c65843b98ea13c89890"> 3739</a></span> <span class="preprocessor">#define DMA2D_CR_TWIE ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l03740"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf750d5a2ed4ca7f746777dbf6927149e"> 3740</a></span> <span class="preprocessor">#define DMA2D_CR_CAEIE ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l03741"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6c26d2a790fef15f60efa32c442918f"> 3741</a></span> <span class="preprocessor">#define DMA2D_CR_CTCIE ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l03742"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd16a66047d3972bc09c799fa5d83294"> 3742</a></span> <span class="preprocessor">#define DMA2D_CR_CEIE ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l03743"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1799fced31c6fca2cde47755211f05dd"> 3743</a></span> <span class="preprocessor">#define DMA2D_CR_MODE ((uint32_t)0x00030000) </span></div>
|
|
<div class="line"><a name="l03745"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad8f10cbb0de796eb4a96448806ecf56"> 3745</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for DMA2D_ISR register *****************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03746"></a><span class="lineno"> 3746</span> </div>
|
|
<div class="line"><a name="l03747"></a><span class="lineno"> 3747</span> <span class="preprocessor">#define DMA2D_ISR_TEIF ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l03748"></a><span class="lineno"> 3748</span> <span class="preprocessor">#define DMA2D_ISR_TCIF ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l03749"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga797e73d0317c5351ebfa81fcec9ee74a"> 3749</a></span> <span class="preprocessor">#define DMA2D_ISR_TWIF ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l03750"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaebfdf3351d8b08d4e6cb20e53027f286"> 3750</a></span> <span class="preprocessor">#define DMA2D_ISR_CAEIF ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l03751"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2602aa4cf6d5ddc62a69221e81650f6d"> 3751</a></span> <span class="preprocessor">#define DMA2D_ISR_CTCIF ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l03752"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae12132e7245c4850274fcdd20bd1b1fd"> 3752</a></span> <span class="preprocessor">#define DMA2D_ISR_CEIF ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l03754"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00b811475a96958284c17f32467a19a4"> 3754</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for DMA2D_IFSR register ****************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03755"></a><span class="lineno"> 3755</span> </div>
|
|
<div class="line"><a name="l03756"></a><span class="lineno"> 3756</span> <span class="preprocessor">#define DMA2D_IFSR_CTEIF ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l03757"></a><span class="lineno"> 3757</span> <span class="preprocessor">#define DMA2D_IFSR_CTCIF ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l03758"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga700ffb7c66ff9b6e587f54b4d6f9d409"> 3758</a></span> <span class="preprocessor">#define DMA2D_IFSR_CTWIF ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l03759"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5ff825263374c6a82a940cef3f22def"> 3759</a></span> <span class="preprocessor">#define DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l03760"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08d11dcc310801f1a21fa1621a911a69"> 3760</a></span> <span class="preprocessor">#define DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l03761"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9331ca07d508ec2330248ead234e759"> 3761</a></span> <span class="preprocessor">#define DMA2D_IFSR_CCEIF ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l03763"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga037c3669077ab408fc19f9a56d85dbeb"> 3763</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for DMA2D_FGMAR register ***************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03764"></a><span class="lineno"> 3764</span> </div>
|
|
<div class="line"><a name="l03765"></a><span class="lineno"> 3765</span> <span class="preprocessor">#define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF) </span></div>
|
|
<div class="line"><a name="l03767"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga040254533141c16e79385b1d53f5e200"> 3767</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for DMA2D_FGOR register ****************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03768"></a><span class="lineno"> 3768</span> </div>
|
|
<div class="line"><a name="l03769"></a><span class="lineno"> 3769</span> <span class="preprocessor">#define DMA2D_FGOR_LO ((uint32_t)0x00003FFF) </span></div>
|
|
<div class="line"><a name="l03771"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3994214fb7867cdd705a98306261d4d"> 3771</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for DMA2D_BGMAR register ***************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03772"></a><span class="lineno"> 3772</span> </div>
|
|
<div class="line"><a name="l03773"></a><span class="lineno"> 3773</span> <span class="preprocessor">#define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF) </span></div>
|
|
<div class="line"><a name="l03775"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae232ec07c8af265cf273378b9bd1441"> 3775</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for DMA2D_BGOR register ****************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03776"></a><span class="lineno"> 3776</span> </div>
|
|
<div class="line"><a name="l03777"></a><span class="lineno"> 3777</span> <span class="preprocessor">#define DMA2D_BGOR_LO ((uint32_t)0x00003FFF) </span></div>
|
|
<div class="line"><a name="l03779"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52a7059b6f751d5c08c80f2685ad6ae0"> 3779</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for DMA2D_FGPFCCR register *************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03780"></a><span class="lineno"> 3780</span> </div>
|
|
<div class="line"><a name="l03781"></a><span class="lineno"> 3781</span> <span class="preprocessor">#define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F) </span></div>
|
|
<div class="line"><a name="l03782"></a><span class="lineno"> 3782</span> <span class="preprocessor">#define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l03783"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab96e4329f0cce1ff4939b86794ace4a5"> 3783</a></span> <span class="preprocessor">#define DMA2D_FGPFCCR_START ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l03784"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91559d3b49cc6eabc6e5c56fed4d90df"> 3784</a></span> <span class="preprocessor">#define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00) </span></div>
|
|
<div class="line"><a name="l03785"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79281f18fe5f1d8f72bfc5493f7fa5f5"> 3785</a></span> <span class="preprocessor">#define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000) </span></div>
|
|
<div class="line"><a name="l03786"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga499d209664516db6d8e51c156d297a64"> 3786</a></span> <span class="preprocessor">#define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000) </span></div>
|
|
<div class="line"><a name="l03788"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31134d8c12473dc1a2993ae779c97764"> 3788</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for DMA2D_FGCOLR register **************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03789"></a><span class="lineno"> 3789</span> </div>
|
|
<div class="line"><a name="l03790"></a><span class="lineno"> 3790</span> <span class="preprocessor">#define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF) </span></div>
|
|
<div class="line"><a name="l03791"></a><span class="lineno"> 3791</span> <span class="preprocessor">#define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00) </span></div>
|
|
<div class="line"><a name="l03792"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a5f83d5dbcacb5368cbd7b961eb681a"> 3792</a></span> <span class="preprocessor">#define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000) </span></div>
|
|
<div class="line"><a name="l03794"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d6b0972e557412c73e0f16f36fcb5c2"> 3794</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for DMA2D_BGPFCCR register *************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03795"></a><span class="lineno"> 3795</span> </div>
|
|
<div class="line"><a name="l03796"></a><span class="lineno"> 3796</span> <span class="preprocessor">#define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F) </span></div>
|
|
<div class="line"><a name="l03797"></a><span class="lineno"> 3797</span> <span class="preprocessor">#define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l03798"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68eb0acaf75ebd3ad3c91c09d1120f4e"> 3798</a></span> <span class="preprocessor">#define DMA2D_BGPFCCR_START ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l03799"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7af16ab77cfa65b68d87955f8174c374"> 3799</a></span> <span class="preprocessor">#define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00) </span></div>
|
|
<div class="line"><a name="l03800"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a80d7360eacbea6bdaf6e9e917fcfb3"> 3800</a></span> <span class="preprocessor">#define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000) </span></div>
|
|
<div class="line"><a name="l03801"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6815a2ca2215068895c9a472d7ddda39"> 3801</a></span> <span class="preprocessor">#define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000) </span></div>
|
|
<div class="line"><a name="l03803"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4bc612a1b1244f639b71a4d32951d0ed"> 3803</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for DMA2D_BGCOLR register **************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03804"></a><span class="lineno"> 3804</span> </div>
|
|
<div class="line"><a name="l03805"></a><span class="lineno"> 3805</span> <span class="preprocessor">#define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF) </span></div>
|
|
<div class="line"><a name="l03806"></a><span class="lineno"> 3806</span> <span class="preprocessor">#define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00) </span></div>
|
|
<div class="line"><a name="l03807"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7eed8c8ec566069a0d09afb988562b85"> 3807</a></span> <span class="preprocessor">#define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000) </span></div>
|
|
<div class="line"><a name="l03809"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40b707327b395aa7ed5dcb17d5d63025"> 3809</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for DMA2D_FGCMAR register **************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03810"></a><span class="lineno"> 3810</span> </div>
|
|
<div class="line"><a name="l03811"></a><span class="lineno"> 3811</span> <span class="preprocessor">#define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF) </span></div>
|
|
<div class="line"><a name="l03813"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44e06e669220bd1ec2684822441e98b3"> 3813</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for DMA2D_BGCMAR register **************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03814"></a><span class="lineno"> 3814</span> </div>
|
|
<div class="line"><a name="l03815"></a><span class="lineno"> 3815</span> <span class="preprocessor">#define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF) </span></div>
|
|
<div class="line"><a name="l03817"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6dc532dedbdffb9510e22260244a0559"> 3817</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for DMA2D_OPFCCR register **************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03818"></a><span class="lineno"> 3818</span> </div>
|
|
<div class="line"><a name="l03819"></a><span class="lineno"> 3819</span> <span class="preprocessor">#define DMA2D_OPFCCR_CM ((uint32_t)0x00000007) </span></div>
|
|
<div class="line"><a name="l03821"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab6aab6b2bb5740ad6b5b79f5510eed4a"> 3821</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for DMA2D_OCOLR register ***************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03822"></a><span class="lineno"> 3822</span> </div>
|
|
<div class="line"><a name="l03825"></a><span class="lineno"> 3825</span> <span class="preprocessor">#define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF) </span></div>
|
|
<div class="line"><a name="l03826"></a><span class="lineno"> 3826</span> <span class="preprocessor">#define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00) </span></div>
|
|
<div class="line"><a name="l03827"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga164c96762ec6cbaac2bff45dd84b97cf"> 3827</a></span> <span class="preprocessor">#define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000) </span></div>
|
|
<div class="line"><a name="l03828"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8545d0dcde8b511d0ec64eb0c338fe2c"> 3828</a></span> <span class="preprocessor">#define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) </span></div>
|
|
<div class="line"><a name="l03831"></a><span class="lineno"> 3831</span> <span class="preprocessor">#define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F) </span></div>
|
|
<div class="line"><a name="l03832"></a><span class="lineno"> 3832</span> <span class="preprocessor">#define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0) </span></div>
|
|
<div class="line"><a name="l03833"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga302e4754b96470c3c0e1c42f7a513001"> 3833</a></span> <span class="preprocessor">#define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800) </span></div>
|
|
<div class="line"><a name="l03836"></a><span class="lineno"> 3836</span> <span class="preprocessor">#define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F) </span></div>
|
|
<div class="line"><a name="l03837"></a><span class="lineno"> 3837</span> <span class="preprocessor">#define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0) </span></div>
|
|
<div class="line"><a name="l03838"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0aa0634e409fb6d9fc68ecf9533c8d9c"> 3838</a></span> <span class="preprocessor">#define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00) </span></div>
|
|
<div class="line"><a name="l03839"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf4c97dc43e39e09956c2f4d8e092d17"> 3839</a></span> <span class="preprocessor">#define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000) </span></div>
|
|
<div class="line"><a name="l03842"></a><span class="lineno"> 3842</span> <span class="preprocessor">#define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F) </span></div>
|
|
<div class="line"><a name="l03843"></a><span class="lineno"> 3843</span> <span class="preprocessor">#define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0) </span></div>
|
|
<div class="line"><a name="l03844"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd2439915c875a33bf9119382276cb89"> 3844</a></span> <span class="preprocessor">#define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00) </span></div>
|
|
<div class="line"><a name="l03845"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga801078def8b64717b6fa0688483e3b78"> 3845</a></span> <span class="preprocessor">#define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000) </span></div>
|
|
<div class="line"><a name="l03847"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab0b00eb37c77d6852cfbb731b603a9d5"> 3847</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for DMA2D_OMAR register ****************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03848"></a><span class="lineno"> 3848</span> </div>
|
|
<div class="line"><a name="l03849"></a><span class="lineno"> 3849</span> <span class="preprocessor">#define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF) </span></div>
|
|
<div class="line"><a name="l03851"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4898744c8de9d7d0d59d7ff41653a04f"> 3851</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for DMA2D_OOR register *****************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03852"></a><span class="lineno"> 3852</span> </div>
|
|
<div class="line"><a name="l03853"></a><span class="lineno"> 3853</span> <span class="preprocessor">#define DMA2D_OOR_LO ((uint32_t)0x00003FFF) </span></div>
|
|
<div class="line"><a name="l03855"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd4dae0dd24a62d5a70fce6d095761ab"> 3855</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for DMA2D_NLR register *****************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03856"></a><span class="lineno"> 3856</span> </div>
|
|
<div class="line"><a name="l03857"></a><span class="lineno"> 3857</span> <span class="preprocessor">#define DMA2D_NLR_NL ((uint32_t)0x0000FFFF) </span></div>
|
|
<div class="line"><a name="l03858"></a><span class="lineno"> 3858</span> <span class="preprocessor">#define DMA2D_NLR_PL ((uint32_t)0x3FFF0000) </span></div>
|
|
<div class="line"><a name="l03860"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade633c0e602bb412837333b687b1619a"> 3860</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for DMA2D_LWR register *****************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03861"></a><span class="lineno"> 3861</span> </div>
|
|
<div class="line"><a name="l03862"></a><span class="lineno"> 3862</span> <span class="preprocessor">#define DMA2D_LWR_LW ((uint32_t)0x0000FFFF) </span></div>
|
|
<div class="line"><a name="l03864"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ebac2dac47e0480401202c86c3dacd4"> 3864</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for DMA2D_AMTCR register ***************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03865"></a><span class="lineno"> 3865</span> </div>
|
|
<div class="line"><a name="l03866"></a><span class="lineno"> 3866</span> <span class="preprocessor">#define DMA2D_AMTCR_EN ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l03867"></a><span class="lineno"> 3867</span> <span class="preprocessor">#define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00) </span></div>
|
|
<div class="line"><a name="l03871"></a><span class="lineno"> 3871</span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for DMA2D_FGCLUT register **************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l03872"></a><span class="lineno"> 3872</span>  </div>
|
|
<div class="line"><a name="l03873"></a><span class="lineno"> 3873</span> <span class="comment">/******************** Bit definition for DMA2D_BGCLUT register **************/</span></div>
|
|
<div class="line"><a name="l03874"></a><span class="lineno"> 3874</span> </div>
|
|
<div class="line"><a name="l03875"></a><span class="lineno"> 3875</span> </div>
|
|
<div class="line"><a name="l03876"></a><span class="lineno"> 3876</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l03877"></a><span class="lineno"> 3877</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l03878"></a><span class="lineno"> 3878</span> <span class="comment">/* External Interrupt/Event Controller */</span></div>
|
|
<div class="line"><a name="l03879"></a><span class="lineno"> 3879</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l03880"></a><span class="lineno"> 3880</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l03881"></a><span class="lineno"> 3881</span> <span class="comment">/******************* Bit definition for EXTI_IMR register *******************/</span></div>
|
|
<div class="line"><a name="l03882"></a><span class="lineno"> 3882</span> <span class="preprocessor">#define EXTI_IMR_MR0 ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l03883"></a><span class="lineno"> 3883</span> <span class="preprocessor">#define EXTI_IMR_MR1 ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l03884"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad03b2ba6cde99065627fccabd54ac097"> 3884</a></span> <span class="preprocessor">#define EXTI_IMR_MR2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l03885"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaaf3f9a86c620149893db38c83f8ba58"> 3885</a></span> <span class="preprocessor">#define EXTI_IMR_MR3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l03886"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga71604d1c29973c5e2bf69c8e94e89f67"> 3886</a></span> <span class="preprocessor">#define EXTI_IMR_MR4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l03887"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5edd42f9b2129c18cfa3c3598dcd1134"> 3887</a></span> <span class="preprocessor">#define EXTI_IMR_MR5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l03888"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23e920ad334439cd2ad4d683054914e3"> 3888</a></span> <span class="preprocessor">#define EXTI_IMR_MR6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l03889"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7cd3c5a2e4c4cb9b81e8965fcbf1c3a5"> 3889</a></span> <span class="preprocessor">#define EXTI_IMR_MR7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l03890"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5533c8ec796e3bbc9dc4474376056e06"> 3890</a></span> <span class="preprocessor">#define EXTI_IMR_MR8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l03891"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab620165d3fea1c564fcf1016805a1a8e"> 3891</a></span> <span class="preprocessor">#define EXTI_IMR_MR9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l03892"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88e8b274e4398fdcb1c68da2b6320d5b"> 3892</a></span> <span class="preprocessor">#define EXTI_IMR_MR10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l03893"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4d177dcf33bb9a34f8590ec509746e8"> 3893</a></span> <span class="preprocessor">#define EXTI_IMR_MR11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l03894"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5fd7db9a1ce82c152ca7bc6fddf31366"> 3894</a></span> <span class="preprocessor">#define EXTI_IMR_MR12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l03895"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68cfe8fe938fcb0fc6925bf493ccfaa7"> 3895</a></span> <span class="preprocessor">#define EXTI_IMR_MR13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l03896"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad21caf923d2083fb106852493667c16e"> 3896</a></span> <span class="preprocessor">#define EXTI_IMR_MR14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l03897"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e1938a063c48d7d6504cb32f7965c0e"> 3897</a></span> <span class="preprocessor">#define EXTI_IMR_MR15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l03898"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8827cee06670f256bc8f6301bea9cab"> 3898</a></span> <span class="preprocessor">#define EXTI_IMR_MR16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l03899"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88d9990be7f8f9e530a9f930a365fa44"> 3899</a></span> <span class="preprocessor">#define EXTI_IMR_MR17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l03900"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7419f78ed9044bdd237b452ef49e1b7f"> 3900</a></span> <span class="preprocessor">#define EXTI_IMR_MR18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l03901"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4489fa85d1552b8f40faed93483a5d35"> 3901</a></span> <span class="preprocessor">#define EXTI_IMR_MR19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l03903"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad47f7a023cbba165dfb95845d3c8c55c"> 3903</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for EXTI_EMR register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l03904"></a><span class="lineno"> 3904</span> <span class="preprocessor">#define EXTI_EMR_MR0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l03905"></a><span class="lineno"> 3905</span> <span class="preprocessor">#define EXTI_EMR_MR1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l03906"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga515c0dc6d2472e06a89e4bb19725e8f3"> 3906</a></span> <span class="preprocessor">#define EXTI_EMR_MR2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l03907"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d88e7c10e5985fa425ea7ab4fe4c3e5"> 3907</a></span> <span class="preprocessor">#define EXTI_EMR_MR3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l03908"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga460d5d4c0b53bcc04d5804e1204ded21"> 3908</a></span> <span class="preprocessor">#define EXTI_EMR_MR4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l03909"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga73944983ce5a6bde9dc172b4f483898c"> 3909</a></span> <span class="preprocessor">#define EXTI_EMR_MR5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l03910"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab80f809ead83e747677a31c80c6aae03"> 3910</a></span> <span class="preprocessor">#define EXTI_EMR_MR6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l03911"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65976f75b703f740dea3562ba3b8db59"> 3911</a></span> <span class="preprocessor">#define EXTI_EMR_MR7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l03912"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea480bd932cd1fa0904f5eb1caee9a12"> 3912</a></span> <span class="preprocessor">#define EXTI_EMR_MR8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l03913"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbb27ff8664928994ef96f87052d14be"> 3913</a></span> <span class="preprocessor">#define EXTI_EMR_MR9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l03914"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ed4b371da871ffd0cc12ee00147282f"> 3914</a></span> <span class="preprocessor">#define EXTI_EMR_MR10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l03915"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga109af342179fff1fccfdde582834867a"> 3915</a></span> <span class="preprocessor">#define EXTI_EMR_MR11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l03916"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf342d34ed1b8e4aa916bf49e30c2a234"> 3916</a></span> <span class="preprocessor">#define EXTI_EMR_MR12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l03917"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ec516af1de770c82c3c9c458cbc0172"> 3917</a></span> <span class="preprocessor">#define EXTI_EMR_MR13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l03918"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15732553e5b0de9f58180a0b024d4cad"> 3918</a></span> <span class="preprocessor">#define EXTI_EMR_MR14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l03919"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9fd2ec6472e46869956acb28f5e1b55f"> 3919</a></span> <span class="preprocessor">#define EXTI_EMR_MR15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l03920"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaecf5890ea71eea034ec1cd9e96284f89"> 3920</a></span> <span class="preprocessor">#define EXTI_EMR_MR16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l03921"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a7bacc32351a36aefcd5614abc76ae3"> 3921</a></span> <span class="preprocessor">#define EXTI_EMR_MR17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l03922"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34b1a6934265da759bc061f73d5d1374"> 3922</a></span> <span class="preprocessor">#define EXTI_EMR_MR18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l03923"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a30aa20cf475eecf7e15171e83035e4"> 3923</a></span> <span class="preprocessor">#define EXTI_EMR_MR19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l03925"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaeababa85e5ebe6aa93d011d83fd7994"> 3925</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for EXTI_RTSR register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l03926"></a><span class="lineno"> 3926</span> <span class="preprocessor">#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l03927"></a><span class="lineno"> 3927</span> <span class="preprocessor">#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l03928"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb1823a87cd797a6066681a3256cecc6"> 3928</a></span> <span class="preprocessor">#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l03929"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c42cc3763c52d1061b32219fc441566"> 3929</a></span> <span class="preprocessor">#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l03930"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c073b519f09b130e4ab4039823e290c"> 3930</a></span> <span class="preprocessor">#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l03931"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga090f295579a774c215585a55e5066b11"> 3931</a></span> <span class="preprocessor">#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l03932"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabce4722e99e3f44d40bfb6afb63444cc"> 3932</a></span> <span class="preprocessor">#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l03933"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac57b970ebc88f7bb015119ece9dd32de"> 3933</a></span> <span class="preprocessor">#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l03934"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaccc2212ce653d34cf48446ae0a68bed6"> 3934</a></span> <span class="preprocessor">#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l03935"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad380a0bc59524f4a0846a0b91d3c65c1"> 3935</a></span> <span class="preprocessor">#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l03936"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26cd6a5115b0bbe113f39545bff1ee39"> 3936</a></span> <span class="preprocessor">#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l03937"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3127246b2db3571b00c6af2453941d17"> 3937</a></span> <span class="preprocessor">#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l03938"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa29df7ddbd067889992eb60ecddce0e4"> 3938</a></span> <span class="preprocessor">#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l03939"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8cf7a92cdb61b3f8cf6eec9513317ab7"> 3939</a></span> <span class="preprocessor">#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l03940"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0423be12bfb13f34eec9656d6d274e04"> 3940</a></span> <span class="preprocessor">#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l03941"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5d5ef451fd76dc0fa9c76d7c520d8f12"> 3941</a></span> <span class="preprocessor">#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l03942"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95b0d883fa0fbc49105bda5596463cda"> 3942</a></span> <span class="preprocessor">#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l03943"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4fe54b09102a18676829c0bafb0aead2"> 3943</a></span> <span class="preprocessor">#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l03944"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8e4fb52990f0fa3fb9bed5b74f1a589"> 3944</a></span> <span class="preprocessor">#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l03945"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0a8fcb63516a4ed0d91b556f696f806"> 3945</a></span> <span class="preprocessor">#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l03947"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40a722b0c36e832f619b2136f1510b3e"> 3947</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for EXTI_FTSR register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l03948"></a><span class="lineno"> 3948</span> <span class="preprocessor">#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l03949"></a><span class="lineno"> 3949</span> <span class="preprocessor">#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l03950"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacfb6fa5ae3fcaf08aec6d86c3bfefa4c"> 3950</a></span> <span class="preprocessor">#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l03951"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac287be3bd3bad84aed48603dbe8bd4ed"> 3951</a></span> <span class="preprocessor">#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l03952"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c4503803cbe1933cd35519cfc809041"> 3952</a></span> <span class="preprocessor">#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l03953"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23593d2b8a9ec0147bab28765af30e1f"> 3953</a></span> <span class="preprocessor">#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l03954"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa77211bfa8f4d77cf373296954dad6b2"> 3954</a></span> <span class="preprocessor">#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l03955"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga903f9b080c5971dd5d7935e5b87886e2"> 3955</a></span> <span class="preprocessor">#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l03956"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8527cce22f69e02a08ed67a67f8e5ca"> 3956</a></span> <span class="preprocessor">#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l03957"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf408315e497b902922a9bf40a4c6f567"> 3957</a></span> <span class="preprocessor">#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l03958"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00f1bded4d121e21116627b8e80784fc"> 3958</a></span> <span class="preprocessor">#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l03959"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga89f0c4de2b6acb75302d206b697f83ef"> 3959</a></span> <span class="preprocessor">#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l03960"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9a2b80699a213f0d2b03658f21ad643"> 3960</a></span> <span class="preprocessor">#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l03961"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c74d4d520406a14c517784cdd5fc6ef"> 3961</a></span> <span class="preprocessor">#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l03962"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3992511ec1785bdf107873b139d74245"> 3962</a></span> <span class="preprocessor">#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l03963"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0714519a1edcba4695f92f1bba70e825"> 3963</a></span> <span class="preprocessor">#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l03964"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b92577e64a95ef2069f1a56176d35ff"> 3964</a></span> <span class="preprocessor">#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l03965"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a6cc515f13ffe1a3620d06fa08addc7"> 3965</a></span> <span class="preprocessor">#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l03966"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1b4b850094ccc48790a1e4616ceebd2"> 3966</a></span> <span class="preprocessor">#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l03967"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga009e618c9563b3a8dcaec493006115c7"> 3967</a></span> <span class="preprocessor">#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l03969"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1277527e2fa727fdec2dcc7a300ea1af"> 3969</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for EXTI_SWIER register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l03970"></a><span class="lineno"> 3970</span> <span class="preprocessor">#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l03971"></a><span class="lineno"> 3971</span> <span class="preprocessor">#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l03972"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6df16d2e8010a2897888a4acf19cee3"> 3972</a></span> <span class="preprocessor">#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l03973"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaeb0c3fa5a03204d743ae92ff925421ae"> 3973</a></span> <span class="preprocessor">#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l03974"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6bea1dbaf71e830dd357135524166f4c"> 3974</a></span> <span class="preprocessor">#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l03975"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37395ac6729647ab5ee1fa4ca086c08a"> 3975</a></span> <span class="preprocessor">#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l03976"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab051808f7a1ed9aaf43a3df90fc6a575"> 3976</a></span> <span class="preprocessor">#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l03977"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa5b4ace22acacac13ce106b2063a3977"> 3977</a></span> <span class="preprocessor">#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l03978"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8ad0142288597993852e4cf350f61ed"> 3978</a></span> <span class="preprocessor">#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l03979"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabdf8eab3e32cc03ca71f519a9111e28f"> 3979</a></span> <span class="preprocessor">#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l03980"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e83a373926804449d500b115e9090ce"> 3980</a></span> <span class="preprocessor">#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l03981"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab102aa929ffe463ffe9f2db651704a61"> 3981</a></span> <span class="preprocessor">#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l03982"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9d8691936b6cd80ff8e18c0bfe271d7"> 3982</a></span> <span class="preprocessor">#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l03983"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ab9fea9935608ec8ee7fb1e1ae049e7"> 3983</a></span> <span class="preprocessor">#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l03984"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5d67869db50c848f57633ebf00566539"> 3984</a></span> <span class="preprocessor">#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l03985"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga930a1d03fe3c32bd65a336ccee418826"> 3985</a></span> <span class="preprocessor">#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l03986"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5d645db667cd63d1a9b91963c543a4b"> 3986</a></span> <span class="preprocessor">#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l03987"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b9e64d5a1779371fa4678713ab18e08"> 3987</a></span> <span class="preprocessor">#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l03988"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55b528743b11f4ab93ae97ee2e639b5b"> 3988</a></span> <span class="preprocessor">#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l03989"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0da944251419887af3a87c86080fb455"> 3989</a></span> <span class="preprocessor">#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l03991"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab7c48ac5522385cdb1d7882985f909b"> 3991</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for EXTI_PR register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l03992"></a><span class="lineno"> 3992</span> <span class="preprocessor">#define EXTI_PR_PR0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l03993"></a><span class="lineno"> 3993</span> <span class="preprocessor">#define EXTI_PR_PR1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l03994"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6da1c8a465606de1f90a74d369fbf25a"> 3994</a></span> <span class="preprocessor">#define EXTI_PR_PR2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l03995"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b9b5f97edeccf442998a65b19e77f25"> 3995</a></span> <span class="preprocessor">#define EXTI_PR_PR3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l03996"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga085d2105381752a0aadc9be5a93ea665"> 3996</a></span> <span class="preprocessor">#define EXTI_PR_PR4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l03997"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga064dab3e0d5689b92125713100555ce0"> 3997</a></span> <span class="preprocessor">#define EXTI_PR_PR5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l03998"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14f73b3693b3353a006d360cb8fd2ddc"> 3998</a></span> <span class="preprocessor">#define EXTI_PR_PR6 ((uint32_t)0x00000040) </span></div>
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|
<div class="line"><a name="l03999"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga319e167fa6e112061997d9a8d79f02f8"> 3999</a></span> <span class="preprocessor">#define EXTI_PR_PR7 ((uint32_t)0x00000080) </span></div>
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|
<div class="line"><a name="l04000"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6f47cd1f602692258985784ed5e8e76"> 4000</a></span> <span class="preprocessor">#define EXTI_PR_PR8 ((uint32_t)0x00000100) </span></div>
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|
<div class="line"><a name="l04001"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa17ea7e3fb89e98fd6a232f453fcff9e"> 4001</a></span> <span class="preprocessor">#define EXTI_PR_PR9 ((uint32_t)0x00000200) </span></div>
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|
<div class="line"><a name="l04002"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa82e0dcb4961a32a9b7ebdf30493156d"> 4002</a></span> <span class="preprocessor">#define EXTI_PR_PR10 ((uint32_t)0x00000400) </span></div>
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|
<div class="line"><a name="l04003"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2fcc64f03d79af531febc077f45c48eb"> 4003</a></span> <span class="preprocessor">#define EXTI_PR_PR11 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l04004"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ef8e9c691b95763007ed228e98fa108"> 4004</a></span> <span class="preprocessor">#define EXTI_PR_PR12 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l04005"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga144f1a41abb7b87a1619c15ba5fb548b"> 4005</a></span> <span class="preprocessor">#define EXTI_PR_PR13 ((uint32_t)0x00002000) </span></div>
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|
<div class="line"><a name="l04006"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1a68025056b8c84bb13635af5e2a07c"> 4006</a></span> <span class="preprocessor">#define EXTI_PR_PR14 ((uint32_t)0x00004000) </span></div>
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|
<div class="line"><a name="l04007"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3471c79d5b19813785387504a1a5f0c4"> 4007</a></span> <span class="preprocessor">#define EXTI_PR_PR15 ((uint32_t)0x00008000) </span></div>
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|
<div class="line"><a name="l04008"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5396ec2dbbee9d7585224fa12273598"> 4008</a></span> <span class="preprocessor">#define EXTI_PR_PR16 ((uint32_t)0x00010000) </span></div>
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|
<div class="line"><a name="l04009"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga149f9d9d6c1aab867734b59db1117c41"> 4009</a></span> <span class="preprocessor">#define EXTI_PR_PR17 ((uint32_t)0x00020000) </span></div>
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|
<div class="line"><a name="l04010"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa47e5b07d5a407198e09f05262f18bba"> 4010</a></span> <span class="preprocessor">#define EXTI_PR_PR18 ((uint32_t)0x00040000) </span></div>
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|
<div class="line"><a name="l04011"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbc7d82eb61e2adf0a955ef0cc97690f"> 4011</a></span> <span class="preprocessor">#define EXTI_PR_PR19 ((uint32_t)0x00080000) </span></div>
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|
<div class="line"><a name="l04013"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41e43af631a30492e09e5fd5c50f47f5"> 4013</a></span> <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l04014"></a><span class="lineno"> 4014</span> <span class="comment">/* */</span></div>
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<div class="line"><a name="l04015"></a><span class="lineno"> 4015</span> <span class="comment">/* FLASH */</span></div>
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<div class="line"><a name="l04016"></a><span class="lineno"> 4016</span> <span class="comment">/* */</span></div>
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|
<div class="line"><a name="l04017"></a><span class="lineno"> 4017</span> <span class="comment">/******************************************************************************/</span></div>
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|
<div class="line"><a name="l04018"></a><span class="lineno"> 4018</span> <span class="comment">/******************* Bits definition for FLASH_ACR register *****************/</span></div>
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<div class="line"><a name="l04019"></a><span class="lineno"> 4019</span> <span class="preprocessor">#define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)</span></div>
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<div class="line"><a name="l04020"></a><span class="lineno"> 4020</span> <span class="preprocessor">#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)</span></div>
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<div class="line"><a name="l04021"></a><span class="lineno"> 4021</span> <span class="preprocessor">#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)</span></div>
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<div class="line"><a name="l04022"></a><span class="lineno"> 4022</span> <span class="preprocessor">#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)</span></div>
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<div class="line"><a name="l04023"></a><span class="lineno"> 4023</span> <span class="preprocessor">#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)</span></div>
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<div class="line"><a name="l04024"></a><span class="lineno"> 4024</span> <span class="preprocessor">#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)</span></div>
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<div class="line"><a name="l04025"></a><span class="lineno"> 4025</span> <span class="preprocessor">#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)</span></div>
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<div class="line"><a name="l04026"></a><span class="lineno"> 4026</span> <span class="preprocessor">#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)</span></div>
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<div class="line"><a name="l04027"></a><span class="lineno"> 4027</span> <span class="preprocessor">#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)</span></div>
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<div class="line"><a name="l04028"></a><span class="lineno"> 4028</span> <span class="preprocessor">#define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)</span></div>
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<div class="line"><a name="l04029"></a><span class="lineno"> 4029</span> <span class="preprocessor">#define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)</span></div>
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<div class="line"><a name="l04030"></a><span class="lineno"> 4030</span> <span class="preprocessor">#define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)</span></div>
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<div class="line"><a name="l04031"></a><span class="lineno"> 4031</span> <span class="preprocessor">#define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)</span></div>
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<div class="line"><a name="l04032"></a><span class="lineno"> 4032</span> <span class="preprocessor">#define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)</span></div>
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<div class="line"><a name="l04033"></a><span class="lineno"> 4033</span> <span class="preprocessor">#define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)</span></div>
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<div class="line"><a name="l04034"></a><span class="lineno"> 4034</span> <span class="preprocessor">#define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)</span></div>
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<div class="line"><a name="l04035"></a><span class="lineno"> 4035</span> <span class="preprocessor">#define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)</span></div>
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<div class="line"><a name="l04036"></a><span class="lineno"> 4036</span> </div>
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<div class="line"><a name="l04037"></a><span class="lineno"> 4037</span> <span class="preprocessor">#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)</span></div>
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<div class="line"><a name="l04038"></a><span class="lineno"> 4038</span> <span class="preprocessor">#define FLASH_ACR_ICEN ((uint32_t)0x00000200)</span></div>
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<div class="line"><a name="l04039"></a><span class="lineno"> 4039</span> <span class="preprocessor">#define FLASH_ACR_DCEN ((uint32_t)0x00000400)</span></div>
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<div class="line"><a name="l04040"></a><span class="lineno"> 4040</span> <span class="preprocessor">#define FLASH_ACR_ICRST ((uint32_t)0x00000800)</span></div>
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<div class="line"><a name="l04041"></a><span class="lineno"> 4041</span> <span class="preprocessor">#define FLASH_ACR_DCRST ((uint32_t)0x00001000)</span></div>
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<div class="line"><a name="l04042"></a><span class="lineno"> 4042</span> <span class="preprocessor">#define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)</span></div>
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<div class="line"><a name="l04043"></a><span class="lineno"> 4043</span> <span class="preprocessor">#define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)</span></div>
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<div class="line"><a name="l04044"></a><span class="lineno"> 4044</span> </div>
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<div class="line"><a name="l04045"></a><span class="lineno"> 4045</span> <span class="comment">/******************* Bits definition for FLASH_SR register ******************/</span></div>
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|
<div class="line"><a name="l04046"></a><span class="lineno"> 4046</span> <span class="preprocessor">#define FLASH_SR_EOP ((uint32_t)0x00000001)</span></div>
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<div class="line"><a name="l04047"></a><span class="lineno"> 4047</span> <span class="preprocessor">#define FLASH_SR_SOP ((uint32_t)0x00000002)</span></div>
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<div class="line"><a name="l04048"></a><span class="lineno"> 4048</span> <span class="preprocessor">#define FLASH_SR_WRPERR ((uint32_t)0x00000010)</span></div>
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<div class="line"><a name="l04049"></a><span class="lineno"> 4049</span> <span class="preprocessor">#define FLASH_SR_PGAERR ((uint32_t)0x00000020)</span></div>
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<div class="line"><a name="l04050"></a><span class="lineno"> 4050</span> <span class="preprocessor">#define FLASH_SR_PGPERR ((uint32_t)0x00000040)</span></div>
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<div class="line"><a name="l04051"></a><span class="lineno"> 4051</span> <span class="preprocessor">#define FLASH_SR_PGSERR ((uint32_t)0x00000080)</span></div>
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<div class="line"><a name="l04052"></a><span class="lineno"> 4052</span> <span class="preprocessor">#define FLASH_SR_BSY ((uint32_t)0x00010000)</span></div>
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|
<div class="line"><a name="l04053"></a><span class="lineno"> 4053</span> </div>
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<div class="line"><a name="l04054"></a><span class="lineno"> 4054</span> <span class="comment">/******************* Bits definition for FLASH_CR register ******************/</span></div>
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|
<div class="line"><a name="l04055"></a><span class="lineno"> 4055</span> <span class="preprocessor">#define FLASH_CR_PG ((uint32_t)0x00000001)</span></div>
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<div class="line"><a name="l04056"></a><span class="lineno"> 4056</span> <span class="preprocessor">#define FLASH_CR_SER ((uint32_t)0x00000002)</span></div>
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<div class="line"><a name="l04057"></a><span class="lineno"> 4057</span> <span class="preprocessor">#define FLASH_CR_MER ((uint32_t)0x00000004)</span></div>
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<div class="line"><a name="l04058"></a><span class="lineno"> 4058</span> <span class="preprocessor">#define FLASH_CR_MER1 FLASH_CR_MER</span></div>
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<div class="line"><a name="l04059"></a><span class="lineno"> 4059</span> <span class="preprocessor">#define FLASH_CR_SNB ((uint32_t)0x000000F8)</span></div>
|
|
<div class="line"><a name="l04060"></a><span class="lineno"> 4060</span> <span class="preprocessor">#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l04061"></a><span class="lineno"> 4061</span> <span class="preprocessor">#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l04062"></a><span class="lineno"> 4062</span> <span class="preprocessor">#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l04063"></a><span class="lineno"> 4063</span> <span class="preprocessor">#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l04064"></a><span class="lineno"> 4064</span> <span class="preprocessor">#define FLASH_CR_SNB_4 ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l04065"></a><span class="lineno"> 4065</span> <span class="preprocessor">#define FLASH_CR_PSIZE ((uint32_t)0x00000300)</span></div>
|
|
<div class="line"><a name="l04066"></a><span class="lineno"> 4066</span> <span class="preprocessor">#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l04067"></a><span class="lineno"> 4067</span> <span class="preprocessor">#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l04068"></a><span class="lineno"> 4068</span> <span class="preprocessor">#define FLASH_CR_MER2 ((uint32_t)0x00008000)</span></div>
|
|
<div class="line"><a name="l04069"></a><span class="lineno"> 4069</span> <span class="preprocessor">#define FLASH_CR_STRT ((uint32_t)0x00010000)</span></div>
|
|
<div class="line"><a name="l04070"></a><span class="lineno"> 4070</span> <span class="preprocessor">#define FLASH_CR_EOPIE ((uint32_t)0x01000000)</span></div>
|
|
<div class="line"><a name="l04071"></a><span class="lineno"> 4071</span> <span class="preprocessor">#define FLASH_CR_LOCK ((uint32_t)0x80000000)</span></div>
|
|
<div class="line"><a name="l04072"></a><span class="lineno"> 4072</span> </div>
|
|
<div class="line"><a name="l04073"></a><span class="lineno"> 4073</span> <span class="comment">/******************* Bits definition for FLASH_OPTCR register ***************/</span></div>
|
|
<div class="line"><a name="l04074"></a><span class="lineno"> 4074</span> <span class="preprocessor">#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l04075"></a><span class="lineno"> 4075</span> <span class="preprocessor">#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)</span></div>
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|
<div class="line"><a name="l04076"></a><span class="lineno"> 4076</span> <span class="preprocessor">#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)</span></div>
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|
<div class="line"><a name="l04077"></a><span class="lineno"> 4077</span> <span class="preprocessor">#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)</span></div>
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|
<div class="line"><a name="l04078"></a><span class="lineno"> 4078</span> <span class="preprocessor">#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)</span></div>
|
|
<div class="line"><a name="l04079"></a><span class="lineno"> 4079</span> <span class="preprocessor">#define FLASH_OPTCR_BFB2 ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l04080"></a><span class="lineno"> 4080</span> </div>
|
|
<div class="line"><a name="l04081"></a><span class="lineno"> 4081</span> <span class="preprocessor">#define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l04082"></a><span class="lineno"> 4082</span> <span class="preprocessor">#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l04083"></a><span class="lineno"> 4083</span> <span class="preprocessor">#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)</span></div>
|
|
<div class="line"><a name="l04084"></a><span class="lineno"> 4084</span> <span class="preprocessor">#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)</span></div>
|
|
<div class="line"><a name="l04085"></a><span class="lineno"> 4085</span> <span class="preprocessor">#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l04086"></a><span class="lineno"> 4086</span> <span class="preprocessor">#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l04087"></a><span class="lineno"> 4087</span> <span class="preprocessor">#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l04088"></a><span class="lineno"> 4088</span> <span class="preprocessor">#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l04089"></a><span class="lineno"> 4089</span> <span class="preprocessor">#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)</span></div>
|
|
<div class="line"><a name="l04090"></a><span class="lineno"> 4090</span> <span class="preprocessor">#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)</span></div>
|
|
<div class="line"><a name="l04091"></a><span class="lineno"> 4091</span> <span class="preprocessor">#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)</span></div>
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|
<div class="line"><a name="l04092"></a><span class="lineno"> 4092</span> <span class="preprocessor">#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)</span></div>
|
|
<div class="line"><a name="l04093"></a><span class="lineno"> 4093</span> <span class="preprocessor">#define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)</span></div>
|
|
<div class="line"><a name="l04094"></a><span class="lineno"> 4094</span> <span class="preprocessor">#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)</span></div>
|
|
<div class="line"><a name="l04095"></a><span class="lineno"> 4095</span> <span class="preprocessor">#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)</span></div>
|
|
<div class="line"><a name="l04096"></a><span class="lineno"> 4096</span> <span class="preprocessor">#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)</span></div>
|
|
<div class="line"><a name="l04097"></a><span class="lineno"> 4097</span> <span class="preprocessor">#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)</span></div>
|
|
<div class="line"><a name="l04098"></a><span class="lineno"> 4098</span> <span class="preprocessor">#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)</span></div>
|
|
<div class="line"><a name="l04099"></a><span class="lineno"> 4099</span> <span class="preprocessor">#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)</span></div>
|
|
<div class="line"><a name="l04100"></a><span class="lineno"> 4100</span> <span class="preprocessor">#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)</span></div>
|
|
<div class="line"><a name="l04101"></a><span class="lineno"> 4101</span> <span class="preprocessor">#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)</span></div>
|
|
<div class="line"><a name="l04102"></a><span class="lineno"> 4102</span> <span class="preprocessor">#define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)</span></div>
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|
<div class="line"><a name="l04103"></a><span class="lineno"> 4103</span> <span class="preprocessor">#define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)</span></div>
|
|
<div class="line"><a name="l04104"></a><span class="lineno"> 4104</span> <span class="preprocessor">#define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)</span></div>
|
|
<div class="line"><a name="l04105"></a><span class="lineno"> 4105</span> <span class="preprocessor">#define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)</span></div>
|
|
<div class="line"><a name="l04106"></a><span class="lineno"> 4106</span> </div>
|
|
<div class="line"><a name="l04107"></a><span class="lineno"> 4107</span> <span class="preprocessor">#define FLASH_OPTCR_DB1M ((uint32_t)0x40000000) </span></div>
|
|
<div class="line"><a name="l04108"></a><span class="lineno"> 4108</span> <span class="preprocessor">#define FLASH_OPTCR_SPRMOD ((uint32_t)0x80000000) </span></div>
|
|
<div class="line"><a name="l04109"></a><span class="lineno"> 4109</span>  </div>
|
|
<div class="line"><a name="l04110"></a><span class="lineno"> 4110</span> <span class="comment">/****************** Bits definition for FLASH_OPTCR1 register ***************/</span></div>
|
|
<div class="line"><a name="l04111"></a><span class="lineno"> 4111</span> <span class="preprocessor">#define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)</span></div>
|
|
<div class="line"><a name="l04112"></a><span class="lineno"> 4112</span> <span class="preprocessor">#define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)</span></div>
|
|
<div class="line"><a name="l04113"></a><span class="lineno"> 4113</span> <span class="preprocessor">#define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)</span></div>
|
|
<div class="line"><a name="l04114"></a><span class="lineno"> 4114</span> <span class="preprocessor">#define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)</span></div>
|
|
<div class="line"><a name="l04115"></a><span class="lineno"> 4115</span> <span class="preprocessor">#define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)</span></div>
|
|
<div class="line"><a name="l04116"></a><span class="lineno"> 4116</span> <span class="preprocessor">#define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)</span></div>
|
|
<div class="line"><a name="l04117"></a><span class="lineno"> 4117</span> <span class="preprocessor">#define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)</span></div>
|
|
<div class="line"><a name="l04118"></a><span class="lineno"> 4118</span> <span class="preprocessor">#define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)</span></div>
|
|
<div class="line"><a name="l04119"></a><span class="lineno"> 4119</span> <span class="preprocessor">#define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)</span></div>
|
|
<div class="line"><a name="l04120"></a><span class="lineno"> 4120</span> <span class="preprocessor">#define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)</span></div>
|
|
<div class="line"><a name="l04121"></a><span class="lineno"> 4121</span> <span class="preprocessor">#define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)</span></div>
|
|
<div class="line"><a name="l04122"></a><span class="lineno"> 4122</span> <span class="preprocessor">#define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)</span></div>
|
|
<div class="line"><a name="l04123"></a><span class="lineno"> 4123</span> <span class="preprocessor">#define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)</span></div>
|
|
<div class="line"><a name="l04124"></a><span class="lineno"> 4124</span> </div>
|
|
<div class="line"><a name="l04125"></a><span class="lineno"> 4125</span> <span class="preprocessor">#if defined (STM32F40_41xxx)</span></div>
|
|
<div class="line"><a name="l04126"></a><span class="lineno"> 4126</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l04127"></a><span class="lineno"> 4127</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l04128"></a><span class="lineno"> 4128</span> <span class="comment">/* Flexible Static Memory Controller */</span></div>
|
|
<div class="line"><a name="l04129"></a><span class="lineno"> 4129</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l04130"></a><span class="lineno"> 4130</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l04131"></a><span class="lineno"> 4131</span> <span class="comment">/****************** Bit definition for FSMC_BCR1 register *******************/</span></div>
|
|
<div class="line"><a name="l04132"></a><span class="lineno"> 4132</span> <span class="preprocessor">#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l04133"></a><span class="lineno"> 4133</span> <span class="preprocessor">#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l04135"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga28dd9f93d8687cdc08745df9fcc38e89"> 4135</a></span> <span class="preprocessor">#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) </span></div>
|
|
<div class="line"><a name="l04136"></a><span class="lineno"> 4136</span> <span class="preprocessor">#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l04137"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9bab7a47703902d187502ac765ebb05d"> 4137</a></span> <span class="preprocessor">#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l04139"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3fe2fd14b3c0d88aecfb9cf5b44995a0"> 4139</a></span> <span class="preprocessor">#define FSMC_BCR1_MWID ((uint32_t)0x00000030) </span></div>
|
|
<div class="line"><a name="l04140"></a><span class="lineno"> 4140</span> <span class="preprocessor">#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l04141"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa12297787a0580fedbd5244f0caa0a76"> 4141</a></span> <span class="preprocessor">#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l04143"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65592a6a20efa6aed5b59fe1eba508d8"> 4143</a></span> <span class="preprocessor">#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l04144"></a><span class="lineno"> 4144</span> <span class="preprocessor">#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l04145"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14aaca2a8bccab73c7726cf73ee9be16"> 4145</a></span> <span class="preprocessor">#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l04146"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga94857a0177ae12f1172da65d8708ae97"> 4146</a></span> <span class="preprocessor">#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l04147"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57dbc565fbc7d8ec20fda7ef0da30df4"> 4147</a></span> <span class="preprocessor">#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l04148"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad215e95feee8339393bd93a2bcea11f1"> 4148</a></span> <span class="preprocessor">#define FSMC_BCR1_WREN ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l04149"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga141a337e3f1479e79d62b567ba685bcf"> 4149</a></span> <span class="preprocessor">#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l04150"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7349a91da7ba38277a068f4e8eea314"> 4150</a></span> <span class="preprocessor">#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) </span></div>
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|
<div class="line"><a name="l04151"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe4611a02a4fa635b66d5b5e52328fc5"> 4151</a></span> <span class="preprocessor">#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) </span></div>
|
|
<div class="line"><a name="l04152"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7936ff74a1cfba880a9b5bc943dc8661"> 4152</a></span> <span class="preprocessor">#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) </span></div>
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|
<div class="line"><a name="l04154"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga015672f5aa2132a55e316f5b7a577174"> 4154</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FSMC_BCR2 register *******************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l04155"></a><span class="lineno"> 4155</span> <span class="preprocessor">#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) </span></div>
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|
<div class="line"><a name="l04156"></a><span class="lineno"> 4156</span> <span class="preprocessor">#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l04158"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9f65c4348ab55c12695730bde8be8986"> 4158</a></span> <span class="preprocessor">#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) </span></div>
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|
<div class="line"><a name="l04159"></a><span class="lineno"> 4159</span> <span class="preprocessor">#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) </span></div>
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|
<div class="line"><a name="l04160"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabdf82247710aaeff72fb37113bff3daf"> 4160</a></span> <span class="preprocessor">#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) </span></div>
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|
<div class="line"><a name="l04162"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b9e5b00171ea739ba67a627a2484f47"> 4162</a></span> <span class="preprocessor">#define FSMC_BCR2_MWID ((uint32_t)0x00000030) </span></div>
|
|
<div class="line"><a name="l04163"></a><span class="lineno"> 4163</span> <span class="preprocessor">#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) </span></div>
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|
<div class="line"><a name="l04164"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4099746e30f71a98ea71d1048a5d028a"> 4164</a></span> <span class="preprocessor">#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) </span></div>
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|
<div class="line"><a name="l04166"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74276c5828d545cf4b2db2d568c60627"> 4166</a></span> <span class="preprocessor">#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) </span></div>
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|
<div class="line"><a name="l04167"></a><span class="lineno"> 4167</span> <span class="preprocessor">#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) </span></div>
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|
<div class="line"><a name="l04168"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a4e1ad30533ab54b45987cab30d51a0"> 4168</a></span> <span class="preprocessor">#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) </span></div>
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|
<div class="line"><a name="l04169"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d8202b9b40d3912a6294fe2a0e28ebf"> 4169</a></span> <span class="preprocessor">#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) </span></div>
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|
<div class="line"><a name="l04170"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0f59e7aa2664f9c767ce22bec369698"> 4170</a></span> <span class="preprocessor">#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) </span></div>
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|
<div class="line"><a name="l04171"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9e93e4e902a636d4d75a1fd7e884afea"> 4171</a></span> <span class="preprocessor">#define FSMC_BCR2_WREN ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l04172"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5141640b4dcb78a524740b681819f9f1"> 4172</a></span> <span class="preprocessor">#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l04173"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad446f2fcb7909b80a8c1731141be5186"> 4173</a></span> <span class="preprocessor">#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l04174"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad015d2aa1c58b48681f35a4f92eaf7f7"> 4174</a></span> <span class="preprocessor">#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l04175"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76d3e5d899ba2399d3318da577d58ac6"> 4175</a></span> <span class="preprocessor">#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l04177"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae64b1874f1ab83a1d0224cb66e504dff"> 4177</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FSMC_BCR3 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l04178"></a><span class="lineno"> 4178</span> <span class="preprocessor">#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l04179"></a><span class="lineno"> 4179</span> <span class="preprocessor">#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l04181"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadaae648c8591e7650cba828910638d3d"> 4181</a></span> <span class="preprocessor">#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) </span></div>
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<div class="line"><a name="l04182"></a><span class="lineno"> 4182</span> <span class="preprocessor">#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l04183"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga319fb6069b651eb947b4d0ba3c9f6196"> 4183</a></span> <span class="preprocessor">#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l04185"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a038553e3a30df4b6e331cad504069b"> 4185</a></span> <span class="preprocessor">#define FSMC_BCR3_MWID ((uint32_t)0x00000030) </span></div>
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<div class="line"><a name="l04186"></a><span class="lineno"> 4186</span> <span class="preprocessor">#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l04187"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51097cfe8d4263a30d292e7e9dc73cd2"> 4187</a></span> <span class="preprocessor">#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l04189"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43c7292c185269cc11d986f3ae0ceb24"> 4189</a></span> <span class="preprocessor">#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l04190"></a><span class="lineno"> 4190</span> <span class="preprocessor">#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l04191"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga380c39b95426ac9a18c70e3f56016c81"> 4191</a></span> <span class="preprocessor">#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l04192"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9badf60f5caa010e041d66d40af596a"> 4192</a></span> <span class="preprocessor">#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l04193"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabbca3d0aa315f3e9bc6bacf244bdb747"> 4193</a></span> <span class="preprocessor">#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l04194"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44fc6e205695d39b63c0f5b18c3cd214"> 4194</a></span> <span class="preprocessor">#define FSMC_BCR3_WREN ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l04195"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab845515c37adae28d0e1452596cca7ea"> 4195</a></span> <span class="preprocessor">#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l04196"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22c9b0145aa62cafd915a4c7da1931b5"> 4196</a></span> <span class="preprocessor">#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l04197"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9665b36b791862c464f07ad49dea315c"> 4197</a></span> <span class="preprocessor">#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l04198"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ab23550b17dca7ede57f8b5ef05f2e7"> 4198</a></span> <span class="preprocessor">#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l04200"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70c6da37696af84767f82efd0df3a7da"> 4200</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FSMC_BCR4 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l04201"></a><span class="lineno"> 4201</span> <span class="preprocessor">#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l04202"></a><span class="lineno"> 4202</span> <span class="preprocessor">#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l04204"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga92d644d34b59762d0b48f7784d3aed4b"> 4204</a></span> <span class="preprocessor">#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) </span></div>
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<div class="line"><a name="l04205"></a><span class="lineno"> 4205</span> <span class="preprocessor">#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l04206"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f9bf2c236b772e76174aff4388a1b6f"> 4206</a></span> <span class="preprocessor">#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l04208"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac5abffefdc124215182346aba701183"> 4208</a></span> <span class="preprocessor">#define FSMC_BCR4_MWID ((uint32_t)0x00000030) </span></div>
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<div class="line"><a name="l04209"></a><span class="lineno"> 4209</span> <span class="preprocessor">#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l04210"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c4ce32ca454c42344cfe73f71abd274"> 4210</a></span> <span class="preprocessor">#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l04212"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5cd3a31190eb0cea8a72b55d8369970"> 4212</a></span> <span class="preprocessor">#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l04213"></a><span class="lineno"> 4213</span> <span class="preprocessor">#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l04214"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf769d7958a8c610ccca912600e61f30"> 4214</a></span> <span class="preprocessor">#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l04215"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c6ffdcee5dc3de1402bd8b644d6ecf4"> 4215</a></span> <span class="preprocessor">#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l04216"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga485976f8857949064d060374031cad3d"> 4216</a></span> <span class="preprocessor">#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l04217"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa35333cfffc35c7948ee0aa0e5672c3c"> 4217</a></span> <span class="preprocessor">#define FSMC_BCR4_WREN ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l04218"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11c35ab0ee9ee23a5352218b4b84a258"> 4218</a></span> <span class="preprocessor">#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l04219"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf2eef4eb8e6bb99cace5145b6ad09ee"> 4219</a></span> <span class="preprocessor">#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l04220"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga458727d27c2bc7cede05f6537bfc1bd8"> 4220</a></span> <span class="preprocessor">#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l04221"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6794966a05855913923294f5c2ab69ed"> 4221</a></span> <span class="preprocessor">#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l04223"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19293300b8230e38afa1c16c526b3f29"> 4223</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FSMC_BTR1 register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l04224"></a><span class="lineno"> 4224</span> <span class="preprocessor">#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) </span></div>
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<div class="line"><a name="l04225"></a><span class="lineno"> 4225</span> <span class="preprocessor">#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l04226"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab457e5d3a33d80db3ad070b1cf57669a"> 4226</a></span> <span class="preprocessor">#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l04227"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae29ca17c63df62cc12c06e6cfa3429e3"> 4227</a></span> <span class="preprocessor">#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l04228"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaefb98ce348ba665f122e44ddc0390b45"> 4228</a></span> <span class="preprocessor">#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l04230"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f0105afe671cd62730cf879072c80f3"> 4230</a></span> <span class="preprocessor">#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) </span></div>
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<div class="line"><a name="l04231"></a><span class="lineno"> 4231</span> <span class="preprocessor">#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l04232"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc4a3860c48a62ff0290622e1937072d"> 4232</a></span> <span class="preprocessor">#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l04233"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga222a16d5a1a8deebaf39a96d94d3c3f0"> 4233</a></span> <span class="preprocessor">#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l04234"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ad1f9164644c4ff4c6ae5a655478abc"> 4234</a></span> <span class="preprocessor">#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l04236"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e88e45163e76f529b5a94937526f45c"> 4236</a></span> <span class="preprocessor">#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) </span></div>
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<div class="line"><a name="l04237"></a><span class="lineno"> 4237</span> <span class="preprocessor">#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l04238"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae39175370a991b500962fd084230e389"> 4238</a></span> <span class="preprocessor">#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l04239"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4488a428f33d96263a00a30af42b849b"> 4239</a></span> <span class="preprocessor">#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l04240"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad53bd6a1decfafdb420a37453b3b5545"> 4240</a></span> <span class="preprocessor">#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l04242"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99638cc2cbe0dead029c201e5f30c3a8"> 4242</a></span> <span class="preprocessor">#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) </span></div>
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<div class="line"><a name="l04243"></a><span class="lineno"> 4243</span> <span class="preprocessor">#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l04244"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ec9346bbaf845f1dffe33c4a625c0ac"> 4244</a></span> <span class="preprocessor">#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l04245"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6c1578a85c4f2cef9e034c7b5da6d454"> 4245</a></span> <span class="preprocessor">#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l04246"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf873cbfe4827496215eb08bb33ae4784"> 4246</a></span> <span class="preprocessor">#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l04248"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3ecfd25fb64efb3745ee96b2877a017"> 4248</a></span> <span class="preprocessor">#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) </span></div>
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<div class="line"><a name="l04249"></a><span class="lineno"> 4249</span> <span class="preprocessor">#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l04250"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac7c4dbd43df84559e30a9c332b265ad5"> 4250</a></span> <span class="preprocessor">#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l04251"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe9c9e09de00afad666ace28c608032f"> 4251</a></span> <span class="preprocessor">#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l04252"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafffebd7a0cf6e6d80b65804c2c50ce62"> 4252</a></span> <span class="preprocessor">#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l04254"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68a146aec5d723a84945ae6da6c0692f"> 4254</a></span> <span class="preprocessor">#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) </span></div>
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<div class="line"><a name="l04255"></a><span class="lineno"> 4255</span> <span class="preprocessor">#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l04256"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ef6dcccdb11a1b094966be0c019124b"> 4256</a></span> <span class="preprocessor">#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l04257"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2d832593697ba108d99a97e4fdfd159"> 4257</a></span> <span class="preprocessor">#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l04258"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a7e4efc546c1c9d16c750a4542e1c55"> 4258</a></span> <span class="preprocessor">#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l04260"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b42f22fc488e0ed0d06832118773123"> 4260</a></span> <span class="preprocessor">#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) </span></div>
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<div class="line"><a name="l04261"></a><span class="lineno"> 4261</span> <span class="preprocessor">#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l04262"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga027548b6b5971a2c56558932c956fa4c"> 4262</a></span> <span class="preprocessor">#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l04264"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b336cf3ae23cfda19895927b63af558"> 4264</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FSMC_BTR2 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l04265"></a><span class="lineno"> 4265</span> <span class="preprocessor">#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) </span></div>
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<div class="line"><a name="l04266"></a><span class="lineno"> 4266</span> <span class="preprocessor">#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l04267"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23697810b99730ddf52834a5066c1ba5"> 4267</a></span> <span class="preprocessor">#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l04268"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga827398dc098f2d08bb77a04b2e7d6ba3"> 4268</a></span> <span class="preprocessor">#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l04269"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b40f47f2db0db78de6fe2df58b5d591"> 4269</a></span> <span class="preprocessor">#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l04271"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbd4d42459a990825b61962d9118cd7b"> 4271</a></span> <span class="preprocessor">#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) </span></div>
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<div class="line"><a name="l04272"></a><span class="lineno"> 4272</span> <span class="preprocessor">#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l04273"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac37c974d0260ba1dbd1acaf6fceb425c"> 4273</a></span> <span class="preprocessor">#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l04274"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabbf56fc3a549d1e68d56e1587123bd27"> 4274</a></span> <span class="preprocessor">#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l04275"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b7d19f02444ce8b3286d44258c6caef"> 4275</a></span> <span class="preprocessor">#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l04277"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc538e46145ed4947194f3ad63e211b7"> 4277</a></span> <span class="preprocessor">#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) </span></div>
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<div class="line"><a name="l04278"></a><span class="lineno"> 4278</span> <span class="preprocessor">#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l04279"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe1d3fe096ea53ea073b78bd6ddbff58"> 4279</a></span> <span class="preprocessor">#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l04280"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa066dab45a22ebd3a7102b92dcd251bd"> 4280</a></span> <span class="preprocessor">#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l04281"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga68c15ca5fdd13efb5499f0e86bd5bc88"> 4281</a></span> <span class="preprocessor">#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l04283"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga874499b29d2b72a75265f16a2d8ed834"> 4283</a></span> <span class="preprocessor">#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) </span></div>
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<div class="line"><a name="l04284"></a><span class="lineno"> 4284</span> <span class="preprocessor">#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l04285"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ae7c94522af51d2f96a0fa715dfa9b0"> 4285</a></span> <span class="preprocessor">#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l04286"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2617a99e5eab8b31ff168557f93852a3"> 4286</a></span> <span class="preprocessor">#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l04287"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83871fa5cde9d72ec840d29d43aa2e57"> 4287</a></span> <span class="preprocessor">#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l04289"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66ad543195f36fdb3efdf7550381f982"> 4289</a></span> <span class="preprocessor">#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) </span></div>
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<div class="line"><a name="l04290"></a><span class="lineno"> 4290</span> <span class="preprocessor">#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l04291"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37fdb25c494cf314cb680f84c5e0a503"> 4291</a></span> <span class="preprocessor">#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l04292"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ac8729c8ac330f6ade93a6a15a4ba70"> 4292</a></span> <span class="preprocessor">#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l04293"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31920e8bf2d83ad3c2849f8e942bb6e4"> 4293</a></span> <span class="preprocessor">#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l04295"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga453c2a90dc3340596c9d34672cede6a0"> 4295</a></span> <span class="preprocessor">#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) </span></div>
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<div class="line"><a name="l04296"></a><span class="lineno"> 4296</span> <span class="preprocessor">#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l04297"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3247db1653b31df0c34ab7898400bb5"> 4297</a></span> <span class="preprocessor">#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l04298"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0510047c932d2833f6cbe0a4a5d7b9b5"> 4298</a></span> <span class="preprocessor">#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l04299"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e1852b706b3c719c0eab8ef863b39e0"> 4299</a></span> <span class="preprocessor">#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l04301"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99389b63c4dee3c54aa1de36a4119add"> 4301</a></span> <span class="preprocessor">#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) </span></div>
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<div class="line"><a name="l04302"></a><span class="lineno"> 4302</span> <span class="preprocessor">#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l04303"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07b93600977cde6e31a9464f87606043"> 4303</a></span> <span class="preprocessor">#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l04305"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad200e1dc2d1835e3dc0fa8f0483eb2c0"> 4305</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for FSMC_BTR3 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l04306"></a><span class="lineno"> 4306</span> <span class="preprocessor">#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) </span></div>
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<div class="line"><a name="l04307"></a><span class="lineno"> 4307</span> <span class="preprocessor">#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l04308"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3e55daf436a25fadae7384611aa0f89"> 4308</a></span> <span class="preprocessor">#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l04309"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab6a21211dd7a3445e944af0fe1a4b600"> 4309</a></span> <span class="preprocessor">#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l04310"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51c23d36fa8e7e38048d94830bf0f74f"> 4310</a></span> <span class="preprocessor">#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l04312"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab01cf0b1c88857669d10fee8d7ba4d85"> 4312</a></span> <span class="preprocessor">#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) </span></div>
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<div class="line"><a name="l04313"></a><span class="lineno"> 4313</span> <span class="preprocessor">#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l04314"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7833ee760b2400e6fb483b1d83cbdff3"> 4314</a></span> <span class="preprocessor">#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l04315"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad417ccae1c4018d0ff5c76c942aeb2ca"> 4315</a></span> <span class="preprocessor">#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l04316"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60d0ae6af13ef088367cef06c7f207d3"> 4316</a></span> <span class="preprocessor">#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l04318"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b6aab5907bc42e140ca5a4d60fcd64c"> 4318</a></span> <span class="preprocessor">#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) </span></div>
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<div class="line"><a name="l04319"></a><span class="lineno"> 4319</span> <span class="preprocessor">#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l04320"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e9ac671a510ee06e86c41d7876ffe10"> 4320</a></span> <span class="preprocessor">#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l04321"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65fe87d29c1a4ee0b08014ed8e0423e1"> 4321</a></span> <span class="preprocessor">#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l04322"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad33e3df5c80255cb5e11ba427e9c224f"> 4322</a></span> <span class="preprocessor">#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l04324"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad220fbd264261a37eac09d4f6c0b79a2"> 4324</a></span> <span class="preprocessor">#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) </span></div>
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<div class="line"><a name="l04325"></a><span class="lineno"> 4325</span> <span class="preprocessor">#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l04326"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8a3ad9f940c6942682d8d97b1eb0ca4"> 4326</a></span> <span class="preprocessor">#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l04327"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga739f2db66e52626aa9a5ee02c11d7a34"> 4327</a></span> <span class="preprocessor">#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l04328"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e4c4102ea6e6cf2082e78168edfc18e"> 4328</a></span> <span class="preprocessor">#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l04330"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf61e23804e0fa3ca45f851ca98de371"> 4330</a></span> <span class="preprocessor">#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) </span></div>
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<div class="line"><a name="l04331"></a><span class="lineno"> 4331</span> <span class="preprocessor">#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l04332"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47a8d8e279c50995143ecf4124580703"> 4332</a></span> <span class="preprocessor">#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l04333"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd9c93b0ee64856981394a63d6a3a964"> 4333</a></span> <span class="preprocessor">#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l04334"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98fa7611b4ae197ab25cdf1cae9f8ee1"> 4334</a></span> <span class="preprocessor">#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l04336"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa9bf0683d046f9bcfb0d55a065ae69ab"> 4336</a></span> <span class="preprocessor">#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) </span></div>
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<div class="line"><a name="l04337"></a><span class="lineno"> 4337</span> <span class="preprocessor">#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l04338"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa88a80458ddd56b0dfa7cf3599b986dd"> 4338</a></span> <span class="preprocessor">#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l04339"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga655083fdb0e563b9a4d6ea589194ba02"> 4339</a></span> <span class="preprocessor">#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l04340"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga486280713c8f07d7033bce4e74825130"> 4340</a></span> <span class="preprocessor">#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l04342"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac7e7da5269a2dac164c9d1d01da2bc28"> 4342</a></span> <span class="preprocessor">#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) </span></div>
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<div class="line"><a name="l04343"></a><span class="lineno"> 4343</span> <span class="preprocessor">#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l04344"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56c8f213e437ceed2140f2c16a0416cd"> 4344</a></span> <span class="preprocessor">#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l04346"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8bbfd5e08b73d1c5de53ee0ff0ddb9a"> 4346</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FSMC_BTR4 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l04347"></a><span class="lineno"> 4347</span> <span class="preprocessor">#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) </span></div>
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<div class="line"><a name="l04348"></a><span class="lineno"> 4348</span> <span class="preprocessor">#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l04349"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab44cc2146b4cf6bc8f43292512fd8cf8"> 4349</a></span> <span class="preprocessor">#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l04350"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0ee1ab3716b0ab1a4e7b51234af7c63"> 4350</a></span> <span class="preprocessor">#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l04351"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd427c001c5b17a3e083c81f6b228a50"> 4351</a></span> <span class="preprocessor">#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l04353"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f8ab4a1c7fe6e7dc2b093add88c274e"> 4353</a></span> <span class="preprocessor">#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) </span></div>
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<div class="line"><a name="l04354"></a><span class="lineno"> 4354</span> <span class="preprocessor">#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l04355"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e52ae9a5d59507bdf9f4f9da19444ed"> 4355</a></span> <span class="preprocessor">#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l04356"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf6200f13c3eed1e9646750897a987a2"> 4356</a></span> <span class="preprocessor">#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l04357"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0803bc2ad60138e0eef53a53ca5bf537"> 4357</a></span> <span class="preprocessor">#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l04359"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga75c73d4bb0ddcac383ca610a604d95b3"> 4359</a></span> <span class="preprocessor">#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) </span></div>
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<div class="line"><a name="l04360"></a><span class="lineno"> 4360</span> <span class="preprocessor">#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l04361"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c28625ee031527a29f7cb7db1bb97cf"> 4361</a></span> <span class="preprocessor">#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l04362"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabdb0212604c6c58c9524adc7931e2897"> 4362</a></span> <span class="preprocessor">#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l04363"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2353d753ca5532703b4f822b7d2a7382"> 4363</a></span> <span class="preprocessor">#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l04365"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e0860f92bb204c4b5902d3e34b8b30a"> 4365</a></span> <span class="preprocessor">#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) </span></div>
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<div class="line"><a name="l04366"></a><span class="lineno"> 4366</span> <span class="preprocessor">#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l04367"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga207a9eedfc1b244c393be3c34ea60a15"> 4367</a></span> <span class="preprocessor">#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l04368"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4dec1fa50fca6639be7179d445aacfe4"> 4368</a></span> <span class="preprocessor">#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l04369"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab1db211382068251dc5cfe44a175e639"> 4369</a></span> <span class="preprocessor">#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l04371"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbfd74790a1e25339151de440e3a93e5"> 4371</a></span> <span class="preprocessor">#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) </span></div>
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<div class="line"><a name="l04372"></a><span class="lineno"> 4372</span> <span class="preprocessor">#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l04373"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ac39964e3792653e454538407b11504"> 4373</a></span> <span class="preprocessor">#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l04374"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaacee394c98ac568fe1d6df61c887ed53"> 4374</a></span> <span class="preprocessor">#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l04375"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c7cd1d1a4954d494bd107400925f86f"> 4375</a></span> <span class="preprocessor">#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l04377"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga931463443390c5a706303e87a538d1ce"> 4377</a></span> <span class="preprocessor">#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) </span></div>
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<div class="line"><a name="l04378"></a><span class="lineno"> 4378</span> <span class="preprocessor">#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l04379"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa53cb7c299e794915d3aba803374adca"> 4379</a></span> <span class="preprocessor">#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l04380"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2315f17d1cd7dd9da1b0ee2f7e4ea29"> 4380</a></span> <span class="preprocessor">#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l04381"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga808a7d758e6ca75c573d08ee92228745"> 4381</a></span> <span class="preprocessor">#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l04383"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadfc558894dcb263451dbac13f48fffe1"> 4383</a></span> <span class="preprocessor">#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) </span></div>
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<div class="line"><a name="l04384"></a><span class="lineno"> 4384</span> <span class="preprocessor">#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l04385"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabbf731d99007936586f9e15f17c3c771"> 4385</a></span> <span class="preprocessor">#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l04387"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e486b11f6af0f566f8843a5c95c6a6c"> 4387</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FSMC_BWTR1 register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l04388"></a><span class="lineno"> 4388</span> <span class="preprocessor">#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) </span></div>
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<div class="line"><a name="l04389"></a><span class="lineno"> 4389</span> <span class="preprocessor">#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l04390"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4aa5ee153cb4bf79f0d4ae2c47f365c4"> 4390</a></span> <span class="preprocessor">#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l04391"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaacb80aeedb6d0d9cb09e7b4d3ff8b541"> 4391</a></span> <span class="preprocessor">#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l04392"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20dbbdff1e2f1d57727dabbc4b03c840"> 4392</a></span> <span class="preprocessor">#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l04394"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e2bc67999e8d2b63771fa223ffa8e4d"> 4394</a></span> <span class="preprocessor">#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) </span></div>
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<div class="line"><a name="l04395"></a><span class="lineno"> 4395</span> <span class="preprocessor">#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l04396"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa3d8ff62f87ab6aeb5170dd67de15cf"> 4396</a></span> <span class="preprocessor">#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l04397"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e24880c23375636d7504d42077a400a"> 4397</a></span> <span class="preprocessor">#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l04398"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb90dec93198b1d3077feb5fe508f004"> 4398</a></span> <span class="preprocessor">#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l04400"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4a961ecd844e14a90d1b2f6c5d59196"> 4400</a></span> <span class="preprocessor">#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) </span></div>
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<div class="line"><a name="l04401"></a><span class="lineno"> 4401</span> <span class="preprocessor">#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l04402"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee2641a6f415d03df324667662bd3dcf"> 4402</a></span> <span class="preprocessor">#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l04403"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga162800452847dd98d27a4078370518b2"> 4403</a></span> <span class="preprocessor">#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l04404"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16476bfbbcb9726c1fbc593d3568a514"> 4404</a></span> <span class="preprocessor">#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l04406"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade0627f53e3df25fdaa973db6159bd70"> 4406</a></span> <span class="preprocessor">#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) </span></div>
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<div class="line"><a name="l04407"></a><span class="lineno"> 4407</span> <span class="preprocessor">#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l04408"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacab3c524b3e47327b24fa560feb93487"> 4408</a></span> <span class="preprocessor">#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l04409"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa16b4376e693343cf65ab05808398b7f"> 4409</a></span> <span class="preprocessor">#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l04410"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga632860254f0019e87c2e73c872d8d0c3"> 4410</a></span> <span class="preprocessor">#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l04412"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga67c483e37ed994b71337a0e0777c1290"> 4412</a></span> <span class="preprocessor">#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) </span></div>
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<div class="line"><a name="l04413"></a><span class="lineno"> 4413</span> <span class="preprocessor">#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l04414"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f05e337758cdb98cfc833e43bd6d674"> 4414</a></span> <span class="preprocessor">#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l04415"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd6a7a7678ef3afbbed587cf318d1540"> 4415</a></span> <span class="preprocessor">#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l04416"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga515ba99da829728fa7128161786c933d"> 4416</a></span> <span class="preprocessor">#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l04418"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3af303f1131ff3de0894ec908de252c4"> 4418</a></span> <span class="preprocessor">#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) </span></div>
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<div class="line"><a name="l04419"></a><span class="lineno"> 4419</span> <span class="preprocessor">#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l04420"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa676b8e4f48602c27ea8edab61ce5db0"> 4420</a></span> <span class="preprocessor">#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l04422"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac0cddde5db2e0bb09f1c8938afd6ac98"> 4422</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FSMC_BWTR2 register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l04423"></a><span class="lineno"> 4423</span> <span class="preprocessor">#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) </span></div>
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<div class="line"><a name="l04424"></a><span class="lineno"> 4424</span> <span class="preprocessor">#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l04425"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b6553bd9ad305aa42341e08b1736260"> 4425</a></span> <span class="preprocessor">#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l04426"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga593fe1987e8c6052cdb992e629f1d059"> 4426</a></span> <span class="preprocessor">#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l04427"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6dc23a2314a44b6ad9f293716f0c8a11"> 4427</a></span> <span class="preprocessor">#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l04429"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95abc246eb528275d894346c0665e930"> 4429</a></span> <span class="preprocessor">#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) </span></div>
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<div class="line"><a name="l04430"></a><span class="lineno"> 4430</span> <span class="preprocessor">#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l04431"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae879db1879650f99b1c75635884bda17"> 4431</a></span> <span class="preprocessor">#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l04432"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5826c5d5c544cd59210c071358fb8e9"> 4432</a></span> <span class="preprocessor">#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l04433"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga258acf47f7706a1cd0b0a914e63cbe17"> 4433</a></span> <span class="preprocessor">#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l04435"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81de376a21fc25a7e1c31db341dfcd3f"> 4435</a></span> <span class="preprocessor">#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) </span></div>
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<div class="line"><a name="l04436"></a><span class="lineno"> 4436</span> <span class="preprocessor">#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l04437"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab280652524006fbb3820597112136f14"> 4437</a></span> <span class="preprocessor">#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l04438"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78a0f0466162848135313296ebf44890"> 4438</a></span> <span class="preprocessor">#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l04439"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51e43e17e99141c9009c779cc359323a"> 4439</a></span> <span class="preprocessor">#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l04441"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a2a5797dd14b5b89581c5fb08872fae"> 4441</a></span> <span class="preprocessor">#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) </span></div>
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<div class="line"><a name="l04442"></a><span class="lineno"> 4442</span> <span class="preprocessor">#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l04443"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf62bb3c772353b551de22915814115b6"> 4443</a></span> <span class="preprocessor">#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l04444"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d5aaffe4b4c549b247c31dead5585c6"> 4444</a></span> <span class="preprocessor">#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l04445"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6caca8a04c9768a84bcd958656ea8209"> 4445</a></span> <span class="preprocessor">#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l04447"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3cb607738f2c3aa4dae4990d0754f73"> 4447</a></span> <span class="preprocessor">#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) </span></div>
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<div class="line"><a name="l04448"></a><span class="lineno"> 4448</span> <span class="preprocessor">#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l04449"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f04b7ebcecadd4b515cac94159ea8d3"> 4449</a></span> <span class="preprocessor">#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l04450"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac5b453a7316f378f6bf222d5de5b515"> 4450</a></span> <span class="preprocessor">#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l04451"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f5e6363ecbd1c23b1f49a9cfb3301d2"> 4451</a></span> <span class="preprocessor">#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l04453"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9984c8161469dd0922de2d8c4cd9dbe5"> 4453</a></span> <span class="preprocessor">#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) </span></div>
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<div class="line"><a name="l04454"></a><span class="lineno"> 4454</span> <span class="preprocessor">#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l04455"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga320be3e2e266dc25bd02e10787b2ba0d"> 4455</a></span> <span class="preprocessor">#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l04457"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab6cdd284ad94abfef0f24fcb813b4558"> 4457</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FSMC_BWTR3 register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l04458"></a><span class="lineno"> 4458</span> <span class="preprocessor">#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) </span></div>
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<div class="line"><a name="l04459"></a><span class="lineno"> 4459</span> <span class="preprocessor">#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l04460"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga455ba53d0f18173b0694d71757a084ff"> 4460</a></span> <span class="preprocessor">#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l04461"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9dddd5ba924b56867c9cb39484ef498d"> 4461</a></span> <span class="preprocessor">#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l04462"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd242d768da1f9ab4304e91e5dabb5a9"> 4462</a></span> <span class="preprocessor">#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l04464"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga471ebb2d47fb951340df6ba22b40a788"> 4464</a></span> <span class="preprocessor">#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) </span></div>
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<div class="line"><a name="l04465"></a><span class="lineno"> 4465</span> <span class="preprocessor">#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l04466"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae3d031a0d71677932a68639ba88bd13e"> 4466</a></span> <span class="preprocessor">#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l04467"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b3948c407a5a4be6a21cccad0a8d12d"> 4467</a></span> <span class="preprocessor">#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l04468"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea21d05228f7771c6306726af5da5a4a"> 4468</a></span> <span class="preprocessor">#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l04470"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae8216cf865785468af58dbce0002a7c"> 4470</a></span> <span class="preprocessor">#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) </span></div>
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<div class="line"><a name="l04471"></a><span class="lineno"> 4471</span> <span class="preprocessor">#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l04472"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae93d9fee8a67491918526019b439a00f"> 4472</a></span> <span class="preprocessor">#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l04473"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1ec40c6360faeb133cb224a6789bb51"> 4473</a></span> <span class="preprocessor">#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l04474"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacaf23316e44d731620f0cbde29ae9a93"> 4474</a></span> <span class="preprocessor">#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l04476"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a291f74abf021a7fe66ce8afd714c39"> 4476</a></span> <span class="preprocessor">#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) </span></div>
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<div class="line"><a name="l04477"></a><span class="lineno"> 4477</span> <span class="preprocessor">#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l04478"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a270daf60bba0a4a9de6607635b0264"> 4478</a></span> <span class="preprocessor">#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l04479"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab0e2f5c1eb92f5dba7c2d76b6267805a"> 4479</a></span> <span class="preprocessor">#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l04480"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad909c7569c4740c823bf4b31f93d4edb"> 4480</a></span> <span class="preprocessor">#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l04482"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56fbdeda5582325eb5eea0061209adc9"> 4482</a></span> <span class="preprocessor">#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) </span></div>
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<div class="line"><a name="l04483"></a><span class="lineno"> 4483</span> <span class="preprocessor">#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l04484"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05b769f726e31038cfa6bf4897453088"> 4484</a></span> <span class="preprocessor">#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l04485"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga900f347cf4b9debe88252ff1d453098e"> 4485</a></span> <span class="preprocessor">#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l04486"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb44640d0ccf25b8c8ec4b24b3600d26"> 4486</a></span> <span class="preprocessor">#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l04488"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga974cf9ed84e54c78ee995b02cc605706"> 4488</a></span> <span class="preprocessor">#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) </span></div>
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<div class="line"><a name="l04489"></a><span class="lineno"> 4489</span> <span class="preprocessor">#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l04490"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa32a792c0c93d854a90bfbc36fa1329b"> 4490</a></span> <span class="preprocessor">#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l04492"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada733b2bda718299345fd0191b25b49f"> 4492</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FSMC_BWTR4 register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l04493"></a><span class="lineno"> 4493</span> <span class="preprocessor">#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) </span></div>
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<div class="line"><a name="l04494"></a><span class="lineno"> 4494</span> <span class="preprocessor">#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l04495"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa8c3c14faf87768beced4e297edc7bfd"> 4495</a></span> <span class="preprocessor">#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l04496"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65ba73495f6192e409cc00f3e26e27e0"> 4496</a></span> <span class="preprocessor">#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l04497"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3cc9fa3c1ceae0724f5005bb1e101775"> 4497</a></span> <span class="preprocessor">#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l04499"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabcde23639f64241d95b02f5b950ef3cc"> 4499</a></span> <span class="preprocessor">#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) </span></div>
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<div class="line"><a name="l04500"></a><span class="lineno"> 4500</span> <span class="preprocessor">#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l04501"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaafe1198e70d843c883260d354b7ce7b5"> 4501</a></span> <span class="preprocessor">#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l04502"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac62786f538820baa3f0f8edb17ef1b74"> 4502</a></span> <span class="preprocessor">#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l04503"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa69aa2d9cafe8f952721c88083c8a94e"> 4503</a></span> <span class="preprocessor">#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l04505"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac744bdeb5b9ae048b1fa1a07ce9ce9d1"> 4505</a></span> <span class="preprocessor">#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) </span></div>
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<div class="line"><a name="l04506"></a><span class="lineno"> 4506</span> <span class="preprocessor">#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l04507"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6656c89aac87fc226c0e80f8f753abeb"> 4507</a></span> <span class="preprocessor">#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l04508"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5636aaec144530e1c46e819b62c95f09"> 4508</a></span> <span class="preprocessor">#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l04509"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19eb9fccff444a00caf75b9d20a143ed"> 4509</a></span> <span class="preprocessor">#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l04511"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa173c5ff9a7d316cd67897f8e36dbf5"> 4511</a></span> <span class="preprocessor">#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) </span></div>
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<div class="line"><a name="l04512"></a><span class="lineno"> 4512</span> <span class="preprocessor">#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l04513"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace3c57c780586c96ef5756d642c3bd01"> 4513</a></span> <span class="preprocessor">#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l04514"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8eae837a65cdce995c6fc43afd196e76"> 4514</a></span> <span class="preprocessor">#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l04515"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga265d50716e1b6ae2395f0da696b4d12a"> 4515</a></span> <span class="preprocessor">#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l04517"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11d5deb7f2aed21baeb4df3015440bc2"> 4517</a></span> <span class="preprocessor">#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) </span></div>
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<div class="line"><a name="l04518"></a><span class="lineno"> 4518</span> <span class="preprocessor">#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l04519"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6f7e16866ecede5f4258c05d95f571b"> 4519</a></span> <span class="preprocessor">#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l04520"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9841723700d2b9611be2e7a7b0f19c33"> 4520</a></span> <span class="preprocessor">#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l04521"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad628c523ceee80e41c02dd4502baee2c"> 4521</a></span> <span class="preprocessor">#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l04523"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1020e605f8a52d9fd857d3b91d23bf7a"> 4523</a></span> <span class="preprocessor">#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) </span></div>
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<div class="line"><a name="l04524"></a><span class="lineno"> 4524</span> <span class="preprocessor">#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l04525"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d13f46a945d5daf6ec339781d3926a9"> 4525</a></span> <span class="preprocessor">#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l04527"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf7ba26fb09f035addbe1e4c3b0d093c9"> 4527</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FSMC_PCR2 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l04528"></a><span class="lineno"> 4528</span> <span class="preprocessor">#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l04529"></a><span class="lineno"> 4529</span> <span class="preprocessor">#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l04530"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26f3ae80c9bbede6929c20004804476d"> 4530</a></span> <span class="preprocessor">#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l04532"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga175ab8f61bbc0bb5692fb62691db1ce3"> 4532</a></span> <span class="preprocessor">#define FSMC_PCR2_PWID ((uint32_t)0x00000030) </span></div>
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<div class="line"><a name="l04533"></a><span class="lineno"> 4533</span> <span class="preprocessor">#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l04534"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga656155275dc1c2f690687d07717e017a"> 4534</a></span> <span class="preprocessor">#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l04536"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6180d3899a37f7e518b1e4b8bf935baa"> 4536</a></span> <span class="preprocessor">#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l04538"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa528d578aec8bc0f77a2550d4e48438"> 4538</a></span> <span class="preprocessor">#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) </span></div>
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<div class="line"><a name="l04539"></a><span class="lineno"> 4539</span> <span class="preprocessor">#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l04540"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4f2c6c5ed8cd459a0822c35ea9e6800"> 4540</a></span> <span class="preprocessor">#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l04541"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1edc7eec1b5a76a851175e5a7caa6c5c"> 4541</a></span> <span class="preprocessor">#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l04542"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf8baae9949bd0f294a698721da24808f"> 4542</a></span> <span class="preprocessor">#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l04544"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4999b81ed8783cca5f3b25500183ff9a"> 4544</a></span> <span class="preprocessor">#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) </span></div>
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<div class="line"><a name="l04545"></a><span class="lineno"> 4545</span> <span class="preprocessor">#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l04546"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6513b62e23afdbadc4b25697378a0f2"> 4546</a></span> <span class="preprocessor">#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l04547"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd7e456c24f5978e8cb1078c633f0d23"> 4547</a></span> <span class="preprocessor">#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l04548"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f0b2191750ab21af10f009e1a97ca13"> 4548</a></span> <span class="preprocessor">#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l04550"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c70f852bb8809e8ea4800a7dd616266"> 4550</a></span> <span class="preprocessor">#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) </span></div>
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<div class="line"><a name="l04551"></a><span class="lineno"> 4551</span> <span class="preprocessor">#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l04552"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2adbc7b4149193452b69bc55a968cd1"> 4552</a></span> <span class="preprocessor">#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l04553"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0e06e76b0dd7cc1f6b765b4c3ecfacb"> 4553</a></span> <span class="preprocessor">#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l04555"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga199db72eae8707aba0b22ff18bd8bcd0"> 4555</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FSMC_PCR3 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l04556"></a><span class="lineno"> 4556</span> <span class="preprocessor">#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l04557"></a><span class="lineno"> 4557</span> <span class="preprocessor">#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l04558"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae3f15324eb8692ddf3f294f358b1d8c"> 4558</a></span> <span class="preprocessor">#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l04560"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade562589d0572ba223d2f6df265fe5b8"> 4560</a></span> <span class="preprocessor">#define FSMC_PCR3_PWID ((uint32_t)0x00000030) </span></div>
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<div class="line"><a name="l04561"></a><span class="lineno"> 4561</span> <span class="preprocessor">#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l04562"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac6f9b4e4449f105aa9bd3630f0466b9f"> 4562</a></span> <span class="preprocessor">#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l04564"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa8819a742324c0523f3dc6b8959bcdd5"> 4564</a></span> <span class="preprocessor">#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l04566"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga723c4c8c3b97cd1ce18c3b5c888e5b4e"> 4566</a></span> <span class="preprocessor">#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) </span></div>
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<div class="line"><a name="l04567"></a><span class="lineno"> 4567</span> <span class="preprocessor">#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l04568"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga478e4371d8baf2a0b2675b3113edb071"> 4568</a></span> <span class="preprocessor">#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l04569"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadedb0d10b5b53656dc152b9264faffbd"> 4569</a></span> <span class="preprocessor">#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l04570"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5536285f03b1732aed999d20c0e25aa"> 4570</a></span> <span class="preprocessor">#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l04572"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63f96a640afa85d7521b05458f590a19"> 4572</a></span> <span class="preprocessor">#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) </span></div>
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<div class="line"><a name="l04573"></a><span class="lineno"> 4573</span> <span class="preprocessor">#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l04574"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga199c4b0e690f0da0de46e372183da642"> 4574</a></span> <span class="preprocessor">#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l04575"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada0f17bcc683a5a6249348a63004e225"> 4575</a></span> <span class="preprocessor">#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l04576"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4afb373f6f1cb1bedd653d8ea1dca78"> 4576</a></span> <span class="preprocessor">#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l04578"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4bd7aaf7ffcad9f4477ac4f2927a0912"> 4578</a></span> <span class="preprocessor">#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) </span></div>
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<div class="line"><a name="l04579"></a><span class="lineno"> 4579</span> <span class="preprocessor">#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) </span></div>
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|
<div class="line"><a name="l04580"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf8d92853ca6f97f72682c2f53f686998"> 4580</a></span> <span class="preprocessor">#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l04581"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga506daa911151e1b9de3ed2b5030d1a5a"> 4581</a></span> <span class="preprocessor">#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) </span></div>
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|
<div class="line"><a name="l04583"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf041e921fb9af07e9c709d79bbfaec89"> 4583</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FSMC_PCR4 register *******************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l04584"></a><span class="lineno"> 4584</span> <span class="preprocessor">#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) </span></div>
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|
<div class="line"><a name="l04585"></a><span class="lineno"> 4585</span> <span class="preprocessor">#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) </span></div>
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|
<div class="line"><a name="l04586"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab07ce7c785eb296a615b2c50415de21b"> 4586</a></span> <span class="preprocessor">#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) </span></div>
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|
<div class="line"><a name="l04588"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe2d6f4e9bdef35436d521ebbdca5e40"> 4588</a></span> <span class="preprocessor">#define FSMC_PCR4_PWID ((uint32_t)0x00000030) </span></div>
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|
<div class="line"><a name="l04589"></a><span class="lineno"> 4589</span> <span class="preprocessor">#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) </span></div>
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|
<div class="line"><a name="l04590"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9486b2b7346570ecc5715f1d551c168a"> 4590</a></span> <span class="preprocessor">#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) </span></div>
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|
<div class="line"><a name="l04592"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b6be32b3844a299a2c92089e81e27e9"> 4592</a></span> <span class="preprocessor">#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) </span></div>
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|
<div class="line"><a name="l04594"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga646509f8bebb0d662c730ed4cabe741f"> 4594</a></span> <span class="preprocessor">#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) </span></div>
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|
<div class="line"><a name="l04595"></a><span class="lineno"> 4595</span> <span class="preprocessor">#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) </span></div>
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|
<div class="line"><a name="l04596"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c7164974019263cacbc7dda2fc14126"> 4596</a></span> <span class="preprocessor">#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) </span></div>
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|
<div class="line"><a name="l04597"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0dd78ad0c755190a69b37ebac75a11dd"> 4597</a></span> <span class="preprocessor">#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) </span></div>
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|
<div class="line"><a name="l04598"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0ea2e2287999d3c7d6583aab492514d"> 4598</a></span> <span class="preprocessor">#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) </span></div>
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|
<div class="line"><a name="l04600"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0eb8dc60a469cfa96b3b3b7fad25ac92"> 4600</a></span> <span class="preprocessor">#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) </span></div>
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|
<div class="line"><a name="l04601"></a><span class="lineno"> 4601</span> <span class="preprocessor">#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) </span></div>
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|
<div class="line"><a name="l04602"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0c583f305906f19b15ce3dc177fa21bd"> 4602</a></span> <span class="preprocessor">#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) </span></div>
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|
<div class="line"><a name="l04603"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62fe4ede4c658b788596e8ea6f325c9f"> 4603</a></span> <span class="preprocessor">#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) </span></div>
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|
<div class="line"><a name="l04604"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a9958cbf815ac97c3500a46aaf573f5"> 4604</a></span> <span class="preprocessor">#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l04606"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad298ef64d36721696517ed0d4ac12d32"> 4606</a></span> <span class="preprocessor">#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) </span></div>
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|
<div class="line"><a name="l04607"></a><span class="lineno"> 4607</span> <span class="preprocessor">#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l04608"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2308baba97f307b8beb6239702471038"> 4608</a></span> <span class="preprocessor">#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l04609"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76514698225c0734c1e9be46b6dbd298"> 4609</a></span> <span class="preprocessor">#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l04611"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4ba96304e6618d4eb7672cdc3bd8f01"> 4611</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for FSMC_SR2 register *******************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l04612"></a><span class="lineno"> 4612</span> <span class="preprocessor">#define FSMC_SR2_IRS ((uint8_t)0x01) </span></div>
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<div class="line"><a name="l04613"></a><span class="lineno"> 4613</span> <span class="preprocessor">#define FSMC_SR2_ILS ((uint8_t)0x02) </span></div>
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|
<div class="line"><a name="l04614"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19f1b90b2da89b68aa754d0a89d60de9"> 4614</a></span> <span class="preprocessor">#define FSMC_SR2_IFS ((uint8_t)0x04) </span></div>
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<div class="line"><a name="l04615"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga664d6e1440c12e76dfa34f716af85ed1"> 4615</a></span> <span class="preprocessor">#define FSMC_SR2_IREN ((uint8_t)0x08) </span></div>
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<div class="line"><a name="l04616"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6492ad6afe175283d07de38978936dc"> 4616</a></span> <span class="preprocessor">#define FSMC_SR2_ILEN ((uint8_t)0x10) </span></div>
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<div class="line"><a name="l04617"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3216bd665a118239e6ef0b58ec5e8a8e"> 4617</a></span> <span class="preprocessor">#define FSMC_SR2_IFEN ((uint8_t)0x20) </span></div>
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<div class="line"><a name="l04618"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e9df0edd35d0ad6a35ff3a3b045b47c"> 4618</a></span> <span class="preprocessor">#define FSMC_SR2_FEMPT ((uint8_t)0x40) </span></div>
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<div class="line"><a name="l04620"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ae2e544a4a515303f49815cdbd5ebbb"> 4620</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for FSMC_SR3 register *******************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l04621"></a><span class="lineno"> 4621</span> <span class="preprocessor">#define FSMC_SR3_IRS ((uint8_t)0x01) </span></div>
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|
<div class="line"><a name="l04622"></a><span class="lineno"> 4622</span> <span class="preprocessor">#define FSMC_SR3_ILS ((uint8_t)0x02) </span></div>
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<div class="line"><a name="l04623"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad929e4a8c1fdb49ee6f690121336afea"> 4623</a></span> <span class="preprocessor">#define FSMC_SR3_IFS ((uint8_t)0x04) </span></div>
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|
<div class="line"><a name="l04624"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9803b4ab5b8cce213a80abc11c751d21"> 4624</a></span> <span class="preprocessor">#define FSMC_SR3_IREN ((uint8_t)0x08) </span></div>
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|
<div class="line"><a name="l04625"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafadff6b6f9e6430ada2f56bc9921dd7d"> 4625</a></span> <span class="preprocessor">#define FSMC_SR3_ILEN ((uint8_t)0x10) </span></div>
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<div class="line"><a name="l04626"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga12baad15533ecbc57db95ea4939bc782"> 4626</a></span> <span class="preprocessor">#define FSMC_SR3_IFEN ((uint8_t)0x20) </span></div>
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|
<div class="line"><a name="l04627"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86ac8f1f9f99c81a26fb54b597b57f12"> 4627</a></span> <span class="preprocessor">#define FSMC_SR3_FEMPT ((uint8_t)0x40) </span></div>
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<div class="line"><a name="l04629"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga230562cf231dc79cd9354933b39ae7de"> 4629</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for FSMC_SR4 register *******************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l04630"></a><span class="lineno"> 4630</span> <span class="preprocessor">#define FSMC_SR4_IRS ((uint8_t)0x01) </span></div>
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|
<div class="line"><a name="l04631"></a><span class="lineno"> 4631</span> <span class="preprocessor">#define FSMC_SR4_ILS ((uint8_t)0x02) </span></div>
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<div class="line"><a name="l04632"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga163f7143d51b516af0d46b142222957f"> 4632</a></span> <span class="preprocessor">#define FSMC_SR4_IFS ((uint8_t)0x04) </span></div>
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<div class="line"><a name="l04633"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e19feccd1553911d08be673c4af72ad"> 4633</a></span> <span class="preprocessor">#define FSMC_SR4_IREN ((uint8_t)0x08) </span></div>
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<div class="line"><a name="l04634"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1e7d71b32a0b70d772fbdc85f7053fc"> 4634</a></span> <span class="preprocessor">#define FSMC_SR4_ILEN ((uint8_t)0x10) </span></div>
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<div class="line"><a name="l04635"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f5f17d22e07bb6674cbd68740b9708a"> 4635</a></span> <span class="preprocessor">#define FSMC_SR4_IFEN ((uint8_t)0x20) </span></div>
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<div class="line"><a name="l04636"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9b8d7c7b68723a4ef01843d547d95bc"> 4636</a></span> <span class="preprocessor">#define FSMC_SR4_FEMPT ((uint8_t)0x40) </span></div>
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<div class="line"><a name="l04638"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae7081cdf26e75bccfac1b6a29c04124"> 4638</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FSMC_PMEM2 register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l04639"></a><span class="lineno"> 4639</span> <span class="preprocessor">#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) </span></div>
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<div class="line"><a name="l04640"></a><span class="lineno"> 4640</span> <span class="preprocessor">#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l04641"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga50a34195ddb7ab7aebc2acac39b27536"> 4641</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l04642"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga529858550113070878ce680da0a6bf7d"> 4642</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l04643"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga28517c1f5aeded21b3f0326247b0bbe1"> 4643</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l04644"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f59339df091ad8a00d75c32b335b711"> 4644</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l04645"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7715c089272c9709e8f94590b46be609"> 4645</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l04646"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31a0e44106c1ec87375054be15b1cb84"> 4646</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l04647"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga221edf50060c5dad91de3c0b877fdbfc"> 4647</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l04649"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae14181cbd85100c2b3b104525c42ee6c"> 4649</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) </span></div>
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<div class="line"><a name="l04650"></a><span class="lineno"> 4650</span> <span class="preprocessor">#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l04651"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7affee760cfe5d04a58bda9cd7fc5f72"> 4651</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l04652"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ee1c7f3347678dff204e6ac8c6eaf4f"> 4652</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l04653"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56de464fa3f895e75f0ec2ff3f9e1e1e"> 4653</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l04654"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga922a823292054746923fb13b8f4c1b5c"> 4654</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l04655"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44f9c0141f457b0ef0ff42c1645d7337"> 4655</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l04656"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d15645ffe422f3e35cc03efd93361cb"> 4656</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l04657"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga640d5866b22b11924b7e4c9bfc608624"> 4657</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l04659"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga127b0e01d15f1007cfa67247a99da26f"> 4659</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) </span></div>
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<div class="line"><a name="l04660"></a><span class="lineno"> 4660</span> <span class="preprocessor">#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l04661"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad2c79ef9df8b619e93c15b506f4fd7d"> 4661</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l04662"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd16a720c69fcac1f6b798cf6f9bbb7e"> 4662</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l04663"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4630e2bdb842914d0f7b53d4ed610122"> 4663</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l04664"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf699fd414971d0c52159c21652f5e58"> 4664</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l04665"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3e1f50389b82f8737a12ef6d1683c4f"> 4665</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l04666"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00c7b1a8cbcbcbcc0495ebd7c877ca9e"> 4666</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l04667"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9cd7c5637824522c2bd0f2cd165ca218"> 4667</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l04669"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1afae5788b827aebc3df92c74754b38"> 4669</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) </span></div>
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<div class="line"><a name="l04670"></a><span class="lineno"> 4670</span> <span class="preprocessor">#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l04671"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a7783e155a688bf79e68ebf570421c4"> 4671</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l04672"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8bb51ecefa94c1ab3b91c7a14705b8c8"> 4672</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l04673"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c0d8bf861d9918763b7391d4ad287b0"> 4673</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l04674"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaebd6a4457fa0ac4f1b98fdc58bef9999"> 4674</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l04675"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaded9a6b1b516fa2595988c84c5465f9b"> 4675</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l04676"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9b1831fb25422c7a126a7d029223394"> 4676</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l04677"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae828a4dde56e15f78ab156feeb329af9"> 4677</a></span> <span class="preprocessor">#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l04679"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c5ca1880a516478e1b8f1142066c004"> 4679</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FSMC_PMEM3 register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l04680"></a><span class="lineno"> 4680</span> <span class="preprocessor">#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) </span></div>
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<div class="line"><a name="l04681"></a><span class="lineno"> 4681</span> <span class="preprocessor">#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l04682"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf69ac574f9be3c11ada1e2dc4c3abe4f"> 4682</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l04683"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaee68bc7ff3e4cf11c2ca826541858c6a"> 4683</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l04684"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa10132605ec4a4be1ab48ee6b36080e"> 4684</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l04685"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd867b06de7c7a49244b6a35570d2cd2"> 4685</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l04686"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga292a8826723614aa2504a376f4a2e5d5"> 4686</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l04687"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98703fee6465ba580b052ef76f2c63f2"> 4687</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l04688"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaea28a64fc9a7e0df35826b4ec372361"> 4688</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l04690"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga702eeb8c3930ea564af728cc3bb9044b"> 4690</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) </span></div>
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<div class="line"><a name="l04691"></a><span class="lineno"> 4691</span> <span class="preprocessor">#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l04692"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4243cb8b53a10143621872c0d0ed318b"> 4692</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l04693"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30d8aad77f584d1c380b6d04d4984ac5"> 4693</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l04694"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaacf4638838e3cf2dfa076ef795596967"> 4694</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l04695"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1c65a1027062f3fff04dfdd24c33e64"> 4695</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l04696"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae23146168ddc8e06defd6e75390dde1d"> 4696</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l04697"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga79640d63c03f94bd4f38859c46bad820"> 4697</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l04698"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d36841fa1730bbbc825278cffd623f3"> 4698</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l04700"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f485579592b7fdf2e480523ee220418"> 4700</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) </span></div>
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<div class="line"><a name="l04701"></a><span class="lineno"> 4701</span> <span class="preprocessor">#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l04702"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8ef1e0f4db1e2792b0939f9058a149b"> 4702</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l04703"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa1abd4698bb45c784b23b8d431eb90f1"> 4703</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l04704"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a93e71d784bdb1cd115805feac42d6b"> 4704</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l04705"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20a5443b5236e71b8dfe0620abffbd68"> 4705</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l04706"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b330eabb266b26cf6aa93b12bfe7b38"> 4706</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l04707"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac6d1864268bb87124d127d92e8db54dc"> 4707</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l04708"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8968569a91c0b5d6c456074ddfc98aa3"> 4708</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l04710"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf0da29e1e300e47aebb0bd47bf5f0563"> 4710</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) </span></div>
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<div class="line"><a name="l04711"></a><span class="lineno"> 4711</span> <span class="preprocessor">#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l04712"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a77d54c66589f233792d30fc83e7f12"> 4712</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l04713"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d8453ab8a7488ff13c681154bfd293c"> 4713</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l04714"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf023951ad4fd31a691cc26fc3c27ec46"> 4714</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l04715"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf8d790834161e0224c878cd8eab190e"> 4715</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l04716"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26daeb039123824e2de5fdd64cb3a1ff"> 4716</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l04717"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafd06d96e44933ce665b2af8c2a4098e4"> 4717</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l04718"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef1254b2e2251da2b30aa297d1d0a1f8"> 4718</a></span> <span class="preprocessor">#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l04720"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7304d0d28edd32a70be474e656fbf8e"> 4720</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FSMC_PMEM4 register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l04721"></a><span class="lineno"> 4721</span> <span class="preprocessor">#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) </span></div>
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<div class="line"><a name="l04722"></a><span class="lineno"> 4722</span> <span class="preprocessor">#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l04723"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b5cb5385ce2cef772ee4493c25617aa"> 4723</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l04724"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6df1a1190522593b71da113c7ea8cfab"> 4724</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l04725"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6fa76a9c077f40e973df8fe6903c69c4"> 4725</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l04726"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga03ddc1ecb61313593976bf70aec06e9f"> 4726</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l04727"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4280253a6049c7739c6b70a6d7940998"> 4727</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l04728"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga153d7b557dc40b797f93bf5593808279"> 4728</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l04729"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc8fc6eadc2e952227c121b6d6114834"> 4729</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l04731"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04c68698ff6f47551244ae5a26893059"> 4731</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) </span></div>
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<div class="line"><a name="l04732"></a><span class="lineno"> 4732</span> <span class="preprocessor">#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l04733"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9673f81abf15ad70d09520db9ddfc58d"> 4733</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l04734"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c88b294c963e5be76da4bf3048af411"> 4734</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l04735"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga24d45891fa0a503d81f68f62f5fd18e5"> 4735</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l04736"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1fa35a7722b6339a7cef85b5be2280d"> 4736</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l04737"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga929f7f1066e3f2d69c72126615d06cb0"> 4737</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l04738"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5282e3d9205f778b67ef00c27beb2918"> 4738</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l04739"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1eed44a0b89a9f14b08c4ab2578ca5cc"> 4739</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l04741"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga247eb296ad16d1c7f2ebea0ca85619f9"> 4741</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) </span></div>
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<div class="line"><a name="l04742"></a><span class="lineno"> 4742</span> <span class="preprocessor">#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l04743"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5028f0c2a642b7faedf602f0b2c0d64c"> 4743</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l04744"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf07eef15a372886fda3182f49e2e912e"> 4744</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l04745"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa05a691ca81b6fe6df07adb1c5142597"> 4745</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l04746"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaafd4f50c33f4ec69e878983fb6065c73"> 4746</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l04747"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3cf67d6699d41fc042aed2be6d6aef0"> 4747</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l04748"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga963acb8aef1a1e3f7f369421a3f9bfd9"> 4748</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l04749"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3ca8c6eb5fde2be7d38bde8aedb5522"> 4749</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l04751"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga880aa86c933687f7565b7ab79776923e"> 4751</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) </span></div>
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<div class="line"><a name="l04752"></a><span class="lineno"> 4752</span> <span class="preprocessor">#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l04753"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6b194500112e61e5dd41ded843bb08c6"> 4753</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l04754"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9298e847d13d24cbe87a3c477af9f02c"> 4754</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l04755"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga591eb0822bbb91c4ba12f80d35424c4c"> 4755</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l04756"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6db858408154b3694bb1fdc995f7e069"> 4756</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l04757"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e38ef7ec628928bea867de00af9b206"> 4757</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l04758"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81a86c24f41bd5363793953df972d941"> 4758</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l04759"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08a6ec2df1aa20cfcfacaed7e60417a0"> 4759</a></span> <span class="preprocessor">#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l04761"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90cf92af2475f9f7cadbb9553225260d"> 4761</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FSMC_PATT2 register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l04762"></a><span class="lineno"> 4762</span> <span class="preprocessor">#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) </span></div>
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<div class="line"><a name="l04763"></a><span class="lineno"> 4763</span> <span class="preprocessor">#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l04764"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab6cd1418de73ee3b214be589912e45f"> 4764</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l04765"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab4718770edfb1b9b96df7410a58f79b"> 4765</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l04766"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4cde8c8360b22a3fb63615b4274653c9"> 4766</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l04767"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae80034b8760da9dd1faaf7e326b6002a"> 4767</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l04768"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11924ff951b3e939d2d20807901a82bf"> 4768</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l04769"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1b81efbb998d5e86685075396fd83b0"> 4769</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l04770"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e89896b03049ad636484b44c7ecd670"> 4770</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l04772"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb0f3115642332e5aef5cfa1b6b719d8"> 4772</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) </span></div>
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<div class="line"><a name="l04773"></a><span class="lineno"> 4773</span> <span class="preprocessor">#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l04774"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6fda97184969b04e909ac97d31da48e6"> 4774</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l04775"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf43a2874230fbe9b87f9495a736b9363"> 4775</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l04776"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad30fbb45343ced8deb9bbc062dba46b"> 4776</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l04777"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae78c7794f66cd2063464ab2e6ef2bd07"> 4777</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l04778"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga82c2de9009c75560a342122937b25853"> 4778</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l04779"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae80b6a2fc197435f6b50b4ba035fb5fe"> 4779</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l04780"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac924773c5fcbee73186600247618d10b"> 4780</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l04782"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ade8feb15ddcef159ccf3ff55fb0c24"> 4782</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) </span></div>
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<div class="line"><a name="l04783"></a><span class="lineno"> 4783</span> <span class="preprocessor">#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l04784"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad007c3c6fbef432a5e6bb08bd6e0b1ce"> 4784</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l04785"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b5e19eb38592e84b9c0f3f57df51892"> 4785</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l04786"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13dface112bf1300689a4f00ba31abac"> 4786</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l04787"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea0e1b34ac27f20c85db0f96eaeff994"> 4787</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l04788"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1582860673c5e72f9441095d5af7b8ad"> 4788</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l04789"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacdd679f3b80617291639cafcdd8f77d1"> 4789</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l04790"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34e89cd935ec26279bc9876d9dd07b07"> 4790</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l04792"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93558ba1372a3709316b4734160b3874"> 4792</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) </span></div>
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<div class="line"><a name="l04793"></a><span class="lineno"> 4793</span> <span class="preprocessor">#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l04794"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2726cd505612675158551fd9eed763f"> 4794</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l04795"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1ff9b8faa8372116ca931826d18a9c7"> 4795</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l04796"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac4081b55783073164985488c9d4d6b8"> 4796</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l04797"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3cc10b4217452bae11c69ed9f6f1844"> 4797</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l04798"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93e2929a1bcde578f374bbebaa9482d1"> 4798</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l04799"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac536419b5ef258fa3f9140387e2f134f"> 4799</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l04800"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5deab3153671ff06832dd651372f9ca7"> 4800</a></span> <span class="preprocessor">#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l04802"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga859a5af02e12a11e7548085e9e186547"> 4802</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FSMC_PATT3 register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l04803"></a><span class="lineno"> 4803</span> <span class="preprocessor">#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) </span></div>
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<div class="line"><a name="l04804"></a><span class="lineno"> 4804</span> <span class="preprocessor">#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l04805"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0487c57e948411f16c3a35927e60dd5"> 4805</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l04806"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e68a5b1bb5996422eac084d586359d4"> 4806</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l04807"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d8bd09ad36ab8cae67f87cb930ea428"> 4807</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l04808"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga29b9389601899ce2731c612ad05d9a96"> 4808</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l04809"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97893656a7b65ec5420382de0b264a11"> 4809</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l04810"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a6993a1cc304b9300bdc365c2827d43"> 4810</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l04811"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8cf65f61ce823183c3866607cab6bd09"> 4811</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l04813"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7668853b7956cdb13fd73ed10faf4526"> 4813</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) </span></div>
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<div class="line"><a name="l04814"></a><span class="lineno"> 4814</span> <span class="preprocessor">#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l04815"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8aaf4c77a663cab07ac6c365a271599"> 4815</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l04816"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5c5500a07e7885de5c372c55f147836"> 4816</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l04817"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaddddbd0a403b2aeefcfdb28a7da56bf0"> 4817</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l04818"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac34cbe7e282e1074e6c4b9645e48db2f"> 4818</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l04819"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga771f2a5acde98a9760eb8a1338f416a3"> 4819</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l04820"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1bcc944836a379b2b878d5129ff94ddb"> 4820</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l04821"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf722482193ca6a1bf90f17af567e019"> 4821</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l04823"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa66342cc1db5dcad99153b5a2f22140e"> 4823</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) </span></div>
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<div class="line"><a name="l04824"></a><span class="lineno"> 4824</span> <span class="preprocessor">#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l04825"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3a2e634d0f5e3c9716c0910e1efda60"> 4825</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l04826"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad34a9f1b84d670c4132c56fa30ca26f0"> 4826</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l04827"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b2ed392d654694fc330c6721bed5728"> 4827</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l04828"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga679d3ea50788981dac810ec62bc372f0"> 4828</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l04829"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga75d74cf52f238826e87d3a3c27b52acc"> 4829</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l04830"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa8d656d40279e1655a6682dcc2762e92"> 4830</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l04831"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafee75f2fcf37e20e983732f258f85371"> 4831</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l04833"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39acada8d54a7a14d3838d042397bd74"> 4833</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) </span></div>
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<div class="line"><a name="l04834"></a><span class="lineno"> 4834</span> <span class="preprocessor">#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l04835"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea9d34b131aa7db353eef060ca37788c"> 4835</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l04836"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5bc6736af23f6f033568e0085cd19964"> 4836</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l04837"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41270d0ae8670f39b886b49e47e8195b"> 4837</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l04838"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga988ec453492aafacf205895c5398caf2"> 4838</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l04839"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga48885375147c060687bbccc6a234ce39"> 4839</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l04840"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ea193881223470d7b6a6ca3e3474a84"> 4840</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l04841"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ab1f4cb68cfb8717d2b29e3a84987b1"> 4841</a></span> <span class="preprocessor">#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l04843"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ff1a3acc9bbab229000d48845ea1863"> 4843</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FSMC_PATT4 register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l04844"></a><span class="lineno"> 4844</span> <span class="preprocessor">#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) </span></div>
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<div class="line"><a name="l04845"></a><span class="lineno"> 4845</span> <span class="preprocessor">#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l04846"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f4d8fb0d47b4a3fddf55c2532dd3159"> 4846</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l04847"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1dac8bcf03610eb2d43b557f4d81532a"> 4847</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l04848"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaac2576c2a95871cbf9babd0778372571"> 4848</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l04849"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88e760bbe9714ac07f381de3af0abc36"> 4849</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l04850"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b472fd4848733a921998f0305b5bc02"> 4850</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l04851"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae7d0c69190a0d78fedc875c3dc6b9037"> 4851</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l04852"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga168c6f16be9721a5ea0e31230bd1939b"> 4852</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l04854"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4529b17de7cb4eeeff25496620978adc"> 4854</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) </span></div>
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<div class="line"><a name="l04855"></a><span class="lineno"> 4855</span> <span class="preprocessor">#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l04856"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga01edeaedc31867997a188fa89cab2ec0"> 4856</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l04857"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5da7db34cd23f3126f224a0b845a66a8"> 4857</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l04858"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14644aa2ed55afe2094015d74843a994"> 4858</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l04859"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1023d5ae8fab70e7fdfbaff4ed46657"> 4859</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l04860"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga906c9684ffcd8f0f9222cbfd0e21885a"> 4860</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l04861"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8d341a7448f645a2f849e591515f020"> 4861</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l04862"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf278272c5fdaa8fa7c84e1c095690632"> 4862</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l04864"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34afb78710ca450ac7065f0bc263075c"> 4864</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) </span></div>
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<div class="line"><a name="l04865"></a><span class="lineno"> 4865</span> <span class="preprocessor">#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l04866"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0bf06c395d55c775b4fbe202bac517a6"> 4866</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l04867"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5c97b102bd1f2b61dcfb793c0d61d66"> 4867</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l04868"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga738c8d87ebcdff68725a54ff7f39675d"> 4868</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l04869"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d9610198e4710ca394e3aeb32aa229f"> 4869</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l04870"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd14059e9f658f37b3a1f18786395717"> 4870</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l04871"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a39fa40e2d4990097e31b47ad85283a"> 4871</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l04872"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga239e412f20305d58416f10a79e253a87"> 4872</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l04874"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga836fd2ad42b0c9f6d0eb651589d04123"> 4874</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) </span></div>
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<div class="line"><a name="l04875"></a><span class="lineno"> 4875</span> <span class="preprocessor">#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l04876"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga35948e4e9e5ce9d674e9e70ca2aeafe3"> 4876</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l04877"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b746d7b655f6379af4dd4d5ba842492"> 4877</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l04878"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2dd87929111fc0c888dd7c311f8eba3"> 4878</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l04879"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga353c0709e22a06998f05b908a597f525"> 4879</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l04880"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa777a5d42ac1e36044d7b18ffdd61a21"> 4880</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l04881"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65c1778d08bfe2a40961f6acf023b9d4"> 4881</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) </span></div>
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<div class="line"><a name="l04882"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaadb7001986c9a4c28052b46657ad7a7e"> 4882</a></span> <span class="preprocessor">#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) </span></div>
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<div class="line"><a name="l04884"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1a054f48705ec3fef0686c576f414f29"> 4884</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FSMC_PIO4 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l04885"></a><span class="lineno"> 4885</span> <span class="preprocessor">#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) </span></div>
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<div class="line"><a name="l04886"></a><span class="lineno"> 4886</span> <span class="preprocessor">#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) </span></div>
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|
<div class="line"><a name="l04887"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf14b77f09f496a1325b5384eef54dd4a"> 4887</a></span> <span class="preprocessor">#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) </span></div>
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|
<div class="line"><a name="l04888"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga29c07a816f3065ae0c9287b6e3e0e967"> 4888</a></span> <span class="preprocessor">#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) </span></div>
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|
<div class="line"><a name="l04889"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac31898a52e172935f354819c50d3ef8d"> 4889</a></span> <span class="preprocessor">#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) </span></div>
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|
<div class="line"><a name="l04890"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf35797347825725faef495c676269927"> 4890</a></span> <span class="preprocessor">#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) </span></div>
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|
<div class="line"><a name="l04891"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae45109e3dcc3c3a15efd13eddffdd8c9"> 4891</a></span> <span class="preprocessor">#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) </span></div>
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|
<div class="line"><a name="l04892"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga349e3a58f832fbc9de16955521355c29"> 4892</a></span> <span class="preprocessor">#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l04893"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3304545838a6e20742b0203e0cb023a"> 4893</a></span> <span class="preprocessor">#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l04895"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e29b066726c486c6503d417d18904b1"> 4895</a></span> <span class="preprocessor">#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) </span></div>
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|
<div class="line"><a name="l04896"></a><span class="lineno"> 4896</span> <span class="preprocessor">#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) </span></div>
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|
<div class="line"><a name="l04897"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga035a0645caab3851714123302dd0af1c"> 4897</a></span> <span class="preprocessor">#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) </span></div>
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|
<div class="line"><a name="l04898"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb868a5bf3d33997c782f296440cabf7"> 4898</a></span> <span class="preprocessor">#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) </span></div>
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|
<div class="line"><a name="l04899"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa48c96fedf31c6ab444828d60e471da"> 4899</a></span> <span class="preprocessor">#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) </span></div>
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|
<div class="line"><a name="l04900"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga342e42235a123ea11544b1a230b07a75"> 4900</a></span> <span class="preprocessor">#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l04901"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c012d7c41f51516580766d6ac36d82f"> 4901</a></span> <span class="preprocessor">#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) </span></div>
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|
<div class="line"><a name="l04902"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5331b528505a31a2b39deca7a5ddba02"> 4902</a></span> <span class="preprocessor">#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) </span></div>
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|
<div class="line"><a name="l04903"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaabbfbc377efde5170ac484795a0a4215"> 4903</a></span> <span class="preprocessor">#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) </span></div>
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|
<div class="line"><a name="l04905"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e3fc1b8cfa57116c0521cafd7e733cc"> 4905</a></span> <span class="preprocessor">#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) </span></div>
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|
<div class="line"><a name="l04906"></a><span class="lineno"> 4906</span> <span class="preprocessor">#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) </span></div>
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|
<div class="line"><a name="l04907"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab55064df0d9fab8a072da6baa7b85878"> 4907</a></span> <span class="preprocessor">#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) </span></div>
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|
<div class="line"><a name="l04908"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc1a288b385fcf83bfa95da479d387a4"> 4908</a></span> <span class="preprocessor">#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l04909"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga402d7221ee27ce71d1b8bb18539d8307"> 4909</a></span> <span class="preprocessor">#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) </span></div>
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|
<div class="line"><a name="l04910"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga274c5b835ec95c97c4f1c6ebbf72a096"> 4910</a></span> <span class="preprocessor">#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) </span></div>
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|
<div class="line"><a name="l04911"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga519b9b4ae5b136769278eb98eb10c3a6"> 4911</a></span> <span class="preprocessor">#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) </span></div>
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|
<div class="line"><a name="l04912"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2d013be2823d9ea9b81f8f76331c11d"> 4912</a></span> <span class="preprocessor">#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) </span></div>
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|
<div class="line"><a name="l04913"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a14c965f1ff993e0976aaefe638e2f6"> 4913</a></span> <span class="preprocessor">#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) </span></div>
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|
<div class="line"><a name="l04915"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga323dcc3be986d57d14b794cca0038953"> 4915</a></span> <span class="preprocessor">#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) </span></div>
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|
<div class="line"><a name="l04916"></a><span class="lineno"> 4916</span> <span class="preprocessor">#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) </span></div>
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|
<div class="line"><a name="l04917"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4cce93379430df64fd697ad772bc477d"> 4917</a></span> <span class="preprocessor">#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) </span></div>
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|
<div class="line"><a name="l04918"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf3b5c59e3eb4e259ddb722b1e536e5c"> 4918</a></span> <span class="preprocessor">#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) </span></div>
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|
<div class="line"><a name="l04919"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e8c66264d4ec7b69de613cb528cfee2"> 4919</a></span> <span class="preprocessor">#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) </span></div>
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|
<div class="line"><a name="l04920"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab943b8acd274a8892e691ffab36a6a21"> 4920</a></span> <span class="preprocessor">#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) </span></div>
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|
<div class="line"><a name="l04921"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4184c40fd57a850605ac12c73553b6ba"> 4921</a></span> <span class="preprocessor">#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) </span></div>
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|
<div class="line"><a name="l04922"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9f966bdf26f7fa0f52076438219df7ee"> 4922</a></span> <span class="preprocessor">#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) </span></div>
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|
<div class="line"><a name="l04923"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ba68883e73a331543a2990a76d1e91a"> 4923</a></span> <span class="preprocessor">#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) </span></div>
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|
<div class="line"><a name="l04925"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc8aef29e6eaecd3ff2c13bae143b8b4"> 4925</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FSMC_ECCR2 register ******************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l04926"></a><span class="lineno"> 4926</span> <span class="preprocessor">#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) </span></div>
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|
<div class="line"><a name="l04928"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43da355ad2eb7d974488a02921b1b2ba"> 4928</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FSMC_ECCR3 register ******************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l04929"></a><span class="lineno"> 4929</span> <span class="preprocessor">#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) </span></div>
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|
<div class="line"><a name="l04930"></a><span class="lineno"> 4930</span> <span class="preprocessor">#endif </span><span class="comment">/* STM32F40_41xxx */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l04931"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga798b288a17d84edc99ff1f5f81cf70be"> 4931</a></span> </div>
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|
<div class="line"><a name="l04932"></a><span class="lineno"> 4932</span> <span class="preprocessor">#if defined (STM32F427_437xx) || defined (STM32F429_439xx)</span></div>
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|
<div class="line"><a name="l04933"></a><span class="lineno"> 4933</span> <span class="comment">/******************************************************************************/</span></div>
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|
<div class="line"><a name="l04934"></a><span class="lineno"> 4934</span> <span class="comment">/* */</span></div>
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|
<div class="line"><a name="l04935"></a><span class="lineno"> 4935</span> <span class="comment">/* Flexible Memory Controller */</span></div>
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|
<div class="line"><a name="l04936"></a><span class="lineno"> 4936</span> <span class="comment">/* */</span></div>
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|
<div class="line"><a name="l04937"></a><span class="lineno"> 4937</span> <span class="comment">/******************************************************************************/</span></div>
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|
<div class="line"><a name="l04938"></a><span class="lineno"> 4938</span> <span class="comment">/****************** Bit definition for FMC_BCR1 register *******************/</span></div>
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|
<div class="line"><a name="l04939"></a><span class="lineno"> 4939</span> <span class="preprocessor">#define FMC_BCR1_MBKEN ((uint32_t)0x00000001) </span></div>
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|
<div class="line"><a name="l04940"></a><span class="lineno"> 4940</span> <span class="preprocessor">#define FMC_BCR1_MUXEN ((uint32_t)0x00000002) </span></div>
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|
<div class="line"><a name="l04942"></a><span class="lineno"> 4942</span> <span class="preprocessor">#define FMC_BCR1_MTYP ((uint32_t)0x0000000C) </span></div>
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|
<div class="line"><a name="l04943"></a><span class="lineno"> 4943</span> <span class="preprocessor">#define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l04944"></a><span class="lineno"> 4944</span> <span class="preprocessor">#define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l04946"></a><span class="lineno"> 4946</span> <span class="preprocessor">#define FMC_BCR1_MWID ((uint32_t)0x00000030) </span></div>
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|
<div class="line"><a name="l04947"></a><span class="lineno"> 4947</span> <span class="preprocessor">#define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) </span></div>
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|
<div class="line"><a name="l04948"></a><span class="lineno"> 4948</span> <span class="preprocessor">#define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l04950"></a><span class="lineno"> 4950</span> <span class="preprocessor">#define FMC_BCR1_FACCEN ((uint32_t)0x00000040) </span></div>
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|
<div class="line"><a name="l04951"></a><span class="lineno"> 4951</span> <span class="preprocessor">#define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) </span></div>
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|
<div class="line"><a name="l04952"></a><span class="lineno"> 4952</span> <span class="preprocessor">#define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) </span></div>
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|
<div class="line"><a name="l04953"></a><span class="lineno"> 4953</span> <span class="preprocessor">#define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) </span></div>
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|
<div class="line"><a name="l04954"></a><span class="lineno"> 4954</span> <span class="preprocessor">#define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) </span></div>
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|
<div class="line"><a name="l04955"></a><span class="lineno"> 4955</span> <span class="preprocessor">#define FMC_BCR1_WREN ((uint32_t)0x00001000) </span></div>
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|
<div class="line"><a name="l04956"></a><span class="lineno"> 4956</span> <span class="preprocessor">#define FMC_BCR1_WAITEN ((uint32_t)0x00002000) </span></div>
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|
<div class="line"><a name="l04957"></a><span class="lineno"> 4957</span> <span class="preprocessor">#define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) </span></div>
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|
<div class="line"><a name="l04958"></a><span class="lineno"> 4958</span> <span class="preprocessor">#define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) </span></div>
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|
<div class="line"><a name="l04959"></a><span class="lineno"> 4959</span> <span class="preprocessor">#define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) </span></div>
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|
<div class="line"><a name="l04960"></a><span class="lineno"> 4960</span> <span class="preprocessor">#define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) </span></div>
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|
<div class="line"><a name="l04962"></a><span class="lineno"> 4962</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_BCR2 register *******************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l04963"></a><span class="lineno"> 4963</span> <span class="preprocessor">#define FMC_BCR2_MBKEN ((uint32_t)0x00000001) </span></div>
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|
<div class="line"><a name="l04964"></a><span class="lineno"> 4964</span> <span class="preprocessor">#define FMC_BCR2_MUXEN ((uint32_t)0x00000002) </span></div>
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|
<div class="line"><a name="l04966"></a><span class="lineno"> 4966</span> <span class="preprocessor">#define FMC_BCR2_MTYP ((uint32_t)0x0000000C) </span></div>
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|
<div class="line"><a name="l04967"></a><span class="lineno"> 4967</span> <span class="preprocessor">#define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) </span></div>
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|
<div class="line"><a name="l04968"></a><span class="lineno"> 4968</span> <span class="preprocessor">#define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) </span></div>
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|
<div class="line"><a name="l04970"></a><span class="lineno"> 4970</span> <span class="preprocessor">#define FMC_BCR2_MWID ((uint32_t)0x00000030) </span></div>
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|
<div class="line"><a name="l04971"></a><span class="lineno"> 4971</span> <span class="preprocessor">#define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) </span></div>
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|
<div class="line"><a name="l04972"></a><span class="lineno"> 4972</span> <span class="preprocessor">#define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) </span></div>
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|
<div class="line"><a name="l04974"></a><span class="lineno"> 4974</span> <span class="preprocessor">#define FMC_BCR2_FACCEN ((uint32_t)0x00000040) </span></div>
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|
<div class="line"><a name="l04975"></a><span class="lineno"> 4975</span> <span class="preprocessor">#define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) </span></div>
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|
<div class="line"><a name="l04976"></a><span class="lineno"> 4976</span> <span class="preprocessor">#define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) </span></div>
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|
<div class="line"><a name="l04977"></a><span class="lineno"> 4977</span> <span class="preprocessor">#define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) </span></div>
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|
<div class="line"><a name="l04978"></a><span class="lineno"> 4978</span> <span class="preprocessor">#define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l04979"></a><span class="lineno"> 4979</span> <span class="preprocessor">#define FMC_BCR2_WREN ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l04980"></a><span class="lineno"> 4980</span> <span class="preprocessor">#define FMC_BCR2_WAITEN ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l04981"></a><span class="lineno"> 4981</span> <span class="preprocessor">#define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l04982"></a><span class="lineno"> 4982</span> <span class="preprocessor">#define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) </span></div>
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|
<div class="line"><a name="l04983"></a><span class="lineno"> 4983</span> <span class="preprocessor">#define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) </span></div>
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|
<div class="line"><a name="l04985"></a><span class="lineno"> 4985</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_BCR3 register *******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l04986"></a><span class="lineno"> 4986</span> <span class="preprocessor">#define FMC_BCR3_MBKEN ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l04987"></a><span class="lineno"> 4987</span> <span class="preprocessor">#define FMC_BCR3_MUXEN ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l04989"></a><span class="lineno"> 4989</span> <span class="preprocessor">#define FMC_BCR3_MTYP ((uint32_t)0x0000000C) </span></div>
|
|
<div class="line"><a name="l04990"></a><span class="lineno"> 4990</span> <span class="preprocessor">#define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l04991"></a><span class="lineno"> 4991</span> <span class="preprocessor">#define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l04993"></a><span class="lineno"> 4993</span> <span class="preprocessor">#define FMC_BCR3_MWID ((uint32_t)0x00000030) </span></div>
|
|
<div class="line"><a name="l04994"></a><span class="lineno"> 4994</span> <span class="preprocessor">#define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l04995"></a><span class="lineno"> 4995</span> <span class="preprocessor">#define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l04997"></a><span class="lineno"> 4997</span> <span class="preprocessor">#define FMC_BCR3_FACCEN ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l04998"></a><span class="lineno"> 4998</span> <span class="preprocessor">#define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l04999"></a><span class="lineno"> 4999</span> <span class="preprocessor">#define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l05000"></a><span class="lineno"> 5000</span> <span class="preprocessor">#define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l05001"></a><span class="lineno"> 5001</span> <span class="preprocessor">#define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l05002"></a><span class="lineno"> 5002</span> <span class="preprocessor">#define FMC_BCR3_WREN ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l05003"></a><span class="lineno"> 5003</span> <span class="preprocessor">#define FMC_BCR3_WAITEN ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l05004"></a><span class="lineno"> 5004</span> <span class="preprocessor">#define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l05005"></a><span class="lineno"> 5005</span> <span class="preprocessor">#define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) </span></div>
|
|
<div class="line"><a name="l05006"></a><span class="lineno"> 5006</span> <span class="preprocessor">#define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) </span></div>
|
|
<div class="line"><a name="l05008"></a><span class="lineno"> 5008</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_BCR4 register *******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05009"></a><span class="lineno"> 5009</span> <span class="preprocessor">#define FMC_BCR4_MBKEN ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l05010"></a><span class="lineno"> 5010</span> <span class="preprocessor">#define FMC_BCR4_MUXEN ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l05012"></a><span class="lineno"> 5012</span> <span class="preprocessor">#define FMC_BCR4_MTYP ((uint32_t)0x0000000C) </span></div>
|
|
<div class="line"><a name="l05013"></a><span class="lineno"> 5013</span> <span class="preprocessor">#define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l05014"></a><span class="lineno"> 5014</span> <span class="preprocessor">#define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l05016"></a><span class="lineno"> 5016</span> <span class="preprocessor">#define FMC_BCR4_MWID ((uint32_t)0x00000030) </span></div>
|
|
<div class="line"><a name="l05017"></a><span class="lineno"> 5017</span> <span class="preprocessor">#define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l05018"></a><span class="lineno"> 5018</span> <span class="preprocessor">#define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l05020"></a><span class="lineno"> 5020</span> <span class="preprocessor">#define FMC_BCR4_FACCEN ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l05021"></a><span class="lineno"> 5021</span> <span class="preprocessor">#define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l05022"></a><span class="lineno"> 5022</span> <span class="preprocessor">#define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l05023"></a><span class="lineno"> 5023</span> <span class="preprocessor">#define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l05024"></a><span class="lineno"> 5024</span> <span class="preprocessor">#define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l05025"></a><span class="lineno"> 5025</span> <span class="preprocessor">#define FMC_BCR4_WREN ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l05026"></a><span class="lineno"> 5026</span> <span class="preprocessor">#define FMC_BCR4_WAITEN ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l05027"></a><span class="lineno"> 5027</span> <span class="preprocessor">#define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l05028"></a><span class="lineno"> 5028</span> <span class="preprocessor">#define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) </span></div>
|
|
<div class="line"><a name="l05029"></a><span class="lineno"> 5029</span> <span class="preprocessor">#define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) </span></div>
|
|
<div class="line"><a name="l05031"></a><span class="lineno"> 5031</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_BTR1 register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05032"></a><span class="lineno"> 5032</span> <span class="preprocessor">#define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) </span></div>
|
|
<div class="line"><a name="l05033"></a><span class="lineno"> 5033</span> <span class="preprocessor">#define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l05034"></a><span class="lineno"> 5034</span> <span class="preprocessor">#define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l05035"></a><span class="lineno"> 5035</span> <span class="preprocessor">#define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l05036"></a><span class="lineno"> 5036</span> <span class="preprocessor">#define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l05038"></a><span class="lineno"> 5038</span> <span class="preprocessor">#define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) </span></div>
|
|
<div class="line"><a name="l05039"></a><span class="lineno"> 5039</span> <span class="preprocessor">#define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l05040"></a><span class="lineno"> 5040</span> <span class="preprocessor">#define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l05041"></a><span class="lineno"> 5041</span> <span class="preprocessor">#define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l05042"></a><span class="lineno"> 5042</span> <span class="preprocessor">#define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) </span></div>
|
|
<div class="line"><a name="l05044"></a><span class="lineno"> 5044</span> <span class="preprocessor">#define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) </span></div>
|
|
<div class="line"><a name="l05045"></a><span class="lineno"> 5045</span> <span class="preprocessor">#define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l05046"></a><span class="lineno"> 5046</span> <span class="preprocessor">#define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l05047"></a><span class="lineno"> 5047</span> <span class="preprocessor">#define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l05048"></a><span class="lineno"> 5048</span> <span class="preprocessor">#define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l05049"></a><span class="lineno"> 5049</span> <span class="preprocessor">#define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l05050"></a><span class="lineno"> 5050</span> <span class="preprocessor">#define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l05051"></a><span class="lineno"> 5051</span> <span class="preprocessor">#define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l05052"></a><span class="lineno"> 5052</span> <span class="preprocessor">#define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) </span></div>
|
|
<div class="line"><a name="l05054"></a><span class="lineno"> 5054</span> <span class="preprocessor">#define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) </span></div>
|
|
<div class="line"><a name="l05055"></a><span class="lineno"> 5055</span> <span class="preprocessor">#define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) </span></div>
|
|
<div class="line"><a name="l05056"></a><span class="lineno"> 5056</span> <span class="preprocessor">#define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) </span></div>
|
|
<div class="line"><a name="l05057"></a><span class="lineno"> 5057</span> <span class="preprocessor">#define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) </span></div>
|
|
<div class="line"><a name="l05058"></a><span class="lineno"> 5058</span> <span class="preprocessor">#define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) </span></div>
|
|
<div class="line"><a name="l05060"></a><span class="lineno"> 5060</span> <span class="preprocessor">#define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) </span></div>
|
|
<div class="line"><a name="l05061"></a><span class="lineno"> 5061</span> <span class="preprocessor">#define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) </span></div>
|
|
<div class="line"><a name="l05062"></a><span class="lineno"> 5062</span> <span class="preprocessor">#define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) </span></div>
|
|
<div class="line"><a name="l05063"></a><span class="lineno"> 5063</span> <span class="preprocessor">#define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) </span></div>
|
|
<div class="line"><a name="l05064"></a><span class="lineno"> 5064</span> <span class="preprocessor">#define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) </span></div>
|
|
<div class="line"><a name="l05066"></a><span class="lineno"> 5066</span> <span class="preprocessor">#define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) </span></div>
|
|
<div class="line"><a name="l05067"></a><span class="lineno"> 5067</span> <span class="preprocessor">#define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) </span></div>
|
|
<div class="line"><a name="l05068"></a><span class="lineno"> 5068</span> <span class="preprocessor">#define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) </span></div>
|
|
<div class="line"><a name="l05069"></a><span class="lineno"> 5069</span> <span class="preprocessor">#define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) </span></div>
|
|
<div class="line"><a name="l05070"></a><span class="lineno"> 5070</span> <span class="preprocessor">#define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) </span></div>
|
|
<div class="line"><a name="l05072"></a><span class="lineno"> 5072</span> <span class="preprocessor">#define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) </span></div>
|
|
<div class="line"><a name="l05073"></a><span class="lineno"> 5073</span> <span class="preprocessor">#define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) </span></div>
|
|
<div class="line"><a name="l05074"></a><span class="lineno"> 5074</span> <span class="preprocessor">#define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) </span></div>
|
|
<div class="line"><a name="l05076"></a><span class="lineno"> 5076</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_BTR2 register *******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05077"></a><span class="lineno"> 5077</span> <span class="preprocessor">#define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) </span></div>
|
|
<div class="line"><a name="l05078"></a><span class="lineno"> 5078</span> <span class="preprocessor">#define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l05079"></a><span class="lineno"> 5079</span> <span class="preprocessor">#define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l05080"></a><span class="lineno"> 5080</span> <span class="preprocessor">#define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l05081"></a><span class="lineno"> 5081</span> <span class="preprocessor">#define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l05083"></a><span class="lineno"> 5083</span> <span class="preprocessor">#define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) </span></div>
|
|
<div class="line"><a name="l05084"></a><span class="lineno"> 5084</span> <span class="preprocessor">#define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l05085"></a><span class="lineno"> 5085</span> <span class="preprocessor">#define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l05086"></a><span class="lineno"> 5086</span> <span class="preprocessor">#define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l05087"></a><span class="lineno"> 5087</span> <span class="preprocessor">#define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) </span></div>
|
|
<div class="line"><a name="l05089"></a><span class="lineno"> 5089</span> <span class="preprocessor">#define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) </span></div>
|
|
<div class="line"><a name="l05090"></a><span class="lineno"> 5090</span> <span class="preprocessor">#define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l05091"></a><span class="lineno"> 5091</span> <span class="preprocessor">#define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l05092"></a><span class="lineno"> 5092</span> <span class="preprocessor">#define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l05093"></a><span class="lineno"> 5093</span> <span class="preprocessor">#define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l05094"></a><span class="lineno"> 5094</span> <span class="preprocessor">#define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l05095"></a><span class="lineno"> 5095</span> <span class="preprocessor">#define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l05096"></a><span class="lineno"> 5096</span> <span class="preprocessor">#define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l05097"></a><span class="lineno"> 5097</span> <span class="preprocessor">#define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) </span></div>
|
|
<div class="line"><a name="l05099"></a><span class="lineno"> 5099</span> <span class="preprocessor">#define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) </span></div>
|
|
<div class="line"><a name="l05100"></a><span class="lineno"> 5100</span> <span class="preprocessor">#define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) </span></div>
|
|
<div class="line"><a name="l05101"></a><span class="lineno"> 5101</span> <span class="preprocessor">#define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) </span></div>
|
|
<div class="line"><a name="l05102"></a><span class="lineno"> 5102</span> <span class="preprocessor">#define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) </span></div>
|
|
<div class="line"><a name="l05103"></a><span class="lineno"> 5103</span> <span class="preprocessor">#define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) </span></div>
|
|
<div class="line"><a name="l05105"></a><span class="lineno"> 5105</span> <span class="preprocessor">#define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) </span></div>
|
|
<div class="line"><a name="l05106"></a><span class="lineno"> 5106</span> <span class="preprocessor">#define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) </span></div>
|
|
<div class="line"><a name="l05107"></a><span class="lineno"> 5107</span> <span class="preprocessor">#define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) </span></div>
|
|
<div class="line"><a name="l05108"></a><span class="lineno"> 5108</span> <span class="preprocessor">#define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) </span></div>
|
|
<div class="line"><a name="l05109"></a><span class="lineno"> 5109</span> <span class="preprocessor">#define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) </span></div>
|
|
<div class="line"><a name="l05111"></a><span class="lineno"> 5111</span> <span class="preprocessor">#define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) </span></div>
|
|
<div class="line"><a name="l05112"></a><span class="lineno"> 5112</span> <span class="preprocessor">#define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) </span></div>
|
|
<div class="line"><a name="l05113"></a><span class="lineno"> 5113</span> <span class="preprocessor">#define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) </span></div>
|
|
<div class="line"><a name="l05114"></a><span class="lineno"> 5114</span> <span class="preprocessor">#define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) </span></div>
|
|
<div class="line"><a name="l05115"></a><span class="lineno"> 5115</span> <span class="preprocessor">#define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) </span></div>
|
|
<div class="line"><a name="l05117"></a><span class="lineno"> 5117</span> <span class="preprocessor">#define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) </span></div>
|
|
<div class="line"><a name="l05118"></a><span class="lineno"> 5118</span> <span class="preprocessor">#define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) </span></div>
|
|
<div class="line"><a name="l05119"></a><span class="lineno"> 5119</span> <span class="preprocessor">#define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) </span></div>
|
|
<div class="line"><a name="l05121"></a><span class="lineno"> 5121</span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for FMC_BTR3 register *******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05122"></a><span class="lineno"> 5122</span> <span class="preprocessor">#define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) </span></div>
|
|
<div class="line"><a name="l05123"></a><span class="lineno"> 5123</span> <span class="preprocessor">#define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l05124"></a><span class="lineno"> 5124</span> <span class="preprocessor">#define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l05125"></a><span class="lineno"> 5125</span> <span class="preprocessor">#define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l05126"></a><span class="lineno"> 5126</span> <span class="preprocessor">#define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l05128"></a><span class="lineno"> 5128</span> <span class="preprocessor">#define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) </span></div>
|
|
<div class="line"><a name="l05129"></a><span class="lineno"> 5129</span> <span class="preprocessor">#define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l05130"></a><span class="lineno"> 5130</span> <span class="preprocessor">#define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l05131"></a><span class="lineno"> 5131</span> <span class="preprocessor">#define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l05132"></a><span class="lineno"> 5132</span> <span class="preprocessor">#define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) </span></div>
|
|
<div class="line"><a name="l05134"></a><span class="lineno"> 5134</span> <span class="preprocessor">#define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) </span></div>
|
|
<div class="line"><a name="l05135"></a><span class="lineno"> 5135</span> <span class="preprocessor">#define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l05136"></a><span class="lineno"> 5136</span> <span class="preprocessor">#define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l05137"></a><span class="lineno"> 5137</span> <span class="preprocessor">#define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l05138"></a><span class="lineno"> 5138</span> <span class="preprocessor">#define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l05139"></a><span class="lineno"> 5139</span> <span class="preprocessor">#define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l05140"></a><span class="lineno"> 5140</span> <span class="preprocessor">#define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l05141"></a><span class="lineno"> 5141</span> <span class="preprocessor">#define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l05142"></a><span class="lineno"> 5142</span> <span class="preprocessor">#define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) </span></div>
|
|
<div class="line"><a name="l05144"></a><span class="lineno"> 5144</span> <span class="preprocessor">#define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) </span></div>
|
|
<div class="line"><a name="l05145"></a><span class="lineno"> 5145</span> <span class="preprocessor">#define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) </span></div>
|
|
<div class="line"><a name="l05146"></a><span class="lineno"> 5146</span> <span class="preprocessor">#define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) </span></div>
|
|
<div class="line"><a name="l05147"></a><span class="lineno"> 5147</span> <span class="preprocessor">#define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) </span></div>
|
|
<div class="line"><a name="l05148"></a><span class="lineno"> 5148</span> <span class="preprocessor">#define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) </span></div>
|
|
<div class="line"><a name="l05150"></a><span class="lineno"> 5150</span> <span class="preprocessor">#define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) </span></div>
|
|
<div class="line"><a name="l05151"></a><span class="lineno"> 5151</span> <span class="preprocessor">#define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) </span></div>
|
|
<div class="line"><a name="l05152"></a><span class="lineno"> 5152</span> <span class="preprocessor">#define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) </span></div>
|
|
<div class="line"><a name="l05153"></a><span class="lineno"> 5153</span> <span class="preprocessor">#define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) </span></div>
|
|
<div class="line"><a name="l05154"></a><span class="lineno"> 5154</span> <span class="preprocessor">#define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) </span></div>
|
|
<div class="line"><a name="l05156"></a><span class="lineno"> 5156</span> <span class="preprocessor">#define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) </span></div>
|
|
<div class="line"><a name="l05157"></a><span class="lineno"> 5157</span> <span class="preprocessor">#define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) </span></div>
|
|
<div class="line"><a name="l05158"></a><span class="lineno"> 5158</span> <span class="preprocessor">#define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) </span></div>
|
|
<div class="line"><a name="l05159"></a><span class="lineno"> 5159</span> <span class="preprocessor">#define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) </span></div>
|
|
<div class="line"><a name="l05160"></a><span class="lineno"> 5160</span> <span class="preprocessor">#define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) </span></div>
|
|
<div class="line"><a name="l05162"></a><span class="lineno"> 5162</span> <span class="preprocessor">#define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) </span></div>
|
|
<div class="line"><a name="l05163"></a><span class="lineno"> 5163</span> <span class="preprocessor">#define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) </span></div>
|
|
<div class="line"><a name="l05164"></a><span class="lineno"> 5164</span> <span class="preprocessor">#define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) </span></div>
|
|
<div class="line"><a name="l05166"></a><span class="lineno"> 5166</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_BTR4 register *******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05167"></a><span class="lineno"> 5167</span> <span class="preprocessor">#define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) </span></div>
|
|
<div class="line"><a name="l05168"></a><span class="lineno"> 5168</span> <span class="preprocessor">#define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l05169"></a><span class="lineno"> 5169</span> <span class="preprocessor">#define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l05170"></a><span class="lineno"> 5170</span> <span class="preprocessor">#define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l05171"></a><span class="lineno"> 5171</span> <span class="preprocessor">#define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l05173"></a><span class="lineno"> 5173</span> <span class="preprocessor">#define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) </span></div>
|
|
<div class="line"><a name="l05174"></a><span class="lineno"> 5174</span> <span class="preprocessor">#define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l05175"></a><span class="lineno"> 5175</span> <span class="preprocessor">#define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l05176"></a><span class="lineno"> 5176</span> <span class="preprocessor">#define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l05177"></a><span class="lineno"> 5177</span> <span class="preprocessor">#define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) </span></div>
|
|
<div class="line"><a name="l05179"></a><span class="lineno"> 5179</span> <span class="preprocessor">#define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) </span></div>
|
|
<div class="line"><a name="l05180"></a><span class="lineno"> 5180</span> <span class="preprocessor">#define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l05181"></a><span class="lineno"> 5181</span> <span class="preprocessor">#define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l05182"></a><span class="lineno"> 5182</span> <span class="preprocessor">#define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l05183"></a><span class="lineno"> 5183</span> <span class="preprocessor">#define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l05184"></a><span class="lineno"> 5184</span> <span class="preprocessor">#define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l05185"></a><span class="lineno"> 5185</span> <span class="preprocessor">#define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l05186"></a><span class="lineno"> 5186</span> <span class="preprocessor">#define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l05187"></a><span class="lineno"> 5187</span> <span class="preprocessor">#define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) </span></div>
|
|
<div class="line"><a name="l05189"></a><span class="lineno"> 5189</span> <span class="preprocessor">#define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) </span></div>
|
|
<div class="line"><a name="l05190"></a><span class="lineno"> 5190</span> <span class="preprocessor">#define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) </span></div>
|
|
<div class="line"><a name="l05191"></a><span class="lineno"> 5191</span> <span class="preprocessor">#define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) </span></div>
|
|
<div class="line"><a name="l05192"></a><span class="lineno"> 5192</span> <span class="preprocessor">#define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) </span></div>
|
|
<div class="line"><a name="l05193"></a><span class="lineno"> 5193</span> <span class="preprocessor">#define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) </span></div>
|
|
<div class="line"><a name="l05195"></a><span class="lineno"> 5195</span> <span class="preprocessor">#define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) </span></div>
|
|
<div class="line"><a name="l05196"></a><span class="lineno"> 5196</span> <span class="preprocessor">#define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) </span></div>
|
|
<div class="line"><a name="l05197"></a><span class="lineno"> 5197</span> <span class="preprocessor">#define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) </span></div>
|
|
<div class="line"><a name="l05198"></a><span class="lineno"> 5198</span> <span class="preprocessor">#define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) </span></div>
|
|
<div class="line"><a name="l05199"></a><span class="lineno"> 5199</span> <span class="preprocessor">#define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) </span></div>
|
|
<div class="line"><a name="l05201"></a><span class="lineno"> 5201</span> <span class="preprocessor">#define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) </span></div>
|
|
<div class="line"><a name="l05202"></a><span class="lineno"> 5202</span> <span class="preprocessor">#define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) </span></div>
|
|
<div class="line"><a name="l05203"></a><span class="lineno"> 5203</span> <span class="preprocessor">#define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) </span></div>
|
|
<div class="line"><a name="l05204"></a><span class="lineno"> 5204</span> <span class="preprocessor">#define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) </span></div>
|
|
<div class="line"><a name="l05205"></a><span class="lineno"> 5205</span> <span class="preprocessor">#define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) </span></div>
|
|
<div class="line"><a name="l05207"></a><span class="lineno"> 5207</span> <span class="preprocessor">#define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) </span></div>
|
|
<div class="line"><a name="l05208"></a><span class="lineno"> 5208</span> <span class="preprocessor">#define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) </span></div>
|
|
<div class="line"><a name="l05209"></a><span class="lineno"> 5209</span> <span class="preprocessor">#define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) </span></div>
|
|
<div class="line"><a name="l05211"></a><span class="lineno"> 5211</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_BWTR1 register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05212"></a><span class="lineno"> 5212</span> <span class="preprocessor">#define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) </span></div>
|
|
<div class="line"><a name="l05213"></a><span class="lineno"> 5213</span> <span class="preprocessor">#define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l05214"></a><span class="lineno"> 5214</span> <span class="preprocessor">#define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l05215"></a><span class="lineno"> 5215</span> <span class="preprocessor">#define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l05216"></a><span class="lineno"> 5216</span> <span class="preprocessor">#define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l05218"></a><span class="lineno"> 5218</span> <span class="preprocessor">#define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) </span></div>
|
|
<div class="line"><a name="l05219"></a><span class="lineno"> 5219</span> <span class="preprocessor">#define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l05220"></a><span class="lineno"> 5220</span> <span class="preprocessor">#define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l05221"></a><span class="lineno"> 5221</span> <span class="preprocessor">#define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l05222"></a><span class="lineno"> 5222</span> <span class="preprocessor">#define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) </span></div>
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|
<div class="line"><a name="l05224"></a><span class="lineno"> 5224</span> <span class="preprocessor">#define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) </span></div>
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|
<div class="line"><a name="l05225"></a><span class="lineno"> 5225</span> <span class="preprocessor">#define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) </span></div>
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|
<div class="line"><a name="l05226"></a><span class="lineno"> 5226</span> <span class="preprocessor">#define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l05227"></a><span class="lineno"> 5227</span> <span class="preprocessor">#define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) </span></div>
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|
<div class="line"><a name="l05228"></a><span class="lineno"> 5228</span> <span class="preprocessor">#define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) </span></div>
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|
<div class="line"><a name="l05229"></a><span class="lineno"> 5229</span> <span class="preprocessor">#define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) </span></div>
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|
<div class="line"><a name="l05230"></a><span class="lineno"> 5230</span> <span class="preprocessor">#define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l05231"></a><span class="lineno"> 5231</span> <span class="preprocessor">#define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) </span></div>
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|
<div class="line"><a name="l05232"></a><span class="lineno"> 5232</span> <span class="preprocessor">#define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l05234"></a><span class="lineno"> 5234</span> <span class="preprocessor">#define FMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) </span></div>
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<div class="line"><a name="l05235"></a><span class="lineno"> 5235</span> <span class="preprocessor">#define FMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) </span></div>
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|
<div class="line"><a name="l05236"></a><span class="lineno"> 5236</span> <span class="preprocessor">#define FMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l05237"></a><span class="lineno"> 5237</span> <span class="preprocessor">#define FMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l05238"></a><span class="lineno"> 5238</span> <span class="preprocessor">#define FMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l05240"></a><span class="lineno"> 5240</span> <span class="preprocessor">#define FMC_BWTR1_DATLAT ((uint32_t)0x0F000000) </span></div>
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<div class="line"><a name="l05241"></a><span class="lineno"> 5241</span> <span class="preprocessor">#define FMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l05242"></a><span class="lineno"> 5242</span> <span class="preprocessor">#define FMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l05243"></a><span class="lineno"> 5243</span> <span class="preprocessor">#define FMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l05244"></a><span class="lineno"> 5244</span> <span class="preprocessor">#define FMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l05246"></a><span class="lineno"> 5246</span> <span class="preprocessor">#define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) </span></div>
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<div class="line"><a name="l05247"></a><span class="lineno"> 5247</span> <span class="preprocessor">#define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l05248"></a><span class="lineno"> 5248</span> <span class="preprocessor">#define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l05250"></a><span class="lineno"> 5250</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_BWTR2 register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l05251"></a><span class="lineno"> 5251</span> <span class="preprocessor">#define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) </span></div>
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<div class="line"><a name="l05252"></a><span class="lineno"> 5252</span> <span class="preprocessor">#define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l05253"></a><span class="lineno"> 5253</span> <span class="preprocessor">#define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l05254"></a><span class="lineno"> 5254</span> <span class="preprocessor">#define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l05255"></a><span class="lineno"> 5255</span> <span class="preprocessor">#define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l05257"></a><span class="lineno"> 5257</span> <span class="preprocessor">#define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) </span></div>
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<div class="line"><a name="l05258"></a><span class="lineno"> 5258</span> <span class="preprocessor">#define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l05259"></a><span class="lineno"> 5259</span> <span class="preprocessor">#define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l05260"></a><span class="lineno"> 5260</span> <span class="preprocessor">#define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l05261"></a><span class="lineno"> 5261</span> <span class="preprocessor">#define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) </span></div>
|
|
<div class="line"><a name="l05263"></a><span class="lineno"> 5263</span> <span class="preprocessor">#define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) </span></div>
|
|
<div class="line"><a name="l05264"></a><span class="lineno"> 5264</span> <span class="preprocessor">#define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l05265"></a><span class="lineno"> 5265</span> <span class="preprocessor">#define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l05266"></a><span class="lineno"> 5266</span> <span class="preprocessor">#define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l05267"></a><span class="lineno"> 5267</span> <span class="preprocessor">#define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l05268"></a><span class="lineno"> 5268</span> <span class="preprocessor">#define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l05269"></a><span class="lineno"> 5269</span> <span class="preprocessor">#define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l05270"></a><span class="lineno"> 5270</span> <span class="preprocessor">#define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l05271"></a><span class="lineno"> 5271</span> <span class="preprocessor">#define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) </span></div>
|
|
<div class="line"><a name="l05273"></a><span class="lineno"> 5273</span> <span class="preprocessor">#define FMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) </span></div>
|
|
<div class="line"><a name="l05274"></a><span class="lineno"> 5274</span> <span class="preprocessor">#define FMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) </span></div>
|
|
<div class="line"><a name="l05275"></a><span class="lineno"> 5275</span> <span class="preprocessor">#define FMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) </span></div>
|
|
<div class="line"><a name="l05276"></a><span class="lineno"> 5276</span> <span class="preprocessor">#define FMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) </span></div>
|
|
<div class="line"><a name="l05277"></a><span class="lineno"> 5277</span> <span class="preprocessor">#define FMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) </span></div>
|
|
<div class="line"><a name="l05279"></a><span class="lineno"> 5279</span> <span class="preprocessor">#define FMC_BWTR2_DATLAT ((uint32_t)0x0F000000) </span></div>
|
|
<div class="line"><a name="l05280"></a><span class="lineno"> 5280</span> <span class="preprocessor">#define FMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) </span></div>
|
|
<div class="line"><a name="l05281"></a><span class="lineno"> 5281</span> <span class="preprocessor">#define FMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) </span></div>
|
|
<div class="line"><a name="l05282"></a><span class="lineno"> 5282</span> <span class="preprocessor">#define FMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) </span></div>
|
|
<div class="line"><a name="l05283"></a><span class="lineno"> 5283</span> <span class="preprocessor">#define FMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) </span></div>
|
|
<div class="line"><a name="l05285"></a><span class="lineno"> 5285</span> <span class="preprocessor">#define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) </span></div>
|
|
<div class="line"><a name="l05286"></a><span class="lineno"> 5286</span> <span class="preprocessor">#define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) </span></div>
|
|
<div class="line"><a name="l05287"></a><span class="lineno"> 5287</span> <span class="preprocessor">#define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) </span></div>
|
|
<div class="line"><a name="l05289"></a><span class="lineno"> 5289</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_BWTR3 register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05290"></a><span class="lineno"> 5290</span> <span class="preprocessor">#define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) </span></div>
|
|
<div class="line"><a name="l05291"></a><span class="lineno"> 5291</span> <span class="preprocessor">#define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l05292"></a><span class="lineno"> 5292</span> <span class="preprocessor">#define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l05293"></a><span class="lineno"> 5293</span> <span class="preprocessor">#define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l05294"></a><span class="lineno"> 5294</span> <span class="preprocessor">#define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l05296"></a><span class="lineno"> 5296</span> <span class="preprocessor">#define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) </span></div>
|
|
<div class="line"><a name="l05297"></a><span class="lineno"> 5297</span> <span class="preprocessor">#define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l05298"></a><span class="lineno"> 5298</span> <span class="preprocessor">#define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l05299"></a><span class="lineno"> 5299</span> <span class="preprocessor">#define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l05300"></a><span class="lineno"> 5300</span> <span class="preprocessor">#define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) </span></div>
|
|
<div class="line"><a name="l05302"></a><span class="lineno"> 5302</span> <span class="preprocessor">#define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) </span></div>
|
|
<div class="line"><a name="l05303"></a><span class="lineno"> 5303</span> <span class="preprocessor">#define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l05304"></a><span class="lineno"> 5304</span> <span class="preprocessor">#define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l05305"></a><span class="lineno"> 5305</span> <span class="preprocessor">#define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l05306"></a><span class="lineno"> 5306</span> <span class="preprocessor">#define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l05307"></a><span class="lineno"> 5307</span> <span class="preprocessor">#define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l05308"></a><span class="lineno"> 5308</span> <span class="preprocessor">#define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l05309"></a><span class="lineno"> 5309</span> <span class="preprocessor">#define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l05310"></a><span class="lineno"> 5310</span> <span class="preprocessor">#define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) </span></div>
|
|
<div class="line"><a name="l05312"></a><span class="lineno"> 5312</span> <span class="preprocessor">#define FMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) </span></div>
|
|
<div class="line"><a name="l05313"></a><span class="lineno"> 5313</span> <span class="preprocessor">#define FMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) </span></div>
|
|
<div class="line"><a name="l05314"></a><span class="lineno"> 5314</span> <span class="preprocessor">#define FMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) </span></div>
|
|
<div class="line"><a name="l05315"></a><span class="lineno"> 5315</span> <span class="preprocessor">#define FMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) </span></div>
|
|
<div class="line"><a name="l05316"></a><span class="lineno"> 5316</span> <span class="preprocessor">#define FMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) </span></div>
|
|
<div class="line"><a name="l05318"></a><span class="lineno"> 5318</span> <span class="preprocessor">#define FMC_BWTR3_DATLAT ((uint32_t)0x0F000000) </span></div>
|
|
<div class="line"><a name="l05319"></a><span class="lineno"> 5319</span> <span class="preprocessor">#define FMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) </span></div>
|
|
<div class="line"><a name="l05320"></a><span class="lineno"> 5320</span> <span class="preprocessor">#define FMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) </span></div>
|
|
<div class="line"><a name="l05321"></a><span class="lineno"> 5321</span> <span class="preprocessor">#define FMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) </span></div>
|
|
<div class="line"><a name="l05322"></a><span class="lineno"> 5322</span> <span class="preprocessor">#define FMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) </span></div>
|
|
<div class="line"><a name="l05324"></a><span class="lineno"> 5324</span> <span class="preprocessor">#define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) </span></div>
|
|
<div class="line"><a name="l05325"></a><span class="lineno"> 5325</span> <span class="preprocessor">#define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) </span></div>
|
|
<div class="line"><a name="l05326"></a><span class="lineno"> 5326</span> <span class="preprocessor">#define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) </span></div>
|
|
<div class="line"><a name="l05328"></a><span class="lineno"> 5328</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_BWTR4 register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05329"></a><span class="lineno"> 5329</span> <span class="preprocessor">#define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) </span></div>
|
|
<div class="line"><a name="l05330"></a><span class="lineno"> 5330</span> <span class="preprocessor">#define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l05331"></a><span class="lineno"> 5331</span> <span class="preprocessor">#define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l05332"></a><span class="lineno"> 5332</span> <span class="preprocessor">#define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l05333"></a><span class="lineno"> 5333</span> <span class="preprocessor">#define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l05335"></a><span class="lineno"> 5335</span> <span class="preprocessor">#define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) </span></div>
|
|
<div class="line"><a name="l05336"></a><span class="lineno"> 5336</span> <span class="preprocessor">#define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l05337"></a><span class="lineno"> 5337</span> <span class="preprocessor">#define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l05338"></a><span class="lineno"> 5338</span> <span class="preprocessor">#define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l05339"></a><span class="lineno"> 5339</span> <span class="preprocessor">#define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) </span></div>
|
|
<div class="line"><a name="l05341"></a><span class="lineno"> 5341</span> <span class="preprocessor">#define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) </span></div>
|
|
<div class="line"><a name="l05342"></a><span class="lineno"> 5342</span> <span class="preprocessor">#define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l05343"></a><span class="lineno"> 5343</span> <span class="preprocessor">#define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l05344"></a><span class="lineno"> 5344</span> <span class="preprocessor">#define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l05345"></a><span class="lineno"> 5345</span> <span class="preprocessor">#define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l05346"></a><span class="lineno"> 5346</span> <span class="preprocessor">#define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l05347"></a><span class="lineno"> 5347</span> <span class="preprocessor">#define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l05348"></a><span class="lineno"> 5348</span> <span class="preprocessor">#define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l05349"></a><span class="lineno"> 5349</span> <span class="preprocessor">#define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) </span></div>
|
|
<div class="line"><a name="l05351"></a><span class="lineno"> 5351</span> <span class="preprocessor">#define FMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) </span></div>
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|
<div class="line"><a name="l05352"></a><span class="lineno"> 5352</span> <span class="preprocessor">#define FMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) </span></div>
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|
<div class="line"><a name="l05353"></a><span class="lineno"> 5353</span> <span class="preprocessor">#define FMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l05354"></a><span class="lineno"> 5354</span> <span class="preprocessor">#define FMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l05355"></a><span class="lineno"> 5355</span> <span class="preprocessor">#define FMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l05357"></a><span class="lineno"> 5357</span> <span class="preprocessor">#define FMC_BWTR4_DATLAT ((uint32_t)0x0F000000) </span></div>
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<div class="line"><a name="l05358"></a><span class="lineno"> 5358</span> <span class="preprocessor">#define FMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) </span></div>
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<div class="line"><a name="l05359"></a><span class="lineno"> 5359</span> <span class="preprocessor">#define FMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) </span></div>
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<div class="line"><a name="l05360"></a><span class="lineno"> 5360</span> <span class="preprocessor">#define FMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) </span></div>
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<div class="line"><a name="l05361"></a><span class="lineno"> 5361</span> <span class="preprocessor">#define FMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) </span></div>
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<div class="line"><a name="l05363"></a><span class="lineno"> 5363</span> <span class="preprocessor">#define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) </span></div>
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<div class="line"><a name="l05364"></a><span class="lineno"> 5364</span> <span class="preprocessor">#define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) </span></div>
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<div class="line"><a name="l05365"></a><span class="lineno"> 5365</span> <span class="preprocessor">#define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) </span></div>
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<div class="line"><a name="l05367"></a><span class="lineno"> 5367</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_PCR2 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l05368"></a><span class="lineno"> 5368</span> <span class="preprocessor">#define FMC_PCR2_PWAITEN ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l05369"></a><span class="lineno"> 5369</span> <span class="preprocessor">#define FMC_PCR2_PBKEN ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l05370"></a><span class="lineno"> 5370</span> <span class="preprocessor">#define FMC_PCR2_PTYP ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l05372"></a><span class="lineno"> 5372</span> <span class="preprocessor">#define FMC_PCR2_PWID ((uint32_t)0x00000030) </span></div>
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<div class="line"><a name="l05373"></a><span class="lineno"> 5373</span> <span class="preprocessor">#define FMC_PCR2_PWID_0 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l05374"></a><span class="lineno"> 5374</span> <span class="preprocessor">#define FMC_PCR2_PWID_1 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l05376"></a><span class="lineno"> 5376</span> <span class="preprocessor">#define FMC_PCR2_ECCEN ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l05378"></a><span class="lineno"> 5378</span> <span class="preprocessor">#define FMC_PCR2_TCLR ((uint32_t)0x00001E00) </span></div>
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<div class="line"><a name="l05379"></a><span class="lineno"> 5379</span> <span class="preprocessor">#define FMC_PCR2_TCLR_0 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l05380"></a><span class="lineno"> 5380</span> <span class="preprocessor">#define FMC_PCR2_TCLR_1 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l05381"></a><span class="lineno"> 5381</span> <span class="preprocessor">#define FMC_PCR2_TCLR_2 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l05382"></a><span class="lineno"> 5382</span> <span class="preprocessor">#define FMC_PCR2_TCLR_3 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l05384"></a><span class="lineno"> 5384</span> <span class="preprocessor">#define FMC_PCR2_TAR ((uint32_t)0x0001E000) </span></div>
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<div class="line"><a name="l05385"></a><span class="lineno"> 5385</span> <span class="preprocessor">#define FMC_PCR2_TAR_0 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l05386"></a><span class="lineno"> 5386</span> <span class="preprocessor">#define FMC_PCR2_TAR_1 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l05387"></a><span class="lineno"> 5387</span> <span class="preprocessor">#define FMC_PCR2_TAR_2 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l05388"></a><span class="lineno"> 5388</span> <span class="preprocessor">#define FMC_PCR2_TAR_3 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l05390"></a><span class="lineno"> 5390</span> <span class="preprocessor">#define FMC_PCR2_ECCPS ((uint32_t)0x000E0000) </span></div>
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<div class="line"><a name="l05391"></a><span class="lineno"> 5391</span> <span class="preprocessor">#define FMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l05392"></a><span class="lineno"> 5392</span> <span class="preprocessor">#define FMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l05393"></a><span class="lineno"> 5393</span> <span class="preprocessor">#define FMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l05395"></a><span class="lineno"> 5395</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_PCR3 register *******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05396"></a><span class="lineno"> 5396</span> <span class="preprocessor">#define FMC_PCR3_PWAITEN ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l05397"></a><span class="lineno"> 5397</span> <span class="preprocessor">#define FMC_PCR3_PBKEN ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l05398"></a><span class="lineno"> 5398</span> <span class="preprocessor">#define FMC_PCR3_PTYP ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l05400"></a><span class="lineno"> 5400</span> <span class="preprocessor">#define FMC_PCR3_PWID ((uint32_t)0x00000030) </span></div>
|
|
<div class="line"><a name="l05401"></a><span class="lineno"> 5401</span> <span class="preprocessor">#define FMC_PCR3_PWID_0 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l05402"></a><span class="lineno"> 5402</span> <span class="preprocessor">#define FMC_PCR3_PWID_1 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l05404"></a><span class="lineno"> 5404</span> <span class="preprocessor">#define FMC_PCR3_ECCEN ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l05406"></a><span class="lineno"> 5406</span> <span class="preprocessor">#define FMC_PCR3_TCLR ((uint32_t)0x00001E00) </span></div>
|
|
<div class="line"><a name="l05407"></a><span class="lineno"> 5407</span> <span class="preprocessor">#define FMC_PCR3_TCLR_0 ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l05408"></a><span class="lineno"> 5408</span> <span class="preprocessor">#define FMC_PCR3_TCLR_1 ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l05409"></a><span class="lineno"> 5409</span> <span class="preprocessor">#define FMC_PCR3_TCLR_2 ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l05410"></a><span class="lineno"> 5410</span> <span class="preprocessor">#define FMC_PCR3_TCLR_3 ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l05412"></a><span class="lineno"> 5412</span> <span class="preprocessor">#define FMC_PCR3_TAR ((uint32_t)0x0001E000) </span></div>
|
|
<div class="line"><a name="l05413"></a><span class="lineno"> 5413</span> <span class="preprocessor">#define FMC_PCR3_TAR_0 ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l05414"></a><span class="lineno"> 5414</span> <span class="preprocessor">#define FMC_PCR3_TAR_1 ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l05415"></a><span class="lineno"> 5415</span> <span class="preprocessor">#define FMC_PCR3_TAR_2 ((uint32_t)0x00008000) </span></div>
|
|
<div class="line"><a name="l05416"></a><span class="lineno"> 5416</span> <span class="preprocessor">#define FMC_PCR3_TAR_3 ((uint32_t)0x00010000) </span></div>
|
|
<div class="line"><a name="l05418"></a><span class="lineno"> 5418</span> <span class="preprocessor">#define FMC_PCR3_ECCPS ((uint32_t)0x000E0000) </span></div>
|
|
<div class="line"><a name="l05419"></a><span class="lineno"> 5419</span> <span class="preprocessor">#define FMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) </span></div>
|
|
<div class="line"><a name="l05420"></a><span class="lineno"> 5420</span> <span class="preprocessor">#define FMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) </span></div>
|
|
<div class="line"><a name="l05421"></a><span class="lineno"> 5421</span> <span class="preprocessor">#define FMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) </span></div>
|
|
<div class="line"><a name="l05423"></a><span class="lineno"> 5423</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_PCR4 register *******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05424"></a><span class="lineno"> 5424</span> <span class="preprocessor">#define FMC_PCR4_PWAITEN ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l05425"></a><span class="lineno"> 5425</span> <span class="preprocessor">#define FMC_PCR4_PBKEN ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l05426"></a><span class="lineno"> 5426</span> <span class="preprocessor">#define FMC_PCR4_PTYP ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l05428"></a><span class="lineno"> 5428</span> <span class="preprocessor">#define FMC_PCR4_PWID ((uint32_t)0x00000030) </span></div>
|
|
<div class="line"><a name="l05429"></a><span class="lineno"> 5429</span> <span class="preprocessor">#define FMC_PCR4_PWID_0 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l05430"></a><span class="lineno"> 5430</span> <span class="preprocessor">#define FMC_PCR4_PWID_1 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l05432"></a><span class="lineno"> 5432</span> <span class="preprocessor">#define FMC_PCR4_ECCEN ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l05434"></a><span class="lineno"> 5434</span> <span class="preprocessor">#define FMC_PCR4_TCLR ((uint32_t)0x00001E00) </span></div>
|
|
<div class="line"><a name="l05435"></a><span class="lineno"> 5435</span> <span class="preprocessor">#define FMC_PCR4_TCLR_0 ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l05436"></a><span class="lineno"> 5436</span> <span class="preprocessor">#define FMC_PCR4_TCLR_1 ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l05437"></a><span class="lineno"> 5437</span> <span class="preprocessor">#define FMC_PCR4_TCLR_2 ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l05438"></a><span class="lineno"> 5438</span> <span class="preprocessor">#define FMC_PCR4_TCLR_3 ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l05440"></a><span class="lineno"> 5440</span> <span class="preprocessor">#define FMC_PCR4_TAR ((uint32_t)0x0001E000) </span></div>
|
|
<div class="line"><a name="l05441"></a><span class="lineno"> 5441</span> <span class="preprocessor">#define FMC_PCR4_TAR_0 ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l05442"></a><span class="lineno"> 5442</span> <span class="preprocessor">#define FMC_PCR4_TAR_1 ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l05443"></a><span class="lineno"> 5443</span> <span class="preprocessor">#define FMC_PCR4_TAR_2 ((uint32_t)0x00008000) </span></div>
|
|
<div class="line"><a name="l05444"></a><span class="lineno"> 5444</span> <span class="preprocessor">#define FMC_PCR4_TAR_3 ((uint32_t)0x00010000) </span></div>
|
|
<div class="line"><a name="l05446"></a><span class="lineno"> 5446</span> <span class="preprocessor">#define FMC_PCR4_ECCPS ((uint32_t)0x000E0000) </span></div>
|
|
<div class="line"><a name="l05447"></a><span class="lineno"> 5447</span> <span class="preprocessor">#define FMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) </span></div>
|
|
<div class="line"><a name="l05448"></a><span class="lineno"> 5448</span> <span class="preprocessor">#define FMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) </span></div>
|
|
<div class="line"><a name="l05449"></a><span class="lineno"> 5449</span> <span class="preprocessor">#define FMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) </span></div>
|
|
<div class="line"><a name="l05451"></a><span class="lineno"> 5451</span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for FMC_SR2 register *******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05452"></a><span class="lineno"> 5452</span> <span class="preprocessor">#define FMC_SR2_IRS ((uint8_t)0x01) </span></div>
|
|
<div class="line"><a name="l05453"></a><span class="lineno"> 5453</span> <span class="preprocessor">#define FMC_SR2_ILS ((uint8_t)0x02) </span></div>
|
|
<div class="line"><a name="l05454"></a><span class="lineno"> 5454</span> <span class="preprocessor">#define FMC_SR2_IFS ((uint8_t)0x04) </span></div>
|
|
<div class="line"><a name="l05455"></a><span class="lineno"> 5455</span> <span class="preprocessor">#define FMC_SR2_IREN ((uint8_t)0x08) </span></div>
|
|
<div class="line"><a name="l05456"></a><span class="lineno"> 5456</span> <span class="preprocessor">#define FMC_SR2_ILEN ((uint8_t)0x10) </span></div>
|
|
<div class="line"><a name="l05457"></a><span class="lineno"> 5457</span> <span class="preprocessor">#define FMC_SR2_IFEN ((uint8_t)0x20) </span></div>
|
|
<div class="line"><a name="l05458"></a><span class="lineno"> 5458</span> <span class="preprocessor">#define FMC_SR2_FEMPT ((uint8_t)0x40) </span></div>
|
|
<div class="line"><a name="l05460"></a><span class="lineno"> 5460</span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for FMC_SR3 register *******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05461"></a><span class="lineno"> 5461</span> <span class="preprocessor">#define FMC_SR3_IRS ((uint8_t)0x01) </span></div>
|
|
<div class="line"><a name="l05462"></a><span class="lineno"> 5462</span> <span class="preprocessor">#define FMC_SR3_ILS ((uint8_t)0x02) </span></div>
|
|
<div class="line"><a name="l05463"></a><span class="lineno"> 5463</span> <span class="preprocessor">#define FMC_SR3_IFS ((uint8_t)0x04) </span></div>
|
|
<div class="line"><a name="l05464"></a><span class="lineno"> 5464</span> <span class="preprocessor">#define FMC_SR3_IREN ((uint8_t)0x08) </span></div>
|
|
<div class="line"><a name="l05465"></a><span class="lineno"> 5465</span> <span class="preprocessor">#define FMC_SR3_ILEN ((uint8_t)0x10) </span></div>
|
|
<div class="line"><a name="l05466"></a><span class="lineno"> 5466</span> <span class="preprocessor">#define FMC_SR3_IFEN ((uint8_t)0x20) </span></div>
|
|
<div class="line"><a name="l05467"></a><span class="lineno"> 5467</span> <span class="preprocessor">#define FMC_SR3_FEMPT ((uint8_t)0x40) </span></div>
|
|
<div class="line"><a name="l05469"></a><span class="lineno"> 5469</span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for FMC_SR4 register *******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05470"></a><span class="lineno"> 5470</span> <span class="preprocessor">#define FMC_SR4_IRS ((uint8_t)0x01) </span></div>
|
|
<div class="line"><a name="l05471"></a><span class="lineno"> 5471</span> <span class="preprocessor">#define FMC_SR4_ILS ((uint8_t)0x02) </span></div>
|
|
<div class="line"><a name="l05472"></a><span class="lineno"> 5472</span> <span class="preprocessor">#define FMC_SR4_IFS ((uint8_t)0x04) </span></div>
|
|
<div class="line"><a name="l05473"></a><span class="lineno"> 5473</span> <span class="preprocessor">#define FMC_SR4_IREN ((uint8_t)0x08) </span></div>
|
|
<div class="line"><a name="l05474"></a><span class="lineno"> 5474</span> <span class="preprocessor">#define FMC_SR4_ILEN ((uint8_t)0x10) </span></div>
|
|
<div class="line"><a name="l05475"></a><span class="lineno"> 5475</span> <span class="preprocessor">#define FMC_SR4_IFEN ((uint8_t)0x20) </span></div>
|
|
<div class="line"><a name="l05476"></a><span class="lineno"> 5476</span> <span class="preprocessor">#define FMC_SR4_FEMPT ((uint8_t)0x40) </span></div>
|
|
<div class="line"><a name="l05478"></a><span class="lineno"> 5478</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_PMEM2 register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05479"></a><span class="lineno"> 5479</span> <span class="preprocessor">#define FMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) </span></div>
|
|
<div class="line"><a name="l05480"></a><span class="lineno"> 5480</span> <span class="preprocessor">#define FMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l05481"></a><span class="lineno"> 5481</span> <span class="preprocessor">#define FMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l05482"></a><span class="lineno"> 5482</span> <span class="preprocessor">#define FMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l05483"></a><span class="lineno"> 5483</span> <span class="preprocessor">#define FMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l05484"></a><span class="lineno"> 5484</span> <span class="preprocessor">#define FMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l05485"></a><span class="lineno"> 5485</span> <span class="preprocessor">#define FMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l05486"></a><span class="lineno"> 5486</span> <span class="preprocessor">#define FMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l05487"></a><span class="lineno"> 5487</span> <span class="preprocessor">#define FMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) </span></div>
|
|
<div class="line"><a name="l05489"></a><span class="lineno"> 5489</span> <span class="preprocessor">#define FMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) </span></div>
|
|
<div class="line"><a name="l05490"></a><span class="lineno"> 5490</span> <span class="preprocessor">#define FMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l05491"></a><span class="lineno"> 5491</span> <span class="preprocessor">#define FMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l05492"></a><span class="lineno"> 5492</span> <span class="preprocessor">#define FMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l05493"></a><span class="lineno"> 5493</span> <span class="preprocessor">#define FMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l05494"></a><span class="lineno"> 5494</span> <span class="preprocessor">#define FMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l05495"></a><span class="lineno"> 5495</span> <span class="preprocessor">#define FMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l05496"></a><span class="lineno"> 5496</span> <span class="preprocessor">#define FMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l05497"></a><span class="lineno"> 5497</span> <span class="preprocessor">#define FMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) </span></div>
|
|
<div class="line"><a name="l05499"></a><span class="lineno"> 5499</span> <span class="preprocessor">#define FMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) </span></div>
|
|
<div class="line"><a name="l05500"></a><span class="lineno"> 5500</span> <span class="preprocessor">#define FMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) </span></div>
|
|
<div class="line"><a name="l05501"></a><span class="lineno"> 5501</span> <span class="preprocessor">#define FMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) </span></div>
|
|
<div class="line"><a name="l05502"></a><span class="lineno"> 5502</span> <span class="preprocessor">#define FMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) </span></div>
|
|
<div class="line"><a name="l05503"></a><span class="lineno"> 5503</span> <span class="preprocessor">#define FMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) </span></div>
|
|
<div class="line"><a name="l05504"></a><span class="lineno"> 5504</span> <span class="preprocessor">#define FMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) </span></div>
|
|
<div class="line"><a name="l05505"></a><span class="lineno"> 5505</span> <span class="preprocessor">#define FMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) </span></div>
|
|
<div class="line"><a name="l05506"></a><span class="lineno"> 5506</span> <span class="preprocessor">#define FMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) </span></div>
|
|
<div class="line"><a name="l05507"></a><span class="lineno"> 5507</span> <span class="preprocessor">#define FMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) </span></div>
|
|
<div class="line"><a name="l05509"></a><span class="lineno"> 5509</span> <span class="preprocessor">#define FMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) </span></div>
|
|
<div class="line"><a name="l05510"></a><span class="lineno"> 5510</span> <span class="preprocessor">#define FMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) </span></div>
|
|
<div class="line"><a name="l05511"></a><span class="lineno"> 5511</span> <span class="preprocessor">#define FMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) </span></div>
|
|
<div class="line"><a name="l05512"></a><span class="lineno"> 5512</span> <span class="preprocessor">#define FMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) </span></div>
|
|
<div class="line"><a name="l05513"></a><span class="lineno"> 5513</span> <span class="preprocessor">#define FMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) </span></div>
|
|
<div class="line"><a name="l05514"></a><span class="lineno"> 5514</span> <span class="preprocessor">#define FMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) </span></div>
|
|
<div class="line"><a name="l05515"></a><span class="lineno"> 5515</span> <span class="preprocessor">#define FMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) </span></div>
|
|
<div class="line"><a name="l05516"></a><span class="lineno"> 5516</span> <span class="preprocessor">#define FMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) </span></div>
|
|
<div class="line"><a name="l05517"></a><span class="lineno"> 5517</span> <span class="preprocessor">#define FMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) </span></div>
|
|
<div class="line"><a name="l05519"></a><span class="lineno"> 5519</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_PMEM3 register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05520"></a><span class="lineno"> 5520</span> <span class="preprocessor">#define FMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) </span></div>
|
|
<div class="line"><a name="l05521"></a><span class="lineno"> 5521</span> <span class="preprocessor">#define FMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l05522"></a><span class="lineno"> 5522</span> <span class="preprocessor">#define FMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l05523"></a><span class="lineno"> 5523</span> <span class="preprocessor">#define FMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l05524"></a><span class="lineno"> 5524</span> <span class="preprocessor">#define FMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l05525"></a><span class="lineno"> 5525</span> <span class="preprocessor">#define FMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l05526"></a><span class="lineno"> 5526</span> <span class="preprocessor">#define FMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l05527"></a><span class="lineno"> 5527</span> <span class="preprocessor">#define FMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l05528"></a><span class="lineno"> 5528</span> <span class="preprocessor">#define FMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) </span></div>
|
|
<div class="line"><a name="l05530"></a><span class="lineno"> 5530</span> <span class="preprocessor">#define FMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) </span></div>
|
|
<div class="line"><a name="l05531"></a><span class="lineno"> 5531</span> <span class="preprocessor">#define FMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l05532"></a><span class="lineno"> 5532</span> <span class="preprocessor">#define FMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l05533"></a><span class="lineno"> 5533</span> <span class="preprocessor">#define FMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l05534"></a><span class="lineno"> 5534</span> <span class="preprocessor">#define FMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l05535"></a><span class="lineno"> 5535</span> <span class="preprocessor">#define FMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l05536"></a><span class="lineno"> 5536</span> <span class="preprocessor">#define FMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l05537"></a><span class="lineno"> 5537</span> <span class="preprocessor">#define FMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l05538"></a><span class="lineno"> 5538</span> <span class="preprocessor">#define FMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) </span></div>
|
|
<div class="line"><a name="l05540"></a><span class="lineno"> 5540</span> <span class="preprocessor">#define FMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) </span></div>
|
|
<div class="line"><a name="l05541"></a><span class="lineno"> 5541</span> <span class="preprocessor">#define FMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) </span></div>
|
|
<div class="line"><a name="l05542"></a><span class="lineno"> 5542</span> <span class="preprocessor">#define FMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) </span></div>
|
|
<div class="line"><a name="l05543"></a><span class="lineno"> 5543</span> <span class="preprocessor">#define FMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) </span></div>
|
|
<div class="line"><a name="l05544"></a><span class="lineno"> 5544</span> <span class="preprocessor">#define FMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) </span></div>
|
|
<div class="line"><a name="l05545"></a><span class="lineno"> 5545</span> <span class="preprocessor">#define FMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) </span></div>
|
|
<div class="line"><a name="l05546"></a><span class="lineno"> 5546</span> <span class="preprocessor">#define FMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) </span></div>
|
|
<div class="line"><a name="l05547"></a><span class="lineno"> 5547</span> <span class="preprocessor">#define FMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) </span></div>
|
|
<div class="line"><a name="l05548"></a><span class="lineno"> 5548</span> <span class="preprocessor">#define FMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) </span></div>
|
|
<div class="line"><a name="l05550"></a><span class="lineno"> 5550</span> <span class="preprocessor">#define FMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) </span></div>
|
|
<div class="line"><a name="l05551"></a><span class="lineno"> 5551</span> <span class="preprocessor">#define FMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) </span></div>
|
|
<div class="line"><a name="l05552"></a><span class="lineno"> 5552</span> <span class="preprocessor">#define FMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) </span></div>
|
|
<div class="line"><a name="l05553"></a><span class="lineno"> 5553</span> <span class="preprocessor">#define FMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) </span></div>
|
|
<div class="line"><a name="l05554"></a><span class="lineno"> 5554</span> <span class="preprocessor">#define FMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) </span></div>
|
|
<div class="line"><a name="l05555"></a><span class="lineno"> 5555</span> <span class="preprocessor">#define FMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) </span></div>
|
|
<div class="line"><a name="l05556"></a><span class="lineno"> 5556</span> <span class="preprocessor">#define FMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) </span></div>
|
|
<div class="line"><a name="l05557"></a><span class="lineno"> 5557</span> <span class="preprocessor">#define FMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) </span></div>
|
|
<div class="line"><a name="l05558"></a><span class="lineno"> 5558</span> <span class="preprocessor">#define FMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) </span></div>
|
|
<div class="line"><a name="l05560"></a><span class="lineno"> 5560</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_PMEM4 register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05561"></a><span class="lineno"> 5561</span> <span class="preprocessor">#define FMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) </span></div>
|
|
<div class="line"><a name="l05562"></a><span class="lineno"> 5562</span> <span class="preprocessor">#define FMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l05563"></a><span class="lineno"> 5563</span> <span class="preprocessor">#define FMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l05564"></a><span class="lineno"> 5564</span> <span class="preprocessor">#define FMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l05565"></a><span class="lineno"> 5565</span> <span class="preprocessor">#define FMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l05566"></a><span class="lineno"> 5566</span> <span class="preprocessor">#define FMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l05567"></a><span class="lineno"> 5567</span> <span class="preprocessor">#define FMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l05568"></a><span class="lineno"> 5568</span> <span class="preprocessor">#define FMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l05569"></a><span class="lineno"> 5569</span> <span class="preprocessor">#define FMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) </span></div>
|
|
<div class="line"><a name="l05571"></a><span class="lineno"> 5571</span> <span class="preprocessor">#define FMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) </span></div>
|
|
<div class="line"><a name="l05572"></a><span class="lineno"> 5572</span> <span class="preprocessor">#define FMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l05573"></a><span class="lineno"> 5573</span> <span class="preprocessor">#define FMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l05574"></a><span class="lineno"> 5574</span> <span class="preprocessor">#define FMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l05575"></a><span class="lineno"> 5575</span> <span class="preprocessor">#define FMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l05576"></a><span class="lineno"> 5576</span> <span class="preprocessor">#define FMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l05577"></a><span class="lineno"> 5577</span> <span class="preprocessor">#define FMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l05578"></a><span class="lineno"> 5578</span> <span class="preprocessor">#define FMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l05579"></a><span class="lineno"> 5579</span> <span class="preprocessor">#define FMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) </span></div>
|
|
<div class="line"><a name="l05581"></a><span class="lineno"> 5581</span> <span class="preprocessor">#define FMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) </span></div>
|
|
<div class="line"><a name="l05582"></a><span class="lineno"> 5582</span> <span class="preprocessor">#define FMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) </span></div>
|
|
<div class="line"><a name="l05583"></a><span class="lineno"> 5583</span> <span class="preprocessor">#define FMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) </span></div>
|
|
<div class="line"><a name="l05584"></a><span class="lineno"> 5584</span> <span class="preprocessor">#define FMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) </span></div>
|
|
<div class="line"><a name="l05585"></a><span class="lineno"> 5585</span> <span class="preprocessor">#define FMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) </span></div>
|
|
<div class="line"><a name="l05586"></a><span class="lineno"> 5586</span> <span class="preprocessor">#define FMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) </span></div>
|
|
<div class="line"><a name="l05587"></a><span class="lineno"> 5587</span> <span class="preprocessor">#define FMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) </span></div>
|
|
<div class="line"><a name="l05588"></a><span class="lineno"> 5588</span> <span class="preprocessor">#define FMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) </span></div>
|
|
<div class="line"><a name="l05589"></a><span class="lineno"> 5589</span> <span class="preprocessor">#define FMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) </span></div>
|
|
<div class="line"><a name="l05591"></a><span class="lineno"> 5591</span> <span class="preprocessor">#define FMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) </span></div>
|
|
<div class="line"><a name="l05592"></a><span class="lineno"> 5592</span> <span class="preprocessor">#define FMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) </span></div>
|
|
<div class="line"><a name="l05593"></a><span class="lineno"> 5593</span> <span class="preprocessor">#define FMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) </span></div>
|
|
<div class="line"><a name="l05594"></a><span class="lineno"> 5594</span> <span class="preprocessor">#define FMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) </span></div>
|
|
<div class="line"><a name="l05595"></a><span class="lineno"> 5595</span> <span class="preprocessor">#define FMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) </span></div>
|
|
<div class="line"><a name="l05596"></a><span class="lineno"> 5596</span> <span class="preprocessor">#define FMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) </span></div>
|
|
<div class="line"><a name="l05597"></a><span class="lineno"> 5597</span> <span class="preprocessor">#define FMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) </span></div>
|
|
<div class="line"><a name="l05598"></a><span class="lineno"> 5598</span> <span class="preprocessor">#define FMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) </span></div>
|
|
<div class="line"><a name="l05599"></a><span class="lineno"> 5599</span> <span class="preprocessor">#define FMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) </span></div>
|
|
<div class="line"><a name="l05601"></a><span class="lineno"> 5601</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_PATT2 register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05602"></a><span class="lineno"> 5602</span> <span class="preprocessor">#define FMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) </span></div>
|
|
<div class="line"><a name="l05603"></a><span class="lineno"> 5603</span> <span class="preprocessor">#define FMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l05604"></a><span class="lineno"> 5604</span> <span class="preprocessor">#define FMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l05605"></a><span class="lineno"> 5605</span> <span class="preprocessor">#define FMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l05606"></a><span class="lineno"> 5606</span> <span class="preprocessor">#define FMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l05607"></a><span class="lineno"> 5607</span> <span class="preprocessor">#define FMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l05608"></a><span class="lineno"> 5608</span> <span class="preprocessor">#define FMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l05609"></a><span class="lineno"> 5609</span> <span class="preprocessor">#define FMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l05610"></a><span class="lineno"> 5610</span> <span class="preprocessor">#define FMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) </span></div>
|
|
<div class="line"><a name="l05612"></a><span class="lineno"> 5612</span> <span class="preprocessor">#define FMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) </span></div>
|
|
<div class="line"><a name="l05613"></a><span class="lineno"> 5613</span> <span class="preprocessor">#define FMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l05614"></a><span class="lineno"> 5614</span> <span class="preprocessor">#define FMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l05615"></a><span class="lineno"> 5615</span> <span class="preprocessor">#define FMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l05616"></a><span class="lineno"> 5616</span> <span class="preprocessor">#define FMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l05617"></a><span class="lineno"> 5617</span> <span class="preprocessor">#define FMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l05618"></a><span class="lineno"> 5618</span> <span class="preprocessor">#define FMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l05619"></a><span class="lineno"> 5619</span> <span class="preprocessor">#define FMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l05620"></a><span class="lineno"> 5620</span> <span class="preprocessor">#define FMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) </span></div>
|
|
<div class="line"><a name="l05622"></a><span class="lineno"> 5622</span> <span class="preprocessor">#define FMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) </span></div>
|
|
<div class="line"><a name="l05623"></a><span class="lineno"> 5623</span> <span class="preprocessor">#define FMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) </span></div>
|
|
<div class="line"><a name="l05624"></a><span class="lineno"> 5624</span> <span class="preprocessor">#define FMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) </span></div>
|
|
<div class="line"><a name="l05625"></a><span class="lineno"> 5625</span> <span class="preprocessor">#define FMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) </span></div>
|
|
<div class="line"><a name="l05626"></a><span class="lineno"> 5626</span> <span class="preprocessor">#define FMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) </span></div>
|
|
<div class="line"><a name="l05627"></a><span class="lineno"> 5627</span> <span class="preprocessor">#define FMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) </span></div>
|
|
<div class="line"><a name="l05628"></a><span class="lineno"> 5628</span> <span class="preprocessor">#define FMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) </span></div>
|
|
<div class="line"><a name="l05629"></a><span class="lineno"> 5629</span> <span class="preprocessor">#define FMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) </span></div>
|
|
<div class="line"><a name="l05630"></a><span class="lineno"> 5630</span> <span class="preprocessor">#define FMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) </span></div>
|
|
<div class="line"><a name="l05632"></a><span class="lineno"> 5632</span> <span class="preprocessor">#define FMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) </span></div>
|
|
<div class="line"><a name="l05633"></a><span class="lineno"> 5633</span> <span class="preprocessor">#define FMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) </span></div>
|
|
<div class="line"><a name="l05634"></a><span class="lineno"> 5634</span> <span class="preprocessor">#define FMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) </span></div>
|
|
<div class="line"><a name="l05635"></a><span class="lineno"> 5635</span> <span class="preprocessor">#define FMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) </span></div>
|
|
<div class="line"><a name="l05636"></a><span class="lineno"> 5636</span> <span class="preprocessor">#define FMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) </span></div>
|
|
<div class="line"><a name="l05637"></a><span class="lineno"> 5637</span> <span class="preprocessor">#define FMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) </span></div>
|
|
<div class="line"><a name="l05638"></a><span class="lineno"> 5638</span> <span class="preprocessor">#define FMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) </span></div>
|
|
<div class="line"><a name="l05639"></a><span class="lineno"> 5639</span> <span class="preprocessor">#define FMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) </span></div>
|
|
<div class="line"><a name="l05640"></a><span class="lineno"> 5640</span> <span class="preprocessor">#define FMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) </span></div>
|
|
<div class="line"><a name="l05642"></a><span class="lineno"> 5642</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_PATT3 register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05643"></a><span class="lineno"> 5643</span> <span class="preprocessor">#define FMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) </span></div>
|
|
<div class="line"><a name="l05644"></a><span class="lineno"> 5644</span> <span class="preprocessor">#define FMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l05645"></a><span class="lineno"> 5645</span> <span class="preprocessor">#define FMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l05646"></a><span class="lineno"> 5646</span> <span class="preprocessor">#define FMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l05647"></a><span class="lineno"> 5647</span> <span class="preprocessor">#define FMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l05648"></a><span class="lineno"> 5648</span> <span class="preprocessor">#define FMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l05649"></a><span class="lineno"> 5649</span> <span class="preprocessor">#define FMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l05650"></a><span class="lineno"> 5650</span> <span class="preprocessor">#define FMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l05651"></a><span class="lineno"> 5651</span> <span class="preprocessor">#define FMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) </span></div>
|
|
<div class="line"><a name="l05653"></a><span class="lineno"> 5653</span> <span class="preprocessor">#define FMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) </span></div>
|
|
<div class="line"><a name="l05654"></a><span class="lineno"> 5654</span> <span class="preprocessor">#define FMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l05655"></a><span class="lineno"> 5655</span> <span class="preprocessor">#define FMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l05656"></a><span class="lineno"> 5656</span> <span class="preprocessor">#define FMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l05657"></a><span class="lineno"> 5657</span> <span class="preprocessor">#define FMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l05658"></a><span class="lineno"> 5658</span> <span class="preprocessor">#define FMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l05659"></a><span class="lineno"> 5659</span> <span class="preprocessor">#define FMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l05660"></a><span class="lineno"> 5660</span> <span class="preprocessor">#define FMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l05661"></a><span class="lineno"> 5661</span> <span class="preprocessor">#define FMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) </span></div>
|
|
<div class="line"><a name="l05663"></a><span class="lineno"> 5663</span> <span class="preprocessor">#define FMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) </span></div>
|
|
<div class="line"><a name="l05664"></a><span class="lineno"> 5664</span> <span class="preprocessor">#define FMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) </span></div>
|
|
<div class="line"><a name="l05665"></a><span class="lineno"> 5665</span> <span class="preprocessor">#define FMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) </span></div>
|
|
<div class="line"><a name="l05666"></a><span class="lineno"> 5666</span> <span class="preprocessor">#define FMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) </span></div>
|
|
<div class="line"><a name="l05667"></a><span class="lineno"> 5667</span> <span class="preprocessor">#define FMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) </span></div>
|
|
<div class="line"><a name="l05668"></a><span class="lineno"> 5668</span> <span class="preprocessor">#define FMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) </span></div>
|
|
<div class="line"><a name="l05669"></a><span class="lineno"> 5669</span> <span class="preprocessor">#define FMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) </span></div>
|
|
<div class="line"><a name="l05670"></a><span class="lineno"> 5670</span> <span class="preprocessor">#define FMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) </span></div>
|
|
<div class="line"><a name="l05671"></a><span class="lineno"> 5671</span> <span class="preprocessor">#define FMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) </span></div>
|
|
<div class="line"><a name="l05673"></a><span class="lineno"> 5673</span> <span class="preprocessor">#define FMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) </span></div>
|
|
<div class="line"><a name="l05674"></a><span class="lineno"> 5674</span> <span class="preprocessor">#define FMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) </span></div>
|
|
<div class="line"><a name="l05675"></a><span class="lineno"> 5675</span> <span class="preprocessor">#define FMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) </span></div>
|
|
<div class="line"><a name="l05676"></a><span class="lineno"> 5676</span> <span class="preprocessor">#define FMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) </span></div>
|
|
<div class="line"><a name="l05677"></a><span class="lineno"> 5677</span> <span class="preprocessor">#define FMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) </span></div>
|
|
<div class="line"><a name="l05678"></a><span class="lineno"> 5678</span> <span class="preprocessor">#define FMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) </span></div>
|
|
<div class="line"><a name="l05679"></a><span class="lineno"> 5679</span> <span class="preprocessor">#define FMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) </span></div>
|
|
<div class="line"><a name="l05680"></a><span class="lineno"> 5680</span> <span class="preprocessor">#define FMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) </span></div>
|
|
<div class="line"><a name="l05681"></a><span class="lineno"> 5681</span> <span class="preprocessor">#define FMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) </span></div>
|
|
<div class="line"><a name="l05683"></a><span class="lineno"> 5683</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_PATT4 register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05684"></a><span class="lineno"> 5684</span> <span class="preprocessor">#define FMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) </span></div>
|
|
<div class="line"><a name="l05685"></a><span class="lineno"> 5685</span> <span class="preprocessor">#define FMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l05686"></a><span class="lineno"> 5686</span> <span class="preprocessor">#define FMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l05687"></a><span class="lineno"> 5687</span> <span class="preprocessor">#define FMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l05688"></a><span class="lineno"> 5688</span> <span class="preprocessor">#define FMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l05689"></a><span class="lineno"> 5689</span> <span class="preprocessor">#define FMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l05690"></a><span class="lineno"> 5690</span> <span class="preprocessor">#define FMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l05691"></a><span class="lineno"> 5691</span> <span class="preprocessor">#define FMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l05692"></a><span class="lineno"> 5692</span> <span class="preprocessor">#define FMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) </span></div>
|
|
<div class="line"><a name="l05694"></a><span class="lineno"> 5694</span> <span class="preprocessor">#define FMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) </span></div>
|
|
<div class="line"><a name="l05695"></a><span class="lineno"> 5695</span> <span class="preprocessor">#define FMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l05696"></a><span class="lineno"> 5696</span> <span class="preprocessor">#define FMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l05697"></a><span class="lineno"> 5697</span> <span class="preprocessor">#define FMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l05698"></a><span class="lineno"> 5698</span> <span class="preprocessor">#define FMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l05699"></a><span class="lineno"> 5699</span> <span class="preprocessor">#define FMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l05700"></a><span class="lineno"> 5700</span> <span class="preprocessor">#define FMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l05701"></a><span class="lineno"> 5701</span> <span class="preprocessor">#define FMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l05702"></a><span class="lineno"> 5702</span> <span class="preprocessor">#define FMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) </span></div>
|
|
<div class="line"><a name="l05704"></a><span class="lineno"> 5704</span> <span class="preprocessor">#define FMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) </span></div>
|
|
<div class="line"><a name="l05705"></a><span class="lineno"> 5705</span> <span class="preprocessor">#define FMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) </span></div>
|
|
<div class="line"><a name="l05706"></a><span class="lineno"> 5706</span> <span class="preprocessor">#define FMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) </span></div>
|
|
<div class="line"><a name="l05707"></a><span class="lineno"> 5707</span> <span class="preprocessor">#define FMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) </span></div>
|
|
<div class="line"><a name="l05708"></a><span class="lineno"> 5708</span> <span class="preprocessor">#define FMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) </span></div>
|
|
<div class="line"><a name="l05709"></a><span class="lineno"> 5709</span> <span class="preprocessor">#define FMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) </span></div>
|
|
<div class="line"><a name="l05710"></a><span class="lineno"> 5710</span> <span class="preprocessor">#define FMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) </span></div>
|
|
<div class="line"><a name="l05711"></a><span class="lineno"> 5711</span> <span class="preprocessor">#define FMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) </span></div>
|
|
<div class="line"><a name="l05712"></a><span class="lineno"> 5712</span> <span class="preprocessor">#define FMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) </span></div>
|
|
<div class="line"><a name="l05714"></a><span class="lineno"> 5714</span> <span class="preprocessor">#define FMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) </span></div>
|
|
<div class="line"><a name="l05715"></a><span class="lineno"> 5715</span> <span class="preprocessor">#define FMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) </span></div>
|
|
<div class="line"><a name="l05716"></a><span class="lineno"> 5716</span> <span class="preprocessor">#define FMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) </span></div>
|
|
<div class="line"><a name="l05717"></a><span class="lineno"> 5717</span> <span class="preprocessor">#define FMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) </span></div>
|
|
<div class="line"><a name="l05718"></a><span class="lineno"> 5718</span> <span class="preprocessor">#define FMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) </span></div>
|
|
<div class="line"><a name="l05719"></a><span class="lineno"> 5719</span> <span class="preprocessor">#define FMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) </span></div>
|
|
<div class="line"><a name="l05720"></a><span class="lineno"> 5720</span> <span class="preprocessor">#define FMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) </span></div>
|
|
<div class="line"><a name="l05721"></a><span class="lineno"> 5721</span> <span class="preprocessor">#define FMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) </span></div>
|
|
<div class="line"><a name="l05722"></a><span class="lineno"> 5722</span> <span class="preprocessor">#define FMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) </span></div>
|
|
<div class="line"><a name="l05724"></a><span class="lineno"> 5724</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_PIO4 register *******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05725"></a><span class="lineno"> 5725</span> <span class="preprocessor">#define FMC_PIO4_IOSET4 ((uint32_t)0x000000FF) </span></div>
|
|
<div class="line"><a name="l05726"></a><span class="lineno"> 5726</span> <span class="preprocessor">#define FMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l05727"></a><span class="lineno"> 5727</span> <span class="preprocessor">#define FMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l05728"></a><span class="lineno"> 5728</span> <span class="preprocessor">#define FMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l05729"></a><span class="lineno"> 5729</span> <span class="preprocessor">#define FMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l05730"></a><span class="lineno"> 5730</span> <span class="preprocessor">#define FMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l05731"></a><span class="lineno"> 5731</span> <span class="preprocessor">#define FMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l05732"></a><span class="lineno"> 5732</span> <span class="preprocessor">#define FMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l05733"></a><span class="lineno"> 5733</span> <span class="preprocessor">#define FMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) </span></div>
|
|
<div class="line"><a name="l05735"></a><span class="lineno"> 5735</span> <span class="preprocessor">#define FMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) </span></div>
|
|
<div class="line"><a name="l05736"></a><span class="lineno"> 5736</span> <span class="preprocessor">#define FMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l05737"></a><span class="lineno"> 5737</span> <span class="preprocessor">#define FMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l05738"></a><span class="lineno"> 5738</span> <span class="preprocessor">#define FMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l05739"></a><span class="lineno"> 5739</span> <span class="preprocessor">#define FMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l05740"></a><span class="lineno"> 5740</span> <span class="preprocessor">#define FMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l05741"></a><span class="lineno"> 5741</span> <span class="preprocessor">#define FMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l05742"></a><span class="lineno"> 5742</span> <span class="preprocessor">#define FMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l05743"></a><span class="lineno"> 5743</span> <span class="preprocessor">#define FMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) </span></div>
|
|
<div class="line"><a name="l05745"></a><span class="lineno"> 5745</span> <span class="preprocessor">#define FMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) </span></div>
|
|
<div class="line"><a name="l05746"></a><span class="lineno"> 5746</span> <span class="preprocessor">#define FMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) </span></div>
|
|
<div class="line"><a name="l05747"></a><span class="lineno"> 5747</span> <span class="preprocessor">#define FMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) </span></div>
|
|
<div class="line"><a name="l05748"></a><span class="lineno"> 5748</span> <span class="preprocessor">#define FMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) </span></div>
|
|
<div class="line"><a name="l05749"></a><span class="lineno"> 5749</span> <span class="preprocessor">#define FMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) </span></div>
|
|
<div class="line"><a name="l05750"></a><span class="lineno"> 5750</span> <span class="preprocessor">#define FMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) </span></div>
|
|
<div class="line"><a name="l05751"></a><span class="lineno"> 5751</span> <span class="preprocessor">#define FMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) </span></div>
|
|
<div class="line"><a name="l05752"></a><span class="lineno"> 5752</span> <span class="preprocessor">#define FMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) </span></div>
|
|
<div class="line"><a name="l05753"></a><span class="lineno"> 5753</span> <span class="preprocessor">#define FMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) </span></div>
|
|
<div class="line"><a name="l05755"></a><span class="lineno"> 5755</span> <span class="preprocessor">#define FMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) </span></div>
|
|
<div class="line"><a name="l05756"></a><span class="lineno"> 5756</span> <span class="preprocessor">#define FMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) </span></div>
|
|
<div class="line"><a name="l05757"></a><span class="lineno"> 5757</span> <span class="preprocessor">#define FMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) </span></div>
|
|
<div class="line"><a name="l05758"></a><span class="lineno"> 5758</span> <span class="preprocessor">#define FMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) </span></div>
|
|
<div class="line"><a name="l05759"></a><span class="lineno"> 5759</span> <span class="preprocessor">#define FMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) </span></div>
|
|
<div class="line"><a name="l05760"></a><span class="lineno"> 5760</span> <span class="preprocessor">#define FMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) </span></div>
|
|
<div class="line"><a name="l05761"></a><span class="lineno"> 5761</span> <span class="preprocessor">#define FMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) </span></div>
|
|
<div class="line"><a name="l05762"></a><span class="lineno"> 5762</span> <span class="preprocessor">#define FMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) </span></div>
|
|
<div class="line"><a name="l05763"></a><span class="lineno"> 5763</span> <span class="preprocessor">#define FMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) </span></div>
|
|
<div class="line"><a name="l05765"></a><span class="lineno"> 5765</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_ECCR2 register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05766"></a><span class="lineno"> 5766</span> <span class="preprocessor">#define FMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) </span></div>
|
|
<div class="line"><a name="l05768"></a><span class="lineno"> 5768</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_ECCR3 register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05769"></a><span class="lineno"> 5769</span> <span class="preprocessor">#define FMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) </span></div>
|
|
<div class="line"><a name="l05771"></a><span class="lineno"> 5771</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_SDCR1 register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05772"></a><span class="lineno"> 5772</span> <span class="preprocessor">#define FMC_SDCR1_NC ((uint32_t)0x00000003) </span></div>
|
|
<div class="line"><a name="l05773"></a><span class="lineno"> 5773</span> <span class="preprocessor">#define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l05774"></a><span class="lineno"> 5774</span> <span class="preprocessor">#define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l05776"></a><span class="lineno"> 5776</span> <span class="preprocessor">#define FMC_SDCR1_NR ((uint32_t)0x0000000C) </span></div>
|
|
<div class="line"><a name="l05777"></a><span class="lineno"> 5777</span> <span class="preprocessor">#define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l05778"></a><span class="lineno"> 5778</span> <span class="preprocessor">#define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l05780"></a><span class="lineno"> 5780</span> <span class="preprocessor">#define FMC_SDCR1_MWID ((uint32_t)0x00000030) </span></div>
|
|
<div class="line"><a name="l05781"></a><span class="lineno"> 5781</span> <span class="preprocessor">#define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l05782"></a><span class="lineno"> 5782</span> <span class="preprocessor">#define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l05784"></a><span class="lineno"> 5784</span> <span class="preprocessor">#define FMC_SDCR1_NB ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l05786"></a><span class="lineno"> 5786</span> <span class="preprocessor">#define FMC_SDCR1_CAS ((uint32_t)0x00000180) </span></div>
|
|
<div class="line"><a name="l05787"></a><span class="lineno"> 5787</span> <span class="preprocessor">#define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) </span></div>
|
|
<div class="line"><a name="l05788"></a><span class="lineno"> 5788</span> <span class="preprocessor">#define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l05790"></a><span class="lineno"> 5790</span> <span class="preprocessor">#define FMC_SDCR1_WP ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l05792"></a><span class="lineno"> 5792</span> <span class="preprocessor">#define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) </span></div>
|
|
<div class="line"><a name="l05793"></a><span class="lineno"> 5793</span> <span class="preprocessor">#define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l05794"></a><span class="lineno"> 5794</span> <span class="preprocessor">#define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l05796"></a><span class="lineno"> 5796</span> <span class="preprocessor">#define FMC_SDCR1_RBURST ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l05798"></a><span class="lineno"> 5798</span> <span class="preprocessor">#define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) </span></div>
|
|
<div class="line"><a name="l05799"></a><span class="lineno"> 5799</span> <span class="preprocessor">#define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l05800"></a><span class="lineno"> 5800</span> <span class="preprocessor">#define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l05802"></a><span class="lineno"> 5802</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_SDCR2 register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05803"></a><span class="lineno"> 5803</span> <span class="preprocessor">#define FMC_SDCR2_NC ((uint32_t)0x00000003) </span></div>
|
|
<div class="line"><a name="l05804"></a><span class="lineno"> 5804</span> <span class="preprocessor">#define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l05805"></a><span class="lineno"> 5805</span> <span class="preprocessor">#define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l05807"></a><span class="lineno"> 5807</span> <span class="preprocessor">#define FMC_SDCR2_NR ((uint32_t)0x0000000C) </span></div>
|
|
<div class="line"><a name="l05808"></a><span class="lineno"> 5808</span> <span class="preprocessor">#define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l05809"></a><span class="lineno"> 5809</span> <span class="preprocessor">#define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l05811"></a><span class="lineno"> 5811</span> <span class="preprocessor">#define FMC_SDCR2_MWID ((uint32_t)0x00000030) </span></div>
|
|
<div class="line"><a name="l05812"></a><span class="lineno"> 5812</span> <span class="preprocessor">#define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l05813"></a><span class="lineno"> 5813</span> <span class="preprocessor">#define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l05815"></a><span class="lineno"> 5815</span> <span class="preprocessor">#define FMC_SDCR2_NB ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l05817"></a><span class="lineno"> 5817</span> <span class="preprocessor">#define FMC_SDCR2_CAS ((uint32_t)0x00000180) </span></div>
|
|
<div class="line"><a name="l05818"></a><span class="lineno"> 5818</span> <span class="preprocessor">#define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) </span></div>
|
|
<div class="line"><a name="l05819"></a><span class="lineno"> 5819</span> <span class="preprocessor">#define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l05821"></a><span class="lineno"> 5821</span> <span class="preprocessor">#define FMC_SDCR2_WP ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l05823"></a><span class="lineno"> 5823</span> <span class="preprocessor">#define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) </span></div>
|
|
<div class="line"><a name="l05824"></a><span class="lineno"> 5824</span> <span class="preprocessor">#define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l05825"></a><span class="lineno"> 5825</span> <span class="preprocessor">#define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l05827"></a><span class="lineno"> 5827</span> <span class="preprocessor">#define FMC_SDCR2_RBURST ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l05829"></a><span class="lineno"> 5829</span> <span class="preprocessor">#define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) </span></div>
|
|
<div class="line"><a name="l05830"></a><span class="lineno"> 5830</span> <span class="preprocessor">#define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l05831"></a><span class="lineno"> 5831</span> <span class="preprocessor">#define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l05833"></a><span class="lineno"> 5833</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_SDTR1 register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05834"></a><span class="lineno"> 5834</span> <span class="preprocessor">#define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) </span></div>
|
|
<div class="line"><a name="l05835"></a><span class="lineno"> 5835</span> <span class="preprocessor">#define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l05836"></a><span class="lineno"> 5836</span> <span class="preprocessor">#define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l05837"></a><span class="lineno"> 5837</span> <span class="preprocessor">#define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l05838"></a><span class="lineno"> 5838</span> <span class="preprocessor">#define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l05840"></a><span class="lineno"> 5840</span> <span class="preprocessor">#define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) </span></div>
|
|
<div class="line"><a name="l05841"></a><span class="lineno"> 5841</span> <span class="preprocessor">#define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l05842"></a><span class="lineno"> 5842</span> <span class="preprocessor">#define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l05843"></a><span class="lineno"> 5843</span> <span class="preprocessor">#define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l05844"></a><span class="lineno"> 5844</span> <span class="preprocessor">#define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) </span></div>
|
|
<div class="line"><a name="l05846"></a><span class="lineno"> 5846</span> <span class="preprocessor">#define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) </span></div>
|
|
<div class="line"><a name="l05847"></a><span class="lineno"> 5847</span> <span class="preprocessor">#define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l05848"></a><span class="lineno"> 5848</span> <span class="preprocessor">#define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l05849"></a><span class="lineno"> 5849</span> <span class="preprocessor">#define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l05850"></a><span class="lineno"> 5850</span> <span class="preprocessor">#define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l05852"></a><span class="lineno"> 5852</span> <span class="preprocessor">#define FMC_SDTR1_TRC ((uint32_t)0x0000F000) </span></div>
|
|
<div class="line"><a name="l05853"></a><span class="lineno"> 5853</span> <span class="preprocessor">#define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l05854"></a><span class="lineno"> 5854</span> <span class="preprocessor">#define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l05855"></a><span class="lineno"> 5855</span> <span class="preprocessor">#define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l05857"></a><span class="lineno"> 5857</span> <span class="preprocessor">#define FMC_SDTR1_TWR ((uint32_t)0x000F0000) </span></div>
|
|
<div class="line"><a name="l05858"></a><span class="lineno"> 5858</span> <span class="preprocessor">#define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) </span></div>
|
|
<div class="line"><a name="l05859"></a><span class="lineno"> 5859</span> <span class="preprocessor">#define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) </span></div>
|
|
<div class="line"><a name="l05860"></a><span class="lineno"> 5860</span> <span class="preprocessor">#define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) </span></div>
|
|
<div class="line"><a name="l05862"></a><span class="lineno"> 5862</span> <span class="preprocessor">#define FMC_SDTR1_TRP ((uint32_t)0x00F00000) </span></div>
|
|
<div class="line"><a name="l05863"></a><span class="lineno"> 5863</span> <span class="preprocessor">#define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) </span></div>
|
|
<div class="line"><a name="l05864"></a><span class="lineno"> 5864</span> <span class="preprocessor">#define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) </span></div>
|
|
<div class="line"><a name="l05865"></a><span class="lineno"> 5865</span> <span class="preprocessor">#define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) </span></div>
|
|
<div class="line"><a name="l05867"></a><span class="lineno"> 5867</span> <span class="preprocessor">#define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) </span></div>
|
|
<div class="line"><a name="l05868"></a><span class="lineno"> 5868</span> <span class="preprocessor">#define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) </span></div>
|
|
<div class="line"><a name="l05869"></a><span class="lineno"> 5869</span> <span class="preprocessor">#define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) </span></div>
|
|
<div class="line"><a name="l05870"></a><span class="lineno"> 5870</span> <span class="preprocessor">#define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) </span></div>
|
|
<div class="line"><a name="l05872"></a><span class="lineno"> 5872</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_SDTR2 register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05873"></a><span class="lineno"> 5873</span> <span class="preprocessor">#define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) </span></div>
|
|
<div class="line"><a name="l05874"></a><span class="lineno"> 5874</span> <span class="preprocessor">#define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l05875"></a><span class="lineno"> 5875</span> <span class="preprocessor">#define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l05876"></a><span class="lineno"> 5876</span> <span class="preprocessor">#define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l05877"></a><span class="lineno"> 5877</span> <span class="preprocessor">#define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l05879"></a><span class="lineno"> 5879</span> <span class="preprocessor">#define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) </span></div>
|
|
<div class="line"><a name="l05880"></a><span class="lineno"> 5880</span> <span class="preprocessor">#define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l05881"></a><span class="lineno"> 5881</span> <span class="preprocessor">#define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l05882"></a><span class="lineno"> 5882</span> <span class="preprocessor">#define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l05883"></a><span class="lineno"> 5883</span> <span class="preprocessor">#define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) </span></div>
|
|
<div class="line"><a name="l05885"></a><span class="lineno"> 5885</span> <span class="preprocessor">#define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) </span></div>
|
|
<div class="line"><a name="l05886"></a><span class="lineno"> 5886</span> <span class="preprocessor">#define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l05887"></a><span class="lineno"> 5887</span> <span class="preprocessor">#define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l05888"></a><span class="lineno"> 5888</span> <span class="preprocessor">#define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l05889"></a><span class="lineno"> 5889</span> <span class="preprocessor">#define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l05891"></a><span class="lineno"> 5891</span> <span class="preprocessor">#define FMC_SDTR2_TRC ((uint32_t)0x0000F000) </span></div>
|
|
<div class="line"><a name="l05892"></a><span class="lineno"> 5892</span> <span class="preprocessor">#define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l05893"></a><span class="lineno"> 5893</span> <span class="preprocessor">#define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l05894"></a><span class="lineno"> 5894</span> <span class="preprocessor">#define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l05896"></a><span class="lineno"> 5896</span> <span class="preprocessor">#define FMC_SDTR2_TWR ((uint32_t)0x000F0000) </span></div>
|
|
<div class="line"><a name="l05897"></a><span class="lineno"> 5897</span> <span class="preprocessor">#define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) </span></div>
|
|
<div class="line"><a name="l05898"></a><span class="lineno"> 5898</span> <span class="preprocessor">#define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) </span></div>
|
|
<div class="line"><a name="l05899"></a><span class="lineno"> 5899</span> <span class="preprocessor">#define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) </span></div>
|
|
<div class="line"><a name="l05901"></a><span class="lineno"> 5901</span> <span class="preprocessor">#define FMC_SDTR2_TRP ((uint32_t)0x00F00000) </span></div>
|
|
<div class="line"><a name="l05902"></a><span class="lineno"> 5902</span> <span class="preprocessor">#define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) </span></div>
|
|
<div class="line"><a name="l05903"></a><span class="lineno"> 5903</span> <span class="preprocessor">#define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) </span></div>
|
|
<div class="line"><a name="l05904"></a><span class="lineno"> 5904</span> <span class="preprocessor">#define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) </span></div>
|
|
<div class="line"><a name="l05906"></a><span class="lineno"> 5906</span> <span class="preprocessor">#define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) </span></div>
|
|
<div class="line"><a name="l05907"></a><span class="lineno"> 5907</span> <span class="preprocessor">#define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) </span></div>
|
|
<div class="line"><a name="l05908"></a><span class="lineno"> 5908</span> <span class="preprocessor">#define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) </span></div>
|
|
<div class="line"><a name="l05909"></a><span class="lineno"> 5909</span> <span class="preprocessor">#define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) </span></div>
|
|
<div class="line"><a name="l05911"></a><span class="lineno"> 5911</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_SDCMR register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05912"></a><span class="lineno"> 5912</span> <span class="preprocessor">#define FMC_SDCMR_MODE ((uint32_t)0x00000007) </span></div>
|
|
<div class="line"><a name="l05913"></a><span class="lineno"> 5913</span> <span class="preprocessor">#define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l05914"></a><span class="lineno"> 5914</span> <span class="preprocessor">#define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l05915"></a><span class="lineno"> 5915</span> <span class="preprocessor">#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) </span></div>
|
|
<div class="line"><a name="l05917"></a><span class="lineno"> 5917</span> <span class="preprocessor">#define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l05919"></a><span class="lineno"> 5919</span> <span class="preprocessor">#define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l05921"></a><span class="lineno"> 5921</span> <span class="preprocessor">#define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) </span></div>
|
|
<div class="line"><a name="l05922"></a><span class="lineno"> 5922</span> <span class="preprocessor">#define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l05923"></a><span class="lineno"> 5923</span> <span class="preprocessor">#define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l05924"></a><span class="lineno"> 5924</span> <span class="preprocessor">#define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) </span></div>
|
|
<div class="line"><a name="l05925"></a><span class="lineno"> 5925</span> <span class="preprocessor">#define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l05927"></a><span class="lineno"> 5927</span> <span class="preprocessor">#define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) </span></div>
|
|
<div class="line"><a name="l05929"></a><span class="lineno"> 5929</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_SDRTR register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05930"></a><span class="lineno"> 5930</span> <span class="preprocessor">#define FMC_SDRTR_CRE ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l05932"></a><span class="lineno"> 5932</span> <span class="preprocessor">#define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) </span></div>
|
|
<div class="line"><a name="l05934"></a><span class="lineno"> 5934</span> <span class="preprocessor">#define FMC_SDRTR_REIE ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l05936"></a><span class="lineno"> 5936</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for FMC_SDSR register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05937"></a><span class="lineno"> 5937</span> <span class="preprocessor">#define FMC_SDSR_RE ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l05939"></a><span class="lineno"> 5939</span> <span class="preprocessor">#define FMC_SDSR_MODES1 ((uint32_t)0x00000006) </span></div>
|
|
<div class="line"><a name="l05940"></a><span class="lineno"> 5940</span> <span class="preprocessor">#define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l05941"></a><span class="lineno"> 5941</span> <span class="preprocessor">#define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l05943"></a><span class="lineno"> 5943</span> <span class="preprocessor">#define FMC_SDSR_MODES2 ((uint32_t)0x00000018) </span></div>
|
|
<div class="line"><a name="l05944"></a><span class="lineno"> 5944</span> <span class="preprocessor">#define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l05945"></a><span class="lineno"> 5945</span> <span class="preprocessor">#define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l05947"></a><span class="lineno"> 5947</span> <span class="preprocessor">#define FMC_SDSR_BUSY ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l05949"></a><span class="lineno"> 5949</span> <span class="preprocessor">#endif </span><span class="comment">/* STM32F427_437xx || STM32F429_439xx */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l05950"></a><span class="lineno"> 5950</span> </div>
|
|
<div class="line"><a name="l05951"></a><span class="lineno"> 5951</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l05952"></a><span class="lineno"> 5952</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l05953"></a><span class="lineno"> 5953</span> <span class="comment">/* General Purpose I/O */</span></div>
|
|
<div class="line"><a name="l05954"></a><span class="lineno"> 5954</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l05955"></a><span class="lineno"> 5955</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l05956"></a><span class="lineno"> 5956</span> <span class="comment">/****************** Bits definition for GPIO_MODER register *****************/</span></div>
|
|
<div class="line"><a name="l05957"></a><span class="lineno"> 5957</span> <span class="preprocessor">#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)</span></div>
|
|
<div class="line"><a name="l05958"></a><span class="lineno"> 5958</span> <span class="preprocessor">#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l05959"></a><span class="lineno"> 5959</span> <span class="preprocessor">#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l05960"></a><span class="lineno"> 5960</span> </div>
|
|
<div class="line"><a name="l05961"></a><span class="lineno"> 5961</span> <span class="preprocessor">#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)</span></div>
|
|
<div class="line"><a name="l05962"></a><span class="lineno"> 5962</span> <span class="preprocessor">#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l05963"></a><span class="lineno"> 5963</span> <span class="preprocessor">#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l05964"></a><span class="lineno"> 5964</span> </div>
|
|
<div class="line"><a name="l05965"></a><span class="lineno"> 5965</span> <span class="preprocessor">#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)</span></div>
|
|
<div class="line"><a name="l05966"></a><span class="lineno"> 5966</span> <span class="preprocessor">#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l05967"></a><span class="lineno"> 5967</span> <span class="preprocessor">#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l05968"></a><span class="lineno"> 5968</span> </div>
|
|
<div class="line"><a name="l05969"></a><span class="lineno"> 5969</span> <span class="preprocessor">#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)</span></div>
|
|
<div class="line"><a name="l05970"></a><span class="lineno"> 5970</span> <span class="preprocessor">#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l05971"></a><span class="lineno"> 5971</span> <span class="preprocessor">#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)</span></div>
|
|
<div class="line"><a name="l05972"></a><span class="lineno"> 5972</span> </div>
|
|
<div class="line"><a name="l05973"></a><span class="lineno"> 5973</span> <span class="preprocessor">#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)</span></div>
|
|
<div class="line"><a name="l05974"></a><span class="lineno"> 5974</span> <span class="preprocessor">#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l05975"></a><span class="lineno"> 5975</span> <span class="preprocessor">#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l05976"></a><span class="lineno"> 5976</span> </div>
|
|
<div class="line"><a name="l05977"></a><span class="lineno"> 5977</span> <span class="preprocessor">#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)</span></div>
|
|
<div class="line"><a name="l05978"></a><span class="lineno"> 5978</span> <span class="preprocessor">#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l05979"></a><span class="lineno"> 5979</span> <span class="preprocessor">#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l05980"></a><span class="lineno"> 5980</span> </div>
|
|
<div class="line"><a name="l05981"></a><span class="lineno"> 5981</span> <span class="preprocessor">#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)</span></div>
|
|
<div class="line"><a name="l05982"></a><span class="lineno"> 5982</span> <span class="preprocessor">#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)</span></div>
|
|
<div class="line"><a name="l05983"></a><span class="lineno"> 5983</span> <span class="preprocessor">#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)</span></div>
|
|
<div class="line"><a name="l05984"></a><span class="lineno"> 5984</span> </div>
|
|
<div class="line"><a name="l05985"></a><span class="lineno"> 5985</span> <span class="preprocessor">#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)</span></div>
|
|
<div class="line"><a name="l05986"></a><span class="lineno"> 5986</span> <span class="preprocessor">#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)</span></div>
|
|
<div class="line"><a name="l05987"></a><span class="lineno"> 5987</span> <span class="preprocessor">#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)</span></div>
|
|
<div class="line"><a name="l05988"></a><span class="lineno"> 5988</span> </div>
|
|
<div class="line"><a name="l05989"></a><span class="lineno"> 5989</span> <span class="preprocessor">#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)</span></div>
|
|
<div class="line"><a name="l05990"></a><span class="lineno"> 5990</span> <span class="preprocessor">#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)</span></div>
|
|
<div class="line"><a name="l05991"></a><span class="lineno"> 5991</span> <span class="preprocessor">#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)</span></div>
|
|
<div class="line"><a name="l05992"></a><span class="lineno"> 5992</span> </div>
|
|
<div class="line"><a name="l05993"></a><span class="lineno"> 5993</span> <span class="preprocessor">#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)</span></div>
|
|
<div class="line"><a name="l05994"></a><span class="lineno"> 5994</span> <span class="preprocessor">#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)</span></div>
|
|
<div class="line"><a name="l05995"></a><span class="lineno"> 5995</span> <span class="preprocessor">#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)</span></div>
|
|
<div class="line"><a name="l05996"></a><span class="lineno"> 5996</span> </div>
|
|
<div class="line"><a name="l05997"></a><span class="lineno"> 5997</span> <span class="preprocessor">#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)</span></div>
|
|
<div class="line"><a name="l05998"></a><span class="lineno"> 5998</span> <span class="preprocessor">#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)</span></div>
|
|
<div class="line"><a name="l05999"></a><span class="lineno"> 5999</span> <span class="preprocessor">#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)</span></div>
|
|
<div class="line"><a name="l06000"></a><span class="lineno"> 6000</span> </div>
|
|
<div class="line"><a name="l06001"></a><span class="lineno"> 6001</span> <span class="preprocessor">#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)</span></div>
|
|
<div class="line"><a name="l06002"></a><span class="lineno"> 6002</span> <span class="preprocessor">#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)</span></div>
|
|
<div class="line"><a name="l06003"></a><span class="lineno"> 6003</span> <span class="preprocessor">#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)</span></div>
|
|
<div class="line"><a name="l06004"></a><span class="lineno"> 6004</span> </div>
|
|
<div class="line"><a name="l06005"></a><span class="lineno"> 6005</span> <span class="preprocessor">#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)</span></div>
|
|
<div class="line"><a name="l06006"></a><span class="lineno"> 6006</span> <span class="preprocessor">#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)</span></div>
|
|
<div class="line"><a name="l06007"></a><span class="lineno"> 6007</span> <span class="preprocessor">#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)</span></div>
|
|
<div class="line"><a name="l06008"></a><span class="lineno"> 6008</span> </div>
|
|
<div class="line"><a name="l06009"></a><span class="lineno"> 6009</span> <span class="preprocessor">#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)</span></div>
|
|
<div class="line"><a name="l06010"></a><span class="lineno"> 6010</span> <span class="preprocessor">#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)</span></div>
|
|
<div class="line"><a name="l06011"></a><span class="lineno"> 6011</span> <span class="preprocessor">#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)</span></div>
|
|
<div class="line"><a name="l06012"></a><span class="lineno"> 6012</span> </div>
|
|
<div class="line"><a name="l06013"></a><span class="lineno"> 6013</span> <span class="preprocessor">#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)</span></div>
|
|
<div class="line"><a name="l06014"></a><span class="lineno"> 6014</span> <span class="preprocessor">#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)</span></div>
|
|
<div class="line"><a name="l06015"></a><span class="lineno"> 6015</span> <span class="preprocessor">#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)</span></div>
|
|
<div class="line"><a name="l06016"></a><span class="lineno"> 6016</span> </div>
|
|
<div class="line"><a name="l06017"></a><span class="lineno"> 6017</span> <span class="preprocessor">#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)</span></div>
|
|
<div class="line"><a name="l06018"></a><span class="lineno"> 6018</span> <span class="preprocessor">#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)</span></div>
|
|
<div class="line"><a name="l06019"></a><span class="lineno"> 6019</span> <span class="preprocessor">#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)</span></div>
|
|
<div class="line"><a name="l06020"></a><span class="lineno"> 6020</span> </div>
|
|
<div class="line"><a name="l06021"></a><span class="lineno"> 6021</span> <span class="comment">/****************** Bits definition for GPIO_OTYPER register ****************/</span></div>
|
|
<div class="line"><a name="l06022"></a><span class="lineno"> 6022</span> <span class="preprocessor">#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l06023"></a><span class="lineno"> 6023</span> <span class="preprocessor">#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l06024"></a><span class="lineno"> 6024</span> <span class="preprocessor">#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l06025"></a><span class="lineno"> 6025</span> <span class="preprocessor">#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l06026"></a><span class="lineno"> 6026</span> <span class="preprocessor">#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l06027"></a><span class="lineno"> 6027</span> <span class="preprocessor">#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l06028"></a><span class="lineno"> 6028</span> <span class="preprocessor">#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l06029"></a><span class="lineno"> 6029</span> <span class="preprocessor">#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)</span></div>
|
|
<div class="line"><a name="l06030"></a><span class="lineno"> 6030</span> <span class="preprocessor">#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l06031"></a><span class="lineno"> 6031</span> <span class="preprocessor">#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l06032"></a><span class="lineno"> 6032</span> <span class="preprocessor">#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l06033"></a><span class="lineno"> 6033</span> <span class="preprocessor">#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l06034"></a><span class="lineno"> 6034</span> <span class="preprocessor">#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)</span></div>
|
|
<div class="line"><a name="l06035"></a><span class="lineno"> 6035</span> <span class="preprocessor">#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)</span></div>
|
|
<div class="line"><a name="l06036"></a><span class="lineno"> 6036</span> <span class="preprocessor">#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)</span></div>
|
|
<div class="line"><a name="l06037"></a><span class="lineno"> 6037</span> <span class="preprocessor">#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)</span></div>
|
|
<div class="line"><a name="l06038"></a><span class="lineno"> 6038</span> </div>
|
|
<div class="line"><a name="l06039"></a><span class="lineno"> 6039</span> <span class="comment">/****************** Bits definition for GPIO_OSPEEDR register ***************/</span></div>
|
|
<div class="line"><a name="l06040"></a><span class="lineno"> 6040</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)</span></div>
|
|
<div class="line"><a name="l06041"></a><span class="lineno"> 6041</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l06042"></a><span class="lineno"> 6042</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l06043"></a><span class="lineno"> 6043</span> </div>
|
|
<div class="line"><a name="l06044"></a><span class="lineno"> 6044</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)</span></div>
|
|
<div class="line"><a name="l06045"></a><span class="lineno"> 6045</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l06046"></a><span class="lineno"> 6046</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l06047"></a><span class="lineno"> 6047</span> </div>
|
|
<div class="line"><a name="l06048"></a><span class="lineno"> 6048</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)</span></div>
|
|
<div class="line"><a name="l06049"></a><span class="lineno"> 6049</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l06050"></a><span class="lineno"> 6050</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l06051"></a><span class="lineno"> 6051</span> </div>
|
|
<div class="line"><a name="l06052"></a><span class="lineno"> 6052</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)</span></div>
|
|
<div class="line"><a name="l06053"></a><span class="lineno"> 6053</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l06054"></a><span class="lineno"> 6054</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)</span></div>
|
|
<div class="line"><a name="l06055"></a><span class="lineno"> 6055</span> </div>
|
|
<div class="line"><a name="l06056"></a><span class="lineno"> 6056</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)</span></div>
|
|
<div class="line"><a name="l06057"></a><span class="lineno"> 6057</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l06058"></a><span class="lineno"> 6058</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l06059"></a><span class="lineno"> 6059</span> </div>
|
|
<div class="line"><a name="l06060"></a><span class="lineno"> 6060</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)</span></div>
|
|
<div class="line"><a name="l06061"></a><span class="lineno"> 6061</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l06062"></a><span class="lineno"> 6062</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l06063"></a><span class="lineno"> 6063</span> </div>
|
|
<div class="line"><a name="l06064"></a><span class="lineno"> 6064</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)</span></div>
|
|
<div class="line"><a name="l06065"></a><span class="lineno"> 6065</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)</span></div>
|
|
<div class="line"><a name="l06066"></a><span class="lineno"> 6066</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)</span></div>
|
|
<div class="line"><a name="l06067"></a><span class="lineno"> 6067</span> </div>
|
|
<div class="line"><a name="l06068"></a><span class="lineno"> 6068</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)</span></div>
|
|
<div class="line"><a name="l06069"></a><span class="lineno"> 6069</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)</span></div>
|
|
<div class="line"><a name="l06070"></a><span class="lineno"> 6070</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)</span></div>
|
|
<div class="line"><a name="l06071"></a><span class="lineno"> 6071</span> </div>
|
|
<div class="line"><a name="l06072"></a><span class="lineno"> 6072</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)</span></div>
|
|
<div class="line"><a name="l06073"></a><span class="lineno"> 6073</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)</span></div>
|
|
<div class="line"><a name="l06074"></a><span class="lineno"> 6074</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)</span></div>
|
|
<div class="line"><a name="l06075"></a><span class="lineno"> 6075</span> </div>
|
|
<div class="line"><a name="l06076"></a><span class="lineno"> 6076</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)</span></div>
|
|
<div class="line"><a name="l06077"></a><span class="lineno"> 6077</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)</span></div>
|
|
<div class="line"><a name="l06078"></a><span class="lineno"> 6078</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)</span></div>
|
|
<div class="line"><a name="l06079"></a><span class="lineno"> 6079</span> </div>
|
|
<div class="line"><a name="l06080"></a><span class="lineno"> 6080</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)</span></div>
|
|
<div class="line"><a name="l06081"></a><span class="lineno"> 6081</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)</span></div>
|
|
<div class="line"><a name="l06082"></a><span class="lineno"> 6082</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)</span></div>
|
|
<div class="line"><a name="l06083"></a><span class="lineno"> 6083</span> </div>
|
|
<div class="line"><a name="l06084"></a><span class="lineno"> 6084</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)</span></div>
|
|
<div class="line"><a name="l06085"></a><span class="lineno"> 6085</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)</span></div>
|
|
<div class="line"><a name="l06086"></a><span class="lineno"> 6086</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)</span></div>
|
|
<div class="line"><a name="l06087"></a><span class="lineno"> 6087</span> </div>
|
|
<div class="line"><a name="l06088"></a><span class="lineno"> 6088</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)</span></div>
|
|
<div class="line"><a name="l06089"></a><span class="lineno"> 6089</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)</span></div>
|
|
<div class="line"><a name="l06090"></a><span class="lineno"> 6090</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)</span></div>
|
|
<div class="line"><a name="l06091"></a><span class="lineno"> 6091</span> </div>
|
|
<div class="line"><a name="l06092"></a><span class="lineno"> 6092</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)</span></div>
|
|
<div class="line"><a name="l06093"></a><span class="lineno"> 6093</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)</span></div>
|
|
<div class="line"><a name="l06094"></a><span class="lineno"> 6094</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)</span></div>
|
|
<div class="line"><a name="l06095"></a><span class="lineno"> 6095</span> </div>
|
|
<div class="line"><a name="l06096"></a><span class="lineno"> 6096</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)</span></div>
|
|
<div class="line"><a name="l06097"></a><span class="lineno"> 6097</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)</span></div>
|
|
<div class="line"><a name="l06098"></a><span class="lineno"> 6098</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)</span></div>
|
|
<div class="line"><a name="l06099"></a><span class="lineno"> 6099</span> </div>
|
|
<div class="line"><a name="l06100"></a><span class="lineno"> 6100</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)</span></div>
|
|
<div class="line"><a name="l06101"></a><span class="lineno"> 6101</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)</span></div>
|
|
<div class="line"><a name="l06102"></a><span class="lineno"> 6102</span> <span class="preprocessor">#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)</span></div>
|
|
<div class="line"><a name="l06103"></a><span class="lineno"> 6103</span> </div>
|
|
<div class="line"><a name="l06104"></a><span class="lineno"> 6104</span> <span class="comment">/****************** Bits definition for GPIO_PUPDR register *****************/</span></div>
|
|
<div class="line"><a name="l06105"></a><span class="lineno"> 6105</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)</span></div>
|
|
<div class="line"><a name="l06106"></a><span class="lineno"> 6106</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l06107"></a><span class="lineno"> 6107</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l06108"></a><span class="lineno"> 6108</span> </div>
|
|
<div class="line"><a name="l06109"></a><span class="lineno"> 6109</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)</span></div>
|
|
<div class="line"><a name="l06110"></a><span class="lineno"> 6110</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l06111"></a><span class="lineno"> 6111</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l06112"></a><span class="lineno"> 6112</span> </div>
|
|
<div class="line"><a name="l06113"></a><span class="lineno"> 6113</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)</span></div>
|
|
<div class="line"><a name="l06114"></a><span class="lineno"> 6114</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l06115"></a><span class="lineno"> 6115</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l06116"></a><span class="lineno"> 6116</span> </div>
|
|
<div class="line"><a name="l06117"></a><span class="lineno"> 6117</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)</span></div>
|
|
<div class="line"><a name="l06118"></a><span class="lineno"> 6118</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l06119"></a><span class="lineno"> 6119</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)</span></div>
|
|
<div class="line"><a name="l06120"></a><span class="lineno"> 6120</span> </div>
|
|
<div class="line"><a name="l06121"></a><span class="lineno"> 6121</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)</span></div>
|
|
<div class="line"><a name="l06122"></a><span class="lineno"> 6122</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l06123"></a><span class="lineno"> 6123</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l06124"></a><span class="lineno"> 6124</span> </div>
|
|
<div class="line"><a name="l06125"></a><span class="lineno"> 6125</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)</span></div>
|
|
<div class="line"><a name="l06126"></a><span class="lineno"> 6126</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l06127"></a><span class="lineno"> 6127</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l06128"></a><span class="lineno"> 6128</span> </div>
|
|
<div class="line"><a name="l06129"></a><span class="lineno"> 6129</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)</span></div>
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|
<div class="line"><a name="l06130"></a><span class="lineno"> 6130</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)</span></div>
|
|
<div class="line"><a name="l06131"></a><span class="lineno"> 6131</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)</span></div>
|
|
<div class="line"><a name="l06132"></a><span class="lineno"> 6132</span> </div>
|
|
<div class="line"><a name="l06133"></a><span class="lineno"> 6133</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)</span></div>
|
|
<div class="line"><a name="l06134"></a><span class="lineno"> 6134</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)</span></div>
|
|
<div class="line"><a name="l06135"></a><span class="lineno"> 6135</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)</span></div>
|
|
<div class="line"><a name="l06136"></a><span class="lineno"> 6136</span> </div>
|
|
<div class="line"><a name="l06137"></a><span class="lineno"> 6137</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)</span></div>
|
|
<div class="line"><a name="l06138"></a><span class="lineno"> 6138</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)</span></div>
|
|
<div class="line"><a name="l06139"></a><span class="lineno"> 6139</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)</span></div>
|
|
<div class="line"><a name="l06140"></a><span class="lineno"> 6140</span> </div>
|
|
<div class="line"><a name="l06141"></a><span class="lineno"> 6141</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)</span></div>
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|
<div class="line"><a name="l06142"></a><span class="lineno"> 6142</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)</span></div>
|
|
<div class="line"><a name="l06143"></a><span class="lineno"> 6143</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)</span></div>
|
|
<div class="line"><a name="l06144"></a><span class="lineno"> 6144</span> </div>
|
|
<div class="line"><a name="l06145"></a><span class="lineno"> 6145</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)</span></div>
|
|
<div class="line"><a name="l06146"></a><span class="lineno"> 6146</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)</span></div>
|
|
<div class="line"><a name="l06147"></a><span class="lineno"> 6147</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)</span></div>
|
|
<div class="line"><a name="l06148"></a><span class="lineno"> 6148</span> </div>
|
|
<div class="line"><a name="l06149"></a><span class="lineno"> 6149</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)</span></div>
|
|
<div class="line"><a name="l06150"></a><span class="lineno"> 6150</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)</span></div>
|
|
<div class="line"><a name="l06151"></a><span class="lineno"> 6151</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)</span></div>
|
|
<div class="line"><a name="l06152"></a><span class="lineno"> 6152</span> </div>
|
|
<div class="line"><a name="l06153"></a><span class="lineno"> 6153</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)</span></div>
|
|
<div class="line"><a name="l06154"></a><span class="lineno"> 6154</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)</span></div>
|
|
<div class="line"><a name="l06155"></a><span class="lineno"> 6155</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)</span></div>
|
|
<div class="line"><a name="l06156"></a><span class="lineno"> 6156</span> </div>
|
|
<div class="line"><a name="l06157"></a><span class="lineno"> 6157</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)</span></div>
|
|
<div class="line"><a name="l06158"></a><span class="lineno"> 6158</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)</span></div>
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|
<div class="line"><a name="l06159"></a><span class="lineno"> 6159</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)</span></div>
|
|
<div class="line"><a name="l06160"></a><span class="lineno"> 6160</span> </div>
|
|
<div class="line"><a name="l06161"></a><span class="lineno"> 6161</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)</span></div>
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|
<div class="line"><a name="l06162"></a><span class="lineno"> 6162</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)</span></div>
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|
<div class="line"><a name="l06163"></a><span class="lineno"> 6163</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)</span></div>
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|
<div class="line"><a name="l06164"></a><span class="lineno"> 6164</span> </div>
|
|
<div class="line"><a name="l06165"></a><span class="lineno"> 6165</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)</span></div>
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|
<div class="line"><a name="l06166"></a><span class="lineno"> 6166</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)</span></div>
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|
<div class="line"><a name="l06167"></a><span class="lineno"> 6167</span> <span class="preprocessor">#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)</span></div>
|
|
<div class="line"><a name="l06168"></a><span class="lineno"> 6168</span> </div>
|
|
<div class="line"><a name="l06169"></a><span class="lineno"> 6169</span> <span class="comment">/****************** Bits definition for GPIO_IDR register *******************/</span></div>
|
|
<div class="line"><a name="l06170"></a><span class="lineno"> 6170</span> <span class="preprocessor">#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)</span></div>
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|
<div class="line"><a name="l06171"></a><span class="lineno"> 6171</span> <span class="preprocessor">#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)</span></div>
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|
<div class="line"><a name="l06172"></a><span class="lineno"> 6172</span> <span class="preprocessor">#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)</span></div>
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|
<div class="line"><a name="l06173"></a><span class="lineno"> 6173</span> <span class="preprocessor">#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)</span></div>
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|
<div class="line"><a name="l06174"></a><span class="lineno"> 6174</span> <span class="preprocessor">#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)</span></div>
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|
<div class="line"><a name="l06175"></a><span class="lineno"> 6175</span> <span class="preprocessor">#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l06176"></a><span class="lineno"> 6176</span> <span class="preprocessor">#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l06177"></a><span class="lineno"> 6177</span> <span class="preprocessor">#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)</span></div>
|
|
<div class="line"><a name="l06178"></a><span class="lineno"> 6178</span> <span class="preprocessor">#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)</span></div>
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|
<div class="line"><a name="l06179"></a><span class="lineno"> 6179</span> <span class="preprocessor">#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l06180"></a><span class="lineno"> 6180</span> <span class="preprocessor">#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l06181"></a><span class="lineno"> 6181</span> <span class="preprocessor">#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l06182"></a><span class="lineno"> 6182</span> <span class="preprocessor">#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)</span></div>
|
|
<div class="line"><a name="l06183"></a><span class="lineno"> 6183</span> <span class="preprocessor">#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)</span></div>
|
|
<div class="line"><a name="l06184"></a><span class="lineno"> 6184</span> <span class="preprocessor">#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)</span></div>
|
|
<div class="line"><a name="l06185"></a><span class="lineno"> 6185</span> <span class="preprocessor">#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)</span></div>
|
|
<div class="line"><a name="l06186"></a><span class="lineno"> 6186</span> <span class="comment">/* Old GPIO_IDR register bits definition, maintained for legacy purpose */</span></div>
|
|
<div class="line"><a name="l06187"></a><span class="lineno"> 6187</span> <span class="preprocessor">#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0</span></div>
|
|
<div class="line"><a name="l06188"></a><span class="lineno"> 6188</span> <span class="preprocessor">#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1</span></div>
|
|
<div class="line"><a name="l06189"></a><span class="lineno"> 6189</span> <span class="preprocessor">#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2</span></div>
|
|
<div class="line"><a name="l06190"></a><span class="lineno"> 6190</span> <span class="preprocessor">#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3</span></div>
|
|
<div class="line"><a name="l06191"></a><span class="lineno"> 6191</span> <span class="preprocessor">#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4</span></div>
|
|
<div class="line"><a name="l06192"></a><span class="lineno"> 6192</span> <span class="preprocessor">#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5</span></div>
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|
<div class="line"><a name="l06193"></a><span class="lineno"> 6193</span> <span class="preprocessor">#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6</span></div>
|
|
<div class="line"><a name="l06194"></a><span class="lineno"> 6194</span> <span class="preprocessor">#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7</span></div>
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<div class="line"><a name="l06195"></a><span class="lineno"> 6195</span> <span class="preprocessor">#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8</span></div>
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|
<div class="line"><a name="l06196"></a><span class="lineno"> 6196</span> <span class="preprocessor">#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9</span></div>
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<div class="line"><a name="l06197"></a><span class="lineno"> 6197</span> <span class="preprocessor">#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10</span></div>
|
|
<div class="line"><a name="l06198"></a><span class="lineno"> 6198</span> <span class="preprocessor">#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11</span></div>
|
|
<div class="line"><a name="l06199"></a><span class="lineno"> 6199</span> <span class="preprocessor">#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12</span></div>
|
|
<div class="line"><a name="l06200"></a><span class="lineno"> 6200</span> <span class="preprocessor">#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13</span></div>
|
|
<div class="line"><a name="l06201"></a><span class="lineno"> 6201</span> <span class="preprocessor">#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14</span></div>
|
|
<div class="line"><a name="l06202"></a><span class="lineno"> 6202</span> <span class="preprocessor">#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15</span></div>
|
|
<div class="line"><a name="l06203"></a><span class="lineno"> 6203</span> </div>
|
|
<div class="line"><a name="l06204"></a><span class="lineno"> 6204</span> <span class="comment">/****************** Bits definition for GPIO_ODR register *******************/</span></div>
|
|
<div class="line"><a name="l06205"></a><span class="lineno"> 6205</span> <span class="preprocessor">#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l06206"></a><span class="lineno"> 6206</span> <span class="preprocessor">#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l06207"></a><span class="lineno"> 6207</span> <span class="preprocessor">#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l06208"></a><span class="lineno"> 6208</span> <span class="preprocessor">#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l06209"></a><span class="lineno"> 6209</span> <span class="preprocessor">#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l06210"></a><span class="lineno"> 6210</span> <span class="preprocessor">#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l06211"></a><span class="lineno"> 6211</span> <span class="preprocessor">#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l06212"></a><span class="lineno"> 6212</span> <span class="preprocessor">#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)</span></div>
|
|
<div class="line"><a name="l06213"></a><span class="lineno"> 6213</span> <span class="preprocessor">#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l06214"></a><span class="lineno"> 6214</span> <span class="preprocessor">#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l06215"></a><span class="lineno"> 6215</span> <span class="preprocessor">#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l06216"></a><span class="lineno"> 6216</span> <span class="preprocessor">#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l06217"></a><span class="lineno"> 6217</span> <span class="preprocessor">#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)</span></div>
|
|
<div class="line"><a name="l06218"></a><span class="lineno"> 6218</span> <span class="preprocessor">#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)</span></div>
|
|
<div class="line"><a name="l06219"></a><span class="lineno"> 6219</span> <span class="preprocessor">#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)</span></div>
|
|
<div class="line"><a name="l06220"></a><span class="lineno"> 6220</span> <span class="preprocessor">#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)</span></div>
|
|
<div class="line"><a name="l06221"></a><span class="lineno"> 6221</span> <span class="comment">/* Old GPIO_ODR register bits definition, maintained for legacy purpose */</span></div>
|
|
<div class="line"><a name="l06222"></a><span class="lineno"> 6222</span> <span class="preprocessor">#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0</span></div>
|
|
<div class="line"><a name="l06223"></a><span class="lineno"> 6223</span> <span class="preprocessor">#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1</span></div>
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|
<div class="line"><a name="l06224"></a><span class="lineno"> 6224</span> <span class="preprocessor">#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2</span></div>
|
|
<div class="line"><a name="l06225"></a><span class="lineno"> 6225</span> <span class="preprocessor">#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3</span></div>
|
|
<div class="line"><a name="l06226"></a><span class="lineno"> 6226</span> <span class="preprocessor">#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4</span></div>
|
|
<div class="line"><a name="l06227"></a><span class="lineno"> 6227</span> <span class="preprocessor">#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5</span></div>
|
|
<div class="line"><a name="l06228"></a><span class="lineno"> 6228</span> <span class="preprocessor">#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6</span></div>
|
|
<div class="line"><a name="l06229"></a><span class="lineno"> 6229</span> <span class="preprocessor">#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7</span></div>
|
|
<div class="line"><a name="l06230"></a><span class="lineno"> 6230</span> <span class="preprocessor">#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8</span></div>
|
|
<div class="line"><a name="l06231"></a><span class="lineno"> 6231</span> <span class="preprocessor">#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9</span></div>
|
|
<div class="line"><a name="l06232"></a><span class="lineno"> 6232</span> <span class="preprocessor">#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10</span></div>
|
|
<div class="line"><a name="l06233"></a><span class="lineno"> 6233</span> <span class="preprocessor">#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11</span></div>
|
|
<div class="line"><a name="l06234"></a><span class="lineno"> 6234</span> <span class="preprocessor">#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12</span></div>
|
|
<div class="line"><a name="l06235"></a><span class="lineno"> 6235</span> <span class="preprocessor">#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13</span></div>
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|
<div class="line"><a name="l06236"></a><span class="lineno"> 6236</span> <span class="preprocessor">#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14</span></div>
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|
<div class="line"><a name="l06237"></a><span class="lineno"> 6237</span> <span class="preprocessor">#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15</span></div>
|
|
<div class="line"><a name="l06238"></a><span class="lineno"> 6238</span> </div>
|
|
<div class="line"><a name="l06239"></a><span class="lineno"> 6239</span> <span class="comment">/****************** Bits definition for GPIO_BSRR register ******************/</span></div>
|
|
<div class="line"><a name="l06240"></a><span class="lineno"> 6240</span> <span class="preprocessor">#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)</span></div>
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|
<div class="line"><a name="l06241"></a><span class="lineno"> 6241</span> <span class="preprocessor">#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)</span></div>
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|
<div class="line"><a name="l06242"></a><span class="lineno"> 6242</span> <span class="preprocessor">#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)</span></div>
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|
<div class="line"><a name="l06243"></a><span class="lineno"> 6243</span> <span class="preprocessor">#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)</span></div>
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|
<div class="line"><a name="l06244"></a><span class="lineno"> 6244</span> <span class="preprocessor">#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l06245"></a><span class="lineno"> 6245</span> <span class="preprocessor">#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l06246"></a><span class="lineno"> 6246</span> <span class="preprocessor">#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l06247"></a><span class="lineno"> 6247</span> <span class="preprocessor">#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)</span></div>
|
|
<div class="line"><a name="l06248"></a><span class="lineno"> 6248</span> <span class="preprocessor">#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l06249"></a><span class="lineno"> 6249</span> <span class="preprocessor">#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l06250"></a><span class="lineno"> 6250</span> <span class="preprocessor">#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l06251"></a><span class="lineno"> 6251</span> <span class="preprocessor">#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l06252"></a><span class="lineno"> 6252</span> <span class="preprocessor">#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)</span></div>
|
|
<div class="line"><a name="l06253"></a><span class="lineno"> 6253</span> <span class="preprocessor">#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)</span></div>
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|
<div class="line"><a name="l06254"></a><span class="lineno"> 6254</span> <span class="preprocessor">#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)</span></div>
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|
<div class="line"><a name="l06255"></a><span class="lineno"> 6255</span> <span class="preprocessor">#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)</span></div>
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|
<div class="line"><a name="l06256"></a><span class="lineno"> 6256</span> <span class="preprocessor">#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)</span></div>
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|
<div class="line"><a name="l06257"></a><span class="lineno"> 6257</span> <span class="preprocessor">#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)</span></div>
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|
<div class="line"><a name="l06258"></a><span class="lineno"> 6258</span> <span class="preprocessor">#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)</span></div>
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|
<div class="line"><a name="l06259"></a><span class="lineno"> 6259</span> <span class="preprocessor">#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)</span></div>
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|
<div class="line"><a name="l06260"></a><span class="lineno"> 6260</span> <span class="preprocessor">#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)</span></div>
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|
<div class="line"><a name="l06261"></a><span class="lineno"> 6261</span> <span class="preprocessor">#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)</span></div>
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|
<div class="line"><a name="l06262"></a><span class="lineno"> 6262</span> <span class="preprocessor">#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)</span></div>
|
|
<div class="line"><a name="l06263"></a><span class="lineno"> 6263</span> <span class="preprocessor">#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)</span></div>
|
|
<div class="line"><a name="l06264"></a><span class="lineno"> 6264</span> <span class="preprocessor">#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)</span></div>
|
|
<div class="line"><a name="l06265"></a><span class="lineno"> 6265</span> <span class="preprocessor">#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)</span></div>
|
|
<div class="line"><a name="l06266"></a><span class="lineno"> 6266</span> <span class="preprocessor">#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)</span></div>
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|
<div class="line"><a name="l06267"></a><span class="lineno"> 6267</span> <span class="preprocessor">#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)</span></div>
|
|
<div class="line"><a name="l06268"></a><span class="lineno"> 6268</span> <span class="preprocessor">#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)</span></div>
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|
<div class="line"><a name="l06269"></a><span class="lineno"> 6269</span> <span class="preprocessor">#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)</span></div>
|
|
<div class="line"><a name="l06270"></a><span class="lineno"> 6270</span> <span class="preprocessor">#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)</span></div>
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|
<div class="line"><a name="l06271"></a><span class="lineno"> 6271</span> <span class="preprocessor">#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)</span></div>
|
|
<div class="line"><a name="l06272"></a><span class="lineno"> 6272</span> </div>
|
|
<div class="line"><a name="l06273"></a><span class="lineno"> 6273</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l06274"></a><span class="lineno"> 6274</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l06275"></a><span class="lineno"> 6275</span> <span class="comment">/* HASH */</span></div>
|
|
<div class="line"><a name="l06276"></a><span class="lineno"> 6276</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l06277"></a><span class="lineno"> 6277</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l06278"></a><span class="lineno"> 6278</span> <span class="comment">/****************** Bits definition for HASH_CR register ********************/</span></div>
|
|
<div class="line"><a name="l06279"></a><span class="lineno"> 6279</span> <span class="preprocessor">#define HASH_CR_INIT ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l06280"></a><span class="lineno"> 6280</span> <span class="preprocessor">#define HASH_CR_DMAE ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l06281"></a><span class="lineno"> 6281</span> <span class="preprocessor">#define HASH_CR_DATATYPE ((uint32_t)0x00000030)</span></div>
|
|
<div class="line"><a name="l06282"></a><span class="lineno"> 6282</span> <span class="preprocessor">#define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l06283"></a><span class="lineno"> 6283</span> <span class="preprocessor">#define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l06284"></a><span class="lineno"> 6284</span> <span class="preprocessor">#define HASH_CR_MODE ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l06285"></a><span class="lineno"> 6285</span> <span class="preprocessor">#define HASH_CR_ALGO ((uint32_t)0x00040080)</span></div>
|
|
<div class="line"><a name="l06286"></a><span class="lineno"> 6286</span> <span class="preprocessor">#define HASH_CR_ALGO_0 ((uint32_t)0x00000080)</span></div>
|
|
<div class="line"><a name="l06287"></a><span class="lineno"> 6287</span> <span class="preprocessor">#define HASH_CR_ALGO_1 ((uint32_t)0x00040000)</span></div>
|
|
<div class="line"><a name="l06288"></a><span class="lineno"> 6288</span> <span class="preprocessor">#define HASH_CR_NBW ((uint32_t)0x00000F00)</span></div>
|
|
<div class="line"><a name="l06289"></a><span class="lineno"> 6289</span> <span class="preprocessor">#define HASH_CR_NBW_0 ((uint32_t)0x00000100)</span></div>
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|
<div class="line"><a name="l06290"></a><span class="lineno"> 6290</span> <span class="preprocessor">#define HASH_CR_NBW_1 ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l06291"></a><span class="lineno"> 6291</span> <span class="preprocessor">#define HASH_CR_NBW_2 ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l06292"></a><span class="lineno"> 6292</span> <span class="preprocessor">#define HASH_CR_NBW_3 ((uint32_t)0x00000800)</span></div>
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|
<div class="line"><a name="l06293"></a><span class="lineno"> 6293</span> <span class="preprocessor">#define HASH_CR_DINNE ((uint32_t)0x00001000)</span></div>
|
|
<div class="line"><a name="l06294"></a><span class="lineno"> 6294</span> <span class="preprocessor">#define HASH_CR_MDMAT ((uint32_t)0x00002000)</span></div>
|
|
<div class="line"><a name="l06295"></a><span class="lineno"> 6295</span> <span class="preprocessor">#define HASH_CR_LKEY ((uint32_t)0x00010000)</span></div>
|
|
<div class="line"><a name="l06296"></a><span class="lineno"> 6296</span> </div>
|
|
<div class="line"><a name="l06297"></a><span class="lineno"> 6297</span> <span class="comment">/****************** Bits definition for HASH_STR register *******************/</span></div>
|
|
<div class="line"><a name="l06298"></a><span class="lineno"> 6298</span> <span class="preprocessor">#define HASH_STR_NBW ((uint32_t)0x0000001F)</span></div>
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|
<div class="line"><a name="l06299"></a><span class="lineno"> 6299</span> <span class="preprocessor">#define HASH_STR_NBW_0 ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l06300"></a><span class="lineno"> 6300</span> <span class="preprocessor">#define HASH_STR_NBW_1 ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l06301"></a><span class="lineno"> 6301</span> <span class="preprocessor">#define HASH_STR_NBW_2 ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l06302"></a><span class="lineno"> 6302</span> <span class="preprocessor">#define HASH_STR_NBW_3 ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l06303"></a><span class="lineno"> 6303</span> <span class="preprocessor">#define HASH_STR_NBW_4 ((uint32_t)0x00000010)</span></div>
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|
<div class="line"><a name="l06304"></a><span class="lineno"> 6304</span> <span class="preprocessor">#define HASH_STR_DCAL ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l06305"></a><span class="lineno"> 6305</span> </div>
|
|
<div class="line"><a name="l06306"></a><span class="lineno"> 6306</span> <span class="comment">/****************** Bits definition for HASH_IMR register *******************/</span></div>
|
|
<div class="line"><a name="l06307"></a><span class="lineno"> 6307</span> <span class="preprocessor">#define HASH_IMR_DINIM ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l06308"></a><span class="lineno"> 6308</span> <span class="preprocessor">#define HASH_IMR_DCIM ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l06309"></a><span class="lineno"> 6309</span> </div>
|
|
<div class="line"><a name="l06310"></a><span class="lineno"> 6310</span> <span class="comment">/****************** Bits definition for HASH_SR register ********************/</span></div>
|
|
<div class="line"><a name="l06311"></a><span class="lineno"> 6311</span> <span class="preprocessor">#define HASH_SR_DINIS ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l06312"></a><span class="lineno"> 6312</span> <span class="preprocessor">#define HASH_SR_DCIS ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l06313"></a><span class="lineno"> 6313</span> <span class="preprocessor">#define HASH_SR_DMAS ((uint32_t)0x00000004)</span></div>
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|
<div class="line"><a name="l06314"></a><span class="lineno"> 6314</span> <span class="preprocessor">#define HASH_SR_BUSY ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l06315"></a><span class="lineno"> 6315</span> </div>
|
|
<div class="line"><a name="l06316"></a><span class="lineno"> 6316</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l06317"></a><span class="lineno"> 6317</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l06318"></a><span class="lineno"> 6318</span> <span class="comment">/* Inter-integrated Circuit Interface */</span></div>
|
|
<div class="line"><a name="l06319"></a><span class="lineno"> 6319</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l06320"></a><span class="lineno"> 6320</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l06321"></a><span class="lineno"> 6321</span> <span class="comment">/******************* Bit definition for I2C_CR1 register ********************/</span></div>
|
|
<div class="line"><a name="l06322"></a><span class="lineno"> 6322</span> <span class="preprocessor">#define I2C_CR1_PE ((uint16_t)0x0001) </span></div>
|
|
<div class="line"><a name="l06323"></a><span class="lineno"> 6323</span> <span class="preprocessor">#define I2C_CR1_SMBUS ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l06324"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga953b0d38414808db79da116842ed3262"> 6324</a></span> <span class="preprocessor">#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l06325"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4cfee7b020a49bd037fa7cf27c796abc"> 6325</a></span> <span class="preprocessor">#define I2C_CR1_ENARP ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l06326"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga001198ff898802888edf58f56d5371c9"> 6326</a></span> <span class="preprocessor">#define I2C_CR1_ENPEC ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l06327"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4598185d9092edfbf943464bcbb342ac"> 6327</a></span> <span class="preprocessor">#define I2C_CR1_ENGC ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l06328"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40d2eb849f9d55e6298035b61e84ca42"> 6328</a></span> <span class="preprocessor">#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l06329"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d8c219193b11f8507d7b85831d14912"> 6329</a></span> <span class="preprocessor">#define I2C_CR1_START ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l06330"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga197aaca79f64e832af3a0a0864c2a08c"> 6330</a></span> <span class="preprocessor">#define I2C_CR1_STOP ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l06331"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ca7f18dd5bc1130dbefae4ff8736143"> 6331</a></span> <span class="preprocessor">#define I2C_CR1_ACK ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l06332"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace70293f3dfa24d448b600fc58e45223"> 6332</a></span> <span class="preprocessor">#define I2C_CR1_POS ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l06333"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf933b105259a4bc46a957576adb8d96d"> 6333</a></span> <span class="preprocessor">#define I2C_CR1_PEC ((uint16_t)0x1000) </span></div>
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<div class="line"><a name="l06334"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34721958229a5983f2e95dfeaa8e55c3"> 6334</a></span> <span class="preprocessor">#define I2C_CR1_ALERT ((uint16_t)0x2000) </span></div>
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<div class="line"><a name="l06335"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab4d0119253d93a106b5ca704e5020c12"> 6335</a></span> <span class="preprocessor">#define I2C_CR1_SWRST ((uint16_t)0x8000) </span></div>
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<div class="line"><a name="l06337"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8dc661ef13da02e5bcb943f2003d576d"> 6337</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for I2C_CR2 register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l06338"></a><span class="lineno"> 6338</span> <span class="preprocessor">#define I2C_CR2_FREQ ((uint16_t)0x003F) </span></div>
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<div class="line"><a name="l06339"></a><span class="lineno"> 6339</span> <span class="preprocessor">#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) </span></div>
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<div class="line"><a name="l06340"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga293fbe15ed5fd1fc95915bd6437859e7"> 6340</a></span> <span class="preprocessor">#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l06341"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09d944f5260f40a0eb714d41859e0d23"> 6341</a></span> <span class="preprocessor">#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l06342"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25ab0ef2a7795e3326900b277479d89c"> 6342</a></span> <span class="preprocessor">#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l06343"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga657af5a02534cc900cbddc260319d845"> 6343</a></span> <span class="preprocessor">#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l06344"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga655214f8327fd1322998c9d8bffe308d"> 6344</a></span> <span class="preprocessor">#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l06346"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3b1a2b777fcf158c9e4264485682a20"> 6346</a></span> <span class="preprocessor">#define I2C_CR2_ITERREN ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l06347"></a><span class="lineno"> 6347</span> <span class="preprocessor">#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l06348"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f14ae48e4609c2b3645211234cba974"> 6348</a></span> <span class="preprocessor">#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l06349"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b1ebaf8173090ec469b055b98e585d2"> 6349</a></span> <span class="preprocessor">#define I2C_CR2_DMAEN ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l06350"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2efbe5d96ed0ce447a45a62e8317a68a"> 6350</a></span> <span class="preprocessor">#define I2C_CR2_LAST ((uint16_t)0x1000) </span></div>
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<div class="line"><a name="l06352"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a0955008cbabbb6b726ba0b4f8da609"> 6352</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for I2C_OAR1 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l06353"></a><span class="lineno"> 6353</span> <span class="preprocessor">#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) </span></div>
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<div class="line"><a name="l06354"></a><span class="lineno"> 6354</span> <span class="preprocessor">#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) </span></div>
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<div class="line"><a name="l06356"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8141dcd63a8429a64d488cc78ef3ec1"> 6356</a></span> <span class="preprocessor">#define I2C_OAR1_ADD0 ((uint16_t)0x0001) </span></div>
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<div class="line"><a name="l06357"></a><span class="lineno"> 6357</span> <span class="preprocessor">#define I2C_OAR1_ADD1 ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l06358"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8b7c20c81f79d17921718412b8fca6d7"> 6358</a></span> <span class="preprocessor">#define I2C_OAR1_ADD2 ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l06359"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga499a61f0013c5c6fe38b848901f58769"> 6359</a></span> <span class="preprocessor">#define I2C_OAR1_ADD3 ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l06360"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab44a263e36a7f34d922ff124aebd99c3"> 6360</a></span> <span class="preprocessor">#define I2C_OAR1_ADD4 ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l06361"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9584dca3b1b414a63cf7ba75e557155b"> 6361</a></span> <span class="preprocessor">#define I2C_OAR1_ADD5 ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l06362"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga110b915b907f4bf29ff03da1f077bd97"> 6362</a></span> <span class="preprocessor">#define I2C_OAR1_ADD6 ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l06363"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0856dee2657cf0a04d79084da86988ca"> 6363</a></span> <span class="preprocessor">#define I2C_OAR1_ADD7 ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l06364"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5507af6154f60125dadc4654f57776ca"> 6364</a></span> <span class="preprocessor">#define I2C_OAR1_ADD8 ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l06365"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca710515f0aac5abdac02a630e09097c"> 6365</a></span> <span class="preprocessor">#define I2C_OAR1_ADD9 ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l06367"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga10cf2dfc6b1ed55413be06acca413430"> 6367</a></span> <span class="preprocessor">#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) </span></div>
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<div class="line"><a name="l06369"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d8df80cd27313c896e887aae81fa639"> 6369</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for I2C_OAR2 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l06370"></a><span class="lineno"> 6370</span> <span class="preprocessor">#define I2C_OAR2_ENDUAL ((uint8_t)0x01) </span></div>
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<div class="line"><a name="l06371"></a><span class="lineno"> 6371</span> <span class="preprocessor">#define I2C_OAR2_ADD2 ((uint8_t)0xFE) </span></div>
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<div class="line"><a name="l06373"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd3d8fd1de1f16d051efb52dd3d657c4"> 6373</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for I2C_DR register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l06374"></a><span class="lineno"> 6374</span> <span class="preprocessor">#define I2C_DR_DR ((uint8_t)0xFF) </span></div>
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<div class="line"><a name="l06376"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac43021a4a7f79672d27c36a469b301d5"> 6376</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for I2C_SR1 register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l06377"></a><span class="lineno"> 6377</span> <span class="preprocessor">#define I2C_SR1_SB ((uint16_t)0x0001) </span></div>
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<div class="line"><a name="l06378"></a><span class="lineno"> 6378</span> <span class="preprocessor">#define I2C_SR1_ADDR ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l06379"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6935c920da59d755d0cf834548a70ec4"> 6379</a></span> <span class="preprocessor">#define I2C_SR1_BTF ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l06380"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3db361a4d9dd84b187085a11d933b45d"> 6380</a></span> <span class="preprocessor">#define I2C_SR1_ADD10 ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l06381"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb279f85d78cfe5abd3eeb0b40a65ab1"> 6381</a></span> <span class="preprocessor">#define I2C_SR1_STOPF ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l06382"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6faaa55a1e48aa7c1f2b69669901445d"> 6382</a></span> <span class="preprocessor">#define I2C_SR1_RXNE ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l06383"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaafcea4cdbe2f6da31566c897fa893a7c"> 6383</a></span> <span class="preprocessor">#define I2C_SR1_TXE ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l06384"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6ebe33c992611bc2e25bbb01c1441a5"> 6384</a></span> <span class="preprocessor">#define I2C_SR1_BERR ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l06385"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafdc4da49c163910203255e384591b6f7"> 6385</a></span> <span class="preprocessor">#define I2C_SR1_ARLO ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l06386"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d12990c90ab0757dcfea150ea50b227"> 6386</a></span> <span class="preprocessor">#define I2C_SR1_AF ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l06387"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacbc52f6ec6172c71d8b026a22c2f69d2"> 6387</a></span> <span class="preprocessor">#define I2C_SR1_OVR ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l06388"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62aa2496d4b3955214a16a7bd998fd88"> 6388</a></span> <span class="preprocessor">#define I2C_SR1_PECERR ((uint16_t)0x1000) </span></div>
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<div class="line"><a name="l06389"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad42d2435d2e64bf710c701c9b17adfb4"> 6389</a></span> <span class="preprocessor">#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) </span></div>
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<div class="line"><a name="l06390"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b2976279024e832e53ad12796a7bb71"> 6390</a></span> <span class="preprocessor">#define I2C_SR1_SMBALERT ((uint16_t)0x8000) </span></div>
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<div class="line"><a name="l06392"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8df36c38deb8791d0ac3cb5881298c1c"> 6392</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for I2C_SR2 register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l06393"></a><span class="lineno"> 6393</span> <span class="preprocessor">#define I2C_SR2_MSL ((uint16_t)0x0001) </span></div>
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<div class="line"><a name="l06394"></a><span class="lineno"> 6394</span> <span class="preprocessor">#define I2C_SR2_BUSY ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l06395"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga75cc361adf0e72e33d6771ebfa17b52d"> 6395</a></span> <span class="preprocessor">#define I2C_SR2_TRA ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l06396"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b1e75a82da73ae2873cff1cd27c3179"> 6396</a></span> <span class="preprocessor">#define I2C_SR2_GENCALL ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l06397"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga288b20416b42a79e591aa80d9a690fca"> 6397</a></span> <span class="preprocessor">#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l06398"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3aeb79cbe04f7ec1e3c2615921c4fab"> 6398</a></span> <span class="preprocessor">#define I2C_SR2_SMBHOST ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l06399"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafcf50334903013177a8c6f4e36b8d6fe"> 6399</a></span> <span class="preprocessor">#define I2C_SR2_DUALF ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l06400"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa07cf3e404f9f57e98d1ba3793079c80"> 6400</a></span> <span class="preprocessor">#define I2C_SR2_PEC ((uint16_t)0xFF00) </span></div>
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<div class="line"><a name="l06402"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a4fd5d9c9e2593be920d19a5f6ae732"> 6402</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for I2C_CCR register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l06403"></a><span class="lineno"> 6403</span> <span class="preprocessor">#define I2C_CCR_CCR ((uint16_t)0x0FFF) </span></div>
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<div class="line"><a name="l06404"></a><span class="lineno"> 6404</span> <span class="preprocessor">#define I2C_CCR_DUTY ((uint16_t)0x4000) </span></div>
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<div class="line"><a name="l06405"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c8cb2bd83dd7dbdcf6ca4bbf4a841de"> 6405</a></span> <span class="preprocessor">#define I2C_CCR_FS ((uint16_t)0x8000) </span></div>
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<div class="line"><a name="l06407"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea64e5d7eba609ac9a84964bc0bc2def"> 6407</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for I2C_TRISE register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l06408"></a><span class="lineno"> 6408</span> <span class="preprocessor">#define I2C_TRISE_TRISE ((uint8_t)0x3F) </span></div>
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<div class="line"><a name="l06410"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaff77a39aba630647af62dc7f1a5dc218"> 6410</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for I2C_FLTR register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l06411"></a><span class="lineno"> 6411</span> <span class="preprocessor">#define I2C_FLTR_DNF ((uint8_t)0x0F) </span></div>
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<div class="line"><a name="l06412"></a><span class="lineno"> 6412</span> <span class="preprocessor">#define I2C_FLTR_ANOFF ((uint8_t)0x10) </span></div>
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<div class="line"><a name="l06414"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f312cebb37d3e5d0a690dc6fda86f32"> 6414</a></span> <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l06415"></a><span class="lineno"> 6415</span> <span class="comment">/* */</span></div>
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<div class="line"><a name="l06416"></a><span class="lineno"> 6416</span> <span class="comment">/* Independent WATCHDOG */</span></div>
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<div class="line"><a name="l06417"></a><span class="lineno"> 6417</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l06418"></a><span class="lineno"> 6418</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l06419"></a><span class="lineno"> 6419</span> <span class="comment">/******************* Bit definition for IWDG_KR register ********************/</span></div>
|
|
<div class="line"><a name="l06420"></a><span class="lineno"> 6420</span> <span class="preprocessor">#define IWDG_KR_KEY ((uint16_t)0xFFFF) </span></div>
|
|
<div class="line"><a name="l06422"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga957f7d5f8a0ec1a6956a7f05cfbd97c2"> 6422</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for IWDG_PR register ********************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06423"></a><span class="lineno"> 6423</span> <span class="preprocessor">#define IWDG_PR_PR ((uint8_t)0x07) </span></div>
|
|
<div class="line"><a name="l06424"></a><span class="lineno"> 6424</span> <span class="preprocessor">#define IWDG_PR_PR_0 ((uint8_t)0x01) </span></div>
|
|
<div class="line"><a name="l06425"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4de39c5672f17d326fceb5adc9adc090"> 6425</a></span> <span class="preprocessor">#define IWDG_PR_PR_1 ((uint8_t)0x02) </span></div>
|
|
<div class="line"><a name="l06426"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9b727e7882603df1684cbf230520ca76"> 6426</a></span> <span class="preprocessor">#define IWDG_PR_PR_2 ((uint8_t)0x04) </span></div>
|
|
<div class="line"><a name="l06428"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga55a1d7fde4e3e724a8644652ba9bb2b9"> 6428</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for IWDG_RLR register *******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06429"></a><span class="lineno"> 6429</span> <span class="preprocessor">#define IWDG_RLR_RL ((uint16_t)0x0FFF) </span></div>
|
|
<div class="line"><a name="l06431"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga87024bbb19f26def4c4c1510b22d3033"> 6431</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for IWDG_SR register ********************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06432"></a><span class="lineno"> 6432</span> <span class="preprocessor">#define IWDG_SR_PVU ((uint8_t)0x01) </span></div>
|
|
<div class="line"><a name="l06433"></a><span class="lineno"> 6433</span> <span class="preprocessor">#define IWDG_SR_RVU ((uint8_t)0x02) </span></div>
|
|
<div class="line"><a name="l06435"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadffb8339e556a3b10120b15f0dacc232"> 6435</a></span> <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06436"></a><span class="lineno"> 6436</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l06437"></a><span class="lineno"> 6437</span> <span class="comment">/* LCD-TFT Display Controller (LTDC) */</span></div>
|
|
<div class="line"><a name="l06438"></a><span class="lineno"> 6438</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l06439"></a><span class="lineno"> 6439</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l06440"></a><span class="lineno"> 6440</span> </div>
|
|
<div class="line"><a name="l06441"></a><span class="lineno"> 6441</span> <span class="comment">/******************** Bit definition for LTDC_SSCR register *****************/</span></div>
|
|
<div class="line"><a name="l06442"></a><span class="lineno"> 6442</span> </div>
|
|
<div class="line"><a name="l06443"></a><span class="lineno"> 6443</span> <span class="preprocessor">#define LTDC_SSCR_VSH ((uint32_t)0x000007FF) </span></div>
|
|
<div class="line"><a name="l06444"></a><span class="lineno"> 6444</span> <span class="preprocessor">#define LTDC_SSCR_HSW ((uint32_t)0x0FFF0000) </span></div>
|
|
<div class="line"><a name="l06446"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga907f3558ae8795a88438115a0f4b9ea5"> 6446</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for LTDC_BPCR register *****************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06447"></a><span class="lineno"> 6447</span> </div>
|
|
<div class="line"><a name="l06448"></a><span class="lineno"> 6448</span> <span class="preprocessor">#define LTDC_BPCR_AVBP ((uint32_t)0x000007FF) </span></div>
|
|
<div class="line"><a name="l06449"></a><span class="lineno"> 6449</span> <span class="preprocessor">#define LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000) </span></div>
|
|
<div class="line"><a name="l06451"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6935a2c30e44ad5c705ae26199f60782"> 6451</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for LTDC_AWCR register *****************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06452"></a><span class="lineno"> 6452</span> </div>
|
|
<div class="line"><a name="l06453"></a><span class="lineno"> 6453</span> <span class="preprocessor">#define LTDC_AWCR_AAH ((uint32_t)0x000007FF) </span></div>
|
|
<div class="line"><a name="l06454"></a><span class="lineno"> 6454</span> <span class="preprocessor">#define LTDC_AWCR_AAW ((uint32_t)0x0FFF0000) </span></div>
|
|
<div class="line"><a name="l06456"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a2a074b96e4a6f856d34efa93265baa"> 6456</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for LTDC_TWCR register *****************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06457"></a><span class="lineno"> 6457</span> </div>
|
|
<div class="line"><a name="l06458"></a><span class="lineno"> 6458</span> <span class="preprocessor">#define LTDC_TWCR_TOTALH ((uint32_t)0x000007FF) </span></div>
|
|
<div class="line"><a name="l06459"></a><span class="lineno"> 6459</span> <span class="preprocessor">#define LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000) </span></div>
|
|
<div class="line"><a name="l06461"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca9cb93332d3b62207e86bb7f3e126e0"> 6461</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for LTDC_GCR register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06462"></a><span class="lineno"> 6462</span> </div>
|
|
<div class="line"><a name="l06463"></a><span class="lineno"> 6463</span> <span class="preprocessor">#define LTDC_GCR_LTDCEN ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l06464"></a><span class="lineno"> 6464</span> <span class="preprocessor">#define LTDC_GCR_DBW ((uint32_t)0x00000070) </span></div>
|
|
<div class="line"><a name="l06465"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf55426883a15eeb7222f2afdb474078c"> 6465</a></span> <span class="preprocessor">#define LTDC_GCR_DGW ((uint32_t)0x00000700) </span></div>
|
|
<div class="line"><a name="l06466"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1686ca70b7713b92388428cec667f3e1"> 6466</a></span> <span class="preprocessor">#define LTDC_GCR_DRW ((uint32_t)0x00007000) </span></div>
|
|
<div class="line"><a name="l06467"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaeda36ed8fd82123f98869492dfa44ac"> 6467</a></span> <span class="preprocessor">#define LTDC_GCR_DTEN ((uint32_t)0x00010000) </span></div>
|
|
<div class="line"><a name="l06468"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0240de6352abcfc4efb15b7ebf576822"> 6468</a></span> <span class="preprocessor">#define LTDC_GCR_PCPOL ((uint32_t)0x10000000) </span></div>
|
|
<div class="line"><a name="l06469"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae926ae4dfa16282de074099da8b22647"> 6469</a></span> <span class="preprocessor">#define LTDC_GCR_DEPOL ((uint32_t)0x20000000) </span></div>
|
|
<div class="line"><a name="l06470"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3718fea213202d0fd836bfa24b744a10"> 6470</a></span> <span class="preprocessor">#define LTDC_GCR_VSPOL ((uint32_t)0x40000000) </span></div>
|
|
<div class="line"><a name="l06471"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b52f55ad6c0d4755ea7555661362bd0"> 6471</a></span> <span class="preprocessor">#define LTDC_GCR_HSPOL ((uint32_t)0x80000000) </span></div>
|
|
<div class="line"><a name="l06473"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8773e0967763b93c618099e9d173936e"> 6473</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for LTDC_SRCR register *****************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06474"></a><span class="lineno"> 6474</span> </div>
|
|
<div class="line"><a name="l06475"></a><span class="lineno"> 6475</span> <span class="preprocessor">#define LTDC_SRCR_IMR ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l06476"></a><span class="lineno"> 6476</span> <span class="preprocessor">#define LTDC_SRCR_VBR ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l06478"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a469ec4989f09bd45c0fa1bcd8fbb0a"> 6478</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for LTDC_BCCR register *****************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06479"></a><span class="lineno"> 6479</span> </div>
|
|
<div class="line"><a name="l06480"></a><span class="lineno"> 6480</span> <span class="preprocessor">#define LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF) </span></div>
|
|
<div class="line"><a name="l06481"></a><span class="lineno"> 6481</span> <span class="preprocessor">#define LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00) </span></div>
|
|
<div class="line"><a name="l06482"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17515cc05bb25a491a9f27d6740c0169"> 6482</a></span> <span class="preprocessor">#define LTDC_BCCR_BCRED ((uint32_t)0x00FF0000) </span></div>
|
|
<div class="line"><a name="l06484"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5cdd228eaac63eafbb44f5402f772495"> 6484</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for LTDC_IER register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06485"></a><span class="lineno"> 6485</span> </div>
|
|
<div class="line"><a name="l06486"></a><span class="lineno"> 6486</span> <span class="preprocessor">#define LTDC_IER_LIE ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l06487"></a><span class="lineno"> 6487</span> <span class="preprocessor">#define LTDC_IER_FUIE ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l06488"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga986f9c276c5c09d609099fb9df0466f0"> 6488</a></span> <span class="preprocessor">#define LTDC_IER_TERRIE ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l06489"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga59e996a111de2bfbc7353ad721d23b62"> 6489</a></span> <span class="preprocessor">#define LTDC_IER_RRIE ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l06491"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8b81bb2975282a8c97904fb27f379b6"> 6491</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for LTDC_ISR register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06492"></a><span class="lineno"> 6492</span> </div>
|
|
<div class="line"><a name="l06493"></a><span class="lineno"> 6493</span> <span class="preprocessor">#define LTDC_ISR_LIF ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l06494"></a><span class="lineno"> 6494</span> <span class="preprocessor">#define LTDC_ISR_FUIF ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l06495"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1430a5052fa2be26d885e6019326f374"> 6495</a></span> <span class="preprocessor">#define LTDC_ISR_TERRIF ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l06496"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad25511dce2346382813fbb8f38ed0afe"> 6496</a></span> <span class="preprocessor">#define LTDC_ISR_RRIF ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l06498"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8735819d356373cd4ee6f5fdb4889fc"> 6498</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for LTDC_ICR register ******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06499"></a><span class="lineno"> 6499</span> </div>
|
|
<div class="line"><a name="l06500"></a><span class="lineno"> 6500</span> <span class="preprocessor">#define LTDC_ICR_CLIF ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l06501"></a><span class="lineno"> 6501</span> <span class="preprocessor">#define LTDC_ICR_CFUIF ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l06502"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15295bfc88388bbb0472e718dbb2e5e9"> 6502</a></span> <span class="preprocessor">#define LTDC_ICR_CTERRIF ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l06503"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36d2e96e5ac6c5a269131c6eadf5f552"> 6503</a></span> <span class="preprocessor">#define LTDC_ICR_CRRIF ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l06505"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45709c66c8322628434d48bacdc9f92d"> 6505</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for LTDC_LIPCR register ****************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06506"></a><span class="lineno"> 6506</span> </div>
|
|
<div class="line"><a name="l06507"></a><span class="lineno"> 6507</span> <span class="preprocessor">#define LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF) </span></div>
|
|
<div class="line"><a name="l06509"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1818ec63a734052e0b3652eb492a9cf3"> 6509</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for LTDC_CPSR register *****************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06510"></a><span class="lineno"> 6510</span> </div>
|
|
<div class="line"><a name="l06511"></a><span class="lineno"> 6511</span> <span class="preprocessor">#define LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF) </span></div>
|
|
<div class="line"><a name="l06512"></a><span class="lineno"> 6512</span> <span class="preprocessor">#define LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000) </span></div>
|
|
<div class="line"><a name="l06514"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1056b9d14adcc3a2bd1057fcb71eec9"> 6514</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for LTDC_CDSR register *****************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06515"></a><span class="lineno"> 6515</span> </div>
|
|
<div class="line"><a name="l06516"></a><span class="lineno"> 6516</span> <span class="preprocessor">#define LTDC_CDSR_VDES ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l06517"></a><span class="lineno"> 6517</span> <span class="preprocessor">#define LTDC_CDSR_HDES ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l06518"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e4c498e3baf6490c83ae67b7859b1ce"> 6518</a></span> <span class="preprocessor">#define LTDC_CDSR_VSYNCS ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l06519"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaea3bfe7426e5ee59e4a136f408a09716"> 6519</a></span> <span class="preprocessor">#define LTDC_CDSR_HSYNCS ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l06521"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9556e6ff6318d564c481fb022b9f254e"> 6521</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for LTDC_LxCR register *****************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06522"></a><span class="lineno"> 6522</span> </div>
|
|
<div class="line"><a name="l06523"></a><span class="lineno"> 6523</span> <span class="preprocessor">#define LTDC_LxCR_LEN ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l06524"></a><span class="lineno"> 6524</span> <span class="preprocessor">#define LTDC_LxCR_COLKEN ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l06525"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab4137ed7793f1e0399d2d4184f73eceb"> 6525</a></span> <span class="preprocessor">#define LTDC_LxCR_CLUTEN ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l06527"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ed020e503cd29e946528c9ac63846d5"> 6527</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for LTDC_LxWHPCR register **************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06528"></a><span class="lineno"> 6528</span> </div>
|
|
<div class="line"><a name="l06529"></a><span class="lineno"> 6529</span> <span class="preprocessor">#define LTDC_LxWHPCR_WHSTPOS ((uint32_t)0x00000FFF) </span></div>
|
|
<div class="line"><a name="l06530"></a><span class="lineno"> 6530</span> <span class="preprocessor">#define LTDC_LxWHPCR_WHSPPOS ((uint32_t)0xFFFF0000) </span></div>
|
|
<div class="line"><a name="l06532"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad75b147ab755274aa4baca5541a6993e"> 6532</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for LTDC_LxWVPCR register **************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06533"></a><span class="lineno"> 6533</span> </div>
|
|
<div class="line"><a name="l06534"></a><span class="lineno"> 6534</span> <span class="preprocessor">#define LTDC_LxWVPCR_WVSTPOS ((uint32_t)0x00000FFF) </span></div>
|
|
<div class="line"><a name="l06535"></a><span class="lineno"> 6535</span> <span class="preprocessor">#define LTDC_LxWVPCR_WVSPPOS ((uint32_t)0xFFFF0000) </span></div>
|
|
<div class="line"><a name="l06537"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8339caa7759f7159bb2aec90f6af49f9"> 6537</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for LTDC_LxCKCR register ***************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06538"></a><span class="lineno"> 6538</span> </div>
|
|
<div class="line"><a name="l06539"></a><span class="lineno"> 6539</span> <span class="preprocessor">#define LTDC_LxCKCR_CKBLUE ((uint32_t)0x000000FF) </span></div>
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|
<div class="line"><a name="l06540"></a><span class="lineno"> 6540</span> <span class="preprocessor">#define LTDC_LxCKCR_CKGREEN ((uint32_t)0x0000FF00) </span></div>
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|
<div class="line"><a name="l06541"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8fec067b174a76fcf8ee14b86addc7fa"> 6541</a></span> <span class="preprocessor">#define LTDC_LxCKCR_CKRED ((uint32_t)0x00FF0000) </span></div>
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|
<div class="line"><a name="l06543"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d0da8eeba215cd5327332a557b77c87"> 6543</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for LTDC_LxPFCR register ***************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06544"></a><span class="lineno"> 6544</span> </div>
|
|
<div class="line"><a name="l06545"></a><span class="lineno"> 6545</span> <span class="preprocessor">#define LTDC_LxPFCR_PF ((uint32_t)0x00000007) </span></div>
|
|
<div class="line"><a name="l06547"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6badb297e740d959d1971c6109a7f417"> 6547</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for LTDC_LxCACR register ***************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06548"></a><span class="lineno"> 6548</span> </div>
|
|
<div class="line"><a name="l06549"></a><span class="lineno"> 6549</span> <span class="preprocessor">#define LTDC_LxCACR_CONSTA ((uint32_t)0x000000FF) </span></div>
|
|
<div class="line"><a name="l06551"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad538e4df55b9d97c61bca14d93346a3"> 6551</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for LTDC_LxDCCR register ***************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06552"></a><span class="lineno"> 6552</span> </div>
|
|
<div class="line"><a name="l06553"></a><span class="lineno"> 6553</span> <span class="preprocessor">#define LTDC_LxDCCR_DCBLUE ((uint32_t)0x000000FF) </span></div>
|
|
<div class="line"><a name="l06554"></a><span class="lineno"> 6554</span> <span class="preprocessor">#define LTDC_LxDCCR_DCGREEN ((uint32_t)0x0000FF00) </span></div>
|
|
<div class="line"><a name="l06555"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91f017addde6d63278ed0872f95e9978"> 6555</a></span> <span class="preprocessor">#define LTDC_LxDCCR_DCRED ((uint32_t)0x00FF0000) </span></div>
|
|
<div class="line"><a name="l06556"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabab49201f0db066d5578b6a5e9cd3753"> 6556</a></span> <span class="preprocessor">#define LTDC_LxDCCR_DCALPHA ((uint32_t)0xFF000000) </span></div>
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|
<div class="line"><a name="l06558"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaacd6b290af2380f0e6d952200cc7b541"> 6558</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for LTDC_LxBFCR register ***************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06559"></a><span class="lineno"> 6559</span> </div>
|
|
<div class="line"><a name="l06560"></a><span class="lineno"> 6560</span> <span class="preprocessor">#define LTDC_LxBFCR_BF2 ((uint32_t)0x00000007) </span></div>
|
|
<div class="line"><a name="l06561"></a><span class="lineno"> 6561</span> <span class="preprocessor">#define LTDC_LxBFCR_BF1 ((uint32_t)0x00000700) </span></div>
|
|
<div class="line"><a name="l06563"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a130d060626796428774293042188f2"> 6563</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for LTDC_LxCFBAR register **************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06564"></a><span class="lineno"> 6564</span> </div>
|
|
<div class="line"><a name="l06565"></a><span class="lineno"> 6565</span> <span class="preprocessor">#define LTDC_LxCFBAR_CFBADD ((uint32_t)0xFFFFFFFF) </span></div>
|
|
<div class="line"><a name="l06567"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga533aa67a63316950180faf61ef5b72a9"> 6567</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for LTDC_LxCFBLR register **************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06568"></a><span class="lineno"> 6568</span> </div>
|
|
<div class="line"><a name="l06569"></a><span class="lineno"> 6569</span> <span class="preprocessor">#define LTDC_LxCFBLR_CFBLL ((uint32_t)0x00001FFF) </span></div>
|
|
<div class="line"><a name="l06570"></a><span class="lineno"> 6570</span> <span class="preprocessor">#define LTDC_LxCFBLR_CFBP ((uint32_t)0x1FFF0000) </span></div>
|
|
<div class="line"><a name="l06572"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08649b490876b957949df5334c9bdafe"> 6572</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for LTDC_LxCFBLNR register *************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06573"></a><span class="lineno"> 6573</span> </div>
|
|
<div class="line"><a name="l06574"></a><span class="lineno"> 6574</span> <span class="preprocessor">#define LTDC_LxCFBLNR_CFBLNBR ((uint32_t)0x000007FF) </span></div>
|
|
<div class="line"><a name="l06576"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5209baf02f3685749b1f22ea9de5532"> 6576</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for LTDC_LxCLUTWR register *************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06577"></a><span class="lineno"> 6577</span> </div>
|
|
<div class="line"><a name="l06578"></a><span class="lineno"> 6578</span> <span class="preprocessor">#define LTDC_LxCLUTWR_BLUE ((uint32_t)0x000000FF) </span></div>
|
|
<div class="line"><a name="l06579"></a><span class="lineno"> 6579</span> <span class="preprocessor">#define LTDC_LxCLUTWR_GREEN ((uint32_t)0x0000FF00) </span></div>
|
|
<div class="line"><a name="l06580"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae00786e8173c10ab75d240557a384590"> 6580</a></span> <span class="preprocessor">#define LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000) </span></div>
|
|
<div class="line"><a name="l06581"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad69ebaef3fa5e207583c452383902745"> 6581</a></span> <span class="preprocessor">#define LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000) </span></div>
|
|
<div class="line"><a name="l06583"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5b936eefb3a3b537f4914a745d94a41"> 6583</a></span> <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06584"></a><span class="lineno"> 6584</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l06585"></a><span class="lineno"> 6585</span> <span class="comment">/* Power Control */</span></div>
|
|
<div class="line"><a name="l06586"></a><span class="lineno"> 6586</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l06587"></a><span class="lineno"> 6587</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l06588"></a><span class="lineno"> 6588</span> <span class="comment">/******************** Bit definition for PWR_CR register ********************/</span></div>
|
|
<div class="line"><a name="l06589"></a><span class="lineno"> 6589</span> <span class="preprocessor">#define PWR_CR_LPDS ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l06590"></a><span class="lineno"> 6590</span> <span class="preprocessor">#define PWR_CR_PDDS ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l06591"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3aeb8d6f2539b0a3a4b851aeba0eea66"> 6591</a></span> <span class="preprocessor">#define PWR_CR_CWUF ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l06592"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8c8075e98772470804c9e3fe74984115"> 6592</a></span> <span class="preprocessor">#define PWR_CR_CSBF ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l06593"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3928de64f633b84770b1cfecea702fa7"> 6593</a></span> <span class="preprocessor">#define PWR_CR_PVDE ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l06595"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga05d5c39759e69a294c0ab9bea8f142e5"> 6595</a></span> <span class="preprocessor">#define PWR_CR_PLS ((uint32_t)0x000000E0) </span></div>
|
|
<div class="line"><a name="l06596"></a><span class="lineno"> 6596</span> <span class="preprocessor">#define PWR_CR_PLS_0 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l06597"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac73c24d43953c7598e42acdd4c4e7435"> 6597</a></span> <span class="preprocessor">#define PWR_CR_PLS_1 ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l06598"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacef447510818c468c202e3b4991ea08e"> 6598</a></span> <span class="preprocessor">#define PWR_CR_PLS_2 ((uint32_t)0x00000080) </span></div>
|
|
<div class="line"><a name="l06601"></a><span class="lineno"> 6601</span> <span class="preprocessor">#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) </span></div>
|
|
<div class="line"><a name="l06602"></a><span class="lineno"> 6602</span> <span class="preprocessor">#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l06603"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacb6b904b20d7e4fff958c75748861216"> 6603</a></span> <span class="preprocessor">#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l06604"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15b71263f73f0c4e53ca91fc8d096818"> 6604</a></span> <span class="preprocessor">#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) </span></div>
|
|
<div class="line"><a name="l06605"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ea128abc2fc4252b53d09ca2850e69e"> 6605</a></span> <span class="preprocessor">#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) </span></div>
|
|
<div class="line"><a name="l06606"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c1782980a2fb12de80058729a74f174"> 6606</a></span> <span class="preprocessor">#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) </span></div>
|
|
<div class="line"><a name="l06607"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0fe79f097ea6c30a4ccf69ed3e177f85"> 6607</a></span> <span class="preprocessor">#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) </span></div>
|
|
<div class="line"><a name="l06608"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga326781d09a07b4d215424fbbae11b7b2"> 6608</a></span> <span class="preprocessor">#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) </span></div>
|
|
<div class="line"><a name="l06610"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95e3b301b5470ae94d32c53a9fbdfc8b"> 6610</a></span> <span class="preprocessor">#define PWR_CR_DBP ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l06611"></a><span class="lineno"> 6611</span> <span class="preprocessor">#define PWR_CR_FPDS ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l06612"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf5c65ab845794ef48f09faa2ee44f718"> 6612</a></span> <span class="preprocessor">#define PWR_CR_LPUDS ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l06613"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc01f8b6d4bd0294f745fde6d8e57002"> 6613</a></span> <span class="preprocessor">#define PWR_CR_MRUDS ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l06614"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1c7718e2c1a57985f79776683bb5464"> 6614</a></span> <span class="preprocessor">#define PWR_CR_LPLVDS ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l06615"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga59c516cad11a310e8c5b560b00220d45"> 6615</a></span> <span class="preprocessor">#define PWR_CR_MRLVDS ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l06617"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40e8c390899e9e836f1c52d90b64488d"> 6617</a></span> <span class="preprocessor">#define PWR_CR_ADCDC1 ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l06619"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga977b89f2739e32b704194a6995d3d33d"> 6619</a></span> <span class="preprocessor">#define PWR_CR_VOS ((uint32_t)0x0000C000) </span></div>
|
|
<div class="line"><a name="l06620"></a><span class="lineno"> 6620</span> <span class="preprocessor">#define PWR_CR_VOS_0 ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l06621"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaccc33f1ba4e374e116ffa50f3a503030"> 6621</a></span> <span class="preprocessor">#define PWR_CR_VOS_1 ((uint32_t)0x00008000) </span></div>
|
|
<div class="line"><a name="l06623"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3093c26b256c965cebec3b2e388a3b4"> 6623</a></span> <span class="preprocessor">#define PWR_CR_ODEN ((uint32_t)0x00010000) </span></div>
|
|
<div class="line"><a name="l06624"></a><span class="lineno"> 6624</span> <span class="preprocessor">#define PWR_CR_ODSWEN ((uint32_t)0x00020000) </span></div>
|
|
<div class="line"><a name="l06625"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbb849c6c4908d6f08f4fdc28d702522"> 6625</a></span> <span class="preprocessor">#define PWR_CR_UDEN ((uint32_t)0x000C0000) </span></div>
|
|
<div class="line"><a name="l06626"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1e865d13e084ed53bded37c3cdea173"> 6626</a></span> <span class="preprocessor">#define PWR_CR_UDEN_0 ((uint32_t)0x00040000) </span></div>
|
|
<div class="line"><a name="l06627"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga150acdf90bcc4c040af0d1f5e1055f4a"> 6627</a></span> <span class="preprocessor">#define PWR_CR_UDEN_1 ((uint32_t)0x00080000) </span></div>
|
|
<div class="line"><a name="l06629"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab974d921fa98b211719002f5830bbae4"> 6629</a></span> <span class="preprocessor">#define PWR_CR_FMSSR ((uint32_t)0x00100000) </span></div>
|
|
<div class="line"><a name="l06630"></a><span class="lineno"> 6630</span> <span class="preprocessor">#define PWR_CR_FISSR ((uint32_t)0x00200000) </span></div>
|
|
<div class="line"><a name="l06632"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga36967ef7baeaedfc30f125092ee59b30"> 6632</a></span> <span class="preprocessor"></span><span class="comment">/* Legacy define */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06633"></a><span class="lineno"> 6633</span> <span class="preprocessor">#define PWR_CR_PMODE PWR_CR_VOS</span></div>
|
|
<div class="line"><a name="l06634"></a><span class="lineno"> 6634</span> </div>
|
|
<div class="line"><a name="l06635"></a><span class="lineno"> 6635</span> <span class="comment">/******************* Bit definition for PWR_CSR register ********************/</span></div>
|
|
<div class="line"><a name="l06636"></a><span class="lineno"> 6636</span> <span class="preprocessor">#define PWR_CSR_WUF ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l06637"></a><span class="lineno"> 6637</span> <span class="preprocessor">#define PWR_CSR_SBF ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l06638"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9465bb7ad9ca936688344e2a077539e6"> 6638</a></span> <span class="preprocessor">#define PWR_CSR_PVDO ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l06639"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab4fd42f153660593cad6f4fe22ff76bb"> 6639</a></span> <span class="preprocessor">#define PWR_CSR_BRR ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l06640"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3535ce181895cc00afeb28dcac68d04c"> 6640</a></span> <span class="preprocessor">#define PWR_CSR_EWUP ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l06641"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga939410de980c5bc297ff04bcf30875cc"> 6641</a></span> <span class="preprocessor">#define PWR_CSR_BRE ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l06642"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ac8c15a08bbee754ea720b0d4a4f580"> 6642</a></span> <span class="preprocessor">#define PWR_CSR_VOSRDY ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l06643"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f99becaceb185431dbf46fb22718d0a"> 6643</a></span> <span class="preprocessor">#define PWR_CSR_ODRDY ((uint32_t)0x00010000) </span></div>
|
|
<div class="line"><a name="l06644"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4126ed19cce54a5411ff8dd440171695"> 6644</a></span> <span class="preprocessor">#define PWR_CSR_ODSWRDY ((uint32_t)0x00020000) </span></div>
|
|
<div class="line"><a name="l06645"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae35dfabd53bc335d95d330442cdfac6d"> 6645</a></span> <span class="preprocessor">#define PWR_CSR_UDSWRDY ((uint32_t)0x000C0000) </span></div>
|
|
<div class="line"><a name="l06647"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31f0172b9dcefa55d772d4cb0eed6687"> 6647</a></span> <span class="preprocessor"></span><span class="comment">/* Legacy define */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l06648"></a><span class="lineno"> 6648</span> <span class="preprocessor">#define PWR_CSR_REGRDY PWR_CSR_VOSRDY</span></div>
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<div class="line"><a name="l06649"></a><span class="lineno"> 6649</span> </div>
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<div class="line"><a name="l06650"></a><span class="lineno"> 6650</span> <span class="comment">/******************************************************************************/</span></div>
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<div class="line"><a name="l06651"></a><span class="lineno"> 6651</span> <span class="comment">/* */</span></div>
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<div class="line"><a name="l06652"></a><span class="lineno"> 6652</span> <span class="comment">/* Reset and Clock Control */</span></div>
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<div class="line"><a name="l06653"></a><span class="lineno"> 6653</span> <span class="comment">/* */</span></div>
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<div class="line"><a name="l06654"></a><span class="lineno"> 6654</span> <span class="comment">/******************************************************************************/</span></div>
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<div class="line"><a name="l06655"></a><span class="lineno"> 6655</span> <span class="comment">/******************** Bit definition for RCC_CR register ********************/</span></div>
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<div class="line"><a name="l06656"></a><span class="lineno"> 6656</span> <span class="preprocessor">#define RCC_CR_HSION ((uint32_t)0x00000001)</span></div>
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<div class="line"><a name="l06657"></a><span class="lineno"> 6657</span> <span class="preprocessor">#define RCC_CR_HSIRDY ((uint32_t)0x00000002)</span></div>
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<div class="line"><a name="l06658"></a><span class="lineno"> 6658</span> </div>
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<div class="line"><a name="l06659"></a><span class="lineno"> 6659</span> <span class="preprocessor">#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)</span></div>
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<div class="line"><a name="l06660"></a><span class="lineno"> 6660</span> <span class="preprocessor">#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)</span></div>
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<div class="line"><a name="l06661"></a><span class="lineno"> 6661</span> <span class="preprocessor">#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)</span></div>
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|
<div class="line"><a name="l06662"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab999bbbc1d365d0100d34eaa9f426eb"> 6662</a></span> <span class="preprocessor">#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)</span></div>
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|
<div class="line"><a name="l06663"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga569d6a29d774e0f125b0c2b3671fae3c"> 6663</a></span> <span class="preprocessor">#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)</span></div>
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|
<div class="line"><a name="l06664"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga10d80d64137e36f5183f6aa7002de6f5"> 6664</a></span> <span class="preprocessor">#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)</span></div>
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|
<div class="line"><a name="l06666"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f9ab2e93a0b9b70d33812bcc5e920c1"> 6666</a></span> <span class="preprocessor">#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)</span></div>
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<div class="line"><a name="l06667"></a><span class="lineno"> 6667</span> <span class="preprocessor">#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)</span></div>
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<div class="line"><a name="l06668"></a><span class="lineno"> 6668</span> <span class="preprocessor">#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)</span></div>
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|
<div class="line"><a name="l06669"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad7daa7754e54d65916ddc54f37274d3a"> 6669</a></span> <span class="preprocessor">#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)</span></div>
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|
<div class="line"><a name="l06670"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78054087161dee567cadbb4b4b96fb08"> 6670</a></span> <span class="preprocessor">#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)</span></div>
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|
<div class="line"><a name="l06671"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab0c4bac85beb7de5916897f88150dc3f"> 6671</a></span> <span class="preprocessor">#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)</span></div>
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|
<div class="line"><a name="l06672"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga03f71cd53f075e9d35fcbfe7ed3f6e12"> 6672</a></span> <span class="preprocessor">#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)</span></div>
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|
<div class="line"><a name="l06673"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf26eb00e1872a3754f200a3c32019e50"> 6673</a></span> <span class="preprocessor">#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)</span></div>
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|
<div class="line"><a name="l06674"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c5b733061a3c4c6d69a7a15cbcb0b87"> 6674</a></span> <span class="preprocessor">#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)</span></div>
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|
<div class="line"><a name="l06676"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab42d5e412867df093ec2ea4b8dc2bf29"> 6676</a></span> <span class="preprocessor">#define RCC_CR_HSEON ((uint32_t)0x00010000)</span></div>
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|
<div class="line"><a name="l06677"></a><span class="lineno"> 6677</span> <span class="preprocessor">#define RCC_CR_HSERDY ((uint32_t)0x00020000)</span></div>
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|
<div class="line"><a name="l06678"></a><span class="lineno"> 6678</span> <span class="preprocessor">#define RCC_CR_HSEBYP ((uint32_t)0x00040000)</span></div>
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|
<div class="line"><a name="l06679"></a><span class="lineno"> 6679</span> <span class="preprocessor">#define RCC_CR_CSSON ((uint32_t)0x00080000)</span></div>
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|
<div class="line"><a name="l06680"></a><span class="lineno"> 6680</span> <span class="preprocessor">#define RCC_CR_PLLON ((uint32_t)0x01000000)</span></div>
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|
<div class="line"><a name="l06681"></a><span class="lineno"> 6681</span> <span class="preprocessor">#define RCC_CR_PLLRDY ((uint32_t)0x02000000)</span></div>
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|
<div class="line"><a name="l06682"></a><span class="lineno"> 6682</span> <span class="preprocessor">#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)</span></div>
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|
<div class="line"><a name="l06683"></a><span class="lineno"> 6683</span> <span class="preprocessor">#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)</span></div>
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|
<div class="line"><a name="l06684"></a><span class="lineno"> 6684</span> <span class="preprocessor">#define RCC_CR_PLLSAION ((uint32_t)0x10000000)</span></div>
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|
<div class="line"><a name="l06685"></a><span class="lineno"> 6685</span> <span class="preprocessor">#define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)</span></div>
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|
<div class="line"><a name="l06686"></a><span class="lineno"> 6686</span> </div>
|
|
<div class="line"><a name="l06687"></a><span class="lineno"> 6687</span> <span class="comment">/******************** Bit definition for RCC_PLLCFGR register ***************/</span></div>
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|
<div class="line"><a name="l06688"></a><span class="lineno"> 6688</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)</span></div>
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|
<div class="line"><a name="l06689"></a><span class="lineno"> 6689</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)</span></div>
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|
<div class="line"><a name="l06690"></a><span class="lineno"> 6690</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)</span></div>
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|
<div class="line"><a name="l06691"></a><span class="lineno"> 6691</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)</span></div>
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|
<div class="line"><a name="l06692"></a><span class="lineno"> 6692</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)</span></div>
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|
<div class="line"><a name="l06693"></a><span class="lineno"> 6693</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)</span></div>
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|
<div class="line"><a name="l06694"></a><span class="lineno"> 6694</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)</span></div>
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|
<div class="line"><a name="l06695"></a><span class="lineno"> 6695</span> </div>
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|
<div class="line"><a name="l06696"></a><span class="lineno"> 6696</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)</span></div>
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|
<div class="line"><a name="l06697"></a><span class="lineno"> 6697</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)</span></div>
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|
<div class="line"><a name="l06698"></a><span class="lineno"> 6698</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)</span></div>
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|
<div class="line"><a name="l06699"></a><span class="lineno"> 6699</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)</span></div>
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|
<div class="line"><a name="l06700"></a><span class="lineno"> 6700</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)</span></div>
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|
<div class="line"><a name="l06701"></a><span class="lineno"> 6701</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)</span></div>
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|
<div class="line"><a name="l06702"></a><span class="lineno"> 6702</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)</span></div>
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|
<div class="line"><a name="l06703"></a><span class="lineno"> 6703</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)</span></div>
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|
<div class="line"><a name="l06704"></a><span class="lineno"> 6704</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)</span></div>
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|
<div class="line"><a name="l06705"></a><span class="lineno"> 6705</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)</span></div>
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|
<div class="line"><a name="l06706"></a><span class="lineno"> 6706</span> </div>
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|
<div class="line"><a name="l06707"></a><span class="lineno"> 6707</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)</span></div>
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|
<div class="line"><a name="l06708"></a><span class="lineno"> 6708</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)</span></div>
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|
<div class="line"><a name="l06709"></a><span class="lineno"> 6709</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)</span></div>
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|
<div class="line"><a name="l06710"></a><span class="lineno"> 6710</span> </div>
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|
<div class="line"><a name="l06711"></a><span class="lineno"> 6711</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)</span></div>
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|
<div class="line"><a name="l06712"></a><span class="lineno"> 6712</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)</span></div>
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|
<div class="line"><a name="l06713"></a><span class="lineno"> 6713</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)</span></div>
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|
<div class="line"><a name="l06714"></a><span class="lineno"> 6714</span> </div>
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|
<div class="line"><a name="l06715"></a><span class="lineno"> 6715</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)</span></div>
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|
<div class="line"><a name="l06716"></a><span class="lineno"> 6716</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)</span></div>
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|
<div class="line"><a name="l06717"></a><span class="lineno"> 6717</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)</span></div>
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|
<div class="line"><a name="l06718"></a><span class="lineno"> 6718</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)</span></div>
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|
<div class="line"><a name="l06719"></a><span class="lineno"> 6719</span> <span class="preprocessor">#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)</span></div>
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|
<div class="line"><a name="l06720"></a><span class="lineno"> 6720</span> </div>
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|
<div class="line"><a name="l06721"></a><span class="lineno"> 6721</span> <span class="comment">/******************** Bit definition for RCC_CFGR register ******************/</span></div>
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|
<div class="line"><a name="l06723"></a><span class="lineno"> 6723</span> <span class="preprocessor">#define RCC_CFGR_SW ((uint32_t)0x00000003) </span></div>
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|
<div class="line"><a name="l06724"></a><span class="lineno"> 6724</span> <span class="preprocessor">#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) </span></div>
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|
<div class="line"><a name="l06725"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0eea5e5f7743a7e8995b8beeb18355c1"> 6725</a></span> <span class="preprocessor">#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) </span></div>
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|
<div class="line"><a name="l06727"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga72d51cb5d66ee1aa4d2c6f14796a072f"> 6727</a></span> <span class="preprocessor">#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) </span></div>
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|
<div class="line"><a name="l06728"></a><span class="lineno"> 6728</span> <span class="preprocessor">#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) </span></div>
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|
<div class="line"><a name="l06729"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacbac8bae4f0808b3c3a5185aa10081fb"> 6729</a></span> <span class="preprocessor">#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) </span></div>
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|
<div class="line"><a name="l06732"></a><span class="lineno"> 6732</span> <span class="preprocessor">#define RCC_CFGR_SWS ((uint32_t)0x0000000C) </span></div>
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<div class="line"><a name="l06733"></a><span class="lineno"> 6733</span> <span class="preprocessor">#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) </span></div>
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|
<div class="line"><a name="l06734"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15bf2269500dc97e137315f44aa015c9"> 6734</a></span> <span class="preprocessor">#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) </span></div>
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|
<div class="line"><a name="l06736"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad3a5718999d7259f216137a23c2a379"> 6736</a></span> <span class="preprocessor">#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) </span></div>
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|
<div class="line"><a name="l06737"></a><span class="lineno"> 6737</span> <span class="preprocessor">#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) </span></div>
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|
<div class="line"><a name="l06738"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6764639cf221e1ebc0b5448dcaed590a"> 6738</a></span> <span class="preprocessor">#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l06741"></a><span class="lineno"> 6741</span> <span class="preprocessor">#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) </span></div>
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<div class="line"><a name="l06742"></a><span class="lineno"> 6742</span> <span class="preprocessor">#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l06743"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe10e66938644ee8054a2426ff23efea"> 6743</a></span> <span class="preprocessor">#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l06744"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga88ece6ca270b3ecf6f63bf20893bc172"> 6744</a></span> <span class="preprocessor">#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l06745"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacbdd3a02814178ba02b8ebbaccd91599"> 6745</a></span> <span class="preprocessor">#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) </span></div>
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|
<div class="line"><a name="l06747"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a1180512cc5f3dde7895040a9037286"> 6747</a></span> <span class="preprocessor">#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) </span></div>
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<div class="line"><a name="l06748"></a><span class="lineno"> 6748</span> <span class="preprocessor">#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l06749"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b7d7f29b09a49c31404fc0d44645c84"> 6749</a></span> <span class="preprocessor">#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) </span></div>
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<div class="line"><a name="l06750"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa9eeb5e38e53e79b08a4ac438497ebea"> 6750</a></span> <span class="preprocessor">#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) </span></div>
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<div class="line"><a name="l06751"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaffe860867ae4b1b6d28473ded1546d91"> 6751</a></span> <span class="preprocessor">#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) </span></div>
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<div class="line"><a name="l06752"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaca71d6b42bdb83b5ff5320578869a058"> 6752</a></span> <span class="preprocessor">#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) </span></div>
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<div class="line"><a name="l06753"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3806da4f1afc9e5be0fca001c8c57815"> 6753</a></span> <span class="preprocessor">#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) </span></div>
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<div class="line"><a name="l06754"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1caeba8dc2b4c0bb11be600e983e3370"> 6754</a></span> <span class="preprocessor">#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) </span></div>
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<div class="line"><a name="l06755"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga280da821f0da1bec1f4c0e132ddf8eab"> 6755</a></span> <span class="preprocessor">#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) </span></div>
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<div class="line"><a name="l06758"></a><span class="lineno"> 6758</span> <span class="preprocessor">#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) </span></div>
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<div class="line"><a name="l06759"></a><span class="lineno"> 6759</span> <span class="preprocessor">#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l06760"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga50b2423a5fea74a47b9eb8ab51869412"> 6760</a></span> <span class="preprocessor">#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l06761"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d37c20686faa340a77021117f5908b7"> 6761</a></span> <span class="preprocessor">#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l06763"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5fcb524f6ca203ddff1862c124d4f89f"> 6763</a></span> <span class="preprocessor">#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) </span></div>
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<div class="line"><a name="l06764"></a><span class="lineno"> 6764</span> <span class="preprocessor">#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l06765"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8f6562bb2ecf65055a2f42cbb48ef11"> 6765</a></span> <span class="preprocessor">#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) </span></div>
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<div class="line"><a name="l06766"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf832ad6844c907d9bb37c1536defcb0d"> 6766</a></span> <span class="preprocessor">#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) </span></div>
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<div class="line"><a name="l06767"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e340725f46e9462d9b02a079b9fa8ae"> 6767</a></span> <span class="preprocessor">#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) </span></div>
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<div class="line"><a name="l06770"></a><span class="lineno"> 6770</span> <span class="preprocessor">#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) </span></div>
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<div class="line"><a name="l06771"></a><span class="lineno"> 6771</span> <span class="preprocessor">#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l06772"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad61bd4f9f345ba41806813b0bfff1311"> 6772</a></span> <span class="preprocessor">#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l06773"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga82ca63155494ed59eb5e34bec1e5f4e9"> 6773</a></span> <span class="preprocessor">#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l06775"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9adc802687eab5b6ece99a20793219db"> 6775</a></span> <span class="preprocessor">#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) </span></div>
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<div class="line"><a name="l06776"></a><span class="lineno"> 6776</span> <span class="preprocessor">#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l06777"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga247aebf1999a38ea07785558d277bb1a"> 6777</a></span> <span class="preprocessor">#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) </span></div>
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<div class="line"><a name="l06778"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99d9c91eaad122460d324a71cc939d1b"> 6778</a></span> <span class="preprocessor">#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) </span></div>
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<div class="line"><a name="l06779"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4340fc3fc52eca36eb302959fbecb715"> 6779</a></span> <span class="preprocessor">#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) </span></div>
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<div class="line"><a name="l06782"></a><span class="lineno"> 6782</span> <span class="preprocessor">#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)</span></div>
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<div class="line"><a name="l06783"></a><span class="lineno"> 6783</span> <span class="preprocessor">#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)</span></div>
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<div class="line"><a name="l06784"></a><span class="lineno"> 6784</span> <span class="preprocessor">#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)</span></div>
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<div class="line"><a name="l06785"></a><span class="lineno"> 6785</span> <span class="preprocessor">#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)</span></div>
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<div class="line"><a name="l06786"></a><span class="lineno"> 6786</span> <span class="preprocessor">#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)</span></div>
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<div class="line"><a name="l06787"></a><span class="lineno"> 6787</span> <span class="preprocessor">#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)</span></div>
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<div class="line"><a name="l06788"></a><span class="lineno"> 6788</span> </div>
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<div class="line"><a name="l06790"></a><span class="lineno"> 6790</span> <span class="preprocessor">#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)</span></div>
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<div class="line"><a name="l06791"></a><span class="lineno"> 6791</span> <span class="preprocessor">#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)</span></div>
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<div class="line"><a name="l06792"></a><span class="lineno"> 6792</span> <span class="preprocessor">#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)</span></div>
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<div class="line"><a name="l06793"></a><span class="lineno"> 6793</span> </div>
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<div class="line"><a name="l06794"></a><span class="lineno"> 6794</span> <span class="preprocessor">#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)</span></div>
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<div class="line"><a name="l06795"></a><span class="lineno"> 6795</span> </div>
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<div class="line"><a name="l06796"></a><span class="lineno"> 6796</span> <span class="preprocessor">#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)</span></div>
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<div class="line"><a name="l06797"></a><span class="lineno"> 6797</span> <span class="preprocessor">#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)</span></div>
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<div class="line"><a name="l06798"></a><span class="lineno"> 6798</span> <span class="preprocessor">#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)</span></div>
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<div class="line"><a name="l06799"></a><span class="lineno"> 6799</span> <span class="preprocessor">#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)</span></div>
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<div class="line"><a name="l06800"></a><span class="lineno"> 6800</span> </div>
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<div class="line"><a name="l06801"></a><span class="lineno"> 6801</span> <span class="preprocessor">#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)</span></div>
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<div class="line"><a name="l06802"></a><span class="lineno"> 6802</span> <span class="preprocessor">#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)</span></div>
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<div class="line"><a name="l06803"></a><span class="lineno"> 6803</span> <span class="preprocessor">#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)</span></div>
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<div class="line"><a name="l06804"></a><span class="lineno"> 6804</span> <span class="preprocessor">#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)</span></div>
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<div class="line"><a name="l06805"></a><span class="lineno"> 6805</span> </div>
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<div class="line"><a name="l06806"></a><span class="lineno"> 6806</span> <span class="preprocessor">#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)</span></div>
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<div class="line"><a name="l06807"></a><span class="lineno"> 6807</span> <span class="preprocessor">#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)</span></div>
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<div class="line"><a name="l06808"></a><span class="lineno"> 6808</span> <span class="preprocessor">#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)</span></div>
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<div class="line"><a name="l06809"></a><span class="lineno"> 6809</span> </div>
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<div class="line"><a name="l06810"></a><span class="lineno"> 6810</span> <span class="comment">/******************** Bit definition for RCC_CIR register *******************/</span></div>
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<div class="line"><a name="l06811"></a><span class="lineno"> 6811</span> <span class="preprocessor">#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)</span></div>
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<div class="line"><a name="l06812"></a><span class="lineno"> 6812</span> <span class="preprocessor">#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)</span></div>
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<div class="line"><a name="l06813"></a><span class="lineno"> 6813</span> <span class="preprocessor">#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)</span></div>
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<div class="line"><a name="l06814"></a><span class="lineno"> 6814</span> <span class="preprocessor">#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)</span></div>
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<div class="line"><a name="l06815"></a><span class="lineno"> 6815</span> <span class="preprocessor">#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)</span></div>
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<div class="line"><a name="l06816"></a><span class="lineno"> 6816</span> <span class="preprocessor">#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)</span></div>
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<div class="line"><a name="l06817"></a><span class="lineno"> 6817</span> <span class="preprocessor">#define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)</span></div>
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<div class="line"><a name="l06818"></a><span class="lineno"> 6818</span> <span class="preprocessor">#define RCC_CIR_CSSF ((uint32_t)0x00000080)</span></div>
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<div class="line"><a name="l06819"></a><span class="lineno"> 6819</span> <span class="preprocessor">#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)</span></div>
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<div class="line"><a name="l06820"></a><span class="lineno"> 6820</span> <span class="preprocessor">#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)</span></div>
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<div class="line"><a name="l06821"></a><span class="lineno"> 6821</span> <span class="preprocessor">#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)</span></div>
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<div class="line"><a name="l06822"></a><span class="lineno"> 6822</span> <span class="preprocessor">#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)</span></div>
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<div class="line"><a name="l06823"></a><span class="lineno"> 6823</span> <span class="preprocessor">#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)</span></div>
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<div class="line"><a name="l06824"></a><span class="lineno"> 6824</span> <span class="preprocessor">#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)</span></div>
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<div class="line"><a name="l06825"></a><span class="lineno"> 6825</span> <span class="preprocessor">#define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)</span></div>
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<div class="line"><a name="l06826"></a><span class="lineno"> 6826</span> <span class="preprocessor">#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)</span></div>
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<div class="line"><a name="l06827"></a><span class="lineno"> 6827</span> <span class="preprocessor">#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)</span></div>
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<div class="line"><a name="l06828"></a><span class="lineno"> 6828</span> <span class="preprocessor">#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)</span></div>
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<div class="line"><a name="l06829"></a><span class="lineno"> 6829</span> <span class="preprocessor">#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)</span></div>
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<div class="line"><a name="l06830"></a><span class="lineno"> 6830</span> <span class="preprocessor">#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)</span></div>
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<div class="line"><a name="l06831"></a><span class="lineno"> 6831</span> <span class="preprocessor">#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)</span></div>
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<div class="line"><a name="l06832"></a><span class="lineno"> 6832</span> <span class="preprocessor">#define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)</span></div>
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<div class="line"><a name="l06833"></a><span class="lineno"> 6833</span> <span class="preprocessor">#define RCC_CIR_CSSC ((uint32_t)0x00800000)</span></div>
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<div class="line"><a name="l06834"></a><span class="lineno"> 6834</span> </div>
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<div class="line"><a name="l06835"></a><span class="lineno"> 6835</span> <span class="comment">/******************** Bit definition for RCC_AHB1RSTR register **************/</span></div>
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<div class="line"><a name="l06836"></a><span class="lineno"> 6836</span> <span class="preprocessor">#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)</span></div>
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<div class="line"><a name="l06837"></a><span class="lineno"> 6837</span> <span class="preprocessor">#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)</span></div>
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<div class="line"><a name="l06838"></a><span class="lineno"> 6838</span> <span class="preprocessor">#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)</span></div>
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<div class="line"><a name="l06839"></a><span class="lineno"> 6839</span> <span class="preprocessor">#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)</span></div>
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<div class="line"><a name="l06840"></a><span class="lineno"> 6840</span> <span class="preprocessor">#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)</span></div>
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<div class="line"><a name="l06841"></a><span class="lineno"> 6841</span> <span class="preprocessor">#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)</span></div>
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<div class="line"><a name="l06842"></a><span class="lineno"> 6842</span> <span class="preprocessor">#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)</span></div>
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<div class="line"><a name="l06843"></a><span class="lineno"> 6843</span> <span class="preprocessor">#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)</span></div>
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<div class="line"><a name="l06844"></a><span class="lineno"> 6844</span> <span class="preprocessor">#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)</span></div>
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<div class="line"><a name="l06845"></a><span class="lineno"> 6845</span> <span class="preprocessor">#define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)</span></div>
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<div class="line"><a name="l06846"></a><span class="lineno"> 6846</span> <span class="preprocessor">#define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)</span></div>
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<div class="line"><a name="l06847"></a><span class="lineno"> 6847</span> <span class="preprocessor">#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)</span></div>
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<div class="line"><a name="l06848"></a><span class="lineno"> 6848</span> <span class="preprocessor">#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)</span></div>
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<div class="line"><a name="l06849"></a><span class="lineno"> 6849</span> <span class="preprocessor">#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)</span></div>
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<div class="line"><a name="l06850"></a><span class="lineno"> 6850</span> <span class="preprocessor">#define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)</span></div>
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<div class="line"><a name="l06851"></a><span class="lineno"> 6851</span> <span class="preprocessor">#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)</span></div>
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<div class="line"><a name="l06852"></a><span class="lineno"> 6852</span> <span class="preprocessor">#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)</span></div>
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<div class="line"><a name="l06853"></a><span class="lineno"> 6853</span> </div>
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<div class="line"><a name="l06854"></a><span class="lineno"> 6854</span> <span class="comment">/******************** Bit definition for RCC_AHB2RSTR register **************/</span></div>
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<div class="line"><a name="l06855"></a><span class="lineno"> 6855</span> <span class="preprocessor">#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)</span></div>
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<div class="line"><a name="l06856"></a><span class="lineno"> 6856</span> <span class="preprocessor">#define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)</span></div>
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<div class="line"><a name="l06857"></a><span class="lineno"> 6857</span> <span class="preprocessor">#define RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020)</span></div>
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<div class="line"><a name="l06858"></a><span class="lineno"> 6858</span>  <span class="comment">/* maintained for legacy purpose */</span></div>
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<div class="line"><a name="l06859"></a><span class="lineno"> 6859</span> <span class="preprocessor"> #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST</span></div>
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<div class="line"><a name="l06860"></a><span class="lineno"> 6860</span> <span class="preprocessor">#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)</span></div>
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<div class="line"><a name="l06861"></a><span class="lineno"> 6861</span> <span class="preprocessor">#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)</span></div>
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<div class="line"><a name="l06862"></a><span class="lineno"> 6862</span> </div>
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<div class="line"><a name="l06863"></a><span class="lineno"> 6863</span> <span class="comment">/******************** Bit definition for RCC_AHB3RSTR register **************/</span></div>
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<div class="line"><a name="l06864"></a><span class="lineno"> 6864</span> <span class="preprocessor">#if defined(STM32F40_41xxx)</span></div>
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<div class="line"><a name="l06865"></a><span class="lineno"> 6865</span> <span class="preprocessor">#define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)</span></div>
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<div class="line"><a name="l06866"></a><span class="lineno"> 6866</span> <span class="preprocessor">#endif </span><span class="comment">/* STM32F40_41xxx */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l06867"></a><span class="lineno"> 6867</span> </div>
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<div class="line"><a name="l06868"></a><span class="lineno"> 6868</span> <span class="preprocessor">#if defined (STM32F427_437xx) || defined (STM32F429_439xx)</span></div>
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<div class="line"><a name="l06869"></a><span class="lineno"> 6869</span> <span class="preprocessor">#define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)</span></div>
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<div class="line"><a name="l06870"></a><span class="lineno"> 6870</span> <span class="preprocessor">#endif </span><span class="comment">/* STM32F427_437xx || STM32F429_439xx */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l06871"></a><span class="lineno"> 6871</span> <span class="comment">/******************** Bit definition for RCC_APB1RSTR register **************/</span></div>
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<div class="line"><a name="l06872"></a><span class="lineno"> 6872</span> <span class="preprocessor">#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)</span></div>
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<div class="line"><a name="l06873"></a><span class="lineno"> 6873</span> <span class="preprocessor">#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)</span></div>
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<div class="line"><a name="l06874"></a><span class="lineno"> 6874</span> <span class="preprocessor">#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)</span></div>
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<div class="line"><a name="l06875"></a><span class="lineno"> 6875</span> <span class="preprocessor">#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)</span></div>
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<div class="line"><a name="l06876"></a><span class="lineno"> 6876</span> <span class="preprocessor">#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)</span></div>
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<div class="line"><a name="l06877"></a><span class="lineno"> 6877</span> <span class="preprocessor">#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)</span></div>
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<div class="line"><a name="l06878"></a><span class="lineno"> 6878</span> <span class="preprocessor">#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)</span></div>
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<div class="line"><a name="l06879"></a><span class="lineno"> 6879</span> <span class="preprocessor">#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)</span></div>
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<div class="line"><a name="l06880"></a><span class="lineno"> 6880</span> <span class="preprocessor">#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)</span></div>
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<div class="line"><a name="l06881"></a><span class="lineno"> 6881</span> <span class="preprocessor">#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)</span></div>
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<div class="line"><a name="l06882"></a><span class="lineno"> 6882</span> <span class="preprocessor">#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)</span></div>
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<div class="line"><a name="l06883"></a><span class="lineno"> 6883</span> <span class="preprocessor">#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)</span></div>
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<div class="line"><a name="l06884"></a><span class="lineno"> 6884</span> <span class="preprocessor">#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)</span></div>
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<div class="line"><a name="l06885"></a><span class="lineno"> 6885</span> <span class="preprocessor">#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)</span></div>
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<div class="line"><a name="l06886"></a><span class="lineno"> 6886</span> <span class="preprocessor">#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)</span></div>
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<div class="line"><a name="l06887"></a><span class="lineno"> 6887</span> <span class="preprocessor">#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)</span></div>
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|
<div class="line"><a name="l06888"></a><span class="lineno"> 6888</span> <span class="preprocessor">#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)</span></div>
|
|
<div class="line"><a name="l06889"></a><span class="lineno"> 6889</span> <span class="preprocessor">#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)</span></div>
|
|
<div class="line"><a name="l06890"></a><span class="lineno"> 6890</span> <span class="preprocessor">#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)</span></div>
|
|
<div class="line"><a name="l06891"></a><span class="lineno"> 6891</span> <span class="preprocessor">#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)</span></div>
|
|
<div class="line"><a name="l06892"></a><span class="lineno"> 6892</span> <span class="preprocessor">#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)</span></div>
|
|
<div class="line"><a name="l06893"></a><span class="lineno"> 6893</span> <span class="preprocessor">#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)</span></div>
|
|
<div class="line"><a name="l06894"></a><span class="lineno"> 6894</span> <span class="preprocessor">#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)</span></div>
|
|
<div class="line"><a name="l06895"></a><span class="lineno"> 6895</span> <span class="preprocessor">#define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)</span></div>
|
|
<div class="line"><a name="l06896"></a><span class="lineno"> 6896</span> <span class="preprocessor">#define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)</span></div>
|
|
<div class="line"><a name="l06897"></a><span class="lineno"> 6897</span> </div>
|
|
<div class="line"><a name="l06898"></a><span class="lineno"> 6898</span> <span class="comment">/******************** Bit definition for RCC_APB2RSTR register **************/</span></div>
|
|
<div class="line"><a name="l06899"></a><span class="lineno"> 6899</span> <span class="preprocessor">#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l06900"></a><span class="lineno"> 6900</span> <span class="preprocessor">#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l06901"></a><span class="lineno"> 6901</span> <span class="preprocessor">#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l06902"></a><span class="lineno"> 6902</span> <span class="preprocessor">#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l06903"></a><span class="lineno"> 6903</span> <span class="preprocessor">#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l06904"></a><span class="lineno"> 6904</span> <span class="preprocessor">#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l06905"></a><span class="lineno"> 6905</span> <span class="preprocessor">#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)</span></div>
|
|
<div class="line"><a name="l06906"></a><span class="lineno"> 6906</span> <span class="preprocessor">#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)</span></div>
|
|
<div class="line"><a name="l06907"></a><span class="lineno"> 6907</span> <span class="preprocessor">#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)</span></div>
|
|
<div class="line"><a name="l06908"></a><span class="lineno"> 6908</span> <span class="preprocessor">#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)</span></div>
|
|
<div class="line"><a name="l06909"></a><span class="lineno"> 6909</span> <span class="preprocessor">#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)</span></div>
|
|
<div class="line"><a name="l06910"></a><span class="lineno"> 6910</span> <span class="preprocessor">#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)</span></div>
|
|
<div class="line"><a name="l06911"></a><span class="lineno"> 6911</span> <span class="preprocessor">#define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)</span></div>
|
|
<div class="line"><a name="l06912"></a><span class="lineno"> 6912</span> <span class="preprocessor">#define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)</span></div>
|
|
<div class="line"><a name="l06913"></a><span class="lineno"> 6913</span> <span class="preprocessor">#define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)</span></div>
|
|
<div class="line"><a name="l06914"></a><span class="lineno"> 6914</span> <span class="preprocessor">#define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000)</span></div>
|
|
<div class="line"><a name="l06915"></a><span class="lineno"> 6915</span> </div>
|
|
<div class="line"><a name="l06916"></a><span class="lineno"> 6916</span> <span class="comment">/* Old SPI1RST bit definition, maintained for legacy purpose */</span></div>
|
|
<div class="line"><a name="l06917"></a><span class="lineno"> 6917</span> <span class="preprocessor">#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST</span></div>
|
|
<div class="line"><a name="l06918"></a><span class="lineno"> 6918</span> </div>
|
|
<div class="line"><a name="l06919"></a><span class="lineno"> 6919</span> <span class="comment">/******************** Bit definition for RCC_AHB1ENR register ***************/</span></div>
|
|
<div class="line"><a name="l06920"></a><span class="lineno"> 6920</span> <span class="preprocessor">#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l06921"></a><span class="lineno"> 6921</span> <span class="preprocessor">#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l06922"></a><span class="lineno"> 6922</span> <span class="preprocessor">#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l06923"></a><span class="lineno"> 6923</span> <span class="preprocessor">#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l06924"></a><span class="lineno"> 6924</span> <span class="preprocessor">#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l06925"></a><span class="lineno"> 6925</span> <span class="preprocessor">#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l06926"></a><span class="lineno"> 6926</span> <span class="preprocessor">#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l06927"></a><span class="lineno"> 6927</span> <span class="preprocessor">#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)</span></div>
|
|
<div class="line"><a name="l06928"></a><span class="lineno"> 6928</span> <span class="preprocessor">#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l06929"></a><span class="lineno"> 6929</span> <span class="preprocessor">#define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l06930"></a><span class="lineno"> 6930</span> <span class="preprocessor">#define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l06931"></a><span class="lineno"> 6931</span> <span class="preprocessor">#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)</span></div>
|
|
<div class="line"><a name="l06932"></a><span class="lineno"> 6932</span> <span class="preprocessor">#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)</span></div>
|
|
<div class="line"><a name="l06933"></a><span class="lineno"> 6933</span> <span class="preprocessor">#define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)</span></div>
|
|
<div class="line"><a name="l06934"></a><span class="lineno"> 6934</span> <span class="preprocessor">#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)</span></div>
|
|
<div class="line"><a name="l06935"></a><span class="lineno"> 6935</span> <span class="preprocessor">#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)</span></div>
|
|
<div class="line"><a name="l06936"></a><span class="lineno"> 6936</span> <span class="preprocessor">#define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)</span></div>
|
|
<div class="line"><a name="l06937"></a><span class="lineno"> 6937</span> <span class="preprocessor">#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)</span></div>
|
|
<div class="line"><a name="l06938"></a><span class="lineno"> 6938</span> <span class="preprocessor">#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)</span></div>
|
|
<div class="line"><a name="l06939"></a><span class="lineno"> 6939</span> <span class="preprocessor">#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)</span></div>
|
|
<div class="line"><a name="l06940"></a><span class="lineno"> 6940</span> <span class="preprocessor">#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)</span></div>
|
|
<div class="line"><a name="l06941"></a><span class="lineno"> 6941</span> <span class="preprocessor">#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)</span></div>
|
|
<div class="line"><a name="l06942"></a><span class="lineno"> 6942</span> <span class="preprocessor">#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)</span></div>
|
|
<div class="line"><a name="l06943"></a><span class="lineno"> 6943</span> </div>
|
|
<div class="line"><a name="l06944"></a><span class="lineno"> 6944</span> <span class="comment">/******************** Bit definition for RCC_AHB2ENR register ***************/</span></div>
|
|
<div class="line"><a name="l06945"></a><span class="lineno"> 6945</span> <span class="preprocessor">#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l06946"></a><span class="lineno"> 6946</span> <span class="preprocessor">#define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l06947"></a><span class="lineno"> 6947</span> <span class="preprocessor">#define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l06948"></a><span class="lineno"> 6948</span> <span class="preprocessor">#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l06949"></a><span class="lineno"> 6949</span> <span class="preprocessor">#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)</span></div>
|
|
<div class="line"><a name="l06950"></a><span class="lineno"> 6950</span> </div>
|
|
<div class="line"><a name="l06951"></a><span class="lineno"> 6951</span> <span class="comment">/******************** Bit definition for RCC_AHB3ENR register ***************/</span></div>
|
|
<div class="line"><a name="l06952"></a><span class="lineno"> 6952</span> </div>
|
|
<div class="line"><a name="l06953"></a><span class="lineno"> 6953</span> <span class="preprocessor">#if defined(STM32F40_41xxx)</span></div>
|
|
<div class="line"><a name="l06954"></a><span class="lineno"> 6954</span> <span class="preprocessor">#define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l06955"></a><span class="lineno"> 6955</span> <span class="preprocessor">#endif </span><span class="comment">/* STM32F40_41xxx */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06956"></a><span class="lineno"> 6956</span> </div>
|
|
<div class="line"><a name="l06957"></a><span class="lineno"> 6957</span> <span class="preprocessor">#if defined (STM32F427_437xx) || defined (STM32F429_439xx)</span></div>
|
|
<div class="line"><a name="l06958"></a><span class="lineno"> 6958</span> <span class="preprocessor">#define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l06959"></a><span class="lineno"> 6959</span> <span class="preprocessor">#endif </span><span class="comment">/* STM32F427_437xx || STM32F429_439xx */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l06960"></a><span class="lineno"> 6960</span> </div>
|
|
<div class="line"><a name="l06961"></a><span class="lineno"> 6961</span> <span class="comment">/******************** Bit definition for RCC_APB1ENR register ***************/</span></div>
|
|
<div class="line"><a name="l06962"></a><span class="lineno"> 6962</span> <span class="preprocessor">#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l06963"></a><span class="lineno"> 6963</span> <span class="preprocessor">#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l06964"></a><span class="lineno"> 6964</span> <span class="preprocessor">#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l06965"></a><span class="lineno"> 6965</span> <span class="preprocessor">#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l06966"></a><span class="lineno"> 6966</span> <span class="preprocessor">#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l06967"></a><span class="lineno"> 6967</span> <span class="preprocessor">#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l06968"></a><span class="lineno"> 6968</span> <span class="preprocessor">#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l06969"></a><span class="lineno"> 6969</span> <span class="preprocessor">#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)</span></div>
|
|
<div class="line"><a name="l06970"></a><span class="lineno"> 6970</span> <span class="preprocessor">#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l06971"></a><span class="lineno"> 6971</span> <span class="preprocessor">#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l06972"></a><span class="lineno"> 6972</span> <span class="preprocessor">#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)</span></div>
|
|
<div class="line"><a name="l06973"></a><span class="lineno"> 6973</span> <span class="preprocessor">#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)</span></div>
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|
<div class="line"><a name="l06974"></a><span class="lineno"> 6974</span> <span class="preprocessor">#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)</span></div>
|
|
<div class="line"><a name="l06975"></a><span class="lineno"> 6975</span> <span class="preprocessor">#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)</span></div>
|
|
<div class="line"><a name="l06976"></a><span class="lineno"> 6976</span> <span class="preprocessor">#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)</span></div>
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|
<div class="line"><a name="l06977"></a><span class="lineno"> 6977</span> <span class="preprocessor">#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)</span></div>
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|
<div class="line"><a name="l06978"></a><span class="lineno"> 6978</span> <span class="preprocessor">#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)</span></div>
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|
<div class="line"><a name="l06979"></a><span class="lineno"> 6979</span> <span class="preprocessor">#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)</span></div>
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|
<div class="line"><a name="l06980"></a><span class="lineno"> 6980</span> <span class="preprocessor">#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)</span></div>
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<div class="line"><a name="l06981"></a><span class="lineno"> 6981</span> <span class="preprocessor">#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)</span></div>
|
|
<div class="line"><a name="l06982"></a><span class="lineno"> 6982</span> <span class="preprocessor">#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)</span></div>
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|
<div class="line"><a name="l06983"></a><span class="lineno"> 6983</span> <span class="preprocessor">#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)</span></div>
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|
<div class="line"><a name="l06984"></a><span class="lineno"> 6984</span> <span class="preprocessor">#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)</span></div>
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|
<div class="line"><a name="l06985"></a><span class="lineno"> 6985</span> <span class="preprocessor">#define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)</span></div>
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|
<div class="line"><a name="l06986"></a><span class="lineno"> 6986</span> <span class="preprocessor">#define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)</span></div>
|
|
<div class="line"><a name="l06987"></a><span class="lineno"> 6987</span> </div>
|
|
<div class="line"><a name="l06988"></a><span class="lineno"> 6988</span> <span class="comment">/******************** Bit definition for RCC_APB2ENR register ***************/</span></div>
|
|
<div class="line"><a name="l06989"></a><span class="lineno"> 6989</span> <span class="preprocessor">#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l06990"></a><span class="lineno"> 6990</span> <span class="preprocessor">#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l06991"></a><span class="lineno"> 6991</span> <span class="preprocessor">#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l06992"></a><span class="lineno"> 6992</span> <span class="preprocessor">#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l06993"></a><span class="lineno"> 6993</span> <span class="preprocessor">#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l06994"></a><span class="lineno"> 6994</span> <span class="preprocessor">#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l06995"></a><span class="lineno"> 6995</span> <span class="preprocessor">#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l06996"></a><span class="lineno"> 6996</span> <span class="preprocessor">#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l06997"></a><span class="lineno"> 6997</span> <span class="preprocessor">#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)</span></div>
|
|
<div class="line"><a name="l06998"></a><span class="lineno"> 6998</span> <span class="preprocessor">#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)</span></div>
|
|
<div class="line"><a name="l06999"></a><span class="lineno"> 6999</span> <span class="preprocessor">#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)</span></div>
|
|
<div class="line"><a name="l07000"></a><span class="lineno"> 7000</span> <span class="preprocessor">#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)</span></div>
|
|
<div class="line"><a name="l07001"></a><span class="lineno"> 7001</span> <span class="preprocessor">#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)</span></div>
|
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<div class="line"><a name="l07002"></a><span class="lineno"> 7002</span> <span class="preprocessor">#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)</span></div>
|
|
<div class="line"><a name="l07003"></a><span class="lineno"> 7003</span> <span class="preprocessor">#define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)</span></div>
|
|
<div class="line"><a name="l07004"></a><span class="lineno"> 7004</span> <span class="preprocessor">#define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)</span></div>
|
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<div class="line"><a name="l07005"></a><span class="lineno"> 7005</span> <span class="preprocessor">#define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)</span></div>
|
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<div class="line"><a name="l07006"></a><span class="lineno"> 7006</span> <span class="preprocessor">#define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)</span></div>
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<div class="line"><a name="l07007"></a><span class="lineno"> 7007</span> </div>
|
|
<div class="line"><a name="l07008"></a><span class="lineno"> 7008</span> <span class="comment">/******************** Bit definition for RCC_AHB1LPENR register *************/</span></div>
|
|
<div class="line"><a name="l07009"></a><span class="lineno"> 7009</span> <span class="preprocessor">#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l07010"></a><span class="lineno"> 7010</span> <span class="preprocessor">#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)</span></div>
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|
<div class="line"><a name="l07011"></a><span class="lineno"> 7011</span> <span class="preprocessor">#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)</span></div>
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|
<div class="line"><a name="l07012"></a><span class="lineno"> 7012</span> <span class="preprocessor">#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)</span></div>
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|
<div class="line"><a name="l07013"></a><span class="lineno"> 7013</span> <span class="preprocessor">#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)</span></div>
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|
<div class="line"><a name="l07014"></a><span class="lineno"> 7014</span> <span class="preprocessor">#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)</span></div>
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|
<div class="line"><a name="l07015"></a><span class="lineno"> 7015</span> <span class="preprocessor">#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)</span></div>
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|
<div class="line"><a name="l07016"></a><span class="lineno"> 7016</span> <span class="preprocessor">#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)</span></div>
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|
<div class="line"><a name="l07017"></a><span class="lineno"> 7017</span> <span class="preprocessor">#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)</span></div>
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|
<div class="line"><a name="l07018"></a><span class="lineno"> 7018</span> <span class="preprocessor">#define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)</span></div>
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|
<div class="line"><a name="l07019"></a><span class="lineno"> 7019</span> <span class="preprocessor">#define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)</span></div>
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|
<div class="line"><a name="l07020"></a><span class="lineno"> 7020</span> <span class="preprocessor">#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)</span></div>
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|
<div class="line"><a name="l07021"></a><span class="lineno"> 7021</span> <span class="preprocessor">#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)</span></div>
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|
<div class="line"><a name="l07022"></a><span class="lineno"> 7022</span> <span class="preprocessor">#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)</span></div>
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|
<div class="line"><a name="l07023"></a><span class="lineno"> 7023</span> <span class="preprocessor">#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)</span></div>
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|
<div class="line"><a name="l07024"></a><span class="lineno"> 7024</span> <span class="preprocessor">#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)</span></div>
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|
<div class="line"><a name="l07025"></a><span class="lineno"> 7025</span> <span class="preprocessor">#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)</span></div>
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|
<div class="line"><a name="l07026"></a><span class="lineno"> 7026</span> <span class="preprocessor">#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)</span></div>
|
|
<div class="line"><a name="l07027"></a><span class="lineno"> 7027</span> <span class="preprocessor">#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)</span></div>
|
|
<div class="line"><a name="l07028"></a><span class="lineno"> 7028</span> <span class="preprocessor">#define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)</span></div>
|
|
<div class="line"><a name="l07029"></a><span class="lineno"> 7029</span> <span class="preprocessor">#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)</span></div>
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|
<div class="line"><a name="l07030"></a><span class="lineno"> 7030</span> <span class="preprocessor">#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)</span></div>
|
|
<div class="line"><a name="l07031"></a><span class="lineno"> 7031</span> <span class="preprocessor">#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)</span></div>
|
|
<div class="line"><a name="l07032"></a><span class="lineno"> 7032</span> <span class="preprocessor">#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)</span></div>
|
|
<div class="line"><a name="l07033"></a><span class="lineno"> 7033</span> <span class="preprocessor">#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)</span></div>
|
|
<div class="line"><a name="l07034"></a><span class="lineno"> 7034</span> <span class="preprocessor">#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)</span></div>
|
|
<div class="line"><a name="l07035"></a><span class="lineno"> 7035</span> </div>
|
|
<div class="line"><a name="l07036"></a><span class="lineno"> 7036</span> <span class="comment">/******************** Bit definition for RCC_AHB2LPENR register *************/</span></div>
|
|
<div class="line"><a name="l07037"></a><span class="lineno"> 7037</span> <span class="preprocessor">#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l07038"></a><span class="lineno"> 7038</span> <span class="preprocessor">#define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l07039"></a><span class="lineno"> 7039</span> <span class="preprocessor">#define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l07040"></a><span class="lineno"> 7040</span> <span class="preprocessor">#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l07041"></a><span class="lineno"> 7041</span> <span class="preprocessor">#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)</span></div>
|
|
<div class="line"><a name="l07042"></a><span class="lineno"> 7042</span> </div>
|
|
<div class="line"><a name="l07043"></a><span class="lineno"> 7043</span> <span class="comment">/******************** Bit definition for RCC_AHB3LPENR register *************/</span></div>
|
|
<div class="line"><a name="l07044"></a><span class="lineno"> 7044</span> <span class="preprocessor">#if defined(STM32F40_41xxx)</span></div>
|
|
<div class="line"><a name="l07045"></a><span class="lineno"> 7045</span> <span class="preprocessor">#define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)</span></div>
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|
<div class="line"><a name="l07046"></a><span class="lineno"> 7046</span> <span class="preprocessor">#endif </span><span class="comment">/* STM32F40_41xxx */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l07047"></a><span class="lineno"> 7047</span> </div>
|
|
<div class="line"><a name="l07048"></a><span class="lineno"> 7048</span> <span class="preprocessor">#if defined (STM32F427_437xx) || defined (STM32F429_439xx)</span></div>
|
|
<div class="line"><a name="l07049"></a><span class="lineno"> 7049</span> <span class="preprocessor">#define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l07050"></a><span class="lineno"> 7050</span> <span class="preprocessor">#endif </span><span class="comment">/* STM32F427_437xx || STM32F429_439xx */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l07051"></a><span class="lineno"> 7051</span> </div>
|
|
<div class="line"><a name="l07052"></a><span class="lineno"> 7052</span> <span class="comment">/******************** Bit definition for RCC_APB1LPENR register *************/</span></div>
|
|
<div class="line"><a name="l07053"></a><span class="lineno"> 7053</span> <span class="preprocessor">#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l07054"></a><span class="lineno"> 7054</span> <span class="preprocessor">#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l07055"></a><span class="lineno"> 7055</span> <span class="preprocessor">#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l07056"></a><span class="lineno"> 7056</span> <span class="preprocessor">#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l07057"></a><span class="lineno"> 7057</span> <span class="preprocessor">#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l07058"></a><span class="lineno"> 7058</span> <span class="preprocessor">#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l07059"></a><span class="lineno"> 7059</span> <span class="preprocessor">#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l07060"></a><span class="lineno"> 7060</span> <span class="preprocessor">#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)</span></div>
|
|
<div class="line"><a name="l07061"></a><span class="lineno"> 7061</span> <span class="preprocessor">#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l07062"></a><span class="lineno"> 7062</span> <span class="preprocessor">#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l07063"></a><span class="lineno"> 7063</span> <span class="preprocessor">#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)</span></div>
|
|
<div class="line"><a name="l07064"></a><span class="lineno"> 7064</span> <span class="preprocessor">#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)</span></div>
|
|
<div class="line"><a name="l07065"></a><span class="lineno"> 7065</span> <span class="preprocessor">#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)</span></div>
|
|
<div class="line"><a name="l07066"></a><span class="lineno"> 7066</span> <span class="preprocessor">#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)</span></div>
|
|
<div class="line"><a name="l07067"></a><span class="lineno"> 7067</span> <span class="preprocessor">#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)</span></div>
|
|
<div class="line"><a name="l07068"></a><span class="lineno"> 7068</span> <span class="preprocessor">#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)</span></div>
|
|
<div class="line"><a name="l07069"></a><span class="lineno"> 7069</span> <span class="preprocessor">#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)</span></div>
|
|
<div class="line"><a name="l07070"></a><span class="lineno"> 7070</span> <span class="preprocessor">#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)</span></div>
|
|
<div class="line"><a name="l07071"></a><span class="lineno"> 7071</span> <span class="preprocessor">#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)</span></div>
|
|
<div class="line"><a name="l07072"></a><span class="lineno"> 7072</span> <span class="preprocessor">#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)</span></div>
|
|
<div class="line"><a name="l07073"></a><span class="lineno"> 7073</span> <span class="preprocessor">#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)</span></div>
|
|
<div class="line"><a name="l07074"></a><span class="lineno"> 7074</span> <span class="preprocessor">#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)</span></div>
|
|
<div class="line"><a name="l07075"></a><span class="lineno"> 7075</span> <span class="preprocessor">#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)</span></div>
|
|
<div class="line"><a name="l07076"></a><span class="lineno"> 7076</span> <span class="preprocessor">#define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)</span></div>
|
|
<div class="line"><a name="l07077"></a><span class="lineno"> 7077</span> <span class="preprocessor">#define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)</span></div>
|
|
<div class="line"><a name="l07078"></a><span class="lineno"> 7078</span> </div>
|
|
<div class="line"><a name="l07079"></a><span class="lineno"> 7079</span> <span class="comment">/******************** Bit definition for RCC_APB2LPENR register *************/</span></div>
|
|
<div class="line"><a name="l07080"></a><span class="lineno"> 7080</span> <span class="preprocessor">#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l07081"></a><span class="lineno"> 7081</span> <span class="preprocessor">#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l07082"></a><span class="lineno"> 7082</span> <span class="preprocessor">#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l07083"></a><span class="lineno"> 7083</span> <span class="preprocessor">#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l07084"></a><span class="lineno"> 7084</span> <span class="preprocessor">#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l07085"></a><span class="lineno"> 7085</span> <span class="preprocessor">#define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l07086"></a><span class="lineno"> 7086</span> <span class="preprocessor">#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l07087"></a><span class="lineno"> 7087</span> <span class="preprocessor">#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)</span></div>
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|
<div class="line"><a name="l07088"></a><span class="lineno"> 7088</span> <span class="preprocessor">#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)</span></div>
|
|
<div class="line"><a name="l07089"></a><span class="lineno"> 7089</span> <span class="preprocessor">#define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)</span></div>
|
|
<div class="line"><a name="l07090"></a><span class="lineno"> 7090</span> <span class="preprocessor">#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)</span></div>
|
|
<div class="line"><a name="l07091"></a><span class="lineno"> 7091</span> <span class="preprocessor">#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)</span></div>
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|
<div class="line"><a name="l07092"></a><span class="lineno"> 7092</span> <span class="preprocessor">#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)</span></div>
|
|
<div class="line"><a name="l07093"></a><span class="lineno"> 7093</span> <span class="preprocessor">#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)</span></div>
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|
<div class="line"><a name="l07094"></a><span class="lineno"> 7094</span> <span class="preprocessor">#define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)</span></div>
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|
<div class="line"><a name="l07095"></a><span class="lineno"> 7095</span> <span class="preprocessor">#define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)</span></div>
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|
<div class="line"><a name="l07096"></a><span class="lineno"> 7096</span> <span class="preprocessor">#define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)</span></div>
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|
<div class="line"><a name="l07097"></a><span class="lineno"> 7097</span> <span class="preprocessor">#define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)</span></div>
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|
<div class="line"><a name="l07098"></a><span class="lineno"> 7098</span> </div>
|
|
<div class="line"><a name="l07099"></a><span class="lineno"> 7099</span> <span class="comment">/******************** Bit definition for RCC_BDCR register ******************/</span></div>
|
|
<div class="line"><a name="l07100"></a><span class="lineno"> 7100</span> <span class="preprocessor">#define RCC_BDCR_LSEON ((uint32_t)0x00000001)</span></div>
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|
<div class="line"><a name="l07101"></a><span class="lineno"> 7101</span> <span class="preprocessor">#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)</span></div>
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|
<div class="line"><a name="l07102"></a><span class="lineno"> 7102</span> <span class="preprocessor">#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)</span></div>
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|
<div class="line"><a name="l07103"></a><span class="lineno"> 7103</span> <span class="preprocessor">#define RCC_BDCR_LSEMOD ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l07104"></a><span class="lineno"> 7104</span> </div>
|
|
<div class="line"><a name="l07105"></a><span class="lineno"> 7105</span> <span class="preprocessor">#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)</span></div>
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|
<div class="line"><a name="l07106"></a><span class="lineno"> 7106</span> <span class="preprocessor">#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)</span></div>
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|
<div class="line"><a name="l07107"></a><span class="lineno"> 7107</span> <span class="preprocessor">#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l07108"></a><span class="lineno"> 7108</span> </div>
|
|
<div class="line"><a name="l07109"></a><span class="lineno"> 7109</span> <span class="preprocessor">#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)</span></div>
|
|
<div class="line"><a name="l07110"></a><span class="lineno"> 7110</span> <span class="preprocessor">#define RCC_BDCR_BDRST ((uint32_t)0x00010000)</span></div>
|
|
<div class="line"><a name="l07111"></a><span class="lineno"> 7111</span> </div>
|
|
<div class="line"><a name="l07112"></a><span class="lineno"> 7112</span> <span class="comment">/******************** Bit definition for RCC_CSR register *******************/</span></div>
|
|
<div class="line"><a name="l07113"></a><span class="lineno"> 7113</span> <span class="preprocessor">#define RCC_CSR_LSION ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l07114"></a><span class="lineno"> 7114</span> <span class="preprocessor">#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l07115"></a><span class="lineno"> 7115</span> <span class="preprocessor">#define RCC_CSR_RMVF ((uint32_t)0x01000000)</span></div>
|
|
<div class="line"><a name="l07116"></a><span class="lineno"> 7116</span> <span class="preprocessor">#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)</span></div>
|
|
<div class="line"><a name="l07117"></a><span class="lineno"> 7117</span> <span class="preprocessor">#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)</span></div>
|
|
<div class="line"><a name="l07118"></a><span class="lineno"> 7118</span> <span class="preprocessor">#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)</span></div>
|
|
<div class="line"><a name="l07119"></a><span class="lineno"> 7119</span> <span class="preprocessor">#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)</span></div>
|
|
<div class="line"><a name="l07120"></a><span class="lineno"> 7120</span> <span class="preprocessor">#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)</span></div>
|
|
<div class="line"><a name="l07121"></a><span class="lineno"> 7121</span> <span class="preprocessor">#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)</span></div>
|
|
<div class="line"><a name="l07122"></a><span class="lineno"> 7122</span> <span class="preprocessor">#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)</span></div>
|
|
<div class="line"><a name="l07123"></a><span class="lineno"> 7123</span> </div>
|
|
<div class="line"><a name="l07124"></a><span class="lineno"> 7124</span> <span class="comment">/******************** Bit definition for RCC_SSCGR register *****************/</span></div>
|
|
<div class="line"><a name="l07125"></a><span class="lineno"> 7125</span> <span class="preprocessor">#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)</span></div>
|
|
<div class="line"><a name="l07126"></a><span class="lineno"> 7126</span> <span class="preprocessor">#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)</span></div>
|
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<div class="line"><a name="l07127"></a><span class="lineno"> 7127</span> <span class="preprocessor">#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)</span></div>
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<div class="line"><a name="l07128"></a><span class="lineno"> 7128</span> <span class="preprocessor">#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)</span></div>
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|
<div class="line"><a name="l07129"></a><span class="lineno"> 7129</span> </div>
|
|
<div class="line"><a name="l07130"></a><span class="lineno"> 7130</span> <span class="comment">/******************** Bit definition for RCC_PLLI2SCFGR register ************/</span></div>
|
|
<div class="line"><a name="l07131"></a><span class="lineno"> 7131</span> <span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SM ((uint32_t)0x0000003F)</span></div>
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|
<div class="line"><a name="l07132"></a><span class="lineno"> 7132</span> <span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SM_0 ((uint32_t)0x00000001)</span></div>
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|
<div class="line"><a name="l07133"></a><span class="lineno"> 7133</span> <span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SM_1 ((uint32_t)0x00000002)</span></div>
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|
<div class="line"><a name="l07134"></a><span class="lineno"> 7134</span> <span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SM_2 ((uint32_t)0x00000004)</span></div>
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|
<div class="line"><a name="l07135"></a><span class="lineno"> 7135</span> <span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SM_3 ((uint32_t)0x00000008)</span></div>
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<div class="line"><a name="l07136"></a><span class="lineno"> 7136</span> <span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SM_4 ((uint32_t)0x00000010)</span></div>
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|
<div class="line"><a name="l07137"></a><span class="lineno"> 7137</span> <span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SM_5 ((uint32_t)0x00000020)</span></div>
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|
<div class="line"><a name="l07138"></a><span class="lineno"> 7138</span> </div>
|
|
<div class="line"><a name="l07139"></a><span class="lineno"> 7139</span> <span class="comment">/******************** Bit definition for RCC_PLLI2SCFGR register ************/</span></div>
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|
<div class="line"><a name="l07140"></a><span class="lineno"> 7140</span> <span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)</span></div>
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|
<div class="line"><a name="l07141"></a><span class="lineno"> 7141</span> <span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)</span></div>
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<div class="line"><a name="l07142"></a><span class="lineno"> 7142</span> <span class="preprocessor">#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)</span></div>
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|
<div class="line"><a name="l07143"></a><span class="lineno"> 7143</span> </div>
|
|
<div class="line"><a name="l07144"></a><span class="lineno"> 7144</span> <span class="comment">/******************** Bit definition for RCC_PLLSAICFGR register ************/</span></div>
|
|
<div class="line"><a name="l07145"></a><span class="lineno"> 7145</span> <span class="preprocessor">#define RCC_PLLSAICFGR_PLLI2SN ((uint32_t)0x00007FC0)</span></div>
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<div class="line"><a name="l07146"></a><span class="lineno"> 7146</span> <span class="preprocessor">#define RCC_PLLSAICFGR_PLLI2SQ ((uint32_t)0x0F000000)</span></div>
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|
<div class="line"><a name="l07147"></a><span class="lineno"> 7147</span> <span class="preprocessor">#define RCC_PLLSAICFGR_PLLI2SR ((uint32_t)0x70000000)</span></div>
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|
<div class="line"><a name="l07148"></a><span class="lineno"> 7148</span> </div>
|
|
<div class="line"><a name="l07149"></a><span class="lineno"> 7149</span> <span class="comment">/******************** Bit definition for RCC_DCKCFGR register ***************/</span></div>
|
|
<div class="line"><a name="l07150"></a><span class="lineno"> 7150</span> <span class="preprocessor">#define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F)</span></div>
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|
<div class="line"><a name="l07151"></a><span class="lineno"> 7151</span> <span class="preprocessor">#define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)</span></div>
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<div class="line"><a name="l07152"></a><span class="lineno"> 7152</span> <span class="preprocessor">#define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)</span></div>
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<div class="line"><a name="l07153"></a><span class="lineno"> 7153</span> <span class="preprocessor">#define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)</span></div>
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|
<div class="line"><a name="l07154"></a><span class="lineno"> 7154</span> <span class="preprocessor">#define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)</span></div>
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|
<div class="line"><a name="l07155"></a><span class="lineno"> 7155</span> <span class="preprocessor">#define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)</span></div>
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|
<div class="line"><a name="l07156"></a><span class="lineno"> 7156</span> </div>
|
|
<div class="line"><a name="l07157"></a><span class="lineno"> 7157</span> </div>
|
|
<div class="line"><a name="l07158"></a><span class="lineno"> 7158</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l07159"></a><span class="lineno"> 7159</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l07160"></a><span class="lineno"> 7160</span> <span class="comment">/* RNG */</span></div>
|
|
<div class="line"><a name="l07161"></a><span class="lineno"> 7161</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l07162"></a><span class="lineno"> 7162</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l07163"></a><span class="lineno"> 7163</span> <span class="comment">/******************** Bits definition for RNG_CR register *******************/</span></div>
|
|
<div class="line"><a name="l07164"></a><span class="lineno"> 7164</span> <span class="preprocessor">#define RNG_CR_RNGEN ((uint32_t)0x00000004)</span></div>
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|
<div class="line"><a name="l07165"></a><span class="lineno"> 7165</span> <span class="preprocessor">#define RNG_CR_IE ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l07166"></a><span class="lineno"> 7166</span> </div>
|
|
<div class="line"><a name="l07167"></a><span class="lineno"> 7167</span> <span class="comment">/******************** Bits definition for RNG_SR register *******************/</span></div>
|
|
<div class="line"><a name="l07168"></a><span class="lineno"> 7168</span> <span class="preprocessor">#define RNG_SR_DRDY ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l07169"></a><span class="lineno"> 7169</span> <span class="preprocessor">#define RNG_SR_CECS ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l07170"></a><span class="lineno"> 7170</span> <span class="preprocessor">#define RNG_SR_SECS ((uint32_t)0x00000004)</span></div>
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|
<div class="line"><a name="l07171"></a><span class="lineno"> 7171</span> <span class="preprocessor">#define RNG_SR_CEIS ((uint32_t)0x00000020)</span></div>
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|
<div class="line"><a name="l07172"></a><span class="lineno"> 7172</span> <span class="preprocessor">#define RNG_SR_SEIS ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l07173"></a><span class="lineno"> 7173</span> </div>
|
|
<div class="line"><a name="l07174"></a><span class="lineno"> 7174</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l07175"></a><span class="lineno"> 7175</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l07176"></a><span class="lineno"> 7176</span> <span class="comment">/* Real-Time Clock (RTC) */</span></div>
|
|
<div class="line"><a name="l07177"></a><span class="lineno"> 7177</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l07178"></a><span class="lineno"> 7178</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l07179"></a><span class="lineno"> 7179</span> <span class="comment">/******************** Bits definition for RTC_TR register *******************/</span></div>
|
|
<div class="line"><a name="l07180"></a><span class="lineno"> 7180</span> <span class="preprocessor">#define RTC_TR_PM ((uint32_t)0x00400000)</span></div>
|
|
<div class="line"><a name="l07181"></a><span class="lineno"> 7181</span> <span class="preprocessor">#define RTC_TR_HT ((uint32_t)0x00300000)</span></div>
|
|
<div class="line"><a name="l07182"></a><span class="lineno"> 7182</span> <span class="preprocessor">#define RTC_TR_HT_0 ((uint32_t)0x00100000)</span></div>
|
|
<div class="line"><a name="l07183"></a><span class="lineno"> 7183</span> <span class="preprocessor">#define RTC_TR_HT_1 ((uint32_t)0x00200000)</span></div>
|
|
<div class="line"><a name="l07184"></a><span class="lineno"> 7184</span> <span class="preprocessor">#define RTC_TR_HU ((uint32_t)0x000F0000)</span></div>
|
|
<div class="line"><a name="l07185"></a><span class="lineno"> 7185</span> <span class="preprocessor">#define RTC_TR_HU_0 ((uint32_t)0x00010000)</span></div>
|
|
<div class="line"><a name="l07186"></a><span class="lineno"> 7186</span> <span class="preprocessor">#define RTC_TR_HU_1 ((uint32_t)0x00020000)</span></div>
|
|
<div class="line"><a name="l07187"></a><span class="lineno"> 7187</span> <span class="preprocessor">#define RTC_TR_HU_2 ((uint32_t)0x00040000)</span></div>
|
|
<div class="line"><a name="l07188"></a><span class="lineno"> 7188</span> <span class="preprocessor">#define RTC_TR_HU_3 ((uint32_t)0x00080000)</span></div>
|
|
<div class="line"><a name="l07189"></a><span class="lineno"> 7189</span> <span class="preprocessor">#define RTC_TR_MNT ((uint32_t)0x00007000)</span></div>
|
|
<div class="line"><a name="l07190"></a><span class="lineno"> 7190</span> <span class="preprocessor">#define RTC_TR_MNT_0 ((uint32_t)0x00001000)</span></div>
|
|
<div class="line"><a name="l07191"></a><span class="lineno"> 7191</span> <span class="preprocessor">#define RTC_TR_MNT_1 ((uint32_t)0x00002000)</span></div>
|
|
<div class="line"><a name="l07192"></a><span class="lineno"> 7192</span> <span class="preprocessor">#define RTC_TR_MNT_2 ((uint32_t)0x00004000)</span></div>
|
|
<div class="line"><a name="l07193"></a><span class="lineno"> 7193</span> <span class="preprocessor">#define RTC_TR_MNU ((uint32_t)0x00000F00)</span></div>
|
|
<div class="line"><a name="l07194"></a><span class="lineno"> 7194</span> <span class="preprocessor">#define RTC_TR_MNU_0 ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l07195"></a><span class="lineno"> 7195</span> <span class="preprocessor">#define RTC_TR_MNU_1 ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l07196"></a><span class="lineno"> 7196</span> <span class="preprocessor">#define RTC_TR_MNU_2 ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l07197"></a><span class="lineno"> 7197</span> <span class="preprocessor">#define RTC_TR_MNU_3 ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l07198"></a><span class="lineno"> 7198</span> <span class="preprocessor">#define RTC_TR_ST ((uint32_t)0x00000070)</span></div>
|
|
<div class="line"><a name="l07199"></a><span class="lineno"> 7199</span> <span class="preprocessor">#define RTC_TR_ST_0 ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l07200"></a><span class="lineno"> 7200</span> <span class="preprocessor">#define RTC_TR_ST_1 ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l07201"></a><span class="lineno"> 7201</span> <span class="preprocessor">#define RTC_TR_ST_2 ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l07202"></a><span class="lineno"> 7202</span> <span class="preprocessor">#define RTC_TR_SU ((uint32_t)0x0000000F)</span></div>
|
|
<div class="line"><a name="l07203"></a><span class="lineno"> 7203</span> <span class="preprocessor">#define RTC_TR_SU_0 ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l07204"></a><span class="lineno"> 7204</span> <span class="preprocessor">#define RTC_TR_SU_1 ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l07205"></a><span class="lineno"> 7205</span> <span class="preprocessor">#define RTC_TR_SU_2 ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l07206"></a><span class="lineno"> 7206</span> <span class="preprocessor">#define RTC_TR_SU_3 ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l07207"></a><span class="lineno"> 7207</span> </div>
|
|
<div class="line"><a name="l07208"></a><span class="lineno"> 7208</span> <span class="comment">/******************** Bits definition for RTC_DR register *******************/</span></div>
|
|
<div class="line"><a name="l07209"></a><span class="lineno"> 7209</span> <span class="preprocessor">#define RTC_DR_YT ((uint32_t)0x00F00000)</span></div>
|
|
<div class="line"><a name="l07210"></a><span class="lineno"> 7210</span> <span class="preprocessor">#define RTC_DR_YT_0 ((uint32_t)0x00100000)</span></div>
|
|
<div class="line"><a name="l07211"></a><span class="lineno"> 7211</span> <span class="preprocessor">#define RTC_DR_YT_1 ((uint32_t)0x00200000)</span></div>
|
|
<div class="line"><a name="l07212"></a><span class="lineno"> 7212</span> <span class="preprocessor">#define RTC_DR_YT_2 ((uint32_t)0x00400000)</span></div>
|
|
<div class="line"><a name="l07213"></a><span class="lineno"> 7213</span> <span class="preprocessor">#define RTC_DR_YT_3 ((uint32_t)0x00800000)</span></div>
|
|
<div class="line"><a name="l07214"></a><span class="lineno"> 7214</span> <span class="preprocessor">#define RTC_DR_YU ((uint32_t)0x000F0000)</span></div>
|
|
<div class="line"><a name="l07215"></a><span class="lineno"> 7215</span> <span class="preprocessor">#define RTC_DR_YU_0 ((uint32_t)0x00010000)</span></div>
|
|
<div class="line"><a name="l07216"></a><span class="lineno"> 7216</span> <span class="preprocessor">#define RTC_DR_YU_1 ((uint32_t)0x00020000)</span></div>
|
|
<div class="line"><a name="l07217"></a><span class="lineno"> 7217</span> <span class="preprocessor">#define RTC_DR_YU_2 ((uint32_t)0x00040000)</span></div>
|
|
<div class="line"><a name="l07218"></a><span class="lineno"> 7218</span> <span class="preprocessor">#define RTC_DR_YU_3 ((uint32_t)0x00080000)</span></div>
|
|
<div class="line"><a name="l07219"></a><span class="lineno"> 7219</span> <span class="preprocessor">#define RTC_DR_WDU ((uint32_t)0x0000E000)</span></div>
|
|
<div class="line"><a name="l07220"></a><span class="lineno"> 7220</span> <span class="preprocessor">#define RTC_DR_WDU_0 ((uint32_t)0x00002000)</span></div>
|
|
<div class="line"><a name="l07221"></a><span class="lineno"> 7221</span> <span class="preprocessor">#define RTC_DR_WDU_1 ((uint32_t)0x00004000)</span></div>
|
|
<div class="line"><a name="l07222"></a><span class="lineno"> 7222</span> <span class="preprocessor">#define RTC_DR_WDU_2 ((uint32_t)0x00008000)</span></div>
|
|
<div class="line"><a name="l07223"></a><span class="lineno"> 7223</span> <span class="preprocessor">#define RTC_DR_MT ((uint32_t)0x00001000)</span></div>
|
|
<div class="line"><a name="l07224"></a><span class="lineno"> 7224</span> <span class="preprocessor">#define RTC_DR_MU ((uint32_t)0x00000F00)</span></div>
|
|
<div class="line"><a name="l07225"></a><span class="lineno"> 7225</span> <span class="preprocessor">#define RTC_DR_MU_0 ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l07226"></a><span class="lineno"> 7226</span> <span class="preprocessor">#define RTC_DR_MU_1 ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l07227"></a><span class="lineno"> 7227</span> <span class="preprocessor">#define RTC_DR_MU_2 ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l07228"></a><span class="lineno"> 7228</span> <span class="preprocessor">#define RTC_DR_MU_3 ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l07229"></a><span class="lineno"> 7229</span> <span class="preprocessor">#define RTC_DR_DT ((uint32_t)0x00000030)</span></div>
|
|
<div class="line"><a name="l07230"></a><span class="lineno"> 7230</span> <span class="preprocessor">#define RTC_DR_DT_0 ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l07231"></a><span class="lineno"> 7231</span> <span class="preprocessor">#define RTC_DR_DT_1 ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l07232"></a><span class="lineno"> 7232</span> <span class="preprocessor">#define RTC_DR_DU ((uint32_t)0x0000000F)</span></div>
|
|
<div class="line"><a name="l07233"></a><span class="lineno"> 7233</span> <span class="preprocessor">#define RTC_DR_DU_0 ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l07234"></a><span class="lineno"> 7234</span> <span class="preprocessor">#define RTC_DR_DU_1 ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l07235"></a><span class="lineno"> 7235</span> <span class="preprocessor">#define RTC_DR_DU_2 ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l07236"></a><span class="lineno"> 7236</span> <span class="preprocessor">#define RTC_DR_DU_3 ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l07237"></a><span class="lineno"> 7237</span> </div>
|
|
<div class="line"><a name="l07238"></a><span class="lineno"> 7238</span> <span class="comment">/******************** Bits definition for RTC_CR register *******************/</span></div>
|
|
<div class="line"><a name="l07239"></a><span class="lineno"> 7239</span> <span class="preprocessor">#define RTC_CR_COE ((uint32_t)0x00800000)</span></div>
|
|
<div class="line"><a name="l07240"></a><span class="lineno"> 7240</span> <span class="preprocessor">#define RTC_CR_OSEL ((uint32_t)0x00600000)</span></div>
|
|
<div class="line"><a name="l07241"></a><span class="lineno"> 7241</span> <span class="preprocessor">#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)</span></div>
|
|
<div class="line"><a name="l07242"></a><span class="lineno"> 7242</span> <span class="preprocessor">#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)</span></div>
|
|
<div class="line"><a name="l07243"></a><span class="lineno"> 7243</span> <span class="preprocessor">#define RTC_CR_POL ((uint32_t)0x00100000)</span></div>
|
|
<div class="line"><a name="l07244"></a><span class="lineno"> 7244</span> <span class="preprocessor">#define RTC_CR_COSEL ((uint32_t)0x00080000)</span></div>
|
|
<div class="line"><a name="l07245"></a><span class="lineno"> 7245</span> <span class="preprocessor">#define RTC_CR_BCK ((uint32_t)0x00040000)</span></div>
|
|
<div class="line"><a name="l07246"></a><span class="lineno"> 7246</span> <span class="preprocessor">#define RTC_CR_SUB1H ((uint32_t)0x00020000)</span></div>
|
|
<div class="line"><a name="l07247"></a><span class="lineno"> 7247</span> <span class="preprocessor">#define RTC_CR_ADD1H ((uint32_t)0x00010000)</span></div>
|
|
<div class="line"><a name="l07248"></a><span class="lineno"> 7248</span> <span class="preprocessor">#define RTC_CR_TSIE ((uint32_t)0x00008000)</span></div>
|
|
<div class="line"><a name="l07249"></a><span class="lineno"> 7249</span> <span class="preprocessor">#define RTC_CR_WUTIE ((uint32_t)0x00004000)</span></div>
|
|
<div class="line"><a name="l07250"></a><span class="lineno"> 7250</span> <span class="preprocessor">#define RTC_CR_ALRBIE ((uint32_t)0x00002000)</span></div>
|
|
<div class="line"><a name="l07251"></a><span class="lineno"> 7251</span> <span class="preprocessor">#define RTC_CR_ALRAIE ((uint32_t)0x00001000)</span></div>
|
|
<div class="line"><a name="l07252"></a><span class="lineno"> 7252</span> <span class="preprocessor">#define RTC_CR_TSE ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l07253"></a><span class="lineno"> 7253</span> <span class="preprocessor">#define RTC_CR_WUTE ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l07254"></a><span class="lineno"> 7254</span> <span class="preprocessor">#define RTC_CR_ALRBE ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l07255"></a><span class="lineno"> 7255</span> <span class="preprocessor">#define RTC_CR_ALRAE ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l07256"></a><span class="lineno"> 7256</span> <span class="preprocessor">#define RTC_CR_DCE ((uint32_t)0x00000080)</span></div>
|
|
<div class="line"><a name="l07257"></a><span class="lineno"> 7257</span> <span class="preprocessor">#define RTC_CR_FMT ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l07258"></a><span class="lineno"> 7258</span> <span class="preprocessor">#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l07259"></a><span class="lineno"> 7259</span> <span class="preprocessor">#define RTC_CR_REFCKON ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l07260"></a><span class="lineno"> 7260</span> <span class="preprocessor">#define RTC_CR_TSEDGE ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l07261"></a><span class="lineno"> 7261</span> <span class="preprocessor">#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)</span></div>
|
|
<div class="line"><a name="l07262"></a><span class="lineno"> 7262</span> <span class="preprocessor">#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l07263"></a><span class="lineno"> 7263</span> <span class="preprocessor">#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l07264"></a><span class="lineno"> 7264</span> <span class="preprocessor">#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l07265"></a><span class="lineno"> 7265</span> </div>
|
|
<div class="line"><a name="l07266"></a><span class="lineno"> 7266</span> <span class="comment">/******************** Bits definition for RTC_ISR register ******************/</span></div>
|
|
<div class="line"><a name="l07267"></a><span class="lineno"> 7267</span> <span class="preprocessor">#define RTC_ISR_RECALPF ((uint32_t)0x00010000)</span></div>
|
|
<div class="line"><a name="l07268"></a><span class="lineno"> 7268</span> <span class="preprocessor">#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)</span></div>
|
|
<div class="line"><a name="l07269"></a><span class="lineno"> 7269</span> <span class="preprocessor">#define RTC_ISR_TSOVF ((uint32_t)0x00001000)</span></div>
|
|
<div class="line"><a name="l07270"></a><span class="lineno"> 7270</span> <span class="preprocessor">#define RTC_ISR_TSF ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l07271"></a><span class="lineno"> 7271</span> <span class="preprocessor">#define RTC_ISR_WUTF ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l07272"></a><span class="lineno"> 7272</span> <span class="preprocessor">#define RTC_ISR_ALRBF ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l07273"></a><span class="lineno"> 7273</span> <span class="preprocessor">#define RTC_ISR_ALRAF ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l07274"></a><span class="lineno"> 7274</span> <span class="preprocessor">#define RTC_ISR_INIT ((uint32_t)0x00000080)</span></div>
|
|
<div class="line"><a name="l07275"></a><span class="lineno"> 7275</span> <span class="preprocessor">#define RTC_ISR_INITF ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l07276"></a><span class="lineno"> 7276</span> <span class="preprocessor">#define RTC_ISR_RSF ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l07277"></a><span class="lineno"> 7277</span> <span class="preprocessor">#define RTC_ISR_INITS ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l07278"></a><span class="lineno"> 7278</span> <span class="preprocessor">#define RTC_ISR_SHPF ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l07279"></a><span class="lineno"> 7279</span> <span class="preprocessor">#define RTC_ISR_WUTWF ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l07280"></a><span class="lineno"> 7280</span> <span class="preprocessor">#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l07281"></a><span class="lineno"> 7281</span> <span class="preprocessor">#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l07282"></a><span class="lineno"> 7282</span> </div>
|
|
<div class="line"><a name="l07283"></a><span class="lineno"> 7283</span> <span class="comment">/******************** Bits definition for RTC_PRER register *****************/</span></div>
|
|
<div class="line"><a name="l07284"></a><span class="lineno"> 7284</span> <span class="preprocessor">#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)</span></div>
|
|
<div class="line"><a name="l07285"></a><span class="lineno"> 7285</span> <span class="preprocessor">#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)</span></div>
|
|
<div class="line"><a name="l07286"></a><span class="lineno"> 7286</span> </div>
|
|
<div class="line"><a name="l07287"></a><span class="lineno"> 7287</span> <span class="comment">/******************** Bits definition for RTC_WUTR register *****************/</span></div>
|
|
<div class="line"><a name="l07288"></a><span class="lineno"> 7288</span> <span class="preprocessor">#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)</span></div>
|
|
<div class="line"><a name="l07289"></a><span class="lineno"> 7289</span> </div>
|
|
<div class="line"><a name="l07290"></a><span class="lineno"> 7290</span> <span class="comment">/******************** Bits definition for RTC_CALIBR register ***************/</span></div>
|
|
<div class="line"><a name="l07291"></a><span class="lineno"> 7291</span> <span class="preprocessor">#define RTC_CALIBR_DCS ((uint32_t)0x00000080)</span></div>
|
|
<div class="line"><a name="l07292"></a><span class="lineno"> 7292</span> <span class="preprocessor">#define RTC_CALIBR_DC ((uint32_t)0x0000001F)</span></div>
|
|
<div class="line"><a name="l07293"></a><span class="lineno"> 7293</span> </div>
|
|
<div class="line"><a name="l07294"></a><span class="lineno"> 7294</span> <span class="comment">/******************** Bits definition for RTC_ALRMAR register ***************/</span></div>
|
|
<div class="line"><a name="l07295"></a><span class="lineno"> 7295</span> <span class="preprocessor">#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)</span></div>
|
|
<div class="line"><a name="l07296"></a><span class="lineno"> 7296</span> <span class="preprocessor">#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)</span></div>
|
|
<div class="line"><a name="l07297"></a><span class="lineno"> 7297</span> <span class="preprocessor">#define RTC_ALRMAR_DT ((uint32_t)0x30000000)</span></div>
|
|
<div class="line"><a name="l07298"></a><span class="lineno"> 7298</span> <span class="preprocessor">#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)</span></div>
|
|
<div class="line"><a name="l07299"></a><span class="lineno"> 7299</span> <span class="preprocessor">#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)</span></div>
|
|
<div class="line"><a name="l07300"></a><span class="lineno"> 7300</span> <span class="preprocessor">#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)</span></div>
|
|
<div class="line"><a name="l07301"></a><span class="lineno"> 7301</span> <span class="preprocessor">#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)</span></div>
|
|
<div class="line"><a name="l07302"></a><span class="lineno"> 7302</span> <span class="preprocessor">#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)</span></div>
|
|
<div class="line"><a name="l07303"></a><span class="lineno"> 7303</span> <span class="preprocessor">#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)</span></div>
|
|
<div class="line"><a name="l07304"></a><span class="lineno"> 7304</span> <span class="preprocessor">#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)</span></div>
|
|
<div class="line"><a name="l07305"></a><span class="lineno"> 7305</span> <span class="preprocessor">#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)</span></div>
|
|
<div class="line"><a name="l07306"></a><span class="lineno"> 7306</span> <span class="preprocessor">#define RTC_ALRMAR_PM ((uint32_t)0x00400000)</span></div>
|
|
<div class="line"><a name="l07307"></a><span class="lineno"> 7307</span> <span class="preprocessor">#define RTC_ALRMAR_HT ((uint32_t)0x00300000)</span></div>
|
|
<div class="line"><a name="l07308"></a><span class="lineno"> 7308</span> <span class="preprocessor">#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)</span></div>
|
|
<div class="line"><a name="l07309"></a><span class="lineno"> 7309</span> <span class="preprocessor">#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)</span></div>
|
|
<div class="line"><a name="l07310"></a><span class="lineno"> 7310</span> <span class="preprocessor">#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)</span></div>
|
|
<div class="line"><a name="l07311"></a><span class="lineno"> 7311</span> <span class="preprocessor">#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)</span></div>
|
|
<div class="line"><a name="l07312"></a><span class="lineno"> 7312</span> <span class="preprocessor">#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)</span></div>
|
|
<div class="line"><a name="l07313"></a><span class="lineno"> 7313</span> <span class="preprocessor">#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)</span></div>
|
|
<div class="line"><a name="l07314"></a><span class="lineno"> 7314</span> <span class="preprocessor">#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)</span></div>
|
|
<div class="line"><a name="l07315"></a><span class="lineno"> 7315</span> <span class="preprocessor">#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)</span></div>
|
|
<div class="line"><a name="l07316"></a><span class="lineno"> 7316</span> <span class="preprocessor">#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)</span></div>
|
|
<div class="line"><a name="l07317"></a><span class="lineno"> 7317</span> <span class="preprocessor">#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)</span></div>
|
|
<div class="line"><a name="l07318"></a><span class="lineno"> 7318</span> <span class="preprocessor">#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)</span></div>
|
|
<div class="line"><a name="l07319"></a><span class="lineno"> 7319</span> <span class="preprocessor">#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)</span></div>
|
|
<div class="line"><a name="l07320"></a><span class="lineno"> 7320</span> <span class="preprocessor">#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)</span></div>
|
|
<div class="line"><a name="l07321"></a><span class="lineno"> 7321</span> <span class="preprocessor">#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l07322"></a><span class="lineno"> 7322</span> <span class="preprocessor">#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l07323"></a><span class="lineno"> 7323</span> <span class="preprocessor">#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l07324"></a><span class="lineno"> 7324</span> <span class="preprocessor">#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l07325"></a><span class="lineno"> 7325</span> <span class="preprocessor">#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)</span></div>
|
|
<div class="line"><a name="l07326"></a><span class="lineno"> 7326</span> <span class="preprocessor">#define RTC_ALRMAR_ST ((uint32_t)0x00000070)</span></div>
|
|
<div class="line"><a name="l07327"></a><span class="lineno"> 7327</span> <span class="preprocessor">#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l07328"></a><span class="lineno"> 7328</span> <span class="preprocessor">#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l07329"></a><span class="lineno"> 7329</span> <span class="preprocessor">#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l07330"></a><span class="lineno"> 7330</span> <span class="preprocessor">#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)</span></div>
|
|
<div class="line"><a name="l07331"></a><span class="lineno"> 7331</span> <span class="preprocessor">#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l07332"></a><span class="lineno"> 7332</span> <span class="preprocessor">#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l07333"></a><span class="lineno"> 7333</span> <span class="preprocessor">#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l07334"></a><span class="lineno"> 7334</span> <span class="preprocessor">#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l07335"></a><span class="lineno"> 7335</span> </div>
|
|
<div class="line"><a name="l07336"></a><span class="lineno"> 7336</span> <span class="comment">/******************** Bits definition for RTC_ALRMBR register ***************/</span></div>
|
|
<div class="line"><a name="l07337"></a><span class="lineno"> 7337</span> <span class="preprocessor">#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)</span></div>
|
|
<div class="line"><a name="l07338"></a><span class="lineno"> 7338</span> <span class="preprocessor">#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)</span></div>
|
|
<div class="line"><a name="l07339"></a><span class="lineno"> 7339</span> <span class="preprocessor">#define RTC_ALRMBR_DT ((uint32_t)0x30000000)</span></div>
|
|
<div class="line"><a name="l07340"></a><span class="lineno"> 7340</span> <span class="preprocessor">#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)</span></div>
|
|
<div class="line"><a name="l07341"></a><span class="lineno"> 7341</span> <span class="preprocessor">#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)</span></div>
|
|
<div class="line"><a name="l07342"></a><span class="lineno"> 7342</span> <span class="preprocessor">#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)</span></div>
|
|
<div class="line"><a name="l07343"></a><span class="lineno"> 7343</span> <span class="preprocessor">#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)</span></div>
|
|
<div class="line"><a name="l07344"></a><span class="lineno"> 7344</span> <span class="preprocessor">#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)</span></div>
|
|
<div class="line"><a name="l07345"></a><span class="lineno"> 7345</span> <span class="preprocessor">#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)</span></div>
|
|
<div class="line"><a name="l07346"></a><span class="lineno"> 7346</span> <span class="preprocessor">#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)</span></div>
|
|
<div class="line"><a name="l07347"></a><span class="lineno"> 7347</span> <span class="preprocessor">#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)</span></div>
|
|
<div class="line"><a name="l07348"></a><span class="lineno"> 7348</span> <span class="preprocessor">#define RTC_ALRMBR_PM ((uint32_t)0x00400000)</span></div>
|
|
<div class="line"><a name="l07349"></a><span class="lineno"> 7349</span> <span class="preprocessor">#define RTC_ALRMBR_HT ((uint32_t)0x00300000)</span></div>
|
|
<div class="line"><a name="l07350"></a><span class="lineno"> 7350</span> <span class="preprocessor">#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)</span></div>
|
|
<div class="line"><a name="l07351"></a><span class="lineno"> 7351</span> <span class="preprocessor">#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)</span></div>
|
|
<div class="line"><a name="l07352"></a><span class="lineno"> 7352</span> <span class="preprocessor">#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)</span></div>
|
|
<div class="line"><a name="l07353"></a><span class="lineno"> 7353</span> <span class="preprocessor">#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)</span></div>
|
|
<div class="line"><a name="l07354"></a><span class="lineno"> 7354</span> <span class="preprocessor">#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)</span></div>
|
|
<div class="line"><a name="l07355"></a><span class="lineno"> 7355</span> <span class="preprocessor">#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)</span></div>
|
|
<div class="line"><a name="l07356"></a><span class="lineno"> 7356</span> <span class="preprocessor">#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)</span></div>
|
|
<div class="line"><a name="l07357"></a><span class="lineno"> 7357</span> <span class="preprocessor">#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)</span></div>
|
|
<div class="line"><a name="l07358"></a><span class="lineno"> 7358</span> <span class="preprocessor">#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)</span></div>
|
|
<div class="line"><a name="l07359"></a><span class="lineno"> 7359</span> <span class="preprocessor">#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)</span></div>
|
|
<div class="line"><a name="l07360"></a><span class="lineno"> 7360</span> <span class="preprocessor">#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)</span></div>
|
|
<div class="line"><a name="l07361"></a><span class="lineno"> 7361</span> <span class="preprocessor">#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)</span></div>
|
|
<div class="line"><a name="l07362"></a><span class="lineno"> 7362</span> <span class="preprocessor">#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)</span></div>
|
|
<div class="line"><a name="l07363"></a><span class="lineno"> 7363</span> <span class="preprocessor">#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l07364"></a><span class="lineno"> 7364</span> <span class="preprocessor">#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l07365"></a><span class="lineno"> 7365</span> <span class="preprocessor">#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l07366"></a><span class="lineno"> 7366</span> <span class="preprocessor">#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l07367"></a><span class="lineno"> 7367</span> <span class="preprocessor">#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)</span></div>
|
|
<div class="line"><a name="l07368"></a><span class="lineno"> 7368</span> <span class="preprocessor">#define RTC_ALRMBR_ST ((uint32_t)0x00000070)</span></div>
|
|
<div class="line"><a name="l07369"></a><span class="lineno"> 7369</span> <span class="preprocessor">#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l07370"></a><span class="lineno"> 7370</span> <span class="preprocessor">#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l07371"></a><span class="lineno"> 7371</span> <span class="preprocessor">#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l07372"></a><span class="lineno"> 7372</span> <span class="preprocessor">#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)</span></div>
|
|
<div class="line"><a name="l07373"></a><span class="lineno"> 7373</span> <span class="preprocessor">#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l07374"></a><span class="lineno"> 7374</span> <span class="preprocessor">#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l07375"></a><span class="lineno"> 7375</span> <span class="preprocessor">#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l07376"></a><span class="lineno"> 7376</span> <span class="preprocessor">#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l07377"></a><span class="lineno"> 7377</span> </div>
|
|
<div class="line"><a name="l07378"></a><span class="lineno"> 7378</span> <span class="comment">/******************** Bits definition for RTC_WPR register ******************/</span></div>
|
|
<div class="line"><a name="l07379"></a><span class="lineno"> 7379</span> <span class="preprocessor">#define RTC_WPR_KEY ((uint32_t)0x000000FF)</span></div>
|
|
<div class="line"><a name="l07380"></a><span class="lineno"> 7380</span> </div>
|
|
<div class="line"><a name="l07381"></a><span class="lineno"> 7381</span> <span class="comment">/******************** Bits definition for RTC_SSR register ******************/</span></div>
|
|
<div class="line"><a name="l07382"></a><span class="lineno"> 7382</span> <span class="preprocessor">#define RTC_SSR_SS ((uint32_t)0x0000FFFF)</span></div>
|
|
<div class="line"><a name="l07383"></a><span class="lineno"> 7383</span> </div>
|
|
<div class="line"><a name="l07384"></a><span class="lineno"> 7384</span> <span class="comment">/******************** Bits definition for RTC_SHIFTR register ***************/</span></div>
|
|
<div class="line"><a name="l07385"></a><span class="lineno"> 7385</span> <span class="preprocessor">#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)</span></div>
|
|
<div class="line"><a name="l07386"></a><span class="lineno"> 7386</span> <span class="preprocessor">#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)</span></div>
|
|
<div class="line"><a name="l07387"></a><span class="lineno"> 7387</span> </div>
|
|
<div class="line"><a name="l07388"></a><span class="lineno"> 7388</span> <span class="comment">/******************** Bits definition for RTC_TSTR register *****************/</span></div>
|
|
<div class="line"><a name="l07389"></a><span class="lineno"> 7389</span> <span class="preprocessor">#define RTC_TSTR_PM ((uint32_t)0x00400000)</span></div>
|
|
<div class="line"><a name="l07390"></a><span class="lineno"> 7390</span> <span class="preprocessor">#define RTC_TSTR_HT ((uint32_t)0x00300000)</span></div>
|
|
<div class="line"><a name="l07391"></a><span class="lineno"> 7391</span> <span class="preprocessor">#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)</span></div>
|
|
<div class="line"><a name="l07392"></a><span class="lineno"> 7392</span> <span class="preprocessor">#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)</span></div>
|
|
<div class="line"><a name="l07393"></a><span class="lineno"> 7393</span> <span class="preprocessor">#define RTC_TSTR_HU ((uint32_t)0x000F0000)</span></div>
|
|
<div class="line"><a name="l07394"></a><span class="lineno"> 7394</span> <span class="preprocessor">#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)</span></div>
|
|
<div class="line"><a name="l07395"></a><span class="lineno"> 7395</span> <span class="preprocessor">#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)</span></div>
|
|
<div class="line"><a name="l07396"></a><span class="lineno"> 7396</span> <span class="preprocessor">#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)</span></div>
|
|
<div class="line"><a name="l07397"></a><span class="lineno"> 7397</span> <span class="preprocessor">#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)</span></div>
|
|
<div class="line"><a name="l07398"></a><span class="lineno"> 7398</span> <span class="preprocessor">#define RTC_TSTR_MNT ((uint32_t)0x00007000)</span></div>
|
|
<div class="line"><a name="l07399"></a><span class="lineno"> 7399</span> <span class="preprocessor">#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)</span></div>
|
|
<div class="line"><a name="l07400"></a><span class="lineno"> 7400</span> <span class="preprocessor">#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)</span></div>
|
|
<div class="line"><a name="l07401"></a><span class="lineno"> 7401</span> <span class="preprocessor">#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)</span></div>
|
|
<div class="line"><a name="l07402"></a><span class="lineno"> 7402</span> <span class="preprocessor">#define RTC_TSTR_MNU ((uint32_t)0x00000F00)</span></div>
|
|
<div class="line"><a name="l07403"></a><span class="lineno"> 7403</span> <span class="preprocessor">#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l07404"></a><span class="lineno"> 7404</span> <span class="preprocessor">#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l07405"></a><span class="lineno"> 7405</span> <span class="preprocessor">#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l07406"></a><span class="lineno"> 7406</span> <span class="preprocessor">#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l07407"></a><span class="lineno"> 7407</span> <span class="preprocessor">#define RTC_TSTR_ST ((uint32_t)0x00000070)</span></div>
|
|
<div class="line"><a name="l07408"></a><span class="lineno"> 7408</span> <span class="preprocessor">#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l07409"></a><span class="lineno"> 7409</span> <span class="preprocessor">#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l07410"></a><span class="lineno"> 7410</span> <span class="preprocessor">#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l07411"></a><span class="lineno"> 7411</span> <span class="preprocessor">#define RTC_TSTR_SU ((uint32_t)0x0000000F)</span></div>
|
|
<div class="line"><a name="l07412"></a><span class="lineno"> 7412</span> <span class="preprocessor">#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l07413"></a><span class="lineno"> 7413</span> <span class="preprocessor">#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l07414"></a><span class="lineno"> 7414</span> <span class="preprocessor">#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l07415"></a><span class="lineno"> 7415</span> <span class="preprocessor">#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l07416"></a><span class="lineno"> 7416</span> </div>
|
|
<div class="line"><a name="l07417"></a><span class="lineno"> 7417</span> <span class="comment">/******************** Bits definition for RTC_TSDR register *****************/</span></div>
|
|
<div class="line"><a name="l07418"></a><span class="lineno"> 7418</span> <span class="preprocessor">#define RTC_TSDR_WDU ((uint32_t)0x0000E000)</span></div>
|
|
<div class="line"><a name="l07419"></a><span class="lineno"> 7419</span> <span class="preprocessor">#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)</span></div>
|
|
<div class="line"><a name="l07420"></a><span class="lineno"> 7420</span> <span class="preprocessor">#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)</span></div>
|
|
<div class="line"><a name="l07421"></a><span class="lineno"> 7421</span> <span class="preprocessor">#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)</span></div>
|
|
<div class="line"><a name="l07422"></a><span class="lineno"> 7422</span> <span class="preprocessor">#define RTC_TSDR_MT ((uint32_t)0x00001000)</span></div>
|
|
<div class="line"><a name="l07423"></a><span class="lineno"> 7423</span> <span class="preprocessor">#define RTC_TSDR_MU ((uint32_t)0x00000F00)</span></div>
|
|
<div class="line"><a name="l07424"></a><span class="lineno"> 7424</span> <span class="preprocessor">#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l07425"></a><span class="lineno"> 7425</span> <span class="preprocessor">#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l07426"></a><span class="lineno"> 7426</span> <span class="preprocessor">#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l07427"></a><span class="lineno"> 7427</span> <span class="preprocessor">#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l07428"></a><span class="lineno"> 7428</span> <span class="preprocessor">#define RTC_TSDR_DT ((uint32_t)0x00000030)</span></div>
|
|
<div class="line"><a name="l07429"></a><span class="lineno"> 7429</span> <span class="preprocessor">#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l07430"></a><span class="lineno"> 7430</span> <span class="preprocessor">#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l07431"></a><span class="lineno"> 7431</span> <span class="preprocessor">#define RTC_TSDR_DU ((uint32_t)0x0000000F)</span></div>
|
|
<div class="line"><a name="l07432"></a><span class="lineno"> 7432</span> <span class="preprocessor">#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l07433"></a><span class="lineno"> 7433</span> <span class="preprocessor">#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l07434"></a><span class="lineno"> 7434</span> <span class="preprocessor">#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l07435"></a><span class="lineno"> 7435</span> <span class="preprocessor">#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l07436"></a><span class="lineno"> 7436</span> </div>
|
|
<div class="line"><a name="l07437"></a><span class="lineno"> 7437</span> <span class="comment">/******************** Bits definition for RTC_TSSSR register ****************/</span></div>
|
|
<div class="line"><a name="l07438"></a><span class="lineno"> 7438</span> <span class="preprocessor">#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)</span></div>
|
|
<div class="line"><a name="l07439"></a><span class="lineno"> 7439</span> </div>
|
|
<div class="line"><a name="l07440"></a><span class="lineno"> 7440</span> <span class="comment">/******************** Bits definition for RTC_CAL register *****************/</span></div>
|
|
<div class="line"><a name="l07441"></a><span class="lineno"> 7441</span> <span class="preprocessor">#define RTC_CALR_CALP ((uint32_t)0x00008000)</span></div>
|
|
<div class="line"><a name="l07442"></a><span class="lineno"> 7442</span> <span class="preprocessor">#define RTC_CALR_CALW8 ((uint32_t)0x00004000)</span></div>
|
|
<div class="line"><a name="l07443"></a><span class="lineno"> 7443</span> <span class="preprocessor">#define RTC_CALR_CALW16 ((uint32_t)0x00002000)</span></div>
|
|
<div class="line"><a name="l07444"></a><span class="lineno"> 7444</span> <span class="preprocessor">#define RTC_CALR_CALM ((uint32_t)0x000001FF)</span></div>
|
|
<div class="line"><a name="l07445"></a><span class="lineno"> 7445</span> <span class="preprocessor">#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l07446"></a><span class="lineno"> 7446</span> <span class="preprocessor">#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l07447"></a><span class="lineno"> 7447</span> <span class="preprocessor">#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l07448"></a><span class="lineno"> 7448</span> <span class="preprocessor">#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l07449"></a><span class="lineno"> 7449</span> <span class="preprocessor">#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)</span></div>
|
|
<div class="line"><a name="l07450"></a><span class="lineno"> 7450</span> <span class="preprocessor">#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)</span></div>
|
|
<div class="line"><a name="l07451"></a><span class="lineno"> 7451</span> <span class="preprocessor">#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)</span></div>
|
|
<div class="line"><a name="l07452"></a><span class="lineno"> 7452</span> <span class="preprocessor">#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)</span></div>
|
|
<div class="line"><a name="l07453"></a><span class="lineno"> 7453</span> <span class="preprocessor">#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l07454"></a><span class="lineno"> 7454</span> </div>
|
|
<div class="line"><a name="l07455"></a><span class="lineno"> 7455</span> <span class="comment">/******************** Bits definition for RTC_TAFCR register ****************/</span></div>
|
|
<div class="line"><a name="l07456"></a><span class="lineno"> 7456</span> <span class="preprocessor">#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)</span></div>
|
|
<div class="line"><a name="l07457"></a><span class="lineno"> 7457</span> <span class="preprocessor">#define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)</span></div>
|
|
<div class="line"><a name="l07458"></a><span class="lineno"> 7458</span> <span class="preprocessor">#define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)</span></div>
|
|
<div class="line"><a name="l07459"></a><span class="lineno"> 7459</span> <span class="preprocessor">#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)</span></div>
|
|
<div class="line"><a name="l07460"></a><span class="lineno"> 7460</span> <span class="preprocessor">#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)</span></div>
|
|
<div class="line"><a name="l07461"></a><span class="lineno"> 7461</span> <span class="preprocessor">#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)</span></div>
|
|
<div class="line"><a name="l07462"></a><span class="lineno"> 7462</span> <span class="preprocessor">#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)</span></div>
|
|
<div class="line"><a name="l07463"></a><span class="lineno"> 7463</span> <span class="preprocessor">#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)</span></div>
|
|
<div class="line"><a name="l07464"></a><span class="lineno"> 7464</span> <span class="preprocessor">#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)</span></div>
|
|
<div class="line"><a name="l07465"></a><span class="lineno"> 7465</span> <span class="preprocessor">#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)</span></div>
|
|
<div class="line"><a name="l07466"></a><span class="lineno"> 7466</span> <span class="preprocessor">#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)</span></div>
|
|
<div class="line"><a name="l07467"></a><span class="lineno"> 7467</span> <span class="preprocessor">#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)</span></div>
|
|
<div class="line"><a name="l07468"></a><span class="lineno"> 7468</span> <span class="preprocessor">#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)</span></div>
|
|
<div class="line"><a name="l07469"></a><span class="lineno"> 7469</span> <span class="preprocessor">#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)</span></div>
|
|
<div class="line"><a name="l07470"></a><span class="lineno"> 7470</span> <span class="preprocessor">#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)</span></div>
|
|
<div class="line"><a name="l07471"></a><span class="lineno"> 7471</span> <span class="preprocessor">#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)</span></div>
|
|
<div class="line"><a name="l07472"></a><span class="lineno"> 7472</span> <span class="preprocessor">#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)</span></div>
|
|
<div class="line"><a name="l07473"></a><span class="lineno"> 7473</span> <span class="preprocessor">#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l07474"></a><span class="lineno"> 7474</span> </div>
|
|
<div class="line"><a name="l07475"></a><span class="lineno"> 7475</span> <span class="comment">/******************** Bits definition for RTC_ALRMASSR register *************/</span></div>
|
|
<div class="line"><a name="l07476"></a><span class="lineno"> 7476</span> <span class="preprocessor">#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)</span></div>
|
|
<div class="line"><a name="l07477"></a><span class="lineno"> 7477</span> <span class="preprocessor">#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)</span></div>
|
|
<div class="line"><a name="l07478"></a><span class="lineno"> 7478</span> <span class="preprocessor">#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)</span></div>
|
|
<div class="line"><a name="l07479"></a><span class="lineno"> 7479</span> <span class="preprocessor">#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)</span></div>
|
|
<div class="line"><a name="l07480"></a><span class="lineno"> 7480</span> <span class="preprocessor">#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)</span></div>
|
|
<div class="line"><a name="l07481"></a><span class="lineno"> 7481</span> <span class="preprocessor">#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)</span></div>
|
|
<div class="line"><a name="l07482"></a><span class="lineno"> 7482</span> </div>
|
|
<div class="line"><a name="l07483"></a><span class="lineno"> 7483</span> <span class="comment">/******************** Bits definition for RTC_ALRMBSSR register *************/</span></div>
|
|
<div class="line"><a name="l07484"></a><span class="lineno"> 7484</span> <span class="preprocessor">#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)</span></div>
|
|
<div class="line"><a name="l07485"></a><span class="lineno"> 7485</span> <span class="preprocessor">#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)</span></div>
|
|
<div class="line"><a name="l07486"></a><span class="lineno"> 7486</span> <span class="preprocessor">#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)</span></div>
|
|
<div class="line"><a name="l07487"></a><span class="lineno"> 7487</span> <span class="preprocessor">#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)</span></div>
|
|
<div class="line"><a name="l07488"></a><span class="lineno"> 7488</span> <span class="preprocessor">#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)</span></div>
|
|
<div class="line"><a name="l07489"></a><span class="lineno"> 7489</span> <span class="preprocessor">#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)</span></div>
|
|
<div class="line"><a name="l07490"></a><span class="lineno"> 7490</span> </div>
|
|
<div class="line"><a name="l07491"></a><span class="lineno"> 7491</span> <span class="comment">/******************** Bits definition for RTC_BKP0R register ****************/</span></div>
|
|
<div class="line"><a name="l07492"></a><span class="lineno"> 7492</span> <span class="preprocessor">#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)</span></div>
|
|
<div class="line"><a name="l07493"></a><span class="lineno"> 7493</span> </div>
|
|
<div class="line"><a name="l07494"></a><span class="lineno"> 7494</span> <span class="comment">/******************** Bits definition for RTC_BKP1R register ****************/</span></div>
|
|
<div class="line"><a name="l07495"></a><span class="lineno"> 7495</span> <span class="preprocessor">#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)</span></div>
|
|
<div class="line"><a name="l07496"></a><span class="lineno"> 7496</span> </div>
|
|
<div class="line"><a name="l07497"></a><span class="lineno"> 7497</span> <span class="comment">/******************** Bits definition for RTC_BKP2R register ****************/</span></div>
|
|
<div class="line"><a name="l07498"></a><span class="lineno"> 7498</span> <span class="preprocessor">#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)</span></div>
|
|
<div class="line"><a name="l07499"></a><span class="lineno"> 7499</span> </div>
|
|
<div class="line"><a name="l07500"></a><span class="lineno"> 7500</span> <span class="comment">/******************** Bits definition for RTC_BKP3R register ****************/</span></div>
|
|
<div class="line"><a name="l07501"></a><span class="lineno"> 7501</span> <span class="preprocessor">#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)</span></div>
|
|
<div class="line"><a name="l07502"></a><span class="lineno"> 7502</span> </div>
|
|
<div class="line"><a name="l07503"></a><span class="lineno"> 7503</span> <span class="comment">/******************** Bits definition for RTC_BKP4R register ****************/</span></div>
|
|
<div class="line"><a name="l07504"></a><span class="lineno"> 7504</span> <span class="preprocessor">#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)</span></div>
|
|
<div class="line"><a name="l07505"></a><span class="lineno"> 7505</span> </div>
|
|
<div class="line"><a name="l07506"></a><span class="lineno"> 7506</span> <span class="comment">/******************** Bits definition for RTC_BKP5R register ****************/</span></div>
|
|
<div class="line"><a name="l07507"></a><span class="lineno"> 7507</span> <span class="preprocessor">#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)</span></div>
|
|
<div class="line"><a name="l07508"></a><span class="lineno"> 7508</span> </div>
|
|
<div class="line"><a name="l07509"></a><span class="lineno"> 7509</span> <span class="comment">/******************** Bits definition for RTC_BKP6R register ****************/</span></div>
|
|
<div class="line"><a name="l07510"></a><span class="lineno"> 7510</span> <span class="preprocessor">#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)</span></div>
|
|
<div class="line"><a name="l07511"></a><span class="lineno"> 7511</span> </div>
|
|
<div class="line"><a name="l07512"></a><span class="lineno"> 7512</span> <span class="comment">/******************** Bits definition for RTC_BKP7R register ****************/</span></div>
|
|
<div class="line"><a name="l07513"></a><span class="lineno"> 7513</span> <span class="preprocessor">#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)</span></div>
|
|
<div class="line"><a name="l07514"></a><span class="lineno"> 7514</span> </div>
|
|
<div class="line"><a name="l07515"></a><span class="lineno"> 7515</span> <span class="comment">/******************** Bits definition for RTC_BKP8R register ****************/</span></div>
|
|
<div class="line"><a name="l07516"></a><span class="lineno"> 7516</span> <span class="preprocessor">#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)</span></div>
|
|
<div class="line"><a name="l07517"></a><span class="lineno"> 7517</span> </div>
|
|
<div class="line"><a name="l07518"></a><span class="lineno"> 7518</span> <span class="comment">/******************** Bits definition for RTC_BKP9R register ****************/</span></div>
|
|
<div class="line"><a name="l07519"></a><span class="lineno"> 7519</span> <span class="preprocessor">#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)</span></div>
|
|
<div class="line"><a name="l07520"></a><span class="lineno"> 7520</span> </div>
|
|
<div class="line"><a name="l07521"></a><span class="lineno"> 7521</span> <span class="comment">/******************** Bits definition for RTC_BKP10R register ***************/</span></div>
|
|
<div class="line"><a name="l07522"></a><span class="lineno"> 7522</span> <span class="preprocessor">#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)</span></div>
|
|
<div class="line"><a name="l07523"></a><span class="lineno"> 7523</span> </div>
|
|
<div class="line"><a name="l07524"></a><span class="lineno"> 7524</span> <span class="comment">/******************** Bits definition for RTC_BKP11R register ***************/</span></div>
|
|
<div class="line"><a name="l07525"></a><span class="lineno"> 7525</span> <span class="preprocessor">#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)</span></div>
|
|
<div class="line"><a name="l07526"></a><span class="lineno"> 7526</span> </div>
|
|
<div class="line"><a name="l07527"></a><span class="lineno"> 7527</span> <span class="comment">/******************** Bits definition for RTC_BKP12R register ***************/</span></div>
|
|
<div class="line"><a name="l07528"></a><span class="lineno"> 7528</span> <span class="preprocessor">#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)</span></div>
|
|
<div class="line"><a name="l07529"></a><span class="lineno"> 7529</span> </div>
|
|
<div class="line"><a name="l07530"></a><span class="lineno"> 7530</span> <span class="comment">/******************** Bits definition for RTC_BKP13R register ***************/</span></div>
|
|
<div class="line"><a name="l07531"></a><span class="lineno"> 7531</span> <span class="preprocessor">#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)</span></div>
|
|
<div class="line"><a name="l07532"></a><span class="lineno"> 7532</span> </div>
|
|
<div class="line"><a name="l07533"></a><span class="lineno"> 7533</span> <span class="comment">/******************** Bits definition for RTC_BKP14R register ***************/</span></div>
|
|
<div class="line"><a name="l07534"></a><span class="lineno"> 7534</span> <span class="preprocessor">#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)</span></div>
|
|
<div class="line"><a name="l07535"></a><span class="lineno"> 7535</span> </div>
|
|
<div class="line"><a name="l07536"></a><span class="lineno"> 7536</span> <span class="comment">/******************** Bits definition for RTC_BKP15R register ***************/</span></div>
|
|
<div class="line"><a name="l07537"></a><span class="lineno"> 7537</span> <span class="preprocessor">#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)</span></div>
|
|
<div class="line"><a name="l07538"></a><span class="lineno"> 7538</span> </div>
|
|
<div class="line"><a name="l07539"></a><span class="lineno"> 7539</span> <span class="comment">/******************** Bits definition for RTC_BKP16R register ***************/</span></div>
|
|
<div class="line"><a name="l07540"></a><span class="lineno"> 7540</span> <span class="preprocessor">#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)</span></div>
|
|
<div class="line"><a name="l07541"></a><span class="lineno"> 7541</span> </div>
|
|
<div class="line"><a name="l07542"></a><span class="lineno"> 7542</span> <span class="comment">/******************** Bits definition for RTC_BKP17R register ***************/</span></div>
|
|
<div class="line"><a name="l07543"></a><span class="lineno"> 7543</span> <span class="preprocessor">#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)</span></div>
|
|
<div class="line"><a name="l07544"></a><span class="lineno"> 7544</span> </div>
|
|
<div class="line"><a name="l07545"></a><span class="lineno"> 7545</span> <span class="comment">/******************** Bits definition for RTC_BKP18R register ***************/</span></div>
|
|
<div class="line"><a name="l07546"></a><span class="lineno"> 7546</span> <span class="preprocessor">#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)</span></div>
|
|
<div class="line"><a name="l07547"></a><span class="lineno"> 7547</span> </div>
|
|
<div class="line"><a name="l07548"></a><span class="lineno"> 7548</span> <span class="comment">/******************** Bits definition for RTC_BKP19R register ***************/</span></div>
|
|
<div class="line"><a name="l07549"></a><span class="lineno"> 7549</span> <span class="preprocessor">#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)</span></div>
|
|
<div class="line"><a name="l07550"></a><span class="lineno"> 7550</span> </div>
|
|
<div class="line"><a name="l07551"></a><span class="lineno"> 7551</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l07552"></a><span class="lineno"> 7552</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l07553"></a><span class="lineno"> 7553</span> <span class="comment">/* Serial Audio Interface */</span></div>
|
|
<div class="line"><a name="l07554"></a><span class="lineno"> 7554</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l07555"></a><span class="lineno"> 7555</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l07556"></a><span class="lineno"> 7556</span> <span class="comment">/******************** Bit definition for SAI_GCR register *******************/</span></div>
|
|
<div class="line"><a name="l07557"></a><span class="lineno"> 7557</span> <span class="preprocessor">#define SAI_GCR_SYNCIN ((uint32_t)0x00000003) </span></div>
|
|
<div class="line"><a name="l07558"></a><span class="lineno"> 7558</span> <span class="preprocessor">#define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l07559"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabc29912477e15bf48a732a8a3b55ae81"> 7559</a></span> <span class="preprocessor">#define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l07561"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c65de3f7ddbf31c90da6b1453a2ff69"> 7561</a></span> <span class="preprocessor">#define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) </span></div>
|
|
<div class="line"><a name="l07562"></a><span class="lineno"> 7562</span> <span class="preprocessor">#define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l07563"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab0b9aa1a30108cdfe3088c4cacaeb27e"> 7563</a></span> <span class="preprocessor">#define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l07565"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2c03899faccbae6c741743eb032dedc"> 7565</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for SAI_xCR1 register *******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l07566"></a><span class="lineno"> 7566</span> <span class="preprocessor">#define SAI_xCR1_MODE ((uint32_t)0x00000003) </span></div>
|
|
<div class="line"><a name="l07567"></a><span class="lineno"> 7567</span> <span class="preprocessor">#define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l07568"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51af4b787c1e5e049f3bb22b82902866"> 7568</a></span> <span class="preprocessor">#define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l07570"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c25169081899de44a05e793e46d7ca5"> 7570</a></span> <span class="preprocessor">#define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) </span></div>
|
|
<div class="line"><a name="l07571"></a><span class="lineno"> 7571</span> <span class="preprocessor">#define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) </span></div>
|
|
<div class="line"><a name="l07572"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf8432db16a815678078cb1ffbd31a6f"> 7572</a></span> <span class="preprocessor">#define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l07574"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8714977ece0c80ddb952222a0923d81d"> 7574</a></span> <span class="preprocessor">#define SAI_xCR1_DS ((uint32_t)0x000000E0) </span></div>
|
|
<div class="line"><a name="l07575"></a><span class="lineno"> 7575</span> <span class="preprocessor">#define SAI_xCR1_DS_0 ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l07576"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c1204482a8c5427bffe720848696097"> 7576</a></span> <span class="preprocessor">#define SAI_xCR1_DS_1 ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l07577"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb5dd23287a176f80d241f0dfb8fcc7d"> 7577</a></span> <span class="preprocessor">#define SAI_xCR1_DS_2 ((uint32_t)0x00000080) </span></div>
|
|
<div class="line"><a name="l07579"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab50b27e8638b16d12ef00e80bf0f097e"> 7579</a></span> <span class="preprocessor">#define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l07580"></a><span class="lineno"> 7580</span> <span class="preprocessor">#define SAI_xCR1_CKSTR ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l07582"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2c0c68bf65088e0ddeb9a1759aff3f7"> 7582</a></span> <span class="preprocessor">#define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) </span></div>
|
|
<div class="line"><a name="l07583"></a><span class="lineno"> 7583</span> <span class="preprocessor">#define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l07584"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0179f00f5bd962763b6425d930d449db"> 7584</a></span> <span class="preprocessor">#define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l07586"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad59a87c05a0e147d3ed2364ccf91b18b"> 7586</a></span> <span class="preprocessor">#define SAI_xCR1_MONO ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l07587"></a><span class="lineno"> 7587</span> <span class="preprocessor">#define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) </span></div>
|
|
<div class="line"><a name="l07588"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga37f2b989e1a54b2c4393cd222e54f4d2"> 7588</a></span> <span class="preprocessor">#define SAI_xCR1_SAIEN ((uint32_t)0x00010000) </span></div>
|
|
<div class="line"><a name="l07589"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c79a642d52f20f97ab575f655b1ddea"> 7589</a></span> <span class="preprocessor">#define SAI_xCR1_DMAEN ((uint32_t)0x00020000) </span></div>
|
|
<div class="line"><a name="l07590"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7916f81ebe07b5109b0ca405d41eb95b"> 7590</a></span> <span class="preprocessor">#define SAI_xCR1_NODIV ((uint32_t)0x00080000) </span></div>
|
|
<div class="line"><a name="l07592"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98132c4a713c61f232c51b5c5e73622d"> 7592</a></span> <span class="preprocessor">#define SAI_xCR1_MCKDIV ((uint32_t)0x00780000) </span></div>
|
|
<div class="line"><a name="l07593"></a><span class="lineno"> 7593</span> <span class="preprocessor">#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00080000) </span></div>
|
|
<div class="line"><a name="l07594"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga47d3161434e2c4613f37ebe676735aaf"> 7594</a></span> <span class="preprocessor">#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00100000) </span></div>
|
|
<div class="line"><a name="l07595"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga485a62dda2c1af628ead9fd7db830c69"> 7595</a></span> <span class="preprocessor">#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00200000) </span></div>
|
|
<div class="line"><a name="l07596"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa253fffbd9bb4a514266afd305016485"> 7596</a></span> <span class="preprocessor">#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00400000) </span></div>
|
|
<div class="line"><a name="l07598"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac064c863cb6d75c11728a4642079fe99"> 7598</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for SAI_xCR2 register *******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l07599"></a><span class="lineno"> 7599</span> <span class="preprocessor">#define SAI_xCR2_FTH ((uint32_t)0x00000003) </span></div>
|
|
<div class="line"><a name="l07600"></a><span class="lineno"> 7600</span> <span class="preprocessor">#define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l07601"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga713102e56f4bb8c7c942662c82d04463"> 7601</a></span> <span class="preprocessor">#define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) </span></div>
|
|
<div class="line"><a name="l07603"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada48fb2897794cd0d5436909c9706046"> 7603</a></span> <span class="preprocessor">#define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) </span></div>
|
|
<div class="line"><a name="l07604"></a><span class="lineno"> 7604</span> <span class="preprocessor">#define SAI_xCR2_TRIS ((uint32_t)0x00000010) </span></div>
|
|
<div class="line"><a name="l07605"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2baa86fa37d7709b06a04664a52be0a1"> 7605</a></span> <span class="preprocessor">#define SAI_xCR2_MUTE ((uint32_t)0x00000020) </span></div>
|
|
<div class="line"><a name="l07606"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabb67ecd983af1e4f8c9a5935c013752d"> 7606</a></span> <span class="preprocessor">#define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) </span></div>
|
|
<div class="line"><a name="l07608"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5ba4ba2073e0737d432aeca306cc47e2"> 7608</a></span> <span class="preprocessor">#define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) </span></div>
|
|
<div class="line"><a name="l07609"></a><span class="lineno"> 7609</span> <span class="preprocessor">#define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) </span></div>
|
|
<div class="line"><a name="l07610"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafeea35e023c198d82d24fa64ab3081d9"> 7610</a></span> <span class="preprocessor">#define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) </span></div>
|
|
<div class="line"><a name="l07611"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga738aaa45d7140ea8adb69990c6b73f11"> 7611</a></span> <span class="preprocessor">#define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) </span></div>
|
|
<div class="line"><a name="l07612"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8646398473c7b5d42ae6172796848562"> 7612</a></span> <span class="preprocessor">#define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) </span></div>
|
|
<div class="line"><a name="l07613"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga008e089b87f5e7a0a63c565e1f59c206"> 7613</a></span> <span class="preprocessor">#define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) </span></div>
|
|
<div class="line"><a name="l07614"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1271dbdafa65f001779fedc9c9320166"> 7614</a></span> <span class="preprocessor">#define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) </span></div>
|
|
<div class="line"><a name="l07616"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga296db2ad211b0c3b4330a4c3b1f0233f"> 7616</a></span> <span class="preprocessor">#define SAI_xCR2_CPL ((uint32_t)0x00080000) </span></div>
|
|
<div class="line"><a name="l07618"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a8f6db7fd5fe5f0e264fa6c184d02e1"> 7618</a></span> <span class="preprocessor">#define SAI_xCR2_COMP ((uint32_t)0x0000C000) </span></div>
|
|
<div class="line"><a name="l07619"></a><span class="lineno"> 7619</span> <span class="preprocessor">#define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) </span></div>
|
|
<div class="line"><a name="l07620"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf8732274be296455ea01ac0b95232c4d"> 7620</a></span> <span class="preprocessor">#define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) </span></div>
|
|
<div class="line"><a name="l07622"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07d441ea4c041f91e4879a5b32278128"> 7622</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for SAI_xFRCR register *******************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l07623"></a><span class="lineno"> 7623</span> <span class="preprocessor">#define SAI_xFRCR_FRL ((uint32_t)0x000000FF) </span></div>
|
|
<div class="line"><a name="l07624"></a><span class="lineno"> 7624</span> <span class="preprocessor">#define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) </span></div>
|
|
<div class="line"><a name="l07625"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7145cd48fe5f1135082db1dd5bab5697"> 7625</a></span> <span class="preprocessor">#define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l07626"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabeeb587d1dd769e9dba21d96c15b0a5d"> 7626</a></span> <span class="preprocessor">#define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l07627"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad0c5bdfa2777ca5890798d7aaf7067b9"> 7627</a></span> <span class="preprocessor">#define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l07628"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e705e32fff1ba410938636af8b5bc38"> 7628</a></span> <span class="preprocessor">#define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l07629"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad568d991beac0d0f1970ec66731c974b"> 7629</a></span> <span class="preprocessor">#define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l07630"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c72db15f0f18329f497d1809be47298"> 7630</a></span> <span class="preprocessor">#define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l07631"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4ef47f5def6ac6f7e18c52349e427a0a"> 7631</a></span> <span class="preprocessor">#define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l07633"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a63a0bbb35ceb0fedbd1f32c0205544"> 7633</a></span> <span class="preprocessor">#define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) </span></div>
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<div class="line"><a name="l07634"></a><span class="lineno"> 7634</span> <span class="preprocessor">#define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l07635"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5da4d6d92e108bac869ca37a1d9510c"> 7635</a></span> <span class="preprocessor">#define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l07636"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a6c7e235ee451ed574092b0ceb974e1"> 7636</a></span> <span class="preprocessor">#define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l07637"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a74c00e149382365fa40c1fe4535794"> 7637</a></span> <span class="preprocessor">#define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l07638"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3a7f33c72264a5adeb95cb02e413601"> 7638</a></span> <span class="preprocessor">#define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l07639"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga12a31862f1e9c31bf35e35eea8920f38"> 7639</a></span> <span class="preprocessor">#define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l07640"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2dcbbf60f36e99c371327f02a9d151ae"> 7640</a></span> <span class="preprocessor">#define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l07642"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga523a1caf60b37eb9cc56f19e7d0dd91a"> 7642</a></span> <span class="preprocessor">#define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l07643"></a><span class="lineno"> 7643</span> <span class="preprocessor">#define SAI_xFRCR_FSPO ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l07644"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b9e1700cf196e3dec87c1362023ca29"> 7644</a></span> <span class="preprocessor">#define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l07646"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga250708d79ab12828bb6388390790a406"> 7646</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for SAI_xSLOTR register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07647"></a><span class="lineno"> 7647</span> <span class="preprocessor">#define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) </span></div>
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<div class="line"><a name="l07648"></a><span class="lineno"> 7648</span> <span class="preprocessor">#define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l07649"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae7765ebf87061237afaa5995af169e52"> 7649</a></span> <span class="preprocessor">#define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l07650"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b408483c0ead128ebc644ae18f56640"> 7650</a></span> <span class="preprocessor">#define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l07651"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0bccac768ad131f506077eb62bae5735"> 7651</a></span> <span class="preprocessor">#define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l07652"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3bd460f33d3668f3ff845d5bcdb09d1a"> 7652</a></span> <span class="preprocessor">#define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l07654"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4dc62365e1f26821a794a1d6d445e65"> 7654</a></span> <span class="preprocessor">#define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) </span></div>
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<div class="line"><a name="l07655"></a><span class="lineno"> 7655</span> <span class="preprocessor">#define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l07656"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5d5a75af6a1bddfb90900eb32a954b79"> 7656</a></span> <span class="preprocessor">#define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l07658"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf84f10c4f64d886eed350d7227f112a2"> 7658</a></span> <span class="preprocessor">#define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) </span></div>
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<div class="line"><a name="l07659"></a><span class="lineno"> 7659</span> <span class="preprocessor">#define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l07660"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga17cb9f8174d764be83e5317d3e1035d7"> 7660</a></span> <span class="preprocessor">#define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l07661"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6e4da866d6d37aa5bf683719627e987d"> 7661</a></span> <span class="preprocessor">#define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l07662"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6fa38bb50c74d9be58506d6254fcb9eb"> 7662</a></span> <span class="preprocessor">#define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l07664"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbba380cbd21b4a615f3e3c6f5787f5b"> 7664</a></span> <span class="preprocessor">#define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) </span></div>
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<div class="line"><a name="l07666"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3be5abc4ae85eb99423ad87c2742813"> 7666</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for SAI_xIMR register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07667"></a><span class="lineno"> 7667</span> <span class="preprocessor">#define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l07668"></a><span class="lineno"> 7668</span> <span class="preprocessor">#define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l07669"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19cf98322a8a9297bf189674085a3c4d"> 7669</a></span> <span class="preprocessor">#define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l07670"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga86d1812361eb7081a60d575fbc1c664e"> 7670</a></span> <span class="preprocessor">#define SAI_xIMR_FREQIE ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l07671"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4bce2334c9381068661356c84b947507"> 7671</a></span> <span class="preprocessor">#define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l07672"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae0ddbd32ec7f069219827247614454f9"> 7672</a></span> <span class="preprocessor">#define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l07673"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16c51a8eacd28e521cf3da6d3a427a32"> 7673</a></span> <span class="preprocessor">#define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l07675"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ac59347c7f574af79b586a793b2160f"> 7675</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for SAI_xSR register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07676"></a><span class="lineno"> 7676</span> <span class="preprocessor">#define SAI_xSR_OVRUDR ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l07677"></a><span class="lineno"> 7677</span> <span class="preprocessor">#define SAI_xSR_MUTEDET ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l07678"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac935e26343913d548d1fa4a1d53d37df"> 7678</a></span> <span class="preprocessor">#define SAI_xSR_WCKCFG ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l07679"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga92f97a8a22c3301d76e3704fb70d1234"> 7679</a></span> <span class="preprocessor">#define SAI_xSR_FREQ ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l07680"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac85199d384ead397bc7e5874b948e798"> 7680</a></span> <span class="preprocessor">#define SAI_xSR_CNRDY ((uint32_t)0x00000010) </span></div>
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|
<div class="line"><a name="l07681"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab5530f57526edd6dc0d2774042f8f5cc"> 7681</a></span> <span class="preprocessor">#define SAI_xSR_AFSDET ((uint32_t)0x00000020) </span></div>
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|
<div class="line"><a name="l07682"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga59176cbf38a7bf9913215ca9cc716da7"> 7682</a></span> <span class="preprocessor">#define SAI_xSR_LFSDET ((uint32_t)0x00000040) </span></div>
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|
<div class="line"><a name="l07684"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa2d45adbe2be27461e25ecbf736e0500"> 7684</a></span> <span class="preprocessor">#define SAI_xSR_FLVL ((uint32_t)0x00070000) </span></div>
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<div class="line"><a name="l07685"></a><span class="lineno"> 7685</span> <span class="preprocessor">#define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) </span></div>
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|
<div class="line"><a name="l07686"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga59818375f1cff9c6f6f7236282786e05"> 7686</a></span> <span class="preprocessor">#define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l07687"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga997ab54aae94ba235453fdfabd9d87ce"> 7687</a></span> <span class="preprocessor">#define SAI_xSR_FLVL_2 ((uint32_t)0x00030000) </span></div>
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<div class="line"><a name="l07689"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09ba36509d0ee8a339bd65002529fe5d"> 7689</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for SAI_xCLRFR register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07690"></a><span class="lineno"> 7690</span> <span class="preprocessor">#define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l07691"></a><span class="lineno"> 7691</span> <span class="preprocessor">#define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l07692"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2055a162a6d48320dd850efe26666986"> 7692</a></span> <span class="preprocessor">#define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l07693"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8fc93014165f8d5f1543f08ee91602b8"> 7693</a></span> <span class="preprocessor">#define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l07694"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac253542238f77deb2ea84843653cb06b"> 7694</a></span> <span class="preprocessor">#define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l07695"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6594324f23f4ead6abc8fec3b94e4606"> 7695</a></span> <span class="preprocessor">#define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l07696"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaef77e53ee176c9ba61416ca5503ac717"> 7696</a></span> <span class="preprocessor">#define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l07698"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf27f000890347520975d00db031f8998"> 7698</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for SAI_xDR register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07699"></a><span class="lineno"> 7699</span> <span class="preprocessor">#define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF) </span></div>
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<div class="line"><a name="l07700"></a><span class="lineno"> 7700</span> </div>
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<div class="line"><a name="l07701"></a><span class="lineno"> 7701</span> <span class="comment">/******************************************************************************/</span></div>
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<div class="line"><a name="l07702"></a><span class="lineno"> 7702</span> <span class="comment">/* */</span></div>
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<div class="line"><a name="l07703"></a><span class="lineno"> 7703</span> <span class="comment">/* SD host Interface */</span></div>
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<div class="line"><a name="l07704"></a><span class="lineno"> 7704</span> <span class="comment">/* */</span></div>
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<div class="line"><a name="l07705"></a><span class="lineno"> 7705</span> <span class="comment">/******************************************************************************/</span></div>
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<div class="line"><a name="l07706"></a><span class="lineno"> 7706</span> <span class="comment">/****************** Bit definition for SDIO_POWER register ******************/</span></div>
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<div class="line"><a name="l07707"></a><span class="lineno"> 7707</span> <span class="preprocessor">#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) </span></div>
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<div class="line"><a name="l07708"></a><span class="lineno"> 7708</span> <span class="preprocessor">#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) </span></div>
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<div class="line"><a name="l07709"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf125c56eeb40163b617c9fb6329da67f"> 7709</a></span> <span class="preprocessor">#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) </span></div>
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<div class="line"><a name="l07711"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadd149efb1d6062f37165ac01268a875e"> 7711</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for SDIO_CLKCR register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07712"></a><span class="lineno"> 7712</span> <span class="preprocessor">#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) </span></div>
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<div class="line"><a name="l07713"></a><span class="lineno"> 7713</span> <span class="preprocessor">#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l07714"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga316271d0147b22c6267fc563d4c24424"> 7714</a></span> <span class="preprocessor">#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l07715"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf27847573683f91dbfe387a2571b514f"> 7715</a></span> <span class="preprocessor">#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l07717"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1f362c1d228156c50639d79b9be99c9b"> 7717</a></span> <span class="preprocessor">#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) </span></div>
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<div class="line"><a name="l07718"></a><span class="lineno"> 7718</span> <span class="preprocessor">#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l07719"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9d57d7917c39bdc5309506e8c28b7d7"> 7719</a></span> <span class="preprocessor">#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) </span></div>
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<div class="line"><a name="l07721"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49f3e7998bca487f5354ef6f8dffbb21"> 7721</a></span> <span class="preprocessor">#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) </span></div>
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<div class="line"><a name="l07722"></a><span class="lineno"> 7722</span> <span class="preprocessor">#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) </span></div>
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<div class="line"><a name="l07724"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga693d7b533dd5a5a668bc13b4365b18dc"> 7724</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for SDIO_ARG register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07725"></a><span class="lineno"> 7725</span> <span class="preprocessor">#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) </span></div>
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<div class="line"><a name="l07727"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2d917a4fdc7442e270c2c727df78b819"> 7727</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for SDIO_CMD register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07728"></a><span class="lineno"> 7728</span> <span class="preprocessor">#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) </span></div>
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<div class="line"><a name="l07730"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf91b593b5681a68db5ff9fd11600c9c8"> 7730</a></span> <span class="preprocessor">#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) </span></div>
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<div class="line"><a name="l07731"></a><span class="lineno"> 7731</span> <span class="preprocessor">#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l07732"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5d617f0e08d697c3b263e6a79f417d0f"> 7732</a></span> <span class="preprocessor">#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l07734"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f5457b48feda0056466e5c380c44373"> 7734</a></span> <span class="preprocessor">#define SDIO_CMD_WAITINT ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l07735"></a><span class="lineno"> 7735</span> <span class="preprocessor">#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l07736"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b037f34e297f38d56b14d46d008ef58"> 7736</a></span> <span class="preprocessor">#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l07737"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4118c9200bae6732764f6c87a0962a9"> 7737</a></span> <span class="preprocessor">#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) </span></div>
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|
<div class="line"><a name="l07738"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga982f3fd09ce7e31709e0628b1fae86b8"> 7738</a></span> <span class="preprocessor">#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) </span></div>
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<div class="line"><a name="l07739"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad560080c3e7ab5aeafe151dafcc64368"> 7739</a></span> <span class="preprocessor">#define SDIO_CMD_NIEN ((uint16_t)0x2000) </span></div>
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<div class="line"><a name="l07740"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga905b78ecf464857e6501ef5fd5e6ef1b"> 7740</a></span> <span class="preprocessor">#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) </span></div>
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<div class="line"><a name="l07742"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga87422225274de986e7abe6b2a91a79c5"> 7742</a></span> <span class="preprocessor"></span><span class="comment">/***************** Bit definition for SDIO_RESPCMD register *****************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07743"></a><span class="lineno"> 7743</span> <span class="preprocessor">#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) </span></div>
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|
<div class="line"><a name="l07745"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27f9a6cbfd364bbb050b526ebc01d2d7"> 7745</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for SDIO_RESP0 register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07746"></a><span class="lineno"> 7746</span> <span class="preprocessor">#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) </span></div>
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<div class="line"><a name="l07748"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga56a55231f7a91cfd2cefaca0f6135cbc"> 7748</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for SDIO_RESP1 register ******************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l07749"></a><span class="lineno"> 7749</span> <span class="preprocessor">#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) </span></div>
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|
<div class="line"><a name="l07751"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1d20abddfc99835a2954eda5899f6db1"> 7751</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for SDIO_RESP2 register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07752"></a><span class="lineno"> 7752</span> <span class="preprocessor">#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) </span></div>
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|
<div class="line"><a name="l07754"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31a482ff36bde1df56ab603c864c4066"> 7754</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for SDIO_RESP3 register ******************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l07755"></a><span class="lineno"> 7755</span> <span class="preprocessor">#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) </span></div>
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|
<div class="line"><a name="l07757"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1075c96b5818b0500d5cce231ace89cf"> 7757</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for SDIO_RESP4 register ******************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l07758"></a><span class="lineno"> 7758</span> <span class="preprocessor">#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) </span></div>
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<div class="line"><a name="l07760"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga407ab1e46a80426602ab36e86457da26"> 7760</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for SDIO_DTIMER register *****************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07761"></a><span class="lineno"> 7761</span> <span class="preprocessor">#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) </span></div>
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|
<div class="line"><a name="l07763"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27e45eea9ce17b7251f10ea763180690"> 7763</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for SDIO_DLEN register *******************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l07764"></a><span class="lineno"> 7764</span> <span class="preprocessor">#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) </span></div>
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|
<div class="line"><a name="l07766"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d3b07bca9aec8ef5456ba9b73f13adb"> 7766</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for SDIO_DCTRL register ******************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l07767"></a><span class="lineno"> 7767</span> <span class="preprocessor">#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) </span></div>
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|
<div class="line"><a name="l07768"></a><span class="lineno"> 7768</span> <span class="preprocessor">#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) </span></div>
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|
<div class="line"><a name="l07769"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa03ff8fb9ff70e0a623a5c1f7aa2bc9a"> 7769</a></span> <span class="preprocessor">#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) </span></div>
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|
<div class="line"><a name="l07770"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga801fe27f7175a308d56776db19776c93"> 7770</a></span> <span class="preprocessor">#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) </span></div>
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|
<div class="line"><a name="l07772"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga03a2148910ae02dde7e4cd63e0f5e008"> 7772</a></span> <span class="preprocessor">#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) </span></div>
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|
<div class="line"><a name="l07773"></a><span class="lineno"> 7773</span> <span class="preprocessor">#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) </span></div>
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|
<div class="line"><a name="l07774"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga948072d8a6db53d0c377944523a4b15a"> 7774</a></span> <span class="preprocessor">#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) </span></div>
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|
<div class="line"><a name="l07775"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51e2cb99cf325bb32c8910204b1507db"> 7775</a></span> <span class="preprocessor">#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) </span></div>
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|
<div class="line"><a name="l07776"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0add3ad2b72a21e7f8d48da3ea0b3d0f"> 7776</a></span> <span class="preprocessor">#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) </span></div>
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|
<div class="line"><a name="l07778"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac2025aa63b595bfccc747b99caec8799"> 7778</a></span> <span class="preprocessor">#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) </span></div>
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|
<div class="line"><a name="l07779"></a><span class="lineno"> 7779</span> <span class="preprocessor">#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) </span></div>
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|
<div class="line"><a name="l07780"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe9600da3e751118d49ea14ce44e91b9"> 7780</a></span> <span class="preprocessor">#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) </span></div>
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|
<div class="line"><a name="l07781"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f1b5b6a32ce712fbb3767090b1b045e"> 7781</a></span> <span class="preprocessor">#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) </span></div>
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|
<div class="line"><a name="l07783"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa16b4c4037cf974162a591aea753fc21"> 7783</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for SDIO_DCOUNT register *****************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l07784"></a><span class="lineno"> 7784</span> <span class="preprocessor">#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) </span></div>
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|
<div class="line"><a name="l07786"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f8ab9dfe9d4f809b61fa2b7826adbde"> 7786</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for SDIO_STA register ********************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l07787"></a><span class="lineno"> 7787</span> <span class="preprocessor">#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) </span></div>
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|
<div class="line"><a name="l07788"></a><span class="lineno"> 7788</span> <span class="preprocessor">#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) </span></div>
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|
<div class="line"><a name="l07789"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad6dbe59c4bdd8b9a12b092cf84a9daef"> 7789</a></span> <span class="preprocessor">#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) </span></div>
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|
<div class="line"><a name="l07790"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga554d1f9986bf5c715dd6f27a6493ce31"> 7790</a></span> <span class="preprocessor">#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) </span></div>
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|
<div class="line"><a name="l07791"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae72c4f34bb3ccffeef1d7cdcb7415bdc"> 7791</a></span> <span class="preprocessor">#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) </span></div>
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|
<div class="line"><a name="l07792"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a2cad7ef3406a46ddba51f7ab5df94b"> 7792</a></span> <span class="preprocessor">#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) </span></div>
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|
<div class="line"><a name="l07793"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b9dcdb8b90d8266eb0c5a2be81238aa"> 7793</a></span> <span class="preprocessor">#define SDIO_STA_CMDREND ((uint32_t)0x00000040) </span></div>
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|
<div class="line"><a name="l07794"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad4b91289c9f6b773f928706ae8a5ddfc"> 7794</a></span> <span class="preprocessor">#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) </span></div>
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|
<div class="line"><a name="l07795"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga096f11117736a2252f1cd5c4cccdc6e6"> 7795</a></span> <span class="preprocessor">#define SDIO_STA_DATAEND ((uint32_t)0x00000100) </span></div>
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|
<div class="line"><a name="l07796"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa550641dc6aa942e1b524ad0e557a284"> 7796</a></span> <span class="preprocessor">#define SDIO_STA_STBITERR ((uint32_t)0x00000200) </span></div>
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|
<div class="line"><a name="l07797"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafe7e354a903b957943cf5b6bed4cdf6b"> 7797</a></span> <span class="preprocessor">#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) </span></div>
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|
<div class="line"><a name="l07798"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a9ef8e72604e9997da23601a2dd84a4"> 7798</a></span> <span class="preprocessor">#define SDIO_STA_CMDACT ((uint32_t)0x00000800) </span></div>
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|
<div class="line"><a name="l07799"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2fabf2c02cba6d4de1e90d8d1dc9793c"> 7799</a></span> <span class="preprocessor">#define SDIO_STA_TXACT ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l07800"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga99ccdac7a223635ee5b38a4bae8f30cc"> 7800</a></span> <span class="preprocessor">#define SDIO_STA_RXACT ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l07801"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga908feb4957f48390bc2fc0bde47ac784"> 7801</a></span> <span class="preprocessor">#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l07802"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad2f52b50765fa449dcfabc39b099796"> 7802</a></span> <span class="preprocessor">#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l07803"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62b9e38be5956dde69049154facc62fd"> 7803</a></span> <span class="preprocessor">#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l07804"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7916c47ee972376a0eaee584133ca36d"> 7804</a></span> <span class="preprocessor">#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l07805"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1497b46f9a906001dabb7d7604f6c05"> 7805</a></span> <span class="preprocessor">#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l07806"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga85f46f873ca5fe91a1e8206d157b9446"> 7806</a></span> <span class="preprocessor">#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l07807"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4624f95c5224c631f99571b5454acd86"> 7807</a></span> <span class="preprocessor">#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l07808"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44bf9f7321d65a3effd2df469a58a464"> 7808</a></span> <span class="preprocessor">#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l07809"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19b374518e813f7a1ac4aec3b24b7517"> 7809</a></span> <span class="preprocessor">#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l07810"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadcad9b8c0e3ccba1aa389d7713db6803"> 7810</a></span> <span class="preprocessor">#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l07812"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5d8ef3b4157374fd2b5fc8ed12b77a0c"> 7812</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for SDIO_ICR register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07813"></a><span class="lineno"> 7813</span> <span class="preprocessor">#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l07814"></a><span class="lineno"> 7814</span> <span class="preprocessor">#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) </span></div>
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|
<div class="line"><a name="l07815"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44708c45f675cf065f1c7fc9311d6e43"> 7815</a></span> <span class="preprocessor">#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l07816"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2cb6cde5f88a5d2b635a830dd401c4e0"> 7816</a></span> <span class="preprocessor">#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l07817"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4d128bee8a97ae9971d42f844d2e297"> 7817</a></span> <span class="preprocessor">#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l07818"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadcb64d3d07a5841ee9f18ff6bc75350b"> 7818</a></span> <span class="preprocessor">#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l07819"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9628d77973f35d628924172831b029f8"> 7819</a></span> <span class="preprocessor">#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l07820"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2513d040c7695b152b0b423ad6f5c81e"> 7820</a></span> <span class="preprocessor">#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l07821"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8fb5c67aef48d5ee27b60107d938a58f"> 7821</a></span> <span class="preprocessor">#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l07822"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa27fe45ef7461caf704186630b26a196"> 7822</a></span> <span class="preprocessor">#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l07823"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga527e1f9cd295845d5be9975cf26bae7e"> 7823</a></span> <span class="preprocessor">#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l07824"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae614b5ab8a8aecbc3c1ce74645cdc28c"> 7824</a></span> <span class="preprocessor">#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l07825"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadc5518c07e39dc1f91603737d1a7180b"> 7825</a></span> <span class="preprocessor">#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l07827"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6f1cebd40fd1eafb59635b284c5a3f34"> 7827</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for SDIO_MASK register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07828"></a><span class="lineno"> 7828</span> <span class="preprocessor">#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l07829"></a><span class="lineno"> 7829</span> <span class="preprocessor">#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l07830"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e24d12a6c9af91337cb391d3ba698f3"> 7830</a></span> <span class="preprocessor">#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l07831"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e2e106a1f7792f054c6cc1f60906a09"> 7831</a></span> <span class="preprocessor">#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) </span></div>
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<div class="line"><a name="l07832"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23f5a8c06e289522af0a679b08bdb014"> 7832</a></span> <span class="preprocessor">#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) </span></div>
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<div class="line"><a name="l07833"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7b4cc63338fe72abd76e5b399c47379b"> 7833</a></span> <span class="preprocessor">#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) </span></div>
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<div class="line"><a name="l07834"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1e02e525dc6ca1bb294b174e7391753d"> 7834</a></span> <span class="preprocessor">#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) </span></div>
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<div class="line"><a name="l07835"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga39f494cf2a6af6ced9eaeac751ea81e4"> 7835</a></span> <span class="preprocessor">#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) </span></div>
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<div class="line"><a name="l07836"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5fdedfc60a2019ff5f64533fcdd0c3f1"> 7836</a></span> <span class="preprocessor">#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l07837"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d541aea02974c03bd8a8426125c35ff"> 7837</a></span> <span class="preprocessor">#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) </span></div>
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<div class="line"><a name="l07838"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae6398bd3e8312eea3b986ab59b80b466"> 7838</a></span> <span class="preprocessor">#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l07839"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4194bed51eb4a951a58a5d4062ba978f"> 7839</a></span> <span class="preprocessor">#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l07840"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga947e5da36c9eeca0b48f3356067dff00"> 7840</a></span> <span class="preprocessor">#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) </span></div>
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<div class="line"><a name="l07841"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad63b504f02ea0b1e5ec48962799fde88"> 7841</a></span> <span class="preprocessor">#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) </span></div>
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<div class="line"><a name="l07842"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9bbfbc3f69ab77171eb1a0058783b1e0"> 7842</a></span> <span class="preprocessor">#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) </span></div>
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<div class="line"><a name="l07843"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9768c39a5d9d3c5519eb522c62a75eae"> 7843</a></span> <span class="preprocessor">#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) </span></div>
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<div class="line"><a name="l07844"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9cf28de8489fee023ea353df0e13fa7"> 7844</a></span> <span class="preprocessor">#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l07845"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga04d50028fc671494508aecb04e727102"> 7845</a></span> <span class="preprocessor">#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l07846"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga03a602b975ce16ef03083947aded0172"> 7846</a></span> <span class="preprocessor">#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l07847"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf18c4bdf8fa4ee85596a89de00158fbb"> 7847</a></span> <span class="preprocessor">#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) </span></div>
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<div class="line"><a name="l07848"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga11e1d67150fad62dc1ca7783f3a19372"> 7848</a></span> <span class="preprocessor">#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) </span></div>
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<div class="line"><a name="l07849"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbc23fa1c153a9e5216baeef7922e412"> 7849</a></span> <span class="preprocessor">#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) </span></div>
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<div class="line"><a name="l07850"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a1988093a6df087ebb8ff41a51962da"> 7850</a></span> <span class="preprocessor">#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) </span></div>
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<div class="line"><a name="l07851"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafa9da7d15902e6f94b79968a07250696"> 7851</a></span> <span class="preprocessor">#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) </span></div>
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<div class="line"><a name="l07853"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a19dd3039888ebdc40b2406be400749"> 7853</a></span> <span class="preprocessor"></span><span class="comment">/***************** Bit definition for SDIO_FIFOCNT register *****************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07854"></a><span class="lineno"> 7854</span> <span class="preprocessor">#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) </span></div>
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<div class="line"><a name="l07856"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa45f5e0a2be89267f79cad57f456f0a2"> 7856</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for SDIO_FIFO register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07857"></a><span class="lineno"> 7857</span> <span class="preprocessor">#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) </span></div>
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<div class="line"><a name="l07859"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5fc0d1e12c55398e2881fe917672da25"> 7859</a></span> <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07860"></a><span class="lineno"> 7860</span> <span class="comment">/* */</span></div>
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<div class="line"><a name="l07861"></a><span class="lineno"> 7861</span> <span class="comment">/* Serial Peripheral Interface */</span></div>
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<div class="line"><a name="l07862"></a><span class="lineno"> 7862</span> <span class="comment">/* */</span></div>
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<div class="line"><a name="l07863"></a><span class="lineno"> 7863</span> <span class="comment">/******************************************************************************/</span></div>
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<div class="line"><a name="l07864"></a><span class="lineno"> 7864</span> <span class="comment">/******************* Bit definition for SPI_CR1 register ********************/</span></div>
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<div class="line"><a name="l07865"></a><span class="lineno"> 7865</span> <span class="preprocessor">#define SPI_CR1_CPHA ((uint16_t)0x0001) </span></div>
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<div class="line"><a name="l07866"></a><span class="lineno"> 7866</span> <span class="preprocessor">#define SPI_CR1_CPOL ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l07867"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga97602d8ded14bbd2c1deadaf308755a3"> 7867</a></span> <span class="preprocessor">#define SPI_CR1_MSTR ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l07869"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5b3b6ae107fc37bf18e14506298d7a55"> 7869</a></span> <span class="preprocessor">#define SPI_CR1_BR ((uint16_t)0x0038) </span></div>
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<div class="line"><a name="l07870"></a><span class="lineno"> 7870</span> <span class="preprocessor">#define SPI_CR1_BR_0 ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l07871"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga261af22667719a32b3ce566c1e261936"> 7871</a></span> <span class="preprocessor">#define SPI_CR1_BR_1 ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l07872"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa364b123cf797044094cc229330ce321"> 7872</a></span> <span class="preprocessor">#define SPI_CR1_BR_2 ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l07874"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga28b823d564e9d90150bcc6744b4ed622"> 7874</a></span> <span class="preprocessor">#define SPI_CR1_SPE ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l07875"></a><span class="lineno"> 7875</span> <span class="preprocessor">#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l07876"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac5a646d978d3b98eb7c6a5d95d75c3f9"> 7876</a></span> <span class="preprocessor">#define SPI_CR1_SSI ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l07877"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab929e9d5ddbb66f229c501ab18d0e6e8"> 7877</a></span> <span class="preprocessor">#define SPI_CR1_SSM ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l07878"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5f154374b58c0234f82ea326cb303a1e"> 7878</a></span> <span class="preprocessor">#define SPI_CR1_RXONLY ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l07879"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0e236047e05106cf1ba7929766311382"> 7879</a></span> <span class="preprocessor">#define SPI_CR1_DFF ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l07880"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9ffecf774b84a8cdc11ab1f931791883"> 7880</a></span> <span class="preprocessor">#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) </span></div>
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<div class="line"><a name="l07881"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ffabea0de695a19198d906bf6a1d9fd"> 7881</a></span> <span class="preprocessor">#define SPI_CR1_CRCEN ((uint16_t)0x2000) </span></div>
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<div class="line"><a name="l07882"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga57072f13c2e54c12186ae8c5fdecb250"> 7882</a></span> <span class="preprocessor">#define SPI_CR1_BIDIOE ((uint16_t)0x4000) </span></div>
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<div class="line"><a name="l07883"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac9339b7c6466f09ad26c26b3bb81c51b"> 7883</a></span> <span class="preprocessor">#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) </span></div>
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<div class="line"><a name="l07885"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43608d3c2959fc9ca64398d61cbf484e"> 7885</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for SPI_CR2 register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07886"></a><span class="lineno"> 7886</span> <span class="preprocessor">#define SPI_CR2_RXDMAEN ((uint8_t)0x01) </span></div>
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<div class="line"><a name="l07887"></a><span class="lineno"> 7887</span> <span class="preprocessor">#define SPI_CR2_TXDMAEN ((uint8_t)0x02) </span></div>
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<div class="line"><a name="l07888"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf23c590d98279634af05550702a806da"> 7888</a></span> <span class="preprocessor">#define SPI_CR2_SSOE ((uint8_t)0x04) </span></div>
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<div class="line"><a name="l07889"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3eee671793983a3bd669c9173b2ce210"> 7889</a></span> <span class="preprocessor">#define SPI_CR2_ERRIE ((uint8_t)0x20) </span></div>
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<div class="line"><a name="l07890"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae94612b95395eff626f5f3d7d28352dd"> 7890</a></span> <span class="preprocessor">#define SPI_CR2_RXNEIE ((uint8_t)0x40) </span></div>
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<div class="line"><a name="l07891"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf18705567de7ab52a62e5ef3ba27418b"> 7891</a></span> <span class="preprocessor">#define SPI_CR2_TXEIE ((uint8_t)0x80) </span></div>
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<div class="line"><a name="l07893"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23f683a1252ccaf625cae1a978989b2c"> 7893</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for SPI_SR register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07894"></a><span class="lineno"> 7894</span> <span class="preprocessor">#define SPI_SR_RXNE ((uint8_t)0x01) </span></div>
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<div class="line"><a name="l07895"></a><span class="lineno"> 7895</span> <span class="preprocessor">#define SPI_SR_TXE ((uint8_t)0x02) </span></div>
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<div class="line"><a name="l07896"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40e14de547aa06864abcd4b0422d8b48"> 7896</a></span> <span class="preprocessor">#define SPI_SR_CHSIDE ((uint8_t)0x04) </span></div>
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<div class="line"><a name="l07897"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5bd5d21816947fcb25ccae7d3bf8eb2c"> 7897</a></span> <span class="preprocessor">#define SPI_SR_UDR ((uint8_t)0x08) </span></div>
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<div class="line"><a name="l07898"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81bd052f0b2e819ddd6bb16c2292a2de"> 7898</a></span> <span class="preprocessor">#define SPI_SR_CRCERR ((uint8_t)0x10) </span></div>
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<div class="line"><a name="l07899"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga13d3292e963499c0e9a36869909229e6"> 7899</a></span> <span class="preprocessor">#define SPI_SR_MODF ((uint8_t)0x20) </span></div>
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<div class="line"><a name="l07900"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69e543fa9584fd636032a3ee735f750b"> 7900</a></span> <span class="preprocessor">#define SPI_SR_OVR ((uint8_t)0x40) </span></div>
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<div class="line"><a name="l07901"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabaa043349833dc7b8138969c64f63adf"> 7901</a></span> <span class="preprocessor">#define SPI_SR_BSY ((uint8_t)0x80) </span></div>
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<div class="line"><a name="l07903"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa3498df67729ae048dc5f315ef7c16bf"> 7903</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for SPI_DR register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07904"></a><span class="lineno"> 7904</span> <span class="preprocessor">#define SPI_DR_DR ((uint16_t)0xFFFF) </span></div>
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<div class="line"><a name="l07906"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4da7d7f05a28d1aaa52ec557e55e1ad"> 7906</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for SPI_CRCPR register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07907"></a><span class="lineno"> 7907</span> <span class="preprocessor">#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) </span></div>
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<div class="line"><a name="l07909"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae968658ab837800723eafcc21af10247"> 7909</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for SPI_RXCRCR register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07910"></a><span class="lineno"> 7910</span> <span class="preprocessor">#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) </span></div>
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<div class="line"><a name="l07912"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3a01a578c2c7bb4e587a8f1610843181"> 7912</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for SPI_TXCRCR register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07913"></a><span class="lineno"> 7913</span> <span class="preprocessor">#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) </span></div>
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<div class="line"><a name="l07915"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c69dc721e89e40056999b64572dff09"> 7915</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for SPI_I2SCFGR register *****************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07916"></a><span class="lineno"> 7916</span> <span class="preprocessor">#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) </span></div>
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<div class="line"><a name="l07918"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9c362b3d703698a7891f032f6b29056f"> 7918</a></span> <span class="preprocessor">#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) </span></div>
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<div class="line"><a name="l07919"></a><span class="lineno"> 7919</span> <span class="preprocessor">#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l07920"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacc12f9d2003ab169a3f68e9d809f84ae"> 7920</a></span> <span class="preprocessor">#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l07922"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadf6e940d195fa1633cb1b23414f00412"> 7922</a></span> <span class="preprocessor">#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l07924"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c5be1f1c8b4689643e04cd5034e7f5f"> 7924</a></span> <span class="preprocessor">#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) </span></div>
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<div class="line"><a name="l07925"></a><span class="lineno"> 7925</span> <span class="preprocessor">#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l07926"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7a822a80be3a51524b42491248f8031f"> 7926</a></span> <span class="preprocessor">#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l07928"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0142a3667f59bce9bae80d31e88a124a"> 7928</a></span> <span class="preprocessor">#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l07930"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66a29efc32a31f903e89b7ddcd20857b"> 7930</a></span> <span class="preprocessor">#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) </span></div>
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<div class="line"><a name="l07931"></a><span class="lineno"> 7931</span> <span class="preprocessor">#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l07932"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf09fd11f6f97000266b30b015bf2cb68"> 7932</a></span> <span class="preprocessor">#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l07934"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga80c398b9e79fcc61a497f9d7dd910352"> 7934</a></span> <span class="preprocessor">#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l07935"></a><span class="lineno"> 7935</span> <span class="preprocessor">#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l07937"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae99763414b3c2f11fcfecb1f93eb6701"> 7937</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for SPI_I2SPR register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07938"></a><span class="lineno"> 7938</span> <span class="preprocessor">#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) </span></div>
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<div class="line"><a name="l07939"></a><span class="lineno"> 7939</span> <span class="preprocessor">#define SPI_I2SPR_ODD ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l07940"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga406ce88b2580a421f5b28bdbeb303543"> 7940</a></span> <span class="preprocessor">#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l07942"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25669c3686c0c577d2d371ac09200ff0"> 7942</a></span> <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l07943"></a><span class="lineno"> 7943</span> <span class="comment">/* */</span></div>
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|
<div class="line"><a name="l07944"></a><span class="lineno"> 7944</span> <span class="comment">/* SYSCFG */</span></div>
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<div class="line"><a name="l07945"></a><span class="lineno"> 7945</span> <span class="comment">/* */</span></div>
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|
<div class="line"><a name="l07946"></a><span class="lineno"> 7946</span> <span class="comment">/******************************************************************************/</span></div>
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|
<div class="line"><a name="l07947"></a><span class="lineno"> 7947</span> <span class="comment">/****************** Bit definition for SYSCFG_MEMRMP register ***************/</span> </div>
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<div class="line"><a name="l07948"></a><span class="lineno"> 7948</span> <span class="preprocessor">#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) </span></div>
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<div class="line"><a name="l07949"></a><span class="lineno"> 7949</span> <span class="preprocessor">#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l07950"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3c05039ec67573c00da29f58b914f258"> 7950</a></span> <span class="preprocessor">#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) </span></div>
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<div class="line"><a name="l07951"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga30d5f406535f94faea2e7f924d50201b"> 7951</a></span> <span class="preprocessor">#define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004) </span></div>
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<div class="line"><a name="l07953"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42eb2e54640311449d074871dc352819"> 7953</a></span> <span class="preprocessor">#define SYSCFG_MEMRMP_FB_MODE ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l07955"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabd7765535faf23de1a7038d97d44f014"> 7955</a></span> <span class="preprocessor">#define SYSCFG_MEMRMP_SWP_FMC ((uint32_t)0x00000C00) </span></div>
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<div class="line"><a name="l07956"></a><span class="lineno"> 7956</span> <span class="preprocessor">#define SYSCFG_MEMRMP_SWP_FMC_0 ((uint32_t)0x00000400) </span></div>
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<div class="line"><a name="l07957"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5fc9935984aa2d506eb568944cf4a45f"> 7957</a></span> <span class="preprocessor">#define SYSCFG_MEMRMP_SWP_FMC_1 ((uint32_t)0x00000800) </span></div>
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<div class="line"><a name="l07960"></a><span class="lineno"> 7960</span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for SYSCFG_PMC register ******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07961"></a><span class="lineno"> 7961</span> <span class="preprocessor">#define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) </span></div>
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<div class="line"><a name="l07962"></a><span class="lineno"> 7962</span> <span class="preprocessor">#define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) </span></div>
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<div class="line"><a name="l07963"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae44bae7ffc1cdebd5efbefbf679881df"> 7963</a></span> <span class="preprocessor">#define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) </span></div>
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<div class="line"><a name="l07964"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga69d0997434d521e50c9e7339d268482e"> 7964</a></span> <span class="preprocessor">#define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) </span></div>
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<div class="line"><a name="l07966"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa6d0af481dc291ff0419926ec1044bf5"> 7966</a></span> <span class="preprocessor">#define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) </span></div>
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|
<div class="line"><a name="l07967"></a><span class="lineno"> 7967</span> <span class="preprocessor"></span><span class="comment">/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l07968"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9d8ca35cdab213cb2400c49434de326"> 7968</a></span> <span class="preprocessor">#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL</span></div>
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|
<div class="line"><a name="l07969"></a><span class="lineno"> 7969</span> </div>
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|
<div class="line"><a name="l07970"></a><span class="lineno"> 7970</span> <span class="comment">/***************** Bit definition for SYSCFG_EXTICR1 register ***************/</span></div>
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|
<div class="line"><a name="l07971"></a><span class="lineno"> 7971</span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) </span></div>
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<div class="line"><a name="l07972"></a><span class="lineno"> 7972</span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) </span></div>
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<div class="line"><a name="l07973"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga75b70d07448c3037234bc2abb8e3d884"> 7973</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) </span></div>
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<div class="line"><a name="l07974"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7fc84838c77f799cb7e57d6e97c6c16d"> 7974</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) </span></div>
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<div class="line"><a name="l07978"></a><span class="lineno"> 7978</span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) </span></div>
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|
<div class="line"><a name="l07979"></a><span class="lineno"> 7979</span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) </span></div>
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|
<div class="line"><a name="l07980"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6de6aa8e32ae5cd07fd69e42e7226bd1"> 7980</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l07981"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf43c9ef6b61e39655cbe969967c79a69"> 7981</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) </span></div>
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<div class="line"><a name="l07982"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga861a4d7b48ffd93997267baaad12fd51"> 7982</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l07983"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6439042c8cd14f99fe3813cff47c0ee"> 7983</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) </span></div>
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<div class="line"><a name="l07984"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacb087e2ded8ac927ee9e1fc0234bfdef"> 7984</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) </span></div>
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<div class="line"><a name="l07985"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa897f1ac8311e57339eaf7813239eaf4"> 7985</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) </span></div>
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<div class="line"><a name="l07986"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga98b2d929e79e5cc2ee7961a75a0ab094"> 7986</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l07987"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga766d0bf3501e207b0baa066cf756688f"> 7987</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PJ ((uint16_t)0x0009) </span></div>
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<div class="line"><a name="l07988"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacfc4b69ff5f5d9b35bf01f26d6aa4e60"> 7988</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI0_PK ((uint16_t)0x000A) </span></div>
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<div class="line"><a name="l07993"></a><span class="lineno"> 7993</span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) </span></div>
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<div class="line"><a name="l07994"></a><span class="lineno"> 7994</span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l07995"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf4b78c30e4ef4fa441582eb3c102865d"> 7995</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l07996"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19a11fce288d19546c76257483e0dcb6"> 7996</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) </span></div>
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<div class="line"><a name="l07997"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae45a8c814b13fa19f157364dc715c08a"> 7997</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l07998"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93cb136eaf357affc4a28a8d423cabbb"> 7998</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) </span></div>
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<div class="line"><a name="l07999"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f5c3d1e914af78112179a13e9c736d6"> 7999</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) </span></div>
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<div class="line"><a name="l08000"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43ea410456aa31dfe6ec4889de62428b"> 8000</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) </span></div>
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<div class="line"><a name="l08001"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf9118efcafa89eeada012ff5ab98387d"> 8001</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l08002"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ac69d7f391e837d8e8adce27704d87d"> 8002</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PJ ((uint16_t)0x0090) </span></div>
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<div class="line"><a name="l08003"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga010784c7bdee3c742b48c500ee52e223"> 8003</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI1_PK ((uint16_t)0x00A0) </span></div>
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<div class="line"><a name="l08008"></a><span class="lineno"> 8008</span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) </span></div>
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<div class="line"><a name="l08009"></a><span class="lineno"> 8009</span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l08010"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4096f472e87e021f4d4c94457ddaf5f1"> 8010</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l08011"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8cd240d61fd8a9666621f0dee07a08e5"> 8011</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) </span></div>
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<div class="line"><a name="l08012"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga03ce7faaf56aa9efcc74af65619e275e"> 8012</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l08013"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc35fcdcc89b487fab2901e1f5a7f41b"> 8013</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) </span></div>
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<div class="line"><a name="l08014"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac3f2b7465d81745f7a772e7689a29618"> 8014</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) </span></div>
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<div class="line"><a name="l08015"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab538769f1da056b3f57fb984adeef252"> 8015</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700) </span></div>
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<div class="line"><a name="l08016"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe4f5fa56e98b42b64e894f7a9216e05"> 8016</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l08017"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada5ffab92c39cbfc695ce57a4e6177e5"> 8017</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PJ ((uint16_t)0x0900) </span></div>
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<div class="line"><a name="l08018"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga00bc1224b7bfd46dcec32676a601de51"> 8018</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI2_PK ((uint16_t)0x0A00) </span></div>
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<div class="line"><a name="l08023"></a><span class="lineno"> 8023</span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) </span></div>
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<div class="line"><a name="l08024"></a><span class="lineno"> 8024</span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) </span></div>
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<div class="line"><a name="l08025"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga45ed24773c389f4477944c2c43d106c0"> 8025</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) </span></div>
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<div class="line"><a name="l08026"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga652183838bb096717551bf8a1917c257"> 8026</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) </span></div>
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<div class="line"><a name="l08027"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacb1809e5b8a9ebc4b1cbc8967d985929"> 8027</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) </span></div>
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<div class="line"><a name="l08028"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga205440ffa174509d57c2b6a1814f8202"> 8028</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) </span></div>
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<div class="line"><a name="l08029"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab2b33beb6294fd7a257f0f3a36e0dcda"> 8029</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) </span></div>
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<div class="line"><a name="l08030"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40240ee616b6e06ecd8dabe9d8e56e71"> 8030</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000) </span></div>
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<div class="line"><a name="l08031"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa73420dbafb7f20f16c350a12b0a0f5"> 8031</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000) </span></div>
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<div class="line"><a name="l08032"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae49def2961bf528448a4fbb4aa9c9d94"> 8032</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PJ ((uint16_t)0x9000) </span></div>
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<div class="line"><a name="l08033"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga337e37f58e8710ea8305a16c08e390b9"> 8033</a></span> <span class="preprocessor">#define SYSCFG_EXTICR1_EXTI3_PK ((uint16_t)0xA000) </span></div>
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<div class="line"><a name="l08035"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c1bc7d66cef7e2c38001e533b5a2cb3"> 8035</a></span> <span class="preprocessor"></span><span class="comment">/***************** Bit definition for SYSCFG_EXTICR2 register ***************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08036"></a><span class="lineno"> 8036</span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) </span></div>
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<div class="line"><a name="l08037"></a><span class="lineno"> 8037</span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) </span></div>
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<div class="line"><a name="l08038"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad2a57b4872977812e60d521268190e1e"> 8038</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) </span></div>
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<div class="line"><a name="l08039"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6682a1b97b04c5c33085ffd2827ccd17"> 8039</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) </span></div>
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<div class="line"><a name="l08043"></a><span class="lineno"> 8043</span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) </span></div>
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<div class="line"><a name="l08044"></a><span class="lineno"> 8044</span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) </span></div>
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<div class="line"><a name="l08045"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51147f1747daf48dbcfad03285ae8889"> 8045</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l08046"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga917aeb0df688d6b34785085fc85d9e47"> 8046</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) </span></div>
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<div class="line"><a name="l08047"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga14ac312beeb19d3bb34a552546477613"> 8047</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l08048"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec62164e18d1b525e8272169b1efe642"> 8048</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) </span></div>
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<div class="line"><a name="l08049"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac1d2292b6a856a8a71d82f595b580b9b"> 8049</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006) </span></div>
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<div class="line"><a name="l08050"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0adc3c72bddc65977e3ef56df74ed40e"> 8050</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007) </span></div>
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<div class="line"><a name="l08051"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad5aad8ed8589e28677332ea0b200617b"> 8051</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l08052"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga339f8994c317190a387a96b857aa79d0"> 8052</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PJ ((uint16_t)0x0009) </span></div>
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<div class="line"><a name="l08053"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaad36a509bf6deabd5446a07c20964f83"> 8053</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI4_PK ((uint16_t)0x000A) </span></div>
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<div class="line"><a name="l08058"></a><span class="lineno"> 8058</span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) </span></div>
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<div class="line"><a name="l08059"></a><span class="lineno"> 8059</span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l08060"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafb9581c515a4bdf1ed88fe96d8c24794"> 8060</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l08061"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90a3f610234dfa13f56e72c76a12be74"> 8061</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) </span></div>
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<div class="line"><a name="l08062"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga33b6bdc1b4bfeda0d4034dc67f1a6046"> 8062</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l08063"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0eea392f1530c7cb794a63d04e268a70"> 8063</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) </span></div>
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<div class="line"><a name="l08064"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8a4e6644d0144bfb0f913cf20eaf2f8e"> 8064</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060) </span></div>
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<div class="line"><a name="l08065"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga740e27c5bead2c914a134ac4ed4d05b3"> 8065</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070) </span></div>
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<div class="line"><a name="l08066"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d78839e577ab90090abcdcff88e18c8"> 8066</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l08067"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a06842a64138b5010186d980cb594f9"> 8067</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PJ ((uint16_t)0x0090) </span></div>
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<div class="line"><a name="l08068"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f3c4ebe4d750f89465acd067ab0ee30"> 8068</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI5_PK ((uint16_t)0x00A0) </span></div>
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<div class="line"><a name="l08073"></a><span class="lineno"> 8073</span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) </span></div>
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<div class="line"><a name="l08074"></a><span class="lineno"> 8074</span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l08075"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e87c78fb6dfde7c8b7f81fe3b65aae9"> 8075</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l08076"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6528de8e4ca8741e86ae254e1d6b2a70"> 8076</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) </span></div>
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<div class="line"><a name="l08077"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga53d8745705d5eb84c70a8554f61d59ac"> 8077</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l08078"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26c97cdece451441e49120e754020cdc"> 8078</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) </span></div>
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<div class="line"><a name="l08079"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga804218f2dd83c72e672143ec4f283ad3"> 8079</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600) </span></div>
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<div class="line"><a name="l08080"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0d36de53e52c8a4c7991513fec326df6"> 8080</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700) </span></div>
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<div class="line"><a name="l08081"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga278997204184bfe7c951c1da327e6fb5"> 8081</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l08082"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga283486dccd660fbf830e8c44b0161a63"> 8082</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PJ ((uint16_t)0x0900) </span></div>
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<div class="line"><a name="l08083"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4222e7d9ed672ea2de3a038c23f9566b"> 8083</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI6_PK ((uint16_t)0x0A00) </span></div>
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<div class="line"><a name="l08088"></a><span class="lineno"> 8088</span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) </span></div>
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<div class="line"><a name="l08089"></a><span class="lineno"> 8089</span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) </span></div>
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<div class="line"><a name="l08090"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f1bfd3af524288b6ce54d7f9aef410a"> 8090</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) </span></div>
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<div class="line"><a name="l08091"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab18d324986b18858f901febbcc2a57b7"> 8091</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) </span></div>
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<div class="line"><a name="l08092"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae9f53618d9cf13af2b2ecf191da8595a"> 8092</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) </span></div>
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<div class="line"><a name="l08093"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae38aa3b76227bb8e9d8cedc31c023f63"> 8093</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) </span></div>
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<div class="line"><a name="l08094"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga90d097c1b5cbb62dc86327604907dcd4"> 8094</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000) </span></div>
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<div class="line"><a name="l08095"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf2c3a661be3569fffe11515e37de1e4"> 8095</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000) </span></div>
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<div class="line"><a name="l08096"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga987bc0488e57b14b0a98e4952df2b539"> 8096</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000) </span></div>
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<div class="line"><a name="l08097"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab0ce56e15f4eb86a3e262deaa845cb99"> 8097</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PJ ((uint16_t)0x9000) </span></div>
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<div class="line"><a name="l08098"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae68ca6758cf36232dd5ac63afae97cbc"> 8098</a></span> <span class="preprocessor">#define SYSCFG_EXTICR2_EXTI7_PK ((uint16_t)0xA000) </span></div>
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<div class="line"><a name="l08100"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac51ba73786abb388c733ee96ee024de7"> 8100</a></span> <span class="preprocessor"></span><span class="comment">/***************** Bit definition for SYSCFG_EXTICR3 register ***************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08101"></a><span class="lineno"> 8101</span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) </span></div>
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<div class="line"><a name="l08102"></a><span class="lineno"> 8102</span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) </span></div>
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<div class="line"><a name="l08103"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf2a656b18cc728e38acb72cf8d7e7935"> 8103</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) </span></div>
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<div class="line"><a name="l08104"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga002462e4c233adc6dd502de726994575"> 8104</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) </span></div>
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<div class="line"><a name="l08109"></a><span class="lineno"> 8109</span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) </span></div>
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<div class="line"><a name="l08110"></a><span class="lineno"> 8110</span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) </span></div>
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<div class="line"><a name="l08111"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1c6843a871f1a06ca25c0de50048b10"> 8111</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l08112"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4818dc7bffc8dfc2acc48995a62e66c5"> 8112</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) </span></div>
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<div class="line"><a name="l08113"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaba0d34ff57632d7753981404cef548e2"> 8113</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l08114"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa15260ba354dee354f0a71e7913009c3"> 8114</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) </span></div>
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<div class="line"><a name="l08115"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga185287204b8cead31d3760f65c5ca19d"> 8115</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) </span></div>
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<div class="line"><a name="l08116"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga425e41001af4b205b8fbfba723572a81"> 8116</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007) </span></div>
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<div class="line"><a name="l08117"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2ecc7a12103b805da045093eb626614d"> 8117</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l08118"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0bf3fc7a2e35b7cbb9f08f2e3b06a3c4"> 8118</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI8_PJ ((uint16_t)0x0009) </span></div>
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<div class="line"><a name="l08123"></a><span class="lineno"> 8123</span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) </span></div>
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<div class="line"><a name="l08124"></a><span class="lineno"> 8124</span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l08125"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93e284e59c4ff887b2e79851ac0a81c4"> 8125</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l08126"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa9271cbc1ed09774a5fef4b379cab260"> 8126</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) </span></div>
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<div class="line"><a name="l08127"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1cc355176941881870c620c0837cab48"> 8127</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l08128"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga75af3c7a94cfc78361c94b054f9fe064"> 8128</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) </span></div>
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<div class="line"><a name="l08129"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafce176ef4b389251dadb98d9f59f8fe6"> 8129</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) </span></div>
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<div class="line"><a name="l08130"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76ef2422b4d021d0cc038cb6325ed311"> 8130</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070) </span></div>
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<div class="line"><a name="l08131"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae1b37bf746ccfe0750aebd28cfa52a0c"> 8131</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l08132"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31fdedc4a90328881fe8817f4eef61b2"> 8132</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI9_PJ ((uint16_t)0x0090) </span></div>
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<div class="line"><a name="l08137"></a><span class="lineno"> 8137</span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) </span></div>
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<div class="line"><a name="l08138"></a><span class="lineno"> 8138</span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l08139"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25acdbb9e916c440c41a060d861130ee"> 8139</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l08140"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab8d9aec4349bf38a4a9753b267b7de7e"> 8140</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) </span></div>
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<div class="line"><a name="l08141"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga62d2b81d49e30ab4fe96572be5da8484"> 8141</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l08142"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaab3553c540cd836d465824939c2e3b79"> 8142</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) </span></div>
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<div class="line"><a name="l08143"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabde568ef1c8f4bfaf18954e8ee0716a9"> 8143</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) </span></div>
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<div class="line"><a name="l08144"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga09ed841a11367cda67c7a416ed6d9b99"> 8144</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700) </span></div>
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<div class="line"><a name="l08145"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6dff840a6986b440e7633a3671ce57cc"> 8145</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l08146"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga791e7d2bd23ae969540e5509c6718255"> 8146</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI10_PJ ((uint16_t)0x0900) </span></div>
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<div class="line"><a name="l08151"></a><span class="lineno"> 8151</span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) </span></div>
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<div class="line"><a name="l08152"></a><span class="lineno"> 8152</span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) </span></div>
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<div class="line"><a name="l08153"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ca8a85d4512677eff6ed2aac897a366"> 8153</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) </span></div>
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<div class="line"><a name="l08154"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaedb3a8cc6b1763e303986553c0e4e7f8"> 8154</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) </span></div>
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<div class="line"><a name="l08155"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b01c8ba6cb27899a4f5fa494bf2b3f5"> 8155</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) </span></div>
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<div class="line"><a name="l08156"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a69d636cda0352da0982c54f582787d"> 8156</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) </span></div>
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<div class="line"><a name="l08157"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga44affe06868a0490f8d0cbbba51ff412"> 8157</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) </span></div>
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<div class="line"><a name="l08158"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga66fb050835077047b576b3a510700d64"> 8158</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000) </span></div>
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<div class="line"><a name="l08159"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf7b66390eeb4a8d50ebb7e87e2f281b3"> 8159</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000) </span></div>
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<div class="line"><a name="l08160"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa58cfe5d03072c259582ba8fefa322bf"> 8160</a></span> <span class="preprocessor">#define SYSCFG_EXTICR3_EXTI11_PJ ((uint16_t)0x9000) </span></div>
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<div class="line"><a name="l08162"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8543b917331198709a24b7187dfb754f"> 8162</a></span> <span class="preprocessor"></span><span class="comment">/***************** Bit definition for SYSCFG_EXTICR4 register ***************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08163"></a><span class="lineno"> 8163</span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) </span></div>
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<div class="line"><a name="l08164"></a><span class="lineno"> 8164</span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) </span></div>
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<div class="line"><a name="l08165"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d4b31f4a75d935b6a52afe6a16463d1"> 8165</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) </span></div>
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<div class="line"><a name="l08166"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f04cda5bfe876431d5ad864302d7fa1"> 8166</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) </span></div>
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<div class="line"><a name="l08170"></a><span class="lineno"> 8170</span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) </span></div>
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<div class="line"><a name="l08171"></a><span class="lineno"> 8171</span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) </span></div>
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<div class="line"><a name="l08172"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ceaa63866465faa8145ce0c5d9a44d0"> 8172</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l08173"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad8b00a462533a83c75c588340a2fa710"> 8173</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) </span></div>
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<div class="line"><a name="l08174"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d27668b1fa6b1accde06aa144faa970"> 8174</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l08175"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa46ddd43a361d82abcb3cb7779ac74ff"> 8175</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) </span></div>
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<div class="line"><a name="l08176"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga102ee111e27fd67228c169836dd0849e"> 8176</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) </span></div>
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<div class="line"><a name="l08177"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad9785209e7e13fcf9c4f82d57bae0837"> 8177</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_PH ((uint16_t)0x0007) </span></div>
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<div class="line"><a name="l08178"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c78af5f130089bec32d6f782288765c"> 8178</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_PI ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l08179"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0b7baa5b844b78d3e05326607b2910a6"> 8179</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI12_PJ ((uint16_t)0x0009) </span></div>
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<div class="line"><a name="l08184"></a><span class="lineno"> 8184</span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) </span></div>
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<div class="line"><a name="l08185"></a><span class="lineno"> 8185</span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l08186"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0514aaa894c9be44ba47c1346756f90b"> 8186</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l08187"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga34e6776e3ebfecc9e78c5aec77c48eff"> 8187</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) </span></div>
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<div class="line"><a name="l08188"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c7833d4e3c6b7f3878f62a200a6ab14"> 8188</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l08189"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabed530f628b3c37281f7a583af1cdb3c"> 8189</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) </span></div>
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<div class="line"><a name="l08190"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7dc5424bf39509a989464a81ec0714da"> 8190</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) </span></div>
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<div class="line"><a name="l08191"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaf4c995587d7bae6436e6793b8214627"> 8191</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_PH ((uint16_t)0x0070) </span></div>
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<div class="line"><a name="l08192"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4dedb6adbf49c40e5a15ad2afc471155"> 8192</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_PI ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l08193"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga61214ec3d87450f54b959aab49ea65b6"> 8193</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI13_PJ ((uint16_t)0x0009) </span></div>
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<div class="line"><a name="l08198"></a><span class="lineno"> 8198</span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) </span></div>
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<div class="line"><a name="l08199"></a><span class="lineno"> 8199</span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l08200"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ad140a68e3e4e0406a182a504679ea9"> 8200</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l08201"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae5c1b8a0f2b4f79bd868bbb2b4eff617"> 8201</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) </span></div>
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<div class="line"><a name="l08202"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8ca668cdd447acb1740566f46de5eb19"> 8202</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l08203"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f20b2bfa9dc8b57a987c127c6dfa6fe"> 8203</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) </span></div>
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<div class="line"><a name="l08204"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4c13c49f6d93865ba05361cd86fddabf"> 8204</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) </span></div>
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<div class="line"><a name="l08205"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9df1ee6f60db93301acaa9220a591da9"> 8205</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_PH ((uint16_t)0x0700) </span></div>
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<div class="line"><a name="l08206"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae8ae4d091bb2c7148188ef430734020a"> 8206</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_PI ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l08207"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga07b38f38fa3957c6bc45ef4282b58377"> 8207</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI14_PJ ((uint16_t)0x0900) </span></div>
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<div class="line"><a name="l08212"></a><span class="lineno"> 8212</span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) </span></div>
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<div class="line"><a name="l08213"></a><span class="lineno"> 8213</span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) </span></div>
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<div class="line"><a name="l08214"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2f28920677dd99f9132ed28f7b1d5e2"> 8214</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) </span></div>
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<div class="line"><a name="l08215"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga412f44d6a8f8f60420d7e7f8b5635e09"> 8215</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) </span></div>
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<div class="line"><a name="l08216"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga49778592caef3a176ee82c9b83e25148"> 8216</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) </span></div>
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<div class="line"><a name="l08217"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac23e07d92a68cf7f8c3e58b479638885"> 8217</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) </span></div>
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<div class="line"><a name="l08218"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaefd64bc0ea005d03068f2e9b8f425944"> 8218</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) </span></div>
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<div class="line"><a name="l08219"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e88d51ebabe9f70e5b7c2ad60899d54"> 8219</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_PH ((uint16_t)0x7000) </span></div>
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<div class="line"><a name="l08220"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga51d341c45e98ccbd82bf7003bfa56e6b"> 8220</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_PI ((uint16_t)0x8000) </span></div>
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<div class="line"><a name="l08221"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga701c1065ec215a34329017bae69046c3"> 8221</a></span> <span class="preprocessor">#define SYSCFG_EXTICR4_EXTI15_PJ ((uint16_t)0x9000) </span></div>
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<div class="line"><a name="l08223"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaffa9c5da4a6103fc4e5bded02646de74"> 8223</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for SYSCFG_CMPCR register ****************/</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l08224"></a><span class="lineno"> 8224</span> <span class="preprocessor">#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) </span></div>
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<div class="line"><a name="l08225"></a><span class="lineno"> 8225</span> <span class="preprocessor">#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) </span></div>
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<div class="line"><a name="l08227"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae16bcca9b727e68f11467b6b3dad6215"> 8227</a></span> <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08228"></a><span class="lineno"> 8228</span> <span class="comment">/* */</span></div>
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<div class="line"><a name="l08229"></a><span class="lineno"> 8229</span> <span class="comment">/* TIM */</span></div>
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<div class="line"><a name="l08230"></a><span class="lineno"> 8230</span> <span class="comment">/* */</span></div>
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<div class="line"><a name="l08231"></a><span class="lineno"> 8231</span> <span class="comment">/******************************************************************************/</span></div>
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<div class="line"><a name="l08232"></a><span class="lineno"> 8232</span> <span class="comment">/******************* Bit definition for TIM_CR1 register ********************/</span></div>
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<div class="line"><a name="l08233"></a><span class="lineno"> 8233</span> <span class="preprocessor">#define TIM_CR1_CEN ((uint16_t)0x0001) </span></div>
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<div class="line"><a name="l08234"></a><span class="lineno"> 8234</span> <span class="preprocessor">#define TIM_CR1_UDIS ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l08235"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga93d86355e5e3b399ed45e1ca83abed2a"> 8235</a></span> <span class="preprocessor">#define TIM_CR1_URS ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l08236"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4f2a9f0cf7b60e3c623af451f141f3c"> 8236</a></span> <span class="preprocessor">#define TIM_CR1_OPM ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l08237"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga06c997c2c23e8bef7ca07579762c113b"> 8237</a></span> <span class="preprocessor">#define TIM_CR1_DIR ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l08239"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacea10770904af189f3aaeb97b45722aa"> 8239</a></span> <span class="preprocessor">#define TIM_CR1_CMS ((uint16_t)0x0060) </span></div>
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<div class="line"><a name="l08240"></a><span class="lineno"> 8240</span> <span class="preprocessor">#define TIM_CR1_CMS_0 ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l08241"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga352b3c389bde13dd6049de0afdd874f1"> 8241</a></span> <span class="preprocessor">#define TIM_CR1_CMS_1 ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l08243"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3ee4adcde3c001d3b97d2eae1730ea9"> 8243</a></span> <span class="preprocessor">#define TIM_CR1_ARPE ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l08245"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a3ad409f6b147cdcbafbfe29102f3fd"> 8245</a></span> <span class="preprocessor">#define TIM_CR1_CKD ((uint16_t)0x0300) </span></div>
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<div class="line"><a name="l08246"></a><span class="lineno"> 8246</span> <span class="preprocessor">#define TIM_CR1_CKD_0 ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l08247"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacacc4ff7e5b75fd2e4e6b672ccd33a72"> 8247</a></span> <span class="preprocessor">#define TIM_CR1_CKD_1 ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l08249"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ff2d6c2c350e8b719a8ad49c9a6bcbe"> 8249</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for TIM_CR2 register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08250"></a><span class="lineno"> 8250</span> <span class="preprocessor">#define TIM_CR2_CCPC ((uint16_t)0x0001) </span></div>
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<div class="line"><a name="l08251"></a><span class="lineno"> 8251</span> <span class="preprocessor">#define TIM_CR2_CCUS ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l08252"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaae22c9c1197107d6fa629f419a29541e"> 8252</a></span> <span class="preprocessor">#define TIM_CR2_CCDS ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l08254"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade656832d3ec303a2a7a422638dd560e"> 8254</a></span> <span class="preprocessor">#define TIM_CR2_MMS ((uint16_t)0x0070) </span></div>
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<div class="line"><a name="l08255"></a><span class="lineno"> 8255</span> <span class="preprocessor">#define TIM_CR2_MMS_0 ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l08256"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa6987d980e5c4c71c7d0faa1eb97a45"> 8256</a></span> <span class="preprocessor">#define TIM_CR2_MMS_1 ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l08257"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf3e55308e84106d6501201e66bd46ab6"> 8257</a></span> <span class="preprocessor">#define TIM_CR2_MMS_2 ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l08259"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacb74a815afdd856d51cfcf1ddf3fce6a"> 8259</a></span> <span class="preprocessor">#define TIM_CR2_TI1S ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l08260"></a><span class="lineno"> 8260</span> <span class="preprocessor">#define TIM_CR2_OIS1 ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l08261"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad07504497b70af628fa1aee8fe7ef63c"> 8261</a></span> <span class="preprocessor">#define TIM_CR2_OIS1N ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l08262"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31b26bf058f88d771c33aff85ec89358"> 8262</a></span> <span class="preprocessor">#define TIM_CR2_OIS2 ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l08263"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae61f8d54923999fffb6db381e81f2b69"> 8263</a></span> <span class="preprocessor">#define TIM_CR2_OIS2N ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l08264"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga61467648a433bd887683b9a4760021fa"> 8264</a></span> <span class="preprocessor">#define TIM_CR2_OIS3 ((uint16_t)0x1000) </span></div>
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<div class="line"><a name="l08265"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga769146db660b832f3ef26f892b567bd4"> 8265</a></span> <span class="preprocessor">#define TIM_CR2_OIS3N ((uint16_t)0x2000) </span></div>
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<div class="line"><a name="l08266"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad974d7c91edf6f1bd47e892b3b6f7565"> 8266</a></span> <span class="preprocessor">#define TIM_CR2_OIS4 ((uint16_t)0x4000) </span></div>
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<div class="line"><a name="l08268"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad644f2f4b26e46587abedc8d3164e56e"> 8268</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for TIM_SMCR register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08269"></a><span class="lineno"> 8269</span> <span class="preprocessor">#define TIM_SMCR_SMS ((uint16_t)0x0007) </span></div>
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<div class="line"><a name="l08270"></a><span class="lineno"> 8270</span> <span class="preprocessor">#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) </span></div>
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<div class="line"><a name="l08271"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae92349731a6107e0f3a251b44a67c7ea"> 8271</a></span> <span class="preprocessor">#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l08272"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d1ebece401aeb12abd466d2eafa78b2"> 8272</a></span> <span class="preprocessor">#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l08274"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga63847fc3c71f582403e6301b1229c3ed"> 8274</a></span> <span class="preprocessor">#define TIM_SMCR_TS ((uint16_t)0x0070) </span></div>
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<div class="line"><a name="l08275"></a><span class="lineno"> 8275</span> <span class="preprocessor">#define TIM_SMCR_TS_0 ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l08276"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8680e719bca2b672d850504220ae51fc"> 8276</a></span> <span class="preprocessor">#define TIM_SMCR_TS_1 ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l08277"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8d1f040f9259acb3c2fba7b0c7eb3d96"> 8277</a></span> <span class="preprocessor">#define TIM_SMCR_TS_2 ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l08279"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacf0dbaf4a2ec8759f283f82a958ef6a8"> 8279</a></span> <span class="preprocessor">#define TIM_SMCR_MSM ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l08281"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52101db4ca2c7b3003f1b16a49b2032c"> 8281</a></span> <span class="preprocessor">#define TIM_SMCR_ETF ((uint16_t)0x0F00) </span></div>
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<div class="line"><a name="l08282"></a><span class="lineno"> 8282</span> <span class="preprocessor">#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l08283"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae2ed8b32d9eb8eea251bd1dac4f34668"> 8283</a></span> <span class="preprocessor">#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l08284"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga43745c2894cfc1e5ee619ac85d8d5a62"> 8284</a></span> <span class="preprocessor">#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l08285"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga661e6cce23553cf0ad3a60d8573b9a2c"> 8285</a></span> <span class="preprocessor">#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l08287"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6082700946fc61a6f9d6209e258fcc14"> 8287</a></span> <span class="preprocessor">#define TIM_SMCR_ETPS ((uint16_t)0x3000) </span></div>
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<div class="line"><a name="l08288"></a><span class="lineno"> 8288</span> <span class="preprocessor">#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) </span></div>
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<div class="line"><a name="l08289"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ebb9e631876435e276211d88e797386"> 8289</a></span> <span class="preprocessor">#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) </span></div>
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<div class="line"><a name="l08291"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf12f04862dbc92ca238d1518b27b16b"> 8291</a></span> <span class="preprocessor">#define TIM_SMCR_ECE ((uint16_t)0x4000) </span></div>
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<div class="line"><a name="l08292"></a><span class="lineno"> 8292</span> <span class="preprocessor">#define TIM_SMCR_ETP ((uint16_t)0x8000) </span></div>
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<div class="line"><a name="l08294"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2a5f335c3d7a4f82d1e91dc1511e3322"> 8294</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for TIM_DIER register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08295"></a><span class="lineno"> 8295</span> <span class="preprocessor">#define TIM_DIER_UIE ((uint16_t)0x0001) </span></div>
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<div class="line"><a name="l08296"></a><span class="lineno"> 8296</span> <span class="preprocessor">#define TIM_DIER_CC1IE ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l08297"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5c6d3e0495e6c06da4bdd0ad8995a32b"> 8297</a></span> <span class="preprocessor">#define TIM_DIER_CC2IE ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l08298"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1ba7f7ca97eeaf6cc23cd6765c6bf678"> 8298</a></span> <span class="preprocessor">#define TIM_DIER_CC3IE ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l08299"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga757c59b690770adebf33e20d3d9dec15"> 8299</a></span> <span class="preprocessor">#define TIM_DIER_CC4IE ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l08300"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4edf003f04bcf250bddf5ed284201c2e"> 8300</a></span> <span class="preprocessor">#define TIM_DIER_COMIE ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l08301"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ad0f562a014572793b49fe87184338b"> 8301</a></span> <span class="preprocessor">#define TIM_DIER_TIE ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l08302"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade8a374e04740aac1ece248b868522fe"> 8302</a></span> <span class="preprocessor">#define TIM_DIER_BIE ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l08303"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa755fef2c4e96c63f2ea1cd9a32f956a"> 8303</a></span> <span class="preprocessor">#define TIM_DIER_UDE ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l08304"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1fcb0d6d9fb7486a5901032fd81aef6a"> 8304</a></span> <span class="preprocessor">#define TIM_DIER_CC1DE ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l08305"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9f47792b1c2f123464a2955f445c811"> 8305</a></span> <span class="preprocessor">#define TIM_DIER_CC2DE ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l08306"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae181bb16ec916aba8ba86f58f745fdfd"> 8306</a></span> <span class="preprocessor">#define TIM_DIER_CC3DE ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l08307"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga58f97064991095b28c91028ca3cca28e"> 8307</a></span> <span class="preprocessor">#define TIM_DIER_CC4DE ((uint16_t)0x1000) </span></div>
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<div class="line"><a name="l08308"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1567bff5dc0564b26a8b3cff1f0fe0a4"> 8308</a></span> <span class="preprocessor">#define TIM_DIER_COMDE ((uint16_t)0x2000) </span></div>
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<div class="line"><a name="l08309"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaba034412c54fa07024e516492748614"> 8309</a></span> <span class="preprocessor">#define TIM_DIER_TDE ((uint16_t)0x4000) </span></div>
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<div class="line"><a name="l08311"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5a752d4295f100708df9b8be5a7f439d"> 8311</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for TIM_SR register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08312"></a><span class="lineno"> 8312</span> <span class="preprocessor">#define TIM_SR_UIF ((uint16_t)0x0001) </span></div>
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<div class="line"><a name="l08313"></a><span class="lineno"> 8313</span> <span class="preprocessor">#define TIM_SR_CC1IF ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l08314"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8c03fabc10654d2a3f76ea40fcdbde6"> 8314</a></span> <span class="preprocessor">#define TIM_SR_CC2IF ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l08315"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga449a61344a97608d85384c29f003c0e9"> 8315</a></span> <span class="preprocessor">#define TIM_SR_CC3IF ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l08316"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25a48bf099467169aa50464fbf462bd8"> 8316</a></span> <span class="preprocessor">#define TIM_SR_CC4IF ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l08317"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3cf234a1059c0a04799e88382cdc0f2"> 8317</a></span> <span class="preprocessor">#define TIM_SR_COMIF ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l08318"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacade8a06303bf216bfb03140c7e16cac"> 8318</a></span> <span class="preprocessor">#define TIM_SR_TIF ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l08319"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91775c029171c4585e9cca6ebf1cd57a"> 8319</a></span> <span class="preprocessor">#define TIM_SR_BIF ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l08320"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c8b16f3ced6ec03e9001276b134846e"> 8320</a></span> <span class="preprocessor">#define TIM_SR_CC1OF ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l08321"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6d52cd5a57c9a26b0d993c93d9875097"> 8321</a></span> <span class="preprocessor">#define TIM_SR_CC2OF ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l08322"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga819c4b27f8fa99b537c4407521f9780c"> 8322</a></span> <span class="preprocessor">#define TIM_SR_CC3OF ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l08323"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3b7798da5863d559ea9a642af6658050"> 8323</a></span> <span class="preprocessor">#define TIM_SR_CC4OF ((uint16_t)0x1000) </span></div>
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<div class="line"><a name="l08325"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga81ba979e8309b66808e06e4de34bc740"> 8325</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for TIM_EGR register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08326"></a><span class="lineno"> 8326</span> <span class="preprocessor">#define TIM_EGR_UG ((uint8_t)0x01) </span></div>
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<div class="line"><a name="l08327"></a><span class="lineno"> 8327</span> <span class="preprocessor">#define TIM_EGR_CC1G ((uint8_t)0x02) </span></div>
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<div class="line"><a name="l08328"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga16f52a8e9aad153223405b965566ae91"> 8328</a></span> <span class="preprocessor">#define TIM_EGR_CC2G ((uint8_t)0x04) </span></div>
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<div class="line"><a name="l08329"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0a1318609761df5de5213e9e75b5aa6a"> 8329</a></span> <span class="preprocessor">#define TIM_EGR_CC3G ((uint8_t)0x08) </span></div>
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<div class="line"><a name="l08330"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5423de00e86aeb8a4657a509af485055"> 8330</a></span> <span class="preprocessor">#define TIM_EGR_CC4G ((uint8_t)0x10) </span></div>
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<div class="line"><a name="l08331"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga064d2030abccc099ded418fd81d6aa07"> 8331</a></span> <span class="preprocessor">#define TIM_EGR_COMG ((uint8_t)0x20) </span></div>
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<div class="line"><a name="l08332"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1c4e5555dd3be8ab1e631d1053f4a305"> 8332</a></span> <span class="preprocessor">#define TIM_EGR_TG ((uint8_t)0x40) </span></div>
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<div class="line"><a name="l08333"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadb06f8bb364307695c7d6a028391de7b"> 8333</a></span> <span class="preprocessor">#define TIM_EGR_BG ((uint8_t)0x80) </span></div>
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<div class="line"><a name="l08335"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga08c5635a0ac0ce5618485319a4fa0f18"> 8335</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for TIM_CCMR1 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08336"></a><span class="lineno"> 8336</span> <span class="preprocessor">#define TIM_CCMR1_CC1S ((uint16_t)0x0003) </span></div>
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<div class="line"><a name="l08337"></a><span class="lineno"> 8337</span> <span class="preprocessor">#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) </span></div>
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<div class="line"><a name="l08338"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95291df1eaf532c5c996d176648938eb"> 8338</a></span> <span class="preprocessor">#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l08340"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga299207b757f31c9c02471ab5f4f59dbe"> 8340</a></span> <span class="preprocessor">#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l08341"></a><span class="lineno"> 8341</span> <span class="preprocessor">#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l08343"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1aa54ddf87a4b339881a8d5368ec80eb"> 8343</a></span> <span class="preprocessor">#define TIM_CCMR1_OC1M ((uint16_t)0x0070) </span></div>
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<div class="line"><a name="l08344"></a><span class="lineno"> 8344</span> <span class="preprocessor">#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l08345"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6ddb3dc889733e71d812baa3873cb13b"> 8345</a></span> <span class="preprocessor">#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l08346"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga410a4752a98081bad8ab3f72b28e7c5f"> 8346</a></span> <span class="preprocessor">#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l08348"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac024f6b9972b940925ab5786ee38701b"> 8348</a></span> <span class="preprocessor">#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l08350"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8f44c50cf9928d2afab014e2ca29baba"> 8350</a></span> <span class="preprocessor">#define TIM_CCMR1_CC2S ((uint16_t)0x0300) </span></div>
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<div class="line"><a name="l08351"></a><span class="lineno"> 8351</span> <span class="preprocessor">#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l08352"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacdb0986b78bea5b53ea61e4ddd667cbf"> 8352</a></span> <span class="preprocessor">#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l08354"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga78303c37fdbe0be80f5fc7d21e9eba45"> 8354</a></span> <span class="preprocessor">#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l08355"></a><span class="lineno"> 8355</span> <span class="preprocessor">#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l08357"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabddbf508732039730125ab3e87e9d370"> 8357</a></span> <span class="preprocessor">#define TIM_CCMR1_OC2M ((uint16_t)0x7000) </span></div>
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<div class="line"><a name="l08358"></a><span class="lineno"> 8358</span> <span class="preprocessor">#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) </span></div>
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<div class="line"><a name="l08359"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2326bafe64ba2ebdde908d66219eaa6f"> 8359</a></span> <span class="preprocessor">#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) </span></div>
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<div class="line"><a name="l08360"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadbb68b91da16ffd509a6c7a2a397083c"> 8360</a></span> <span class="preprocessor">#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) </span></div>
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<div class="line"><a name="l08362"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad039a41e5fe97ddf904a0f9f95eb539e"> 8362</a></span> <span class="preprocessor">#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) </span></div>
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<div class="line"><a name="l08364"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga19a8dd4ea04d262ec4e97b5c7a8677a5"> 8364</a></span> <span class="preprocessor"></span><span class="comment">/*----------------------------------------------------------------------------*/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08365"></a><span class="lineno"> 8365</span> </div>
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<div class="line"><a name="l08366"></a><span class="lineno"> 8366</span> <span class="preprocessor">#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) </span></div>
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<div class="line"><a name="l08367"></a><span class="lineno"> 8367</span> <span class="preprocessor">#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l08368"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab46b7186665f5308cd2ca52acfb63e72"> 8368</a></span> <span class="preprocessor">#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l08370"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf42b75da9b2f127dca98b6ca616f7add"> 8370</a></span> <span class="preprocessor">#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) </span></div>
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<div class="line"><a name="l08371"></a><span class="lineno"> 8371</span> <span class="preprocessor">#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l08372"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab0ee123675d8b8f98b5a6eeeccf37912"> 8372</a></span> <span class="preprocessor">#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l08373"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7dde4afee556d2d8d22885f191da65a6"> 8373</a></span> <span class="preprocessor">#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l08374"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga201491465e6864088210bccb8491be84"> 8374</a></span> <span class="preprocessor">#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l08376"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga23da95530eb6d6451c7c9e451a580f42"> 8376</a></span> <span class="preprocessor">#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) </span></div>
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<div class="line"><a name="l08377"></a><span class="lineno"> 8377</span> <span class="preprocessor">#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l08378"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5e8e704f9ce5742f45e15e3b3126aa9d"> 8378</a></span> <span class="preprocessor">#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l08380"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae861d74943f3c045421f9fdc8b966841"> 8380</a></span> <span class="preprocessor">#define TIM_CCMR1_IC2F ((uint16_t)0xF000) </span></div>
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<div class="line"><a name="l08381"></a><span class="lineno"> 8381</span> <span class="preprocessor">#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) </span></div>
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<div class="line"><a name="l08382"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b942752d686c23323880ff576e7dffb"> 8382</a></span> <span class="preprocessor">#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) </span></div>
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<div class="line"><a name="l08383"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5d75acd7072f28844074702683d8493f"> 8383</a></span> <span class="preprocessor">#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) </span></div>
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<div class="line"><a name="l08384"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga40e49318b54b16bda6fd7feea7c9a7dd"> 8384</a></span> <span class="preprocessor">#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) </span></div>
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<div class="line"><a name="l08386"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafece48b6f595ef9717d523fa23cea1e8"> 8386</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for TIM_CCMR2 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08387"></a><span class="lineno"> 8387</span> <span class="preprocessor">#define TIM_CCMR2_CC3S ((uint16_t)0x0003) </span></div>
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<div class="line"><a name="l08388"></a><span class="lineno"> 8388</span> <span class="preprocessor">#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) </span></div>
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<div class="line"><a name="l08389"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2eabcc7e322b02c9c406b3ff70308260"> 8389</a></span> <span class="preprocessor">#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l08391"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4bed6648aad6e8d16196246b355452dc"> 8391</a></span> <span class="preprocessor">#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l08392"></a><span class="lineno"> 8392</span> <span class="preprocessor">#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l08394"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga276fd2250d2b085b73ef51cb4c099d24"> 8394</a></span> <span class="preprocessor">#define TIM_CCMR2_OC3M ((uint16_t)0x0070) </span></div>
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<div class="line"><a name="l08395"></a><span class="lineno"> 8395</span> <span class="preprocessor">#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l08396"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga52095cae524adb237339bfee92e8168a"> 8396</a></span> <span class="preprocessor">#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l08397"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga899b26ffa9c5f30f143306b8598a537f"> 8397</a></span> <span class="preprocessor">#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l08399"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga20394da7afcada6c3fc455b05004cff5"> 8399</a></span> <span class="preprocessor">#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l08401"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4209d414df704ce96c54abb2ea2df66a"> 8401</a></span> <span class="preprocessor">#define TIM_CCMR2_CC4S ((uint16_t)0x0300) </span></div>
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<div class="line"><a name="l08402"></a><span class="lineno"> 8402</span> <span class="preprocessor">#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l08403"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga294e216b50edd1c2f891143e1f971048"> 8403</a></span> <span class="preprocessor">#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l08405"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6386ec77a3a451954325a1512d44f893"> 8405</a></span> <span class="preprocessor">#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l08406"></a><span class="lineno"> 8406</span> <span class="preprocessor">#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l08408"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3e951cd3f6593e321cf79b662a1deaaa"> 8408</a></span> <span class="preprocessor">#define TIM_CCMR2_OC4M ((uint16_t)0x7000) </span></div>
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<div class="line"><a name="l08409"></a><span class="lineno"> 8409</span> <span class="preprocessor">#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) </span></div>
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<div class="line"><a name="l08410"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacbed61ff3ba57c7fe6d3386ce3b7af2b"> 8410</a></span> <span class="preprocessor">#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) </span></div>
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<div class="line"><a name="l08411"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad866f52cce9ce32e3c0d181007b82de5"> 8411</a></span> <span class="preprocessor">#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) </span></div>
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<div class="line"><a name="l08413"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga431e5cdc0f3dc02fa5a54aa5193ddbab"> 8413</a></span> <span class="preprocessor">#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) </span></div>
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<div class="line"><a name="l08415"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1447dfe94bdd234382bb1f43307ea5c3"> 8415</a></span> <span class="preprocessor"></span><span class="comment">/*----------------------------------------------------------------------------*/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08416"></a><span class="lineno"> 8416</span> </div>
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<div class="line"><a name="l08417"></a><span class="lineno"> 8417</span> <span class="preprocessor">#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) </span></div>
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<div class="line"><a name="l08418"></a><span class="lineno"> 8418</span> <span class="preprocessor">#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l08419"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gafc3d11f2e968752bc9ec7131c986c3a6"> 8419</a></span> <span class="preprocessor">#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l08421"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gacd27b9bdcc161c90dc1712074a66f29d"> 8421</a></span> <span class="preprocessor">#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) </span></div>
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<div class="line"><a name="l08422"></a><span class="lineno"> 8422</span> <span class="preprocessor">#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l08423"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad218af6bd1de72891e1b85d582b766cd"> 8423</a></span> <span class="preprocessor">#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l08424"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31d5450ebc9ac6ea833a2b341ceea061"> 8424</a></span> <span class="preprocessor">#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l08425"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga26f92a3f831685d6df7ab69e68181849"> 8425</a></span> <span class="preprocessor">#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l08427"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9696c3da027f2b292d077f1ab4cdd14b"> 8427</a></span> <span class="preprocessor">#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) </span></div>
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<div class="line"><a name="l08428"></a><span class="lineno"> 8428</span> <span class="preprocessor">#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l08429"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6fd7591e2de10272f7fafb08cdd1b7b0"> 8429</a></span> <span class="preprocessor">#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l08431"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf6690f5e98e02addd5e75643767c6d66"> 8431</a></span> <span class="preprocessor">#define TIM_CCMR2_IC4F ((uint16_t)0xF000) </span></div>
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<div class="line"><a name="l08432"></a><span class="lineno"> 8432</span> <span class="preprocessor">#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) </span></div>
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<div class="line"><a name="l08433"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad51653fd06a591294d432385e794a19e"> 8433</a></span> <span class="preprocessor">#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) </span></div>
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<div class="line"><a name="l08434"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7d5fc8b9a6ea27582cb6c25f9654888c"> 8434</a></span> <span class="preprocessor">#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) </span></div>
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<div class="line"><a name="l08435"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac4dcc1562c0c017493e4ee6b32354e85"> 8435</a></span> <span class="preprocessor">#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) </span></div>
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<div class="line"><a name="l08437"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga25d0f55e5b751f2caed6a943f5682a09"> 8437</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for TIM_CCER register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08438"></a><span class="lineno"> 8438</span> <span class="preprocessor">#define TIM_CCER_CC1E ((uint16_t)0x0001) </span></div>
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<div class="line"><a name="l08439"></a><span class="lineno"> 8439</span> <span class="preprocessor">#define TIM_CCER_CC1P ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l08440"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f494b9881e7b97bb2d79f7ad4e79937"> 8440</a></span> <span class="preprocessor">#define TIM_CCER_CC1NE ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l08441"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0ca0aedba14241caff739afb3c3ee291"> 8441</a></span> <span class="preprocessor">#define TIM_CCER_CC1NP ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l08442"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga813056b3f90a13c4432aeba55f28957e"> 8442</a></span> <span class="preprocessor">#define TIM_CCER_CC2E ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l08443"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga403fc501d4d8de6cabee6b07acb81a36"> 8443</a></span> <span class="preprocessor">#define TIM_CCER_CC2P ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l08444"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76392a4d63674cd0db0a55762458f16c"> 8444</a></span> <span class="preprocessor">#define TIM_CCER_CC2NE ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l08445"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3136c6e776c6066509d298b6a9b34912"> 8445</a></span> <span class="preprocessor">#define TIM_CCER_CC2NP ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l08446"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6a784649120eddec31998f34323d4156"> 8446</a></span> <span class="preprocessor">#define TIM_CCER_CC3E ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l08447"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga387de559d8b16b16f3934fddd2aa969f"> 8447</a></span> <span class="preprocessor">#define TIM_CCER_CC3P ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l08448"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1da114e666b61f09cf25f50cdaa7f81f"> 8448</a></span> <span class="preprocessor">#define TIM_CCER_CC3NE ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l08449"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga6220a5cd34c7a7a39e10c854aa00d2e5"> 8449</a></span> <span class="preprocessor">#define TIM_CCER_CC3NP ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l08450"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad46cce61d3bd83b64257ba75e54ee1aa"> 8450</a></span> <span class="preprocessor">#define TIM_CCER_CC4E ((uint16_t)0x1000) </span></div>
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<div class="line"><a name="l08451"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4029686d3307111d3f9f4400e29e4521"> 8451</a></span> <span class="preprocessor">#define TIM_CCER_CC4P ((uint16_t)0x2000) </span></div>
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<div class="line"><a name="l08452"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga940b041ab5975311f42f26d314a4b621"> 8452</a></span> <span class="preprocessor">#define TIM_CCER_CC4NP ((uint16_t)0x8000) </span></div>
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<div class="line"><a name="l08454"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga41b88bff3f38cec0617ce66fa5aef260"> 8454</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for TIM_CNT register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08455"></a><span class="lineno"> 8455</span> <span class="preprocessor">#define TIM_CNT_CNT ((uint16_t)0xFFFF) </span></div>
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<div class="line"><a name="l08457"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8bc45c0315de82c1c3a38a243bcd00fc"> 8457</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for TIM_PSC register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08458"></a><span class="lineno"> 8458</span> <span class="preprocessor">#define TIM_PSC_PSC ((uint16_t)0xFFFF) </span></div>
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<div class="line"><a name="l08460"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaefb85e4000ddab0ada67c5964810da35"> 8460</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for TIM_ARR register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08461"></a><span class="lineno"> 8461</span> <span class="preprocessor">#define TIM_ARR_ARR ((uint16_t)0xFFFF) </span></div>
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<div class="line"><a name="l08463"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gace50256fdecc38f641050a4a3266e4d9"> 8463</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for TIM_RCR register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08464"></a><span class="lineno"> 8464</span> <span class="preprocessor">#define TIM_RCR_REP ((uint8_t)0xFF) </span></div>
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<div class="line"><a name="l08466"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gadcef8f28580e36cdfda3be1f7561afc7"> 8466</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for TIM_CCR1 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08467"></a><span class="lineno"> 8467</span> <span class="preprocessor">#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) </span></div>
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<div class="line"><a name="l08469"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac927cc11eff415210dcf94657d8dfbe0"> 8469</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for TIM_CCR2 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08470"></a><span class="lineno"> 8470</span> <span class="preprocessor">#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) </span></div>
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<div class="line"><a name="l08472"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga751e5efd90bdd1fd5f38609f3f5762ba"> 8472</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for TIM_CCR3 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08473"></a><span class="lineno"> 8473</span> <span class="preprocessor">#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) </span></div>
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<div class="line"><a name="l08475"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4e85064d37d387851e95c5c1f35315a1"> 8475</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for TIM_CCR4 register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08476"></a><span class="lineno"> 8476</span> <span class="preprocessor">#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) </span></div>
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<div class="line"><a name="l08478"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga15c9dd67a6701b5498926ae536773eca"> 8478</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for TIM_BDTR register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08479"></a><span class="lineno"> 8479</span> <span class="preprocessor">#define TIM_BDTR_DTG ((uint16_t)0x00FF) </span></div>
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<div class="line"><a name="l08480"></a><span class="lineno"> 8480</span> <span class="preprocessor">#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) </span></div>
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<div class="line"><a name="l08481"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabcf985e9c78f15e1e44b2bc4d2bafc67"> 8481</a></span> <span class="preprocessor">#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l08482"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4b575cca31b0e22ef1d5b842aa162bfc"> 8482</a></span> <span class="preprocessor">#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l08483"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga0f33ae1e9b7847a60032a60d0cc7f81d"> 8483</a></span> <span class="preprocessor">#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l08484"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2f06a132eba960bd6cc972e3580d537c"> 8484</a></span> <span class="preprocessor">#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l08485"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae7868643a65285fc7132f040c8950f43"> 8485</a></span> <span class="preprocessor">#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) </span></div>
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<div class="line"><a name="l08486"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga503b44e30a5fb77c34630d1faca70213"> 8486</a></span> <span class="preprocessor">#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l08487"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga83a12ecb0a8dd21bc164d9a345ea564f"> 8487</a></span> <span class="preprocessor">#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l08489"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac945c8bcf5567912a88eb2acee53c45b"> 8489</a></span> <span class="preprocessor">#define TIM_BDTR_LOCK ((uint16_t)0x0300) </span></div>
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<div class="line"><a name="l08490"></a><span class="lineno"> 8490</span> <span class="preprocessor">#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l08491"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7e4215d17f0548dfcf0b15fe4d0f4651"> 8491</a></span> <span class="preprocessor">#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l08493"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga756df80ff8c34399435f52dca18e6eee"> 8493</a></span> <span class="preprocessor">#define TIM_BDTR_OSSI ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l08494"></a><span class="lineno"> 8494</span> <span class="preprocessor">#define TIM_BDTR_OSSR ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l08495"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab1cf04e70ccf3d4aba5afcf2496a411a"> 8495</a></span> <span class="preprocessor">#define TIM_BDTR_BKE ((uint16_t)0x1000) </span></div>
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<div class="line"><a name="l08496"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf9435f36d53c6be1107e57ab6a82c16e"> 8496</a></span> <span class="preprocessor">#define TIM_BDTR_BKP ((uint16_t)0x2000) </span></div>
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<div class="line"><a name="l08497"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga74250b040dd9fd9c09dcc54cdd6d86d8"> 8497</a></span> <span class="preprocessor">#define TIM_BDTR_AOE ((uint16_t)0x4000) </span></div>
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<div class="line"><a name="l08498"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3247abbbf0d00260be051d176d88020e"> 8498</a></span> <span class="preprocessor">#define TIM_BDTR_MOE ((uint16_t)0x8000) </span></div>
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<div class="line"><a name="l08500"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga277a096614829feba2d0a4fbb7d3dffc"> 8500</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for TIM_DCR register ********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08501"></a><span class="lineno"> 8501</span> <span class="preprocessor">#define TIM_DCR_DBA ((uint16_t)0x001F) </span></div>
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<div class="line"><a name="l08502"></a><span class="lineno"> 8502</span> <span class="preprocessor">#define TIM_DCR_DBA_0 ((uint16_t)0x0001) </span></div>
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<div class="line"><a name="l08503"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabf9051ecac123cd89f9d2a835e4cde2e"> 8503</a></span> <span class="preprocessor">#define TIM_DCR_DBA_1 ((uint16_t)0x0002) </span></div>
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<div class="line"><a name="l08504"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaaf610e5fe4bb4b10736242df3b62bba"> 8504</a></span> <span class="preprocessor">#define TIM_DCR_DBA_2 ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l08505"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a0185643c163930e30f0a1cf5fe364e"> 8505</a></span> <span class="preprocessor">#define TIM_DCR_DBA_3 ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l08506"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaa5a89b93b97b0968a7d5563a18ab9d1"> 8506</a></span> <span class="preprocessor">#define TIM_DCR_DBA_4 ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l08508"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabe1bc4b6dd7265dee2857f23d835b2dc"> 8508</a></span> <span class="preprocessor">#define TIM_DCR_DBL ((uint16_t)0x1F00) </span></div>
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<div class="line"><a name="l08509"></a><span class="lineno"> 8509</span> <span class="preprocessor">#define TIM_DCR_DBL_0 ((uint16_t)0x0100) </span></div>
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<div class="line"><a name="l08510"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab9e197a78484567d4c6093c28265f3eb"> 8510</a></span> <span class="preprocessor">#define TIM_DCR_DBL_1 ((uint16_t)0x0200) </span></div>
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<div class="line"><a name="l08511"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga677195c0b4892bb6717564c0528126a9"> 8511</a></span> <span class="preprocessor">#define TIM_DCR_DBL_2 ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l08512"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad427ba987877e491f7a2be60e320dbea"> 8512</a></span> <span class="preprocessor">#define TIM_DCR_DBL_3 ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l08513"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga369926f2a8ca5cf635ded9bb4619189c"> 8513</a></span> <span class="preprocessor">#define TIM_DCR_DBL_4 ((uint16_t)0x1000) </span></div>
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<div class="line"><a name="l08515"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga607d7b87b1b4bf167aabad36f922a8f9"> 8515</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for TIM_DMAR register *******************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08516"></a><span class="lineno"> 8516</span> <span class="preprocessor">#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) </span></div>
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<div class="line"><a name="l08518"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1afa2fc02bcd75c15122c4eb87d6cf83"> 8518</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for TIM_OR register *********************/</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08519"></a><span class="lineno"> 8519</span> <span class="preprocessor">#define TIM_OR_TI4_RMP ((uint16_t)0x00C0) </span></div>
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<div class="line"><a name="l08520"></a><span class="lineno"> 8520</span> <span class="preprocessor">#define TIM_OR_TI4_RMP_0 ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l08521"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2916847c3545c06578d7ba8c381a4c20"> 8521</a></span> <span class="preprocessor">#define TIM_OR_TI4_RMP_1 ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l08522"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9aea4f8a0abedbf08bb1e686933c1120"> 8522</a></span> <span class="preprocessor">#define TIM_OR_ITR1_RMP ((uint16_t)0x0C00) </span></div>
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<div class="line"><a name="l08523"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa2a46aa18f15f2074b93233a18e85629"> 8523</a></span> <span class="preprocessor">#define TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400) </span></div>
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<div class="line"><a name="l08524"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4f413eac7f503dfddc9a9914efa555ac"> 8524</a></span> <span class="preprocessor">#define TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800) </span></div>
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<div class="line"><a name="l08527"></a><span class="lineno"> 8527</span> <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08528"></a><span class="lineno"> 8528</span> <span class="comment">/* */</span></div>
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<div class="line"><a name="l08529"></a><span class="lineno"> 8529</span> <span class="comment">/* Universal Synchronous Asynchronous Receiver Transmitter */</span></div>
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|
<div class="line"><a name="l08530"></a><span class="lineno"> 8530</span> <span class="comment">/* */</span></div>
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|
<div class="line"><a name="l08531"></a><span class="lineno"> 8531</span> <span class="comment">/******************************************************************************/</span></div>
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|
<div class="line"><a name="l08532"></a><span class="lineno"> 8532</span> <span class="comment">/******************* Bit definition for USART_SR register *******************/</span></div>
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|
<div class="line"><a name="l08533"></a><span class="lineno"> 8533</span> <span class="preprocessor">#define USART_SR_PE ((uint16_t)0x0001) </span></div>
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|
<div class="line"><a name="l08534"></a><span class="lineno"> 8534</span> <span class="preprocessor">#define USART_SR_FE ((uint16_t)0x0002) </span></div>
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|
<div class="line"><a name="l08535"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac88be3484245af8c1b271ae5c1b97a14"> 8535</a></span> <span class="preprocessor">#define USART_SR_NE ((uint16_t)0x0004) </span></div>
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|
<div class="line"><a name="l08536"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9eb6fd3f820bd12e0b5a981de1894804"> 8536</a></span> <span class="preprocessor">#define USART_SR_ORE ((uint16_t)0x0008) </span></div>
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<div class="line"><a name="l08537"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8938468c5666a8305ade6d80d467c572"> 8537</a></span> <span class="preprocessor">#define USART_SR_IDLE ((uint16_t)0x0010) </span></div>
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|
<div class="line"><a name="l08538"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4560fc7a60df4bdf402fc7219ae7b558"> 8538</a></span> <span class="preprocessor">#define USART_SR_RXNE ((uint16_t)0x0020) </span></div>
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|
<div class="line"><a name="l08539"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga336fa8c9965ce18c10972ac80ded611f"> 8539</a></span> <span class="preprocessor">#define USART_SR_TC ((uint16_t)0x0040) </span></div>
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|
<div class="line"><a name="l08540"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0c99e2bb265b3d58a91aca7a93f7836"> 8540</a></span> <span class="preprocessor">#define USART_SR_TXE ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l08541"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga76229b05ac37a5a688e6ba45851a29f1"> 8541</a></span> <span class="preprocessor">#define USART_SR_LBD ((uint16_t)0x0100) </span></div>
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|
<div class="line"><a name="l08542"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga65e9cddf0890113d405342f1d8b5b980"> 8542</a></span> <span class="preprocessor">#define USART_SR_CTS ((uint16_t)0x0200) </span></div>
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|
<div class="line"><a name="l08544"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9250ae2793db0541e6c4bb8837424541"> 8544</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for USART_DR register *******************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08545"></a><span class="lineno"> 8545</span> <span class="preprocessor">#define USART_DR_DR ((uint16_t)0x01FF) </span></div>
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|
<div class="line"><a name="l08547"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad84ad1e1d0202b41021e2d6e40486bff"> 8547</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for USART_BRR register *******************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08548"></a><span class="lineno"> 8548</span> <span class="preprocessor">#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) </span></div>
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|
<div class="line"><a name="l08549"></a><span class="lineno"> 8549</span> <span class="preprocessor">#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) </span></div>
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|
<div class="line"><a name="l08551"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60cfa3802798306b86231f828ed2e71e"> 8551</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for USART_CR1 register *******************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08552"></a><span class="lineno"> 8552</span> <span class="preprocessor">#define USART_CR1_SBK ((uint16_t)0x0001) </span></div>
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|
<div class="line"><a name="l08553"></a><span class="lineno"> 8553</span> <span class="preprocessor">#define USART_CR1_RWU ((uint16_t)0x0002) </span></div>
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|
<div class="line"><a name="l08554"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac457c519baa28359ab7959fbe0c5cda1"> 8554</a></span> <span class="preprocessor">#define USART_CR1_RE ((uint16_t)0x0004) </span></div>
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|
<div class="line"><a name="l08555"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa7d61ab5a4e2beaa3f591c56bd15a27b"> 8555</a></span> <span class="preprocessor">#define USART_CR1_TE ((uint16_t)0x0008) </span></div>
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|
<div class="line"><a name="l08556"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gada0d5d407a22264de847bc1b40a17aeb"> 8556</a></span> <span class="preprocessor">#define USART_CR1_IDLEIE ((uint16_t)0x0010) </span></div>
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|
<div class="line"><a name="l08557"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gade7f090b04fd78b755b43357ecaa9622"> 8557</a></span> <span class="preprocessor">#define USART_CR1_RXNEIE ((uint16_t)0x0020) </span></div>
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|
<div class="line"><a name="l08558"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5221d09eebd12445a20f221bf98066f8"> 8558</a></span> <span class="preprocessor">#define USART_CR1_TCIE ((uint16_t)0x0040) </span></div>
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|
<div class="line"><a name="l08559"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga91118f867adfdb2e805beea86666de04"> 8559</a></span> <span class="preprocessor">#define USART_CR1_TXEIE ((uint16_t)0x0080) </span></div>
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|
<div class="line"><a name="l08560"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa17130690a1ca95b972429eb64d4254e"> 8560</a></span> <span class="preprocessor">#define USART_CR1_PEIE ((uint16_t)0x0100) </span></div>
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|
<div class="line"><a name="l08561"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga70422871d15f974b464365e7fe1877e9"> 8561</a></span> <span class="preprocessor">#define USART_CR1_PS ((uint16_t)0x0200) </span></div>
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|
<div class="line"><a name="l08562"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga27405d413b6d355ccdb076d52fef6875"> 8562</a></span> <span class="preprocessor">#define USART_CR1_PCE ((uint16_t)0x0400) </span></div>
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|
<div class="line"><a name="l08563"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2e159d36ab2c93a2c1942df60e9eebbe"> 8563</a></span> <span class="preprocessor">#define USART_CR1_WAKE ((uint16_t)0x0800) </span></div>
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|
<div class="line"><a name="l08564"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga60f8fcf084f9a8514efafb617c70b074"> 8564</a></span> <span class="preprocessor">#define USART_CR1_M ((uint16_t)0x1000) </span></div>
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|
<div class="line"><a name="l08565"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad831dfc169fcf14b7284984dbecf322d"> 8565</a></span> <span class="preprocessor">#define USART_CR1_UE ((uint16_t)0x2000) </span></div>
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|
<div class="line"><a name="l08566"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga95f0288b9c6aaeca7cb6550a2e6833e2"> 8566</a></span> <span class="preprocessor">#define USART_CR1_OVER8 ((uint16_t)0x8000) </span></div>
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|
<div class="line"><a name="l08568"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed6caeb0cb48f1a7b34090f31a92a8e2"> 8568</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for USART_CR2 register *******************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08569"></a><span class="lineno"> 8569</span> <span class="preprocessor">#define USART_CR2_ADD ((uint16_t)0x000F) </span></div>
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|
<div class="line"><a name="l08570"></a><span class="lineno"> 8570</span> <span class="preprocessor">#define USART_CR2_LBDL ((uint16_t)0x0020) </span></div>
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|
<div class="line"><a name="l08571"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3ee77fac25142271ad56d49685e518b3"> 8571</a></span> <span class="preprocessor">#define USART_CR2_LBDIE ((uint16_t)0x0040) </span></div>
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|
<div class="line"><a name="l08572"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7f9bc41700717fd93548e0e95b6072ed"> 8572</a></span> <span class="preprocessor">#define USART_CR2_LBCL ((uint16_t)0x0100) </span></div>
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|
<div class="line"><a name="l08573"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa02ef5d22553f028ea48e5d9f08192b4"> 8573</a></span> <span class="preprocessor">#define USART_CR2_CPHA ((uint16_t)0x0200) </span></div>
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|
<div class="line"><a name="l08574"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4a62e93ae7864e89622bdd92508b615e"> 8574</a></span> <span class="preprocessor">#define USART_CR2_CPOL ((uint16_t)0x0400) </span></div>
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|
<div class="line"><a name="l08575"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga362976ce813e58310399d113d2cf09cb"> 8575</a></span> <span class="preprocessor">#define USART_CR2_CLKEN ((uint16_t)0x0800) </span></div>
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|
<div class="line"><a name="l08577"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga42a396cde02ffa0c4d3fd9817b6af853"> 8577</a></span> <span class="preprocessor">#define USART_CR2_STOP ((uint16_t)0x3000) </span></div>
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|
<div class="line"><a name="l08578"></a><span class="lineno"> 8578</span> <span class="preprocessor">#define USART_CR2_STOP_0 ((uint16_t)0x1000) </span></div>
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|
<div class="line"><a name="l08579"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf993e483318ebcecffd18649de766dc6"> 8579</a></span> <span class="preprocessor">#define USART_CR2_STOP_1 ((uint16_t)0x2000) </span></div>
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|
<div class="line"><a name="l08581"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2b24d14f0e5d1c76c878b08aad44d02b"> 8581</a></span> <span class="preprocessor">#define USART_CR2_LINEN ((uint16_t)0x4000) </span></div>
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|
<div class="line"><a name="l08583"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac8931efa62c29d92f5c0ec5a05f907ef"> 8583</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for USART_CR3 register *******************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08584"></a><span class="lineno"> 8584</span> <span class="preprocessor">#define USART_CR3_EIE ((uint16_t)0x0001) </span></div>
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|
<div class="line"><a name="l08585"></a><span class="lineno"> 8585</span> <span class="preprocessor">#define USART_CR3_IREN ((uint16_t)0x0002) </span></div>
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|
<div class="line"><a name="l08586"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaaed1a39c551b1641128f81893ff558d0"> 8586</a></span> <span class="preprocessor">#define USART_CR3_IRLP ((uint16_t)0x0004) </span></div>
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|
<div class="line"><a name="l08587"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga31c66373bfbae7724c836ac63b8411dd"> 8587</a></span> <span class="preprocessor">#define USART_CR3_HDSEL ((uint16_t)0x0008) </span></div>
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|
<div class="line"><a name="l08588"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga22af8d399f1adda62e31186f0309af80"> 8588</a></span> <span class="preprocessor">#define USART_CR3_NACK ((uint16_t)0x0010) </span></div>
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|
<div class="line"><a name="l08589"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gac71129810fab0b46d91161a39e3f8d01"> 8589</a></span> <span class="preprocessor">#define USART_CR3_SCEN ((uint16_t)0x0020) </span></div>
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|
<div class="line"><a name="l08590"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga3f3b70b2ee9ff0b59e952fd7ab04373c"> 8590</a></span> <span class="preprocessor">#define USART_CR3_DMAR ((uint16_t)0x0040) </span></div>
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|
<div class="line"><a name="l08591"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9180b9249a26988f71d4bb2b0c3eec27"> 8591</a></span> <span class="preprocessor">#define USART_CR3_DMAT ((uint16_t)0x0080) </span></div>
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|
<div class="line"><a name="l08592"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaff130f15493c765353ec2fd605667c5a"> 8592</a></span> <span class="preprocessor">#define USART_CR3_RTSE ((uint16_t)0x0100) </span></div>
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|
<div class="line"><a name="l08593"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga5bb515d3814d448f84e2c98bf44f3993"> 8593</a></span> <span class="preprocessor">#define USART_CR3_CTSE ((uint16_t)0x0200) </span></div>
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|
<div class="line"><a name="l08594"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7c5d6fcd84a4728cda578a0339b4cac2"> 8594</a></span> <span class="preprocessor">#define USART_CR3_CTSIE ((uint16_t)0x0400) </span></div>
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|
<div class="line"><a name="l08595"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa125f026b1ca2d76eab48b191baed265"> 8595</a></span> <span class="preprocessor">#define USART_CR3_ONEBIT ((uint16_t)0x0800) </span></div>
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|
<div class="line"><a name="l08597"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9a96fb1a7beab602cbc8cb0393593826"> 8597</a></span> <span class="preprocessor"></span><span class="comment">/****************** Bit definition for USART_GTPR register ******************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08598"></a><span class="lineno"> 8598</span> <span class="preprocessor">#define USART_GTPR_PSC ((uint16_t)0x00FF) </span></div>
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|
<div class="line"><a name="l08599"></a><span class="lineno"> 8599</span> <span class="preprocessor">#define USART_GTPR_PSC_0 ((uint16_t)0x0001) </span></div>
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|
<div class="line"><a name="l08600"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa0b423f0f4baf7d510ea70477e5c9203"> 8600</a></span> <span class="preprocessor">#define USART_GTPR_PSC_1 ((uint16_t)0x0002) </span></div>
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|
<div class="line"><a name="l08601"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga2c49c90d83a0e3746b56b2a0a3b0ddcb"> 8601</a></span> <span class="preprocessor">#define USART_GTPR_PSC_2 ((uint16_t)0x0004) </span></div>
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<div class="line"><a name="l08602"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8eab5000ab993991d0da8ffbd386c92b"> 8602</a></span> <span class="preprocessor">#define USART_GTPR_PSC_3 ((uint16_t)0x0008) </span></div>
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|
<div class="line"><a name="l08603"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d74604b6e1ab08a45ea4fe6b3f6b5cd"> 8603</a></span> <span class="preprocessor">#define USART_GTPR_PSC_4 ((uint16_t)0x0010) </span></div>
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<div class="line"><a name="l08604"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga1b6b237fcac675f8f047c4ff64248486"> 8604</a></span> <span class="preprocessor">#define USART_GTPR_PSC_5 ((uint16_t)0x0020) </span></div>
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|
<div class="line"><a name="l08605"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad1c0e92df8edb974008b3d37d12f655a"> 8605</a></span> <span class="preprocessor">#define USART_GTPR_PSC_6 ((uint16_t)0x0040) </span></div>
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<div class="line"><a name="l08606"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga12dda4877432bc181c9684b0830b1b7b"> 8606</a></span> <span class="preprocessor">#define USART_GTPR_PSC_7 ((uint16_t)0x0080) </span></div>
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<div class="line"><a name="l08608"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gad3da67d3c9c3abf436098a86477d2dfc"> 8608</a></span> <span class="preprocessor">#define USART_GTPR_GT ((uint16_t)0xFF00) </span></div>
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<div class="line"><a name="l08610"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga8e927fad0bfa430f54007e158e01f43b"> 8610</a></span> <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08611"></a><span class="lineno"> 8611</span> <span class="comment">/* */</span></div>
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|
<div class="line"><a name="l08612"></a><span class="lineno"> 8612</span> <span class="comment">/* Window WATCHDOG */</span></div>
|
|
<div class="line"><a name="l08613"></a><span class="lineno"> 8613</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l08614"></a><span class="lineno"> 8614</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l08615"></a><span class="lineno"> 8615</span> <span class="comment">/******************* Bit definition for WWDG_CR register ********************/</span></div>
|
|
<div class="line"><a name="l08616"></a><span class="lineno"> 8616</span> <span class="preprocessor">#define WWDG_CR_T ((uint8_t)0x7F) </span></div>
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|
<div class="line"><a name="l08617"></a><span class="lineno"> 8617</span> <span class="preprocessor">#define WWDG_CR_T0 ((uint8_t)0x01) </span></div>
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|
<div class="line"><a name="l08618"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga400774feb33ed7544d57d6a0a76e0f70"> 8618</a></span> <span class="preprocessor">#define WWDG_CR_T1 ((uint8_t)0x02) </span></div>
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<div class="line"><a name="l08619"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga4d510237467b8e10ca1001574671ad8e"> 8619</a></span> <span class="preprocessor">#define WWDG_CR_T2 ((uint8_t)0x04) </span></div>
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<div class="line"><a name="l08620"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaed4b5d3f4d2e0540058fd2253a8feb95"> 8620</a></span> <span class="preprocessor">#define WWDG_CR_T3 ((uint8_t)0x08) </span></div>
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|
<div class="line"><a name="l08621"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaa4e9559da387f10bac2dc8ab0d4f6e6c"> 8621</a></span> <span class="preprocessor">#define WWDG_CR_T4 ((uint8_t)0x10) </span></div>
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|
<div class="line"><a name="l08622"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab1e344f4a12c60e57cb643511379b261"> 8622</a></span> <span class="preprocessor">#define WWDG_CR_T5 ((uint8_t)0x20) </span></div>
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|
<div class="line"><a name="l08623"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaf1f89d17eb4b3bb1b67c2b0185061e45"> 8623</a></span> <span class="preprocessor">#define WWDG_CR_T6 ((uint8_t)0x40) </span></div>
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|
<div class="line"><a name="l08625"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab3a493575c9a7c6006a3af9d13399268"> 8625</a></span> <span class="preprocessor">#define WWDG_CR_WDGA ((uint8_t)0x80) </span></div>
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|
<div class="line"><a name="l08627"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gab647e9997b8b8e67de72af1aaea3f52f"> 8627</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for WWDG_CFR register *******************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08628"></a><span class="lineno"> 8628</span> <span class="preprocessor">#define WWDG_CFR_W ((uint16_t)0x007F) </span></div>
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|
<div class="line"><a name="l08629"></a><span class="lineno"> 8629</span> <span class="preprocessor">#define WWDG_CFR_W0 ((uint16_t)0x0001) </span></div>
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|
<div class="line"><a name="l08630"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gabfbb9991bd6a3699399ca569c71fe8c9"> 8630</a></span> <span class="preprocessor">#define WWDG_CFR_W1 ((uint16_t)0x0002) </span></div>
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|
<div class="line"><a name="l08631"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gae37e08098d003f44eb8770a9d9bd40d0"> 8631</a></span> <span class="preprocessor">#define WWDG_CFR_W2 ((uint16_t)0x0004) </span></div>
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|
<div class="line"><a name="l08632"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga698b68239773862647ef5f9d963b80c4"> 8632</a></span> <span class="preprocessor">#define WWDG_CFR_W3 ((uint16_t)0x0008) </span></div>
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|
<div class="line"><a name="l08633"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga166845425e89d01552bac0baeec686d9"> 8633</a></span> <span class="preprocessor">#define WWDG_CFR_W4 ((uint16_t)0x0010) </span></div>
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|
<div class="line"><a name="l08634"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga344253edc9710aa6db6047b76cce723b"> 8634</a></span> <span class="preprocessor">#define WWDG_CFR_W5 ((uint16_t)0x0020) </span></div>
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|
<div class="line"><a name="l08635"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#gaec3a0817a2dcde78414d02c0cb5d201d"> 8635</a></span> <span class="preprocessor">#define WWDG_CFR_W6 ((uint16_t)0x0040) </span></div>
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|
<div class="line"><a name="l08637"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga106cdb96da03ce192628f54cefcbec2f"> 8637</a></span> <span class="preprocessor">#define WWDG_CFR_WDGTB ((uint16_t)0x0180) </span></div>
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|
<div class="line"><a name="l08638"></a><span class="lineno"> 8638</span> <span class="preprocessor">#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) </span></div>
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|
<div class="line"><a name="l08639"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga067b1d8238f1d5613481aba71a946638"> 8639</a></span> <span class="preprocessor">#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) </span></div>
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|
<div class="line"><a name="l08641"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga9d53e6fa74c43522ebacd6dd6f450d33"> 8641</a></span> <span class="preprocessor">#define WWDG_CFR_EWI ((uint16_t)0x0200) </span></div>
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|
<div class="line"><a name="l08643"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga931941dc5d795502371ac5dd8fbac1e9"> 8643</a></span> <span class="preprocessor"></span><span class="comment">/******************* Bit definition for WWDG_SR register ********************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08644"></a><span class="lineno"> 8644</span> <span class="preprocessor">#define WWDG_SR_EWIF ((uint8_t)0x01) </span></div>
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|
<div class="line"><a name="l08647"></a><span class="lineno"> 8647</span> <span class="preprocessor"></span><span class="comment">/******************************************************************************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08648"></a><span class="lineno"> 8648</span> <span class="comment">/* */</span></div>
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|
<div class="line"><a name="l08649"></a><span class="lineno"> 8649</span> <span class="comment">/* DBG */</span></div>
|
|
<div class="line"><a name="l08650"></a><span class="lineno"> 8650</span> <span class="comment">/* */</span></div>
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|
<div class="line"><a name="l08651"></a><span class="lineno"> 8651</span> <span class="comment">/******************************************************************************/</span></div>
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|
<div class="line"><a name="l08652"></a><span class="lineno"> 8652</span> <span class="comment">/******************** Bit definition for DBGMCU_IDCODE register *************/</span></div>
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|
<div class="line"><a name="l08653"></a><span class="lineno"> 8653</span> <span class="preprocessor">#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)</span></div>
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|
<div class="line"><a name="l08654"></a><span class="lineno"> 8654</span> <span class="preprocessor">#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)</span></div>
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|
<div class="line"><a name="l08655"></a><span class="lineno"> 8655</span> </div>
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|
<div class="line"><a name="l08656"></a><span class="lineno"> 8656</span> <span class="comment">/******************** Bit definition for DBGMCU_CR register *****************/</span></div>
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|
<div class="line"><a name="l08657"></a><span class="lineno"> 8657</span> <span class="preprocessor">#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)</span></div>
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|
<div class="line"><a name="l08658"></a><span class="lineno"> 8658</span> <span class="preprocessor">#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)</span></div>
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|
<div class="line"><a name="l08659"></a><span class="lineno"> 8659</span> <span class="preprocessor">#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)</span></div>
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|
<div class="line"><a name="l08660"></a><span class="lineno"> 8660</span> <span class="preprocessor">#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)</span></div>
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|
<div class="line"><a name="l08661"></a><span class="lineno"> 8661</span> </div>
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|
<div class="line"><a name="l08662"></a><span class="lineno"> 8662</span> <span class="preprocessor">#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)</span></div>
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|
<div class="line"><a name="l08663"></a><span class="lineno"> 8663</span> <span class="preprocessor">#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)</span></div>
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|
<div class="line"><a name="l08664"></a><span class="lineno"> 8664</span> <span class="preprocessor">#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)</span></div>
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|
<div class="line"><a name="l08666"></a><span class="lineno"><a class="line" href="group___peripheral___registers___bits___definition.html#ga7ba3a830051b53d43d850768242c503e"> 8666</a></span> <span class="preprocessor"></span><span class="comment">/******************** Bit definition for DBGMCU_APB1_FZ register ************/</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08667"></a><span class="lineno"> 8667</span> <span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)</span></div>
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|
<div class="line"><a name="l08668"></a><span class="lineno"> 8668</span> <span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)</span></div>
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|
<div class="line"><a name="l08669"></a><span class="lineno"> 8669</span> <span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)</span></div>
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|
<div class="line"><a name="l08670"></a><span class="lineno"> 8670</span> <span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)</span></div>
|
|
<div class="line"><a name="l08671"></a><span class="lineno"> 8671</span> <span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)</span></div>
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|
<div class="line"><a name="l08672"></a><span class="lineno"> 8672</span> <span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)</span></div>
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|
<div class="line"><a name="l08673"></a><span class="lineno"> 8673</span> <span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)</span></div>
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|
<div class="line"><a name="l08674"></a><span class="lineno"> 8674</span> <span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)</span></div>
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|
<div class="line"><a name="l08675"></a><span class="lineno"> 8675</span> <span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)</span></div>
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|
<div class="line"><a name="l08676"></a><span class="lineno"> 8676</span> <span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)</span></div>
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|
<div class="line"><a name="l08677"></a><span class="lineno"> 8677</span> <span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)</span></div>
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|
<div class="line"><a name="l08678"></a><span class="lineno"> 8678</span> <span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)</span></div>
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|
<div class="line"><a name="l08679"></a><span class="lineno"> 8679</span> <span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)</span></div>
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|
<div class="line"><a name="l08680"></a><span class="lineno"> 8680</span> <span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)</span></div>
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|
<div class="line"><a name="l08681"></a><span class="lineno"> 8681</span> <span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)</span></div>
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|
<div class="line"><a name="l08682"></a><span class="lineno"> 8682</span> <span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)</span></div>
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|
<div class="line"><a name="l08683"></a><span class="lineno"> 8683</span> <span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)</span></div>
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|
<div class="line"><a name="l08684"></a><span class="lineno"> 8684</span> <span class="comment">/* Old IWDGSTOP bit definition, maintained for legacy purpose */</span></div>
|
|
<div class="line"><a name="l08685"></a><span class="lineno"> 8685</span> <span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP</span></div>
|
|
<div class="line"><a name="l08686"></a><span class="lineno"> 8686</span> </div>
|
|
<div class="line"><a name="l08687"></a><span class="lineno"> 8687</span> <span class="comment">/******************** Bit definition for DBGMCU_APB1_FZ register ************/</span></div>
|
|
<div class="line"><a name="l08688"></a><span class="lineno"> 8688</span> <span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)</span></div>
|
|
<div class="line"><a name="l08689"></a><span class="lineno"> 8689</span> <span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)</span></div>
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|
<div class="line"><a name="l08690"></a><span class="lineno"> 8690</span> <span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)</span></div>
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|
<div class="line"><a name="l08691"></a><span class="lineno"> 8691</span> <span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)</span></div>
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|
<div class="line"><a name="l08692"></a><span class="lineno"> 8692</span> <span class="preprocessor">#define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)</span></div>
|
|
<div class="line"><a name="l08693"></a><span class="lineno"> 8693</span> </div>
|
|
<div class="line"><a name="l08694"></a><span class="lineno"> 8694</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l08695"></a><span class="lineno"> 8695</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l08696"></a><span class="lineno"> 8696</span> <span class="comment">/* Ethernet MAC Registers bits definitions */</span></div>
|
|
<div class="line"><a name="l08697"></a><span class="lineno"> 8697</span> <span class="comment">/* */</span></div>
|
|
<div class="line"><a name="l08698"></a><span class="lineno"> 8698</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l08699"></a><span class="lineno"> 8699</span> <span class="comment">/* Bit definition for Ethernet MAC Control Register register */</span></div>
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|
<div class="line"><a name="l08700"></a><span class="lineno"> 8700</span> <span class="preprocessor">#define ETH_MACCR_WD ((uint32_t)0x00800000) </span><span class="comment">/* Watchdog disable */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08701"></a><span class="lineno"> 8701</span> <span class="preprocessor">#define ETH_MACCR_JD ((uint32_t)0x00400000) </span><span class="comment">/* Jabber disable */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08702"></a><span class="lineno"> 8702</span> <span class="preprocessor">#define ETH_MACCR_IFG ((uint32_t)0x000E0000) </span><span class="comment">/* Inter-frame gap */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08703"></a><span class="lineno"> 8703</span> <span class="preprocessor">#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) </span><span class="comment">/* Minimum IFG between frames during transmission is 96Bit */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08704"></a><span class="lineno"> 8704</span> <span class="preprocessor"> #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) </span><span class="comment">/* Minimum IFG between frames during transmission is 88Bit */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08705"></a><span class="lineno"> 8705</span> <span class="preprocessor"> #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) </span><span class="comment">/* Minimum IFG between frames during transmission is 80Bit */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08706"></a><span class="lineno"> 8706</span> <span class="preprocessor"> #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) </span><span class="comment">/* Minimum IFG between frames during transmission is 72Bit */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08707"></a><span class="lineno"> 8707</span> <span class="preprocessor"> #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) </span><span class="comment">/* Minimum IFG between frames during transmission is 64Bit */</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l08708"></a><span class="lineno"> 8708</span> <span class="preprocessor"> #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) </span><span class="comment">/* Minimum IFG between frames during transmission is 56Bit */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08709"></a><span class="lineno"> 8709</span> <span class="preprocessor"> #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) </span><span class="comment">/* Minimum IFG between frames during transmission is 48Bit */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08710"></a><span class="lineno"> 8710</span> <span class="preprocessor"> #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) </span><span class="comment">/* Minimum IFG between frames during transmission is 40Bit */</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l08711"></a><span class="lineno"> 8711</span> <span class="preprocessor">#define ETH_MACCR_CSD ((uint32_t)0x00010000) </span><span class="comment">/* Carrier sense disable (during transmission) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08712"></a><span class="lineno"> 8712</span> <span class="preprocessor">#define ETH_MACCR_FES ((uint32_t)0x00004000) </span><span class="comment">/* Fast ethernet speed */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08713"></a><span class="lineno"> 8713</span> <span class="preprocessor">#define ETH_MACCR_ROD ((uint32_t)0x00002000) </span><span class="comment">/* Receive own disable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08714"></a><span class="lineno"> 8714</span> <span class="preprocessor">#define ETH_MACCR_LM ((uint32_t)0x00001000) </span><span class="comment">/* loopback mode */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08715"></a><span class="lineno"> 8715</span> <span class="preprocessor">#define ETH_MACCR_DM ((uint32_t)0x00000800) </span><span class="comment">/* Duplex mode */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08716"></a><span class="lineno"> 8716</span> <span class="preprocessor">#define ETH_MACCR_IPCO ((uint32_t)0x00000400) </span><span class="comment">/* IP Checksum offload */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08717"></a><span class="lineno"> 8717</span> <span class="preprocessor">#define ETH_MACCR_RD ((uint32_t)0x00000200) </span><span class="comment">/* Retry disable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08718"></a><span class="lineno"> 8718</span> <span class="preprocessor">#define ETH_MACCR_APCS ((uint32_t)0x00000080) </span><span class="comment">/* Automatic Pad/CRC stripping */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08719"></a><span class="lineno"> 8719</span> <span class="preprocessor">#define ETH_MACCR_BL ((uint32_t)0x00000060) </span><span class="comment">/* Back-off limit: random integer number (r) of slot time delays before rescheduling</span></div>
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<div class="line"><a name="l08720"></a><span class="lineno"> 8720</span> <span class="comment"> a transmission attempt during retries after a collision: 0 =< r <2^k */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08721"></a><span class="lineno"> 8721</span> <span class="preprocessor"> #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) </span><span class="comment">/* k = min (n, 10) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08722"></a><span class="lineno"> 8722</span> <span class="preprocessor"> #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) </span><span class="comment">/* k = min (n, 8) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08723"></a><span class="lineno"> 8723</span> <span class="preprocessor"> #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) </span><span class="comment">/* k = min (n, 4) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08724"></a><span class="lineno"> 8724</span> <span class="preprocessor"> #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) </span><span class="comment">/* k = min (n, 1) */</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l08725"></a><span class="lineno"> 8725</span> <span class="preprocessor">#define ETH_MACCR_DC ((uint32_t)0x00000010) </span><span class="comment">/* Defferal check */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08726"></a><span class="lineno"> 8726</span> <span class="preprocessor">#define ETH_MACCR_TE ((uint32_t)0x00000008) </span><span class="comment">/* Transmitter enable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08727"></a><span class="lineno"> 8727</span> <span class="preprocessor">#define ETH_MACCR_RE ((uint32_t)0x00000004) </span><span class="comment">/* Receiver enable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08728"></a><span class="lineno"> 8728</span> </div>
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<div class="line"><a name="l08729"></a><span class="lineno"> 8729</span> <span class="comment">/* Bit definition for Ethernet MAC Frame Filter Register */</span></div>
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<div class="line"><a name="l08730"></a><span class="lineno"> 8730</span> <span class="preprocessor">#define ETH_MACFFR_RA ((uint32_t)0x80000000) </span><span class="comment">/* Receive all */</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l08731"></a><span class="lineno"> 8731</span> <span class="preprocessor">#define ETH_MACFFR_HPF ((uint32_t)0x00000400) </span><span class="comment">/* Hash or perfect filter */</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l08732"></a><span class="lineno"> 8732</span> <span class="preprocessor">#define ETH_MACFFR_SAF ((uint32_t)0x00000200) </span><span class="comment">/* Source address filter enable */</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l08733"></a><span class="lineno"> 8733</span> <span class="preprocessor">#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) </span><span class="comment">/* SA inverse filtering */</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l08734"></a><span class="lineno"> 8734</span> <span class="preprocessor">#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) </span><span class="comment">/* Pass control frames: 3 cases */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08735"></a><span class="lineno"> 8735</span> <span class="preprocessor"> #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) </span><span class="comment">/* MAC filters all control frames from reaching the application */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08736"></a><span class="lineno"> 8736</span> <span class="preprocessor"> #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) </span><span class="comment">/* MAC forwards all control frames to application even if they fail the Address Filter */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08737"></a><span class="lineno"> 8737</span> <span class="preprocessor"> #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) </span><span class="comment">/* MAC forwards control frames that pass the Address Filter. */</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l08738"></a><span class="lineno"> 8738</span> <span class="preprocessor">#define ETH_MACFFR_BFD ((uint32_t)0x00000020) </span><span class="comment">/* Broadcast frame disable */</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l08739"></a><span class="lineno"> 8739</span> <span class="preprocessor">#define ETH_MACFFR_PAM ((uint32_t)0x00000010) </span><span class="comment">/* Pass all mutlicast */</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l08740"></a><span class="lineno"> 8740</span> <span class="preprocessor">#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) </span><span class="comment">/* DA Inverse filtering */</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l08741"></a><span class="lineno"> 8741</span> <span class="preprocessor">#define ETH_MACFFR_HM ((uint32_t)0x00000004) </span><span class="comment">/* Hash multicast */</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l08742"></a><span class="lineno"> 8742</span> <span class="preprocessor">#define ETH_MACFFR_HU ((uint32_t)0x00000002) </span><span class="comment">/* Hash unicast */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08743"></a><span class="lineno"> 8743</span> <span class="preprocessor">#define ETH_MACFFR_PM ((uint32_t)0x00000001) </span><span class="comment">/* Promiscuous mode */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08744"></a><span class="lineno"> 8744</span> </div>
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<div class="line"><a name="l08745"></a><span class="lineno"> 8745</span> <span class="comment">/* Bit definition for Ethernet MAC Hash Table High Register */</span></div>
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<div class="line"><a name="l08746"></a><span class="lineno"> 8746</span> <span class="preprocessor">#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* Hash table high */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08747"></a><span class="lineno"> 8747</span> </div>
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|
<div class="line"><a name="l08748"></a><span class="lineno"> 8748</span> <span class="comment">/* Bit definition for Ethernet MAC Hash Table Low Register */</span></div>
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|
<div class="line"><a name="l08749"></a><span class="lineno"> 8749</span> <span class="preprocessor">#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* Hash table low */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08750"></a><span class="lineno"> 8750</span> </div>
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|
<div class="line"><a name="l08751"></a><span class="lineno"> 8751</span> <span class="comment">/* Bit definition for Ethernet MAC MII Address Register */</span></div>
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|
<div class="line"><a name="l08752"></a><span class="lineno"> 8752</span> <span class="preprocessor">#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) </span><span class="comment">/* Physical layer address */</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l08753"></a><span class="lineno"> 8753</span> <span class="preprocessor">#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) </span><span class="comment">/* MII register in the selected PHY */</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l08754"></a><span class="lineno"> 8754</span> <span class="preprocessor">#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) </span><span class="comment">/* CR clock range: 6 cases */</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l08755"></a><span class="lineno"> 8755</span> <span class="preprocessor"> #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) </span><span class="comment">/* HCLK:60-100 MHz; MDC clock= HCLK/42 */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08756"></a><span class="lineno"> 8756</span> <span class="preprocessor"> #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) </span><span class="comment">/* HCLK:100-150 MHz; MDC clock= HCLK/62 */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08757"></a><span class="lineno"> 8757</span> <span class="preprocessor"> #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) </span><span class="comment">/* HCLK:20-35 MHz; MDC clock= HCLK/16 */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08758"></a><span class="lineno"> 8758</span> <span class="preprocessor"> #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) </span><span class="comment">/* HCLK:35-60 MHz; MDC clock= HCLK/26 */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08759"></a><span class="lineno"> 8759</span> <span class="preprocessor"> #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) </span><span class="comment">/* HCLK:150-168 MHz; MDC clock= HCLK/102 */</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l08760"></a><span class="lineno"> 8760</span> <span class="preprocessor">#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) </span><span class="comment">/* MII write */</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l08761"></a><span class="lineno"> 8761</span> <span class="preprocessor">#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) </span><span class="comment">/* MII busy */</span><span class="preprocessor"> </span></div>
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|
<div class="line"><a name="l08762"></a><span class="lineno"> 8762</span>  </div>
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|
<div class="line"><a name="l08763"></a><span class="lineno"> 8763</span> <span class="comment">/* Bit definition for Ethernet MAC MII Data Register */</span></div>
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|
<div class="line"><a name="l08764"></a><span class="lineno"> 8764</span> <span class="preprocessor">#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) </span><span class="comment">/* MII data: read/write data from/to PHY */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08765"></a><span class="lineno"> 8765</span> </div>
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|
<div class="line"><a name="l08766"></a><span class="lineno"> 8766</span> <span class="comment">/* Bit definition for Ethernet MAC Flow Control Register */</span></div>
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|
<div class="line"><a name="l08767"></a><span class="lineno"> 8767</span> <span class="preprocessor">#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) </span><span class="comment">/* Pause time */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08768"></a><span class="lineno"> 8768</span> <span class="preprocessor">#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) </span><span class="comment">/* Zero-quanta pause disable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08769"></a><span class="lineno"> 8769</span> <span class="preprocessor">#define ETH_MACFCR_PLT ((uint32_t)0x00000030) </span><span class="comment">/* Pause low threshold: 4 cases */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08770"></a><span class="lineno"> 8770</span> <span class="preprocessor"> #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) </span><span class="comment">/* Pause time minus 4 slot times */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08771"></a><span class="lineno"> 8771</span> <span class="preprocessor"> #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) </span><span class="comment">/* Pause time minus 28 slot times */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08772"></a><span class="lineno"> 8772</span> <span class="preprocessor"> #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) </span><span class="comment">/* Pause time minus 144 slot times */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08773"></a><span class="lineno"> 8773</span> <span class="preprocessor"> #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) </span><span class="comment">/* Pause time minus 256 slot times */</span><span class="preprocessor"> </span></div>
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<div class="line"><a name="l08774"></a><span class="lineno"> 8774</span> <span class="preprocessor">#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) </span><span class="comment">/* Unicast pause frame detect */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08775"></a><span class="lineno"> 8775</span> <span class="preprocessor">#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) </span><span class="comment">/* Receive flow control enable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08776"></a><span class="lineno"> 8776</span> <span class="preprocessor">#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) </span><span class="comment">/* Transmit flow control enable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08777"></a><span class="lineno"> 8777</span> <span class="preprocessor">#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) </span><span class="comment">/* Flow control busy/backpressure activate */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08778"></a><span class="lineno"> 8778</span> </div>
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|
<div class="line"><a name="l08779"></a><span class="lineno"> 8779</span> <span class="comment">/* Bit definition for Ethernet MAC VLAN Tag Register */</span></div>
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|
<div class="line"><a name="l08780"></a><span class="lineno"> 8780</span> <span class="preprocessor">#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) </span><span class="comment">/* 12-bit VLAN tag comparison */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08781"></a><span class="lineno"> 8781</span> <span class="preprocessor">#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) </span><span class="comment">/* VLAN tag identifier (for receive frames) */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08782"></a><span class="lineno"> 8782</span> </div>
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|
<div class="line"><a name="l08783"></a><span class="lineno"> 8783</span> <span class="comment">/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */</span> </div>
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|
<div class="line"><a name="l08784"></a><span class="lineno"> 8784</span> <span class="preprocessor">#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* Wake-up frame filter register data */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08785"></a><span class="lineno"> 8785</span> <span class="comment">/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.</span></div>
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|
<div class="line"><a name="l08786"></a><span class="lineno"> 8786</span> <span class="comment"> Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */</span></div>
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|
<div class="line"><a name="l08787"></a><span class="lineno"> 8787</span> <span class="comment">/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask</span></div>
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|
<div class="line"><a name="l08788"></a><span class="lineno"> 8788</span> <span class="comment"> Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask</span></div>
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|
<div class="line"><a name="l08789"></a><span class="lineno"> 8789</span> <span class="comment"> Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask</span></div>
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|
<div class="line"><a name="l08790"></a><span class="lineno"> 8790</span> <span class="comment"> Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask</span></div>
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|
<div class="line"><a name="l08791"></a><span class="lineno"> 8791</span> <span class="comment"> Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - </span></div>
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|
<div class="line"><a name="l08792"></a><span class="lineno"> 8792</span> <span class="comment"> RSVD - Filter1 Command - RSVD - Filter0 Command</span></div>
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|
<div class="line"><a name="l08793"></a><span class="lineno"> 8793</span> <span class="comment"> Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset</span></div>
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|
<div class="line"><a name="l08794"></a><span class="lineno"> 8794</span> <span class="comment"> Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16</span></div>
|
|
<div class="line"><a name="l08795"></a><span class="lineno"> 8795</span> <span class="comment"> Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */</span></div>
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|
<div class="line"><a name="l08796"></a><span class="lineno"> 8796</span> </div>
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<div class="line"><a name="l08797"></a><span class="lineno"> 8797</span> <span class="comment">/* Bit definition for Ethernet MAC PMT Control and Status Register */</span> </div>
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<div class="line"><a name="l08798"></a><span class="lineno"> 8798</span> <span class="preprocessor">#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) </span><span class="comment">/* Wake-Up Frame Filter Register Pointer Reset */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08799"></a><span class="lineno"> 8799</span> <span class="preprocessor">#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) </span><span class="comment">/* Global Unicast */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08800"></a><span class="lineno"> 8800</span> <span class="preprocessor">#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) </span><span class="comment">/* Wake-Up Frame Received */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08801"></a><span class="lineno"> 8801</span> <span class="preprocessor">#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) </span><span class="comment">/* Magic Packet Received */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08802"></a><span class="lineno"> 8802</span> <span class="preprocessor">#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) </span><span class="comment">/* Wake-Up Frame Enable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08803"></a><span class="lineno"> 8803</span> <span class="preprocessor">#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) </span><span class="comment">/* Magic Packet Enable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08804"></a><span class="lineno"> 8804</span> <span class="preprocessor">#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) </span><span class="comment">/* Power Down */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08805"></a><span class="lineno"> 8805</span> </div>
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<div class="line"><a name="l08806"></a><span class="lineno"> 8806</span> <span class="comment">/* Bit definition for Ethernet MAC Status Register */</span></div>
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<div class="line"><a name="l08807"></a><span class="lineno"> 8807</span> <span class="preprocessor">#define ETH_MACSR_TSTS ((uint32_t)0x00000200) </span><span class="comment">/* Time stamp trigger status */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08808"></a><span class="lineno"> 8808</span> <span class="preprocessor">#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) </span><span class="comment">/* MMC transmit status */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08809"></a><span class="lineno"> 8809</span> <span class="preprocessor">#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) </span><span class="comment">/* MMC receive status */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08810"></a><span class="lineno"> 8810</span> <span class="preprocessor">#define ETH_MACSR_MMCS ((uint32_t)0x00000010) </span><span class="comment">/* MMC status */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08811"></a><span class="lineno"> 8811</span> <span class="preprocessor">#define ETH_MACSR_PMTS ((uint32_t)0x00000008) </span><span class="comment">/* PMT status */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08812"></a><span class="lineno"> 8812</span> </div>
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<div class="line"><a name="l08813"></a><span class="lineno"> 8813</span> <span class="comment">/* Bit definition for Ethernet MAC Interrupt Mask Register */</span></div>
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<div class="line"><a name="l08814"></a><span class="lineno"> 8814</span> <span class="preprocessor">#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) </span><span class="comment">/* Time stamp trigger interrupt mask */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08815"></a><span class="lineno"> 8815</span> <span class="preprocessor">#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) </span><span class="comment">/* PMT interrupt mask */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08816"></a><span class="lineno"> 8816</span> </div>
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<div class="line"><a name="l08817"></a><span class="lineno"> 8817</span> <span class="comment">/* Bit definition for Ethernet MAC Address0 High Register */</span></div>
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<div class="line"><a name="l08818"></a><span class="lineno"> 8818</span> <span class="preprocessor">#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) </span><span class="comment">/* MAC address0 high */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08819"></a><span class="lineno"> 8819</span> </div>
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<div class="line"><a name="l08820"></a><span class="lineno"> 8820</span> <span class="comment">/* Bit definition for Ethernet MAC Address0 Low Register */</span></div>
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<div class="line"><a name="l08821"></a><span class="lineno"> 8821</span> <span class="preprocessor">#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* MAC address0 low */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08822"></a><span class="lineno"> 8822</span> </div>
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<div class="line"><a name="l08823"></a><span class="lineno"> 8823</span> <span class="comment">/* Bit definition for Ethernet MAC Address1 High Register */</span></div>
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<div class="line"><a name="l08824"></a><span class="lineno"> 8824</span> <span class="preprocessor">#define ETH_MACA1HR_AE ((uint32_t)0x80000000) </span><span class="comment">/* Address enable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08825"></a><span class="lineno"> 8825</span> <span class="preprocessor">#define ETH_MACA1HR_SA ((uint32_t)0x40000000) </span><span class="comment">/* Source address */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08826"></a><span class="lineno"> 8826</span> <span class="preprocessor">#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) </span><span class="comment">/* Mask byte control: bits to mask for comparison of the MAC Address bytes */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08827"></a><span class="lineno"> 8827</span> <span class="preprocessor"> #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) </span><span class="comment">/* Mask MAC Address high reg bits [15:8] */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08828"></a><span class="lineno"> 8828</span> <span class="preprocessor"> #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) </span><span class="comment">/* Mask MAC Address high reg bits [7:0] */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08829"></a><span class="lineno"> 8829</span> <span class="preprocessor"> #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) </span><span class="comment">/* Mask MAC Address low reg bits [31:24] */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08830"></a><span class="lineno"> 8830</span> <span class="preprocessor"> #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) </span><span class="comment">/* Mask MAC Address low reg bits [23:16] */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l08831"></a><span class="lineno"> 8831</span> <span class="preprocessor"> #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) </span><span class="comment">/* Mask MAC Address low reg bits [15:8] */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08832"></a><span class="lineno"> 8832</span> <span class="preprocessor"> #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) </span><span class="comment">/* Mask MAC Address low reg bits [7:0] */</span><span class="preprocessor"> </span></div>
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|
<div class="line"><a name="l08833"></a><span class="lineno"> 8833</span> <span class="preprocessor">#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) </span><span class="comment">/* MAC address1 high */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08834"></a><span class="lineno"> 8834</span> </div>
|
|
<div class="line"><a name="l08835"></a><span class="lineno"> 8835</span> <span class="comment">/* Bit definition for Ethernet MAC Address1 Low Register */</span></div>
|
|
<div class="line"><a name="l08836"></a><span class="lineno"> 8836</span> <span class="preprocessor">#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* MAC address1 low */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08837"></a><span class="lineno"> 8837</span> </div>
|
|
<div class="line"><a name="l08838"></a><span class="lineno"> 8838</span> <span class="comment">/* Bit definition for Ethernet MAC Address2 High Register */</span></div>
|
|
<div class="line"><a name="l08839"></a><span class="lineno"> 8839</span> <span class="preprocessor">#define ETH_MACA2HR_AE ((uint32_t)0x80000000) </span><span class="comment">/* Address enable */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08840"></a><span class="lineno"> 8840</span> <span class="preprocessor">#define ETH_MACA2HR_SA ((uint32_t)0x40000000) </span><span class="comment">/* Source address */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08841"></a><span class="lineno"> 8841</span> <span class="preprocessor">#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) </span><span class="comment">/* Mask byte control */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08842"></a><span class="lineno"> 8842</span> <span class="preprocessor"> #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) </span><span class="comment">/* Mask MAC Address high reg bits [15:8] */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08843"></a><span class="lineno"> 8843</span> <span class="preprocessor"> #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) </span><span class="comment">/* Mask MAC Address high reg bits [7:0] */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08844"></a><span class="lineno"> 8844</span> <span class="preprocessor"> #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) </span><span class="comment">/* Mask MAC Address low reg bits [31:24] */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08845"></a><span class="lineno"> 8845</span> <span class="preprocessor"> #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) </span><span class="comment">/* Mask MAC Address low reg bits [23:16] */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08846"></a><span class="lineno"> 8846</span> <span class="preprocessor"> #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) </span><span class="comment">/* Mask MAC Address low reg bits [15:8] */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08847"></a><span class="lineno"> 8847</span> <span class="preprocessor"> #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) </span><span class="comment">/* Mask MAC Address low reg bits [70] */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08848"></a><span class="lineno"> 8848</span> <span class="preprocessor">#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) </span><span class="comment">/* MAC address1 high */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08849"></a><span class="lineno"> 8849</span> </div>
|
|
<div class="line"><a name="l08850"></a><span class="lineno"> 8850</span> <span class="comment">/* Bit definition for Ethernet MAC Address2 Low Register */</span></div>
|
|
<div class="line"><a name="l08851"></a><span class="lineno"> 8851</span> <span class="preprocessor">#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* MAC address2 low */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08852"></a><span class="lineno"> 8852</span> </div>
|
|
<div class="line"><a name="l08853"></a><span class="lineno"> 8853</span> <span class="comment">/* Bit definition for Ethernet MAC Address3 High Register */</span></div>
|
|
<div class="line"><a name="l08854"></a><span class="lineno"> 8854</span> <span class="preprocessor">#define ETH_MACA3HR_AE ((uint32_t)0x80000000) </span><span class="comment">/* Address enable */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08855"></a><span class="lineno"> 8855</span> <span class="preprocessor">#define ETH_MACA3HR_SA ((uint32_t)0x40000000) </span><span class="comment">/* Source address */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08856"></a><span class="lineno"> 8856</span> <span class="preprocessor">#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) </span><span class="comment">/* Mask byte control */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08857"></a><span class="lineno"> 8857</span> <span class="preprocessor"> #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) </span><span class="comment">/* Mask MAC Address high reg bits [15:8] */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08858"></a><span class="lineno"> 8858</span> <span class="preprocessor"> #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) </span><span class="comment">/* Mask MAC Address high reg bits [7:0] */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08859"></a><span class="lineno"> 8859</span> <span class="preprocessor"> #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) </span><span class="comment">/* Mask MAC Address low reg bits [31:24] */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08860"></a><span class="lineno"> 8860</span> <span class="preprocessor"> #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) </span><span class="comment">/* Mask MAC Address low reg bits [23:16] */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08861"></a><span class="lineno"> 8861</span> <span class="preprocessor"> #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) </span><span class="comment">/* Mask MAC Address low reg bits [15:8] */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08862"></a><span class="lineno"> 8862</span> <span class="preprocessor"> #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) </span><span class="comment">/* Mask MAC Address low reg bits [70] */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08863"></a><span class="lineno"> 8863</span> <span class="preprocessor">#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) </span><span class="comment">/* MAC address3 high */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08864"></a><span class="lineno"> 8864</span> </div>
|
|
<div class="line"><a name="l08865"></a><span class="lineno"> 8865</span> <span class="comment">/* Bit definition for Ethernet MAC Address3 Low Register */</span></div>
|
|
<div class="line"><a name="l08866"></a><span class="lineno"> 8866</span> <span class="preprocessor">#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* MAC address3 low */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08867"></a><span class="lineno"> 8867</span> </div>
|
|
<div class="line"><a name="l08868"></a><span class="lineno"> 8868</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l08869"></a><span class="lineno"> 8869</span> <span class="comment">/* Ethernet MMC Registers bits definition */</span></div>
|
|
<div class="line"><a name="l08870"></a><span class="lineno"> 8870</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l08871"></a><span class="lineno"> 8871</span> </div>
|
|
<div class="line"><a name="l08872"></a><span class="lineno"> 8872</span> <span class="comment">/* Bit definition for Ethernet MMC Contol Register */</span></div>
|
|
<div class="line"><a name="l08873"></a><span class="lineno"> 8873</span> <span class="preprocessor">#define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) </span><span class="comment">/* MMC counter Full-Half preset */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08874"></a><span class="lineno"> 8874</span> <span class="preprocessor">#define ETH_MMCCR_MCP ((uint32_t)0x00000010) </span><span class="comment">/* MMC counter preset */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08875"></a><span class="lineno"> 8875</span> <span class="preprocessor">#define ETH_MMCCR_MCF ((uint32_t)0x00000008) </span><span class="comment">/* MMC Counter Freeze */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08876"></a><span class="lineno"> 8876</span> <span class="preprocessor">#define ETH_MMCCR_ROR ((uint32_t)0x00000004) </span><span class="comment">/* Reset on Read */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08877"></a><span class="lineno"> 8877</span> <span class="preprocessor">#define ETH_MMCCR_CSR ((uint32_t)0x00000002) </span><span class="comment">/* Counter Stop Rollover */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08878"></a><span class="lineno"> 8878</span> <span class="preprocessor">#define ETH_MMCCR_CR ((uint32_t)0x00000001) </span><span class="comment">/* Counters Reset */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08879"></a><span class="lineno"> 8879</span> </div>
|
|
<div class="line"><a name="l08880"></a><span class="lineno"> 8880</span> <span class="comment">/* Bit definition for Ethernet MMC Receive Interrupt Register */</span></div>
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|
<div class="line"><a name="l08881"></a><span class="lineno"> 8881</span> <span class="preprocessor">#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) </span><span class="comment">/* Set when Rx good unicast frames counter reaches half the maximum value */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08882"></a><span class="lineno"> 8882</span> <span class="preprocessor">#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) </span><span class="comment">/* Set when Rx alignment error counter reaches half the maximum value */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08883"></a><span class="lineno"> 8883</span> <span class="preprocessor">#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) </span><span class="comment">/* Set when Rx crc error counter reaches half the maximum value */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08884"></a><span class="lineno"> 8884</span> </div>
|
|
<div class="line"><a name="l08885"></a><span class="lineno"> 8885</span> <span class="comment">/* Bit definition for Ethernet MMC Transmit Interrupt Register */</span></div>
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|
<div class="line"><a name="l08886"></a><span class="lineno"> 8886</span> <span class="preprocessor">#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) </span><span class="comment">/* Set when Tx good frame count counter reaches half the maximum value */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08887"></a><span class="lineno"> 8887</span> <span class="preprocessor">#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) </span><span class="comment">/* Set when Tx good multi col counter reaches half the maximum value */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08888"></a><span class="lineno"> 8888</span> <span class="preprocessor">#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) </span><span class="comment">/* Set when Tx good single col counter reaches half the maximum value */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08889"></a><span class="lineno"> 8889</span> </div>
|
|
<div class="line"><a name="l08890"></a><span class="lineno"> 8890</span> <span class="comment">/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */</span></div>
|
|
<div class="line"><a name="l08891"></a><span class="lineno"> 8891</span> <span class="preprocessor">#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) </span><span class="comment">/* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08892"></a><span class="lineno"> 8892</span> <span class="preprocessor">#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) </span><span class="comment">/* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08893"></a><span class="lineno"> 8893</span> <span class="preprocessor">#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) </span><span class="comment">/* Mask the interrupt when Rx crc error counter reaches half the maximum value */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08894"></a><span class="lineno"> 8894</span> </div>
|
|
<div class="line"><a name="l08895"></a><span class="lineno"> 8895</span> <span class="comment">/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */</span></div>
|
|
<div class="line"><a name="l08896"></a><span class="lineno"> 8896</span> <span class="preprocessor">#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) </span><span class="comment">/* Mask the interrupt when Tx good frame count counter reaches half the maximum value */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08897"></a><span class="lineno"> 8897</span> <span class="preprocessor">#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) </span><span class="comment">/* Mask the interrupt when Tx good multi col counter reaches half the maximum value */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08898"></a><span class="lineno"> 8898</span> <span class="preprocessor">#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) </span><span class="comment">/* Mask the interrupt when Tx good single col counter reaches half the maximum value */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08899"></a><span class="lineno"> 8899</span> </div>
|
|
<div class="line"><a name="l08900"></a><span class="lineno"> 8900</span> <span class="comment">/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */</span></div>
|
|
<div class="line"><a name="l08901"></a><span class="lineno"> 8901</span> <span class="preprocessor">#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* Number of successfully transmitted frames after a single collision in Half-duplex mode. */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08902"></a><span class="lineno"> 8902</span> </div>
|
|
<div class="line"><a name="l08903"></a><span class="lineno"> 8903</span> <span class="comment">/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */</span></div>
|
|
<div class="line"><a name="l08904"></a><span class="lineno"> 8904</span> <span class="preprocessor">#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08905"></a><span class="lineno"> 8905</span> </div>
|
|
<div class="line"><a name="l08906"></a><span class="lineno"> 8906</span> <span class="comment">/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */</span></div>
|
|
<div class="line"><a name="l08907"></a><span class="lineno"> 8907</span> <span class="preprocessor">#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* Number of good frames transmitted. */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08908"></a><span class="lineno"> 8908</span> </div>
|
|
<div class="line"><a name="l08909"></a><span class="lineno"> 8909</span> <span class="comment">/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */</span></div>
|
|
<div class="line"><a name="l08910"></a><span class="lineno"> 8910</span> <span class="preprocessor">#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* Number of frames received with CRC error. */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08911"></a><span class="lineno"> 8911</span> </div>
|
|
<div class="line"><a name="l08912"></a><span class="lineno"> 8912</span> <span class="comment">/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */</span></div>
|
|
<div class="line"><a name="l08913"></a><span class="lineno"> 8913</span> <span class="preprocessor">#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* Number of frames received with alignment (dribble) error */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08914"></a><span class="lineno"> 8914</span> </div>
|
|
<div class="line"><a name="l08915"></a><span class="lineno"> 8915</span> <span class="comment">/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */</span></div>
|
|
<div class="line"><a name="l08916"></a><span class="lineno"> 8916</span> <span class="preprocessor">#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* Number of good unicast frames received. */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08917"></a><span class="lineno"> 8917</span> </div>
|
|
<div class="line"><a name="l08918"></a><span class="lineno"> 8918</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l08919"></a><span class="lineno"> 8919</span> <span class="comment">/* Ethernet PTP Registers bits definition */</span></div>
|
|
<div class="line"><a name="l08920"></a><span class="lineno"> 8920</span> <span class="comment">/******************************************************************************/</span></div>
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|
<div class="line"><a name="l08921"></a><span class="lineno"> 8921</span> </div>
|
|
<div class="line"><a name="l08922"></a><span class="lineno"> 8922</span> <span class="comment">/* Bit definition for Ethernet PTP Time Stamp Contol Register */</span></div>
|
|
<div class="line"><a name="l08923"></a><span class="lineno"> 8923</span> <span class="preprocessor">#define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) </span><span class="comment">/* Time stamp clock node type */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08924"></a><span class="lineno"> 8924</span> <span class="preprocessor">#define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) </span><span class="comment">/* Time stamp snapshot for message relevant to master enable */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08925"></a><span class="lineno"> 8925</span> <span class="preprocessor">#define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) </span><span class="comment">/* Time stamp snapshot for event message enable */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08926"></a><span class="lineno"> 8926</span> <span class="preprocessor">#define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) </span><span class="comment">/* Time stamp snapshot for IPv4 frames enable */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08927"></a><span class="lineno"> 8927</span> <span class="preprocessor">#define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) </span><span class="comment">/* Time stamp snapshot for IPv6 frames enable */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08928"></a><span class="lineno"> 8928</span> <span class="preprocessor">#define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) </span><span class="comment">/* Time stamp snapshot for PTP over ethernet frames enable */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08929"></a><span class="lineno"> 8929</span> <span class="preprocessor">#define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) </span><span class="comment">/* Time stamp PTP packet snooping for version2 format enable */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08930"></a><span class="lineno"> 8930</span> <span class="preprocessor">#define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) </span><span class="comment">/* Time stamp Sub-seconds rollover */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08931"></a><span class="lineno"> 8931</span> <span class="preprocessor">#define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) </span><span class="comment">/* Time stamp snapshot for all received frames enable */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08932"></a><span class="lineno"> 8932</span> </div>
|
|
<div class="line"><a name="l08933"></a><span class="lineno"> 8933</span> <span class="preprocessor">#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) </span><span class="comment">/* Addend register update */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08934"></a><span class="lineno"> 8934</span> <span class="preprocessor">#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) </span><span class="comment">/* Time stamp interrupt trigger enable */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08935"></a><span class="lineno"> 8935</span> <span class="preprocessor">#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) </span><span class="comment">/* Time stamp update */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l08936"></a><span class="lineno"> 8936</span> <span class="preprocessor">#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) </span><span class="comment">/* Time stamp initialize */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08937"></a><span class="lineno"> 8937</span> <span class="preprocessor">#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) </span><span class="comment">/* Time stamp fine or coarse update */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08938"></a><span class="lineno"> 8938</span> <span class="preprocessor">#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) </span><span class="comment">/* Time stamp enable */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08939"></a><span class="lineno"> 8939</span> </div>
|
|
<div class="line"><a name="l08940"></a><span class="lineno"> 8940</span> <span class="comment">/* Bit definition for Ethernet PTP Sub-Second Increment Register */</span></div>
|
|
<div class="line"><a name="l08941"></a><span class="lineno"> 8941</span> <span class="preprocessor">#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) </span><span class="comment">/* System time Sub-second increment value */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08942"></a><span class="lineno"> 8942</span> </div>
|
|
<div class="line"><a name="l08943"></a><span class="lineno"> 8943</span> <span class="comment">/* Bit definition for Ethernet PTP Time Stamp High Register */</span></div>
|
|
<div class="line"><a name="l08944"></a><span class="lineno"> 8944</span> <span class="preprocessor">#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* System Time second */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08945"></a><span class="lineno"> 8945</span> </div>
|
|
<div class="line"><a name="l08946"></a><span class="lineno"> 8946</span> <span class="comment">/* Bit definition for Ethernet PTP Time Stamp Low Register */</span></div>
|
|
<div class="line"><a name="l08947"></a><span class="lineno"> 8947</span> <span class="preprocessor">#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) </span><span class="comment">/* System Time Positive or negative time */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08948"></a><span class="lineno"> 8948</span> <span class="preprocessor">#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) </span><span class="comment">/* System Time sub-seconds */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08949"></a><span class="lineno"> 8949</span> </div>
|
|
<div class="line"><a name="l08950"></a><span class="lineno"> 8950</span> <span class="comment">/* Bit definition for Ethernet PTP Time Stamp High Update Register */</span></div>
|
|
<div class="line"><a name="l08951"></a><span class="lineno"> 8951</span> <span class="preprocessor">#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* Time stamp update seconds */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08952"></a><span class="lineno"> 8952</span> </div>
|
|
<div class="line"><a name="l08953"></a><span class="lineno"> 8953</span> <span class="comment">/* Bit definition for Ethernet PTP Time Stamp Low Update Register */</span></div>
|
|
<div class="line"><a name="l08954"></a><span class="lineno"> 8954</span> <span class="preprocessor">#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) </span><span class="comment">/* Time stamp update Positive or negative time */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08955"></a><span class="lineno"> 8955</span> <span class="preprocessor">#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) </span><span class="comment">/* Time stamp update sub-seconds */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08956"></a><span class="lineno"> 8956</span> </div>
|
|
<div class="line"><a name="l08957"></a><span class="lineno"> 8957</span> <span class="comment">/* Bit definition for Ethernet PTP Time Stamp Addend Register */</span></div>
|
|
<div class="line"><a name="l08958"></a><span class="lineno"> 8958</span> <span class="preprocessor">#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* Time stamp addend */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08959"></a><span class="lineno"> 8959</span> </div>
|
|
<div class="line"><a name="l08960"></a><span class="lineno"> 8960</span> <span class="comment">/* Bit definition for Ethernet PTP Target Time High Register */</span></div>
|
|
<div class="line"><a name="l08961"></a><span class="lineno"> 8961</span> <span class="preprocessor">#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* Target time stamp high */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08962"></a><span class="lineno"> 8962</span> </div>
|
|
<div class="line"><a name="l08963"></a><span class="lineno"> 8963</span> <span class="comment">/* Bit definition for Ethernet PTP Target Time Low Register */</span></div>
|
|
<div class="line"><a name="l08964"></a><span class="lineno"> 8964</span> <span class="preprocessor">#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* Target time stamp low */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08965"></a><span class="lineno"> 8965</span> </div>
|
|
<div class="line"><a name="l08966"></a><span class="lineno"> 8966</span> <span class="comment">/* Bit definition for Ethernet PTP Time Stamp Status Register */</span></div>
|
|
<div class="line"><a name="l08967"></a><span class="lineno"> 8967</span> <span class="preprocessor">#define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) </span><span class="comment">/* Time stamp target time reached */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08968"></a><span class="lineno"> 8968</span> <span class="preprocessor">#define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) </span><span class="comment">/* Time stamp seconds overflow */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08969"></a><span class="lineno"> 8969</span> </div>
|
|
<div class="line"><a name="l08970"></a><span class="lineno"> 8970</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l08971"></a><span class="lineno"> 8971</span> <span class="comment">/* Ethernet DMA Registers bits definition */</span></div>
|
|
<div class="line"><a name="l08972"></a><span class="lineno"> 8972</span> <span class="comment">/******************************************************************************/</span></div>
|
|
<div class="line"><a name="l08973"></a><span class="lineno"> 8973</span> </div>
|
|
<div class="line"><a name="l08974"></a><span class="lineno"> 8974</span> <span class="comment">/* Bit definition for Ethernet DMA Bus Mode Register */</span></div>
|
|
<div class="line"><a name="l08975"></a><span class="lineno"> 8975</span> <span class="preprocessor">#define ETH_DMABMR_AAB ((uint32_t)0x02000000) </span><span class="comment">/* Address-Aligned beats */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08976"></a><span class="lineno"> 8976</span> <span class="preprocessor">#define ETH_DMABMR_FPM ((uint32_t)0x01000000) </span><span class="comment">/* 4xPBL mode */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08977"></a><span class="lineno"> 8977</span> <span class="preprocessor">#define ETH_DMABMR_USP ((uint32_t)0x00800000) </span><span class="comment">/* Use separate PBL */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08978"></a><span class="lineno"> 8978</span> <span class="preprocessor">#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) </span><span class="comment">/* RxDMA PBL */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08979"></a><span class="lineno"> 8979</span> <span class="preprocessor"> #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 1 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08980"></a><span class="lineno"> 8980</span> <span class="preprocessor"> #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 2 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08981"></a><span class="lineno"> 8981</span> <span class="preprocessor"> #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 4 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08982"></a><span class="lineno"> 8982</span> <span class="preprocessor"> #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 8 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08983"></a><span class="lineno"> 8983</span> <span class="preprocessor"> #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 16 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08984"></a><span class="lineno"> 8984</span> <span class="preprocessor"> #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 32 */</span><span class="preprocessor"> </span></div>
|
|
<div class="line"><a name="l08985"></a><span class="lineno"> 8985</span> <span class="preprocessor"> #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 4 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08986"></a><span class="lineno"> 8986</span> <span class="preprocessor"> #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 8 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08987"></a><span class="lineno"> 8987</span> <span class="preprocessor"> #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 16 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08988"></a><span class="lineno"> 8988</span> <span class="preprocessor"> #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 32 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08989"></a><span class="lineno"> 8989</span> <span class="preprocessor"> #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 64 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08990"></a><span class="lineno"> 8990</span> <span class="preprocessor"> #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) </span><span class="comment">/* maximum number of beats to be transferred in one RxDMA transaction is 128 */</span><span class="preprocessor"> </span></div>
|
|
<div class="line"><a name="l08991"></a><span class="lineno"> 8991</span> <span class="preprocessor">#define ETH_DMABMR_FB ((uint32_t)0x00010000) </span><span class="comment">/* Fixed Burst */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08992"></a><span class="lineno"> 8992</span> <span class="preprocessor">#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) </span><span class="comment">/* Rx Tx priority ratio */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08993"></a><span class="lineno"> 8993</span> <span class="preprocessor"> #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) </span><span class="comment">/* Rx Tx priority ratio */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08994"></a><span class="lineno"> 8994</span> <span class="preprocessor"> #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) </span><span class="comment">/* Rx Tx priority ratio */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08995"></a><span class="lineno"> 8995</span> <span class="preprocessor"> #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) </span><span class="comment">/* Rx Tx priority ratio */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08996"></a><span class="lineno"> 8996</span> <span class="preprocessor"> #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) </span><span class="comment">/* Rx Tx priority ratio */</span><span class="preprocessor"> </span></div>
|
|
<div class="line"><a name="l08997"></a><span class="lineno"> 8997</span> <span class="preprocessor">#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) </span><span class="comment">/* Programmable burst length */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08998"></a><span class="lineno"> 8998</span> <span class="preprocessor"> #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l08999"></a><span class="lineno"> 8999</span> <span class="preprocessor"> #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l09000"></a><span class="lineno"> 9000</span> <span class="preprocessor"> #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l09001"></a><span class="lineno"> 9001</span> <span class="preprocessor"> #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l09002"></a><span class="lineno"> 9002</span> <span class="preprocessor"> #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l09003"></a><span class="lineno"> 9003</span> <span class="preprocessor"> #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */</span><span class="preprocessor"> </span></div>
|
|
<div class="line"><a name="l09004"></a><span class="lineno"> 9004</span> <span class="preprocessor"> #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l09005"></a><span class="lineno"> 9005</span> <span class="preprocessor"> #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l09006"></a><span class="lineno"> 9006</span> <span class="preprocessor"> #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l09007"></a><span class="lineno"> 9007</span> <span class="preprocessor"> #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l09008"></a><span class="lineno"> 9008</span> <span class="preprocessor"> #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l09009"></a><span class="lineno"> 9009</span> <span class="preprocessor"> #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) </span><span class="comment">/* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l09010"></a><span class="lineno"> 9010</span> <span class="preprocessor">#define ETH_DMABMR_EDE ((uint32_t)0x00000080) </span><span class="comment">/* Enhanced Descriptor Enable */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l09011"></a><span class="lineno"> 9011</span> <span class="preprocessor">#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) </span><span class="comment">/* Descriptor Skip Length */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l09012"></a><span class="lineno"> 9012</span> <span class="preprocessor">#define ETH_DMABMR_DA ((uint32_t)0x00000002) </span><span class="comment">/* DMA arbitration scheme */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l09013"></a><span class="lineno"> 9013</span> <span class="preprocessor">#define ETH_DMABMR_SR ((uint32_t)0x00000001) </span><span class="comment">/* Software reset */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l09014"></a><span class="lineno"> 9014</span> </div>
|
|
<div class="line"><a name="l09015"></a><span class="lineno"> 9015</span> <span class="comment">/* Bit definition for Ethernet DMA Transmit Poll Demand Register */</span></div>
|
|
<div class="line"><a name="l09016"></a><span class="lineno"> 9016</span> <span class="preprocessor">#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* Transmit poll demand */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l09017"></a><span class="lineno"> 9017</span> </div>
|
|
<div class="line"><a name="l09018"></a><span class="lineno"> 9018</span> <span class="comment">/* Bit definition for Ethernet DMA Receive Poll Demand Register */</span></div>
|
|
<div class="line"><a name="l09019"></a><span class="lineno"> 9019</span> <span class="preprocessor">#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* Receive poll demand */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l09020"></a><span class="lineno"> 9020</span> </div>
|
|
<div class="line"><a name="l09021"></a><span class="lineno"> 9021</span> <span class="comment">/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */</span></div>
|
|
<div class="line"><a name="l09022"></a><span class="lineno"> 9022</span> <span class="preprocessor">#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* Start of receive list */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l09023"></a><span class="lineno"> 9023</span> </div>
|
|
<div class="line"><a name="l09024"></a><span class="lineno"> 9024</span> <span class="comment">/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */</span></div>
|
|
<div class="line"><a name="l09025"></a><span class="lineno"> 9025</span> <span class="preprocessor">#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* Start of transmit list */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l09026"></a><span class="lineno"> 9026</span> </div>
|
|
<div class="line"><a name="l09027"></a><span class="lineno"> 9027</span> <span class="comment">/* Bit definition for Ethernet DMA Status Register */</span></div>
|
|
<div class="line"><a name="l09028"></a><span class="lineno"> 9028</span> <span class="preprocessor">#define ETH_DMASR_TSTS ((uint32_t)0x20000000) </span><span class="comment">/* Time-stamp trigger status */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l09029"></a><span class="lineno"> 9029</span> <span class="preprocessor">#define ETH_DMASR_PMTS ((uint32_t)0x10000000) </span><span class="comment">/* PMT status */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l09030"></a><span class="lineno"> 9030</span> <span class="preprocessor">#define ETH_DMASR_MMCS ((uint32_t)0x08000000) </span><span class="comment">/* MMC status */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l09031"></a><span class="lineno"> 9031</span> <span class="preprocessor">#define ETH_DMASR_EBS ((uint32_t)0x03800000) </span><span class="comment">/* Error bits status */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l09032"></a><span class="lineno"> 9032</span>  <span class="comment">/* combination with EBS[2:0] for GetFlagStatus function */</span></div>
|
|
<div class="line"><a name="l09033"></a><span class="lineno"> 9033</span> <span class="preprocessor"> #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) </span><span class="comment">/* Error bits 0-data buffer, 1-desc. access */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l09034"></a><span class="lineno"> 9034</span> <span class="preprocessor"> #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) </span><span class="comment">/* Error bits 0-write trnsf, 1-read transfr */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l09035"></a><span class="lineno"> 9035</span> <span class="preprocessor"> #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) </span><span class="comment">/* Error bits 0-Rx DMA, 1-Tx DMA */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l09036"></a><span class="lineno"> 9036</span> <span class="preprocessor">#define ETH_DMASR_TPS ((uint32_t)0x00700000) </span><span class="comment">/* Transmit process state */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l09037"></a><span class="lineno"> 9037</span> <span class="preprocessor"> #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) </span><span class="comment">/* Stopped - Reset or Stop Tx Command issued */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09038"></a><span class="lineno"> 9038</span> <span class="preprocessor"> #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) </span><span class="comment">/* Running - fetching the Tx descriptor */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09039"></a><span class="lineno"> 9039</span> <span class="preprocessor"> #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) </span><span class="comment">/* Running - waiting for status */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09040"></a><span class="lineno"> 9040</span> <span class="preprocessor"> #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) </span><span class="comment">/* Running - reading the data from host memory */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09041"></a><span class="lineno"> 9041</span> <span class="preprocessor"> #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) </span><span class="comment">/* Suspended - Tx Descriptor unavailabe */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09042"></a><span class="lineno"> 9042</span> <span class="preprocessor"> #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) </span><span class="comment">/* Running - closing Rx descriptor */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09043"></a><span class="lineno"> 9043</span> <span class="preprocessor">#define ETH_DMASR_RPS ((uint32_t)0x000E0000) </span><span class="comment">/* Receive process state */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09044"></a><span class="lineno"> 9044</span> <span class="preprocessor"> #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) </span><span class="comment">/* Stopped - Reset or Stop Rx Command issued */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09045"></a><span class="lineno"> 9045</span> <span class="preprocessor"> #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) </span><span class="comment">/* Running - fetching the Rx descriptor */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09046"></a><span class="lineno"> 9046</span> <span class="preprocessor"> #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) </span><span class="comment">/* Running - waiting for packet */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09047"></a><span class="lineno"> 9047</span> <span class="preprocessor"> #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) </span><span class="comment">/* Suspended - Rx Descriptor unavailable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09048"></a><span class="lineno"> 9048</span> <span class="preprocessor"> #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) </span><span class="comment">/* Running - closing descriptor */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09049"></a><span class="lineno"> 9049</span> <span class="preprocessor"> #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) </span><span class="comment">/* Running - queuing the recieve frame into host memory */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09050"></a><span class="lineno"> 9050</span> <span class="preprocessor">#define ETH_DMASR_NIS ((uint32_t)0x00010000) </span><span class="comment">/* Normal interrupt summary */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09051"></a><span class="lineno"> 9051</span> <span class="preprocessor">#define ETH_DMASR_AIS ((uint32_t)0x00008000) </span><span class="comment">/* Abnormal interrupt summary */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09052"></a><span class="lineno"> 9052</span> <span class="preprocessor">#define ETH_DMASR_ERS ((uint32_t)0x00004000) </span><span class="comment">/* Early receive status */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09053"></a><span class="lineno"> 9053</span> <span class="preprocessor">#define ETH_DMASR_FBES ((uint32_t)0x00002000) </span><span class="comment">/* Fatal bus error status */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09054"></a><span class="lineno"> 9054</span> <span class="preprocessor">#define ETH_DMASR_ETS ((uint32_t)0x00000400) </span><span class="comment">/* Early transmit status */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09055"></a><span class="lineno"> 9055</span> <span class="preprocessor">#define ETH_DMASR_RWTS ((uint32_t)0x00000200) </span><span class="comment">/* Receive watchdog timeout status */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09056"></a><span class="lineno"> 9056</span> <span class="preprocessor">#define ETH_DMASR_RPSS ((uint32_t)0x00000100) </span><span class="comment">/* Receive process stopped status */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09057"></a><span class="lineno"> 9057</span> <span class="preprocessor">#define ETH_DMASR_RBUS ((uint32_t)0x00000080) </span><span class="comment">/* Receive buffer unavailable status */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09058"></a><span class="lineno"> 9058</span> <span class="preprocessor">#define ETH_DMASR_RS ((uint32_t)0x00000040) </span><span class="comment">/* Receive status */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09059"></a><span class="lineno"> 9059</span> <span class="preprocessor">#define ETH_DMASR_TUS ((uint32_t)0x00000020) </span><span class="comment">/* Transmit underflow status */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09060"></a><span class="lineno"> 9060</span> <span class="preprocessor">#define ETH_DMASR_ROS ((uint32_t)0x00000010) </span><span class="comment">/* Receive overflow status */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09061"></a><span class="lineno"> 9061</span> <span class="preprocessor">#define ETH_DMASR_TJTS ((uint32_t)0x00000008) </span><span class="comment">/* Transmit jabber timeout status */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09062"></a><span class="lineno"> 9062</span> <span class="preprocessor">#define ETH_DMASR_TBUS ((uint32_t)0x00000004) </span><span class="comment">/* Transmit buffer unavailable status */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09063"></a><span class="lineno"> 9063</span> <span class="preprocessor">#define ETH_DMASR_TPSS ((uint32_t)0x00000002) </span><span class="comment">/* Transmit process stopped status */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09064"></a><span class="lineno"> 9064</span> <span class="preprocessor">#define ETH_DMASR_TS ((uint32_t)0x00000001) </span><span class="comment">/* Transmit status */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09065"></a><span class="lineno"> 9065</span> </div>
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<div class="line"><a name="l09066"></a><span class="lineno"> 9066</span> <span class="comment">/* Bit definition for Ethernet DMA Operation Mode Register */</span></div>
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<div class="line"><a name="l09067"></a><span class="lineno"> 9067</span> <span class="preprocessor">#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) </span><span class="comment">/* Disable Dropping of TCP/IP checksum error frames */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09068"></a><span class="lineno"> 9068</span> <span class="preprocessor">#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) </span><span class="comment">/* Receive store and forward */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09069"></a><span class="lineno"> 9069</span> <span class="preprocessor">#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) </span><span class="comment">/* Disable flushing of received frames */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09070"></a><span class="lineno"> 9070</span> <span class="preprocessor">#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) </span><span class="comment">/* Transmit store and forward */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09071"></a><span class="lineno"> 9071</span> <span class="preprocessor">#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) </span><span class="comment">/* Flush transmit FIFO */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09072"></a><span class="lineno"> 9072</span> <span class="preprocessor">#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) </span><span class="comment">/* Transmit threshold control */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09073"></a><span class="lineno"> 9073</span> <span class="preprocessor"> #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) </span><span class="comment">/* threshold level of the MTL Transmit FIFO is 64 Bytes */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09074"></a><span class="lineno"> 9074</span> <span class="preprocessor"> #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) </span><span class="comment">/* threshold level of the MTL Transmit FIFO is 128 Bytes */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09075"></a><span class="lineno"> 9075</span> <span class="preprocessor"> #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) </span><span class="comment">/* threshold level of the MTL Transmit FIFO is 192 Bytes */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09076"></a><span class="lineno"> 9076</span> <span class="preprocessor"> #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) </span><span class="comment">/* threshold level of the MTL Transmit FIFO is 256 Bytes */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09077"></a><span class="lineno"> 9077</span> <span class="preprocessor"> #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) </span><span class="comment">/* threshold level of the MTL Transmit FIFO is 40 Bytes */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09078"></a><span class="lineno"> 9078</span> <span class="preprocessor"> #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) </span><span class="comment">/* threshold level of the MTL Transmit FIFO is 32 Bytes */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09079"></a><span class="lineno"> 9079</span> <span class="preprocessor"> #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) </span><span class="comment">/* threshold level of the MTL Transmit FIFO is 24 Bytes */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09080"></a><span class="lineno"> 9080</span> <span class="preprocessor"> #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) </span><span class="comment">/* threshold level of the MTL Transmit FIFO is 16 Bytes */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09081"></a><span class="lineno"> 9081</span> <span class="preprocessor">#define ETH_DMAOMR_ST ((uint32_t)0x00002000) </span><span class="comment">/* Start/stop transmission command */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09082"></a><span class="lineno"> 9082</span> <span class="preprocessor">#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) </span><span class="comment">/* Forward error frames */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09083"></a><span class="lineno"> 9083</span> <span class="preprocessor">#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) </span><span class="comment">/* Forward undersized good frames */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09084"></a><span class="lineno"> 9084</span> <span class="preprocessor">#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) </span><span class="comment">/* receive threshold control */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09085"></a><span class="lineno"> 9085</span> <span class="preprocessor"> #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) </span><span class="comment">/* threshold level of the MTL Receive FIFO is 64 Bytes */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09086"></a><span class="lineno"> 9086</span> <span class="preprocessor"> #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) </span><span class="comment">/* threshold level of the MTL Receive FIFO is 32 Bytes */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09087"></a><span class="lineno"> 9087</span> <span class="preprocessor"> #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) </span><span class="comment">/* threshold level of the MTL Receive FIFO is 96 Bytes */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09088"></a><span class="lineno"> 9088</span> <span class="preprocessor"> #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) </span><span class="comment">/* threshold level of the MTL Receive FIFO is 128 Bytes */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09089"></a><span class="lineno"> 9089</span> <span class="preprocessor">#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) </span><span class="comment">/* operate on second frame */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09090"></a><span class="lineno"> 9090</span> <span class="preprocessor">#define ETH_DMAOMR_SR ((uint32_t)0x00000002) </span><span class="comment">/* Start/stop receive */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09091"></a><span class="lineno"> 9091</span> </div>
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<div class="line"><a name="l09092"></a><span class="lineno"> 9092</span> <span class="comment">/* Bit definition for Ethernet DMA Interrupt Enable Register */</span></div>
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<div class="line"><a name="l09093"></a><span class="lineno"> 9093</span> <span class="preprocessor">#define ETH_DMAIER_NISE ((uint32_t)0x00010000) </span><span class="comment">/* Normal interrupt summary enable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09094"></a><span class="lineno"> 9094</span> <span class="preprocessor">#define ETH_DMAIER_AISE ((uint32_t)0x00008000) </span><span class="comment">/* Abnormal interrupt summary enable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09095"></a><span class="lineno"> 9095</span> <span class="preprocessor">#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) </span><span class="comment">/* Early receive interrupt enable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09096"></a><span class="lineno"> 9096</span> <span class="preprocessor">#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) </span><span class="comment">/* Fatal bus error interrupt enable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09097"></a><span class="lineno"> 9097</span> <span class="preprocessor">#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) </span><span class="comment">/* Early transmit interrupt enable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09098"></a><span class="lineno"> 9098</span> <span class="preprocessor">#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) </span><span class="comment">/* Receive watchdog timeout interrupt enable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09099"></a><span class="lineno"> 9099</span> <span class="preprocessor">#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) </span><span class="comment">/* Receive process stopped interrupt enable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09100"></a><span class="lineno"> 9100</span> <span class="preprocessor">#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) </span><span class="comment">/* Receive buffer unavailable interrupt enable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09101"></a><span class="lineno"> 9101</span> <span class="preprocessor">#define ETH_DMAIER_RIE ((uint32_t)0x00000040) </span><span class="comment">/* Receive interrupt enable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09102"></a><span class="lineno"> 9102</span> <span class="preprocessor">#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) </span><span class="comment">/* Transmit Underflow interrupt enable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09103"></a><span class="lineno"> 9103</span> <span class="preprocessor">#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) </span><span class="comment">/* Receive Overflow interrupt enable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09104"></a><span class="lineno"> 9104</span> <span class="preprocessor">#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) </span><span class="comment">/* Transmit jabber timeout interrupt enable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09105"></a><span class="lineno"> 9105</span> <span class="preprocessor">#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) </span><span class="comment">/* Transmit buffer unavailable interrupt enable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09106"></a><span class="lineno"> 9106</span> <span class="preprocessor">#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) </span><span class="comment">/* Transmit process stopped interrupt enable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09107"></a><span class="lineno"> 9107</span> <span class="preprocessor">#define ETH_DMAIER_TIE ((uint32_t)0x00000001) </span><span class="comment">/* Transmit interrupt enable */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09108"></a><span class="lineno"> 9108</span> </div>
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<div class="line"><a name="l09109"></a><span class="lineno"> 9109</span> <span class="comment">/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */</span></div>
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<div class="line"><a name="l09110"></a><span class="lineno"> 9110</span> <span class="preprocessor">#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) </span><span class="comment">/* Overflow bit for FIFO overflow counter */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09111"></a><span class="lineno"> 9111</span> <span class="preprocessor">#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) </span><span class="comment">/* Number of frames missed by the application */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09112"></a><span class="lineno"> 9112</span> <span class="preprocessor">#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) </span><span class="comment">/* Overflow bit for missed frame counter */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09113"></a><span class="lineno"> 9113</span> <span class="preprocessor">#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) </span><span class="comment">/* Number of frames missed by the controller */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09114"></a><span class="lineno"> 9114</span> </div>
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<div class="line"><a name="l09115"></a><span class="lineno"> 9115</span> <span class="comment">/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */</span></div>
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<div class="line"><a name="l09116"></a><span class="lineno"> 9116</span> <span class="preprocessor">#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* Host transmit descriptor address pointer */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09117"></a><span class="lineno"> 9117</span> </div>
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<div class="line"><a name="l09118"></a><span class="lineno"> 9118</span> <span class="comment">/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */</span></div>
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<div class="line"><a name="l09119"></a><span class="lineno"> 9119</span> <span class="preprocessor">#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* Host receive descriptor address pointer */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09120"></a><span class="lineno"> 9120</span> </div>
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<div class="line"><a name="l09121"></a><span class="lineno"> 9121</span> <span class="comment">/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */</span></div>
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<div class="line"><a name="l09122"></a><span class="lineno"> 9122</span> <span class="preprocessor">#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* Host transmit buffer address pointer */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09123"></a><span class="lineno"> 9123</span> </div>
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<div class="line"><a name="l09124"></a><span class="lineno"> 9124</span> <span class="comment">/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */</span></div>
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<div class="line"><a name="l09125"></a><span class="lineno"> 9125</span> <span class="preprocessor">#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) </span><span class="comment">/* Host receive buffer address pointer */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09126"></a><span class="lineno"> 9126</span> </div>
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<div class="line"><a name="l09135"></a><span class="lineno"> 9135</span> <span class="preprocessor">#ifdef USE_STDPERIPH_DRIVER</span></div>
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<div class="line"><a name="l09136"></a><span class="lineno"> 9136</span> <span class="preprocessor"> #include "stm32f4xx_conf.h"</span></div>
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<div class="line"><a name="l09137"></a><span class="lineno"> 9137</span> <span class="preprocessor">#endif </span><span class="comment">/* USE_STDPERIPH_DRIVER */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09138"></a><span class="lineno"> 9138</span> </div>
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<div class="line"><a name="l09143"></a><span class="lineno"> 9143</span> <span class="preprocessor">#define SET_BIT(REG, BIT) ((REG) |= (BIT))</span></div>
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<div class="line"><a name="l09144"></a><span class="lineno"> 9144</span> </div>
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<div class="line"><a name="l09145"></a><span class="lineno"> 9145</span> <span class="preprocessor">#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))</span></div>
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<div class="line"><a name="l09146"></a><span class="lineno"> 9146</span> </div>
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<div class="line"><a name="l09147"></a><span class="lineno"> 9147</span> <span class="preprocessor">#define READ_BIT(REG, BIT) ((REG) & (BIT))</span></div>
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<div class="line"><a name="l09148"></a><span class="lineno"> 9148</span> </div>
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<div class="line"><a name="l09149"></a><span class="lineno"> 9149</span> <span class="preprocessor">#define CLEAR_REG(REG) ((REG) = (0x0))</span></div>
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<div class="line"><a name="l09150"></a><span class="lineno"> 9150</span> </div>
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<div class="line"><a name="l09151"></a><span class="lineno"> 9151</span> <span class="preprocessor">#define WRITE_REG(REG, VAL) ((REG) = (VAL))</span></div>
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<div class="line"><a name="l09152"></a><span class="lineno"> 9152</span> </div>
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<div class="line"><a name="l09153"></a><span class="lineno"> 9153</span> <span class="preprocessor">#define READ_REG(REG) ((REG))</span></div>
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<div class="line"><a name="l09154"></a><span class="lineno"> 9154</span> </div>
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<div class="line"><a name="l09155"></a><span class="lineno"> 9155</span> <span class="preprocessor">#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))</span></div>
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<div class="line"><a name="l09156"></a><span class="lineno"> 9156</span> </div>
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<div class="line"><a name="l09161"></a><span class="lineno"> 9161</span> <span class="preprocessor">#ifdef __cplusplus</span></div>
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<div class="line"><a name="l09162"></a><span class="lineno"> 9162</span> }</div>
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<div class="line"><a name="l09163"></a><span class="lineno"> 9163</span> <span class="preprocessor">#endif </span><span class="comment">/* __cplusplus */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09164"></a><span class="lineno"> 9164</span> </div>
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<div class="line"><a name="l09165"></a><span class="lineno"> 9165</span> <span class="preprocessor">#endif </span><span class="comment">/* __STM32F4xx_H */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l09166"></a><span class="lineno"> 9166</span> </div>
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<div class="line"><a name="l09175"></a><span class="lineno"> 9175</span> <span class="comment">/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/</span></div>
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<div class="ttc" id="group___exported__types_html_ga2e08e321a35a55e72c5b3a507e76371f"><div class="ttname"><a href="group___exported__types.html#ga2e08e321a35a55e72c5b3a507e76371f">vuc32</a></div><div class="ttdeci">__I uint32_t vuc32</div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:508</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a60c35f2d48d512bd6818bc9fef7053d7"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a60c35f2d48d512bd6818bc9fef7053d7">I2C2_ER_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:222</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a53cadc1e164ec85d0ea4cd143608e8e1"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a53cadc1e164ec85d0ea4cd143608e8e1">TIM7_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:243</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a637750639eff4e2b4aae80ed6f3cf67f"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a637750639eff4e2b4aae80ed6f3cf67f">TIM8_CC_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:234</div></div>
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<div class="ttc" id="struct_l_t_d_c___type_def_html"><div class="ttname"><a href="struct_l_t_d_c___type_def.html">LTDC_TypeDef</a></div><div class="ttdoc">LCD-TFT Display Controller. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:1060</div></div>
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<div class="ttc" id="struct_c_a_n___f_i_f_o_mail_box___type_def_html"><div class="ttname"><a href="struct_c_a_n___f_i_f_o_mail_box___type_def.html">CAN_FIFOMailBox_TypeDef</a></div><div class="ttdoc">Controller Area Network FIFOMailBox. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:580</div></div>
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<div class="ttc" id="struct_s_y_s_c_f_g___type_def_html"><div class="ttname"><a href="struct_s_y_s_c_f_g___type_def.html">SYSCFG_TypeDef</a></div><div class="ttdoc">System configuration controller. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:1007</div></div>
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<div class="ttc" id="struct_s_p_i___type_def_html"><div class="ttname"><a href="struct_s_p_i___type_def.html">SPI_TypeDef</a></div><div class="ttdoc">Serial Peripheral Interface. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:1257</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a16fe70a39348f3f27906dc268b5654e3"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a16fe70a39348f3f27906dc268b5654e3">SDIO_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:237</div></div>
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<div class="ttc" id="group___exported__types_html_ga47463bcded079ac61d5da46aff497803"><div class="ttname"><a href="group___exported__types.html#ga47463bcded079ac61d5da46aff497803">vsc8</a></div><div class="ttdeci">__I int8_t vsc8</div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:494</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a933d4686213973abc01845a3da1c8a03"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a933d4686213973abc01845a3da1c8a03">DMA2_Stream5_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:256</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083ab6bf73ac43a9856b3f2759a59f3d25b5"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab6bf73ac43a9856b3f2759a59f3d25b5">CAN1_RX0_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:208</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a368b899ca740b9ae0d75841f3abf68c4"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a368b899ca740b9ae0d75841f3abf68c4">TIM4_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:218</div></div>
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<div class="ttc" id="struct_f_s_m_c___bank1___type_def_html"><div class="ttname"><a href="struct_f_s_m_c___bank1___type_def.html">FSMC_Bank1_TypeDef</a></div><div class="ttdoc">Flexible Static Memory Controller. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:855</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083ace3c0fc2c4d05a7c02e3c987da5bc8e8"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ace3c0fc2c4d05a7c02e3c987da5bc8e8">DCMI_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:266</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083aa3879e49013035601e17f83a51e0829f"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa3879e49013035601e17f83a51e0829f">TIM1_UP_TIM10_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:213</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083afe09d6563a21a1540f658163a76a3b37"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083afe09d6563a21a1540f658163a76a3b37">RTC_Alarm_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:229</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a33ff1cf7098de65d61b6354fee6cd5aa"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a33ff1cf7098de65d61b6354fee6cd5aa">MemoryManagement_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:178</div></div>
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<div class="ttc" id="group___exported__types_html_gae9b1af5c037e57a98884758875d3a7c4"><div class="ttname"><a href="group___exported__types.html#gae9b1af5c037e57a98884758875d3a7c4">s32</a></div><div class="ttdeci">int32_t s32</div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:480</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083aedaa9c14e7e5fa9c0dcbb0c2455546e8"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aedaa9c14e7e5fa9c0dcbb0c2455546e8">DMA1_Stream7_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:235</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083aa8d8f67a98f24de6f0b36ad6b1f29a7d"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa8d8f67a98f24de6f0b36ad6b1f29a7d">TIM8_UP_TIM13_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:232</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083ac55a11a64aae7432544d0ab0d4f7de09"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ac55a11a64aae7432544d0ab0d4f7de09">UART5_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:241</div></div>
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<div class="ttc" id="core__cm4_8h_html_af63697ed9952cc71e1225efe205f6cd3"><div class="ttname"><a href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a></div><div class="ttdeci">#define __I</div><div class="ttdef"><b>Definition:</b> core_cm4.h:219</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083aa45ca2c955060e2c2a7cbbe1d6753285"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa45ca2c955060e2c2a7cbbe1d6753285">DMA1_Stream1_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:198</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083ad71328dd95461b7c55b568cf25966f6a"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ad71328dd95461b7c55b568cf25966f6a">ETH_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:249</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083aa92bcb2bc3a87be869f05c5b07f04b8c"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa92bcb2bc3a87be869f05c5b07f04b8c">USART6_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:259</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083ab0b51ffcc4dcf5661141b79c8e5bd924"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab0b51ffcc4dcf5661141b79c8e5bd924">PVD_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:187</div></div>
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<div class="ttc" id="struct_e_x_t_i___type_def_html"><div class="ttname"><a href="struct_e_x_t_i___type_def.html">EXTI_TypeDef</a></div><div class="ttdoc">External Interrupt/Event Controller. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:825</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083ad97cb163e1f678367e37c50d54d161ab"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ad97cb163e1f678367e37c50d54d161ab">USART1_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:225</div></div>
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<div class="ttc" id="struct_f_s_m_c___bank3___type_def_html"><div class="ttname"><a href="struct_f_s_m_c___bank3___type_def.html">FSMC_Bank3_TypeDef</a></div><div class="ttdoc">Flexible Static Memory Controller Bank3. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:887</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a0485578005e12c2e2c0fb253a844ec6f"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a0485578005e12c2e2c0fb253a844ec6f">ETH_WKUP_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:250</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083ab6aa6f87d26bbc6cf99b067b8d75c2f7"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab6aa6f87d26bbc6cf99b067b8d75c2f7">EXTI0_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:192</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a9852dbbe8c014e716ce7e03a7b809751"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9852dbbe8c014e716ce7e03a7b809751">I2C1_EV_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:219</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083aa6b8ff01b016a798c6e639728c179e4f"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa6b8ff01b016a798c6e639728c179e4f">FPU_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:269</div></div>
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<div class="ttc" id="struct_c_r_c___type_def_html"><div class="ttname"><a href="struct_c_r_c___type_def.html">CRC_TypeDef</a></div><div class="ttdoc">CRC calculation unit. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:632</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083abf5e189f3ac7aad9f65e65ea5a0f3b36"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083abf5e189f3ac7aad9f65e65ea5a0f3b36">DMA2_Stream2_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:246</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083ab35b4ce63cfb11453f84a3695c6df368"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab35b4ce63cfb11453f84a3695c6df368">TIM1_BRK_TIM9_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:212</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a505fbd4ccf7c2a14c8b76dc9e58f7ede"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a505fbd4ccf7c2a14c8b76dc9e58f7ede">SPI2_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:224</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083ae54eb8b30273b38a0576f75aba24eec0"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ae54eb8b30273b38a0576f75aba24eec0">DMA2_Stream4_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:248</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083aef5e2b68f62f6f1781fab894f0b8f486"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aef5e2b68f62f6f1781fab894f0b8f486">DMA1_Stream6_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:203</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a86a161642b54055f9bbea3937e6352de"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a86a161642b54055f9bbea3937e6352de">HASH_RNG_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:268</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a3d4cc0cd9b4d71e7ee002c4f8c1f8a77"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3d4cc0cd9b4d71e7ee002c4f8c1f8a77">DMA2_Stream7_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:258</div></div>
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<div class="ttc" id="core__cm4_8h_html_aec43007d9998a0a0e01faede4133d6be"><div class="ttname"><a href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a></div><div class="ttdeci">#define __IO</div><div class="ttdef"><b>Definition:</b> core_cm4.h:222</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a70450df88125476d5771f2ff3f562536"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a70450df88125476d5771f2ff3f562536">FSMC_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:236</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a60b6cc4b6dbeca39e29a475d26c9e080"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a60b6cc4b6dbeca39e29a475d26c9e080">OTG_HS_EP1_OUT_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:262</div></div>
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<div class="ttc" id="core__cm4_8h_html"><div class="ttname"><a href="core__cm4_8h.html">core_cm4.h</a></div><div class="ttdoc">CMSIS Cortex-M4 Core Peripheral Access Layer Header File. </div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083af6b8fbc990ac71c8425647bb684788a4"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af6b8fbc990ac71c8425647bb684788a4">CAN2_TX_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:251</div></div>
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<div class="ttc" id="struct_d_m_a___type_def_html"><div class="ttname"><a href="struct_d_m_a___type_def.html">DMA_TypeDef</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:708</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083aa612f35c4440359c35acbaa3c1458c5f"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa612f35c4440359c35acbaa3c1458c5f">OTG_FS_WKUP_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:230</div></div>
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<div class="ttc" id="struct_w_w_d_g___type_def_html"><div class="ttname"><a href="struct_w_w_d_g___type_def.html">WWDG_TypeDef</a></div><div class="ttdoc">Window WATCHDOG. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:1349</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a9e5c9d81dd3985a88094f8158c0f0267"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9e5c9d81dd3985a88094f8158c0f0267">OTG_HS_WKUP_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:264</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a3f9c48714d0e5baaba6613343f0da68e"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3f9c48714d0e5baaba6613343f0da68e">USART2_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:226</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083af71ef06c4f9ff0e1691c21ff3670acd4"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af71ef06c4f9ff0e1691c21ff3670acd4">CAN1_RX1_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:209</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a0f5f129d88a5606a378811e43039e274"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a0f5f129d88a5606a378811e43039e274">CAN1_SCE_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:210</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a8e033fcef7aed98a31c60a7de206722c"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a8e033fcef7aed98a31c60a7de206722c">DebugMonitor_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:182</div></div>
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<div class="ttc" id="struct_l_t_d_c___layer___type_def_html"><div class="ttname"><a href="struct_l_t_d_c___layer___type_def.html">LTDC_Layer_TypeDef</a></div><div class="ttdoc">LCD-TFT Display layer x Controller. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:1085</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a4e9331739fb76a2ca7781fede070ae44"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a4e9331739fb76a2ca7781fede070ae44">SPI3_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:239</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a851fd2f2ab1418710e7da80e1bdf348a"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a851fd2f2ab1418710e7da80e1bdf348a">CAN2_RX0_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:252</div></div>
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<div class="ttc" id="struct_h_a_s_h___d_i_g_e_s_t___type_def_html"><div class="ttname"><a href="struct_h_a_s_h___d_i_g_e_s_t___type_def.html">HASH_DIGEST_TypeDef</a></div><div class="ttdoc">HASH_DIGEST. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:1420</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a0d9ec75e4478e70235b705d5a6b3efd8"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a0d9ec75e4478e70235b705d5a6b3efd8">DMA1_Stream2_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:199</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083aee2aaf365c6c297a63cee41ecae2301a"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aee2aaf365c6c297a63cee41ecae2301a">DMA1_Stream4_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:201</div></div>
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<div class="ttc" id="group___exported__types_html_ga66ab742a0751bb4e7661b8e874f2ddda"><div class="ttname"><a href="group___exported__types.html#ga66ab742a0751bb4e7661b8e874f2ddda">sc16</a></div><div class="ttdeci">const int16_t sc16</div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:485</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083aa60a30b7ef03446a46fd72e084911f7e"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa60a30b7ef03446a46fd72e084911f7e">OTG_FS_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:255</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a6895237c9443601ac832efa635dd8bbf"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a6895237c9443601ac832efa635dd8bbf">UsageFault_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:180</div></div>
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<div class="ttc" id="struct_g_p_i_o___type_def_html"><div class="ttname"><a href="struct_g_p_i_o___type_def.html">GPIO_TypeDef</a></div><div class="ttdoc">General Purpose I/O. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:989</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083afb13802afc1f5fdf5c90e73ee99e5ff3"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083afb13802afc1f5fdf5c90e73ee99e5ff3">USART3_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:227</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a3e01328006d19f7d32354271b9f61dce"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3e01328006d19f7d32354271b9f61dce">TIM8_BRK_TIM12_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:231</div></div>
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<div class="ttc" id="group___exported__types_html_gaec1d22666cf030b79051e5daa372fbc8"><div class="ttname"><a href="group___exported__types.html#gaec1d22666cf030b79051e5daa372fbc8">vsc32</a></div><div class="ttdeci">__I int32_t vsc32</div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:492</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a4ce820b3cc6cf3a796b41aadc0cf1237"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a4ce820b3cc6cf3a796b41aadc0cf1237">SVCall_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:181</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a8693500eff174f16119e96234fee73af"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a8693500eff174f16119e96234fee73af">BusFault_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:179</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a03c3cc89984928816d81793fc7bce4a2"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a03c3cc89984928816d81793fc7bce4a2">PendSV_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:183</div></div>
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<div class="ttc" id="struct_c_a_n___type_def_html"><div class="ttname"><a href="struct_c_a_n___type_def.html">CAN_TypeDef</a></div><div class="ttdoc">Controller Area Network. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:602</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083ae252b31c3a341acbe9a467e243137307"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ae252b31c3a341acbe9a467e243137307">TIM8_TRG_COM_TIM14_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:233</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a8326db2d570cb865ffa1d49fa29d562a"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a8326db2d570cb865ffa1d49fa29d562a">I2C3_EV_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:260</div></div>
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<div class="ttc" id="struct_d_m_a2_d___type_def_html"><div class="ttname"><a href="struct_d_m_a2_d___type_def.html">DMA2D_TypeDef</a></div><div class="ttdoc">DMA2D Controller. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:720</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a91b73963ce243a1d031576d49e137fab"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a91b73963ce243a1d031576d49e137fab">FLASH_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:190</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083af77770e080206a7558decf09344fb2e2"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af77770e080206a7558decf09344fb2e2">DMA1_Stream3_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:200</div></div>
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<div class="ttc" id="struct_a_d_c___type_def_html"><div class="ttname"><a href="struct_a_d_c___type_def.html">ADC_TypeDef</a></div><div class="ttdoc">Analog to Digital Converter. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:531</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083ab5023ff845be31a488ab63a0b8cf2b7a"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab5023ff845be31a488ab63a0b8cf2b7a">CAN2_RX1_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:253</div></div>
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<div class="ttc" id="struct_s_a_i___type_def_html"><div class="ttname"><a href="struct_s_a_i___type_def.html">SAI_TypeDef</a></div><div class="ttdoc">Serial Audio Interface. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:1208</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a21570761ad0b5ed751adc831691b7800"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a21570761ad0b5ed751adc831691b7800">DMA2_Stream6_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:257</div></div>
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<div class="ttc" id="group___exported__types_html_gac74022c74a461f810e0d4fdc9bfea480"><div class="ttname"><a href="group___exported__types.html#gac74022c74a461f810e0d4fdc9bfea480">uc8</a></div><div class="ttdeci">const uint8_t uc8</div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:502</div></div>
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<div class="ttc" id="struct_f_s_m_c___bank2___type_def_html"><div class="ttname"><a href="struct_f_s_m_c___bank2___type_def.html">FSMC_Bank2_TypeDef</a></div><div class="ttdoc">Flexible Static Memory Controller Bank2. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:873</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a98abb3f02c1feb3831706bc1b82307cb"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a98abb3f02c1feb3831706bc1b82307cb">DMA2_Stream1_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:245</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gac3af4a32370fb28c4ade8bf2add80251"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gac3af4a32370fb28c4ade8bf2add80251">IRQn_Type</a></div><div class="ttdeci">enum IRQn IRQn_Type</div><div class="ttdoc">STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...</div></div>
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<div class="ttc" id="struct_c_a_n___tx_mail_box___type_def_html"><div class="ttname"><a href="struct_c_a_n___tx_mail_box___type_def.html">CAN_TxMailBox_TypeDef</a></div><div class="ttdoc">Controller Area Network TxMailBox. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:568</div></div>
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<div class="ttc" id="struct_e_t_h___type_def_html"><div class="ttname"><a href="struct_e_t_h___type_def.html">ETH_TypeDef</a></div><div class="ttdoc">Ethernet MAC. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:751</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a56c0b5758f26f31494e74aab9273f9fd"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a56c0b5758f26f31494e74aab9273f9fd">CAN2_SCE_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:254</div></div>
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<div class="ttc" id="group___exported__types_html_ga5b628e6a05856ff67e535fa391a57683"><div class="ttname"><a href="group___exported__types.html#ga5b628e6a05856ff67e535fa391a57683">uc32</a></div><div class="ttdeci">const uint32_t uc32</div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:500</div></div>
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<div class="ttc" id="struct_u_s_a_r_t___type_def_html"><div class="ttname"><a href="struct_u_s_a_r_t___type_def.html">USART_TypeDef</a></div><div class="ttdoc">Universal Synchronous Asynchronous Receiver Transmitter. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:1327</div></div>
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<div class="ttc" id="struct_t_i_m___type_def_html"><div class="ttname"><a href="struct_t_i_m___type_def.html">TIM_TypeDef</a></div><div class="ttdoc">TIM. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:1283</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a1b040a7f76278a73cf5ea4c51f1be047"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a1b040a7f76278a73cf5ea4c51f1be047">OTG_HS_EP1_IN_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:263</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a9ceb5175f7c10cf436955173c2246877"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9ceb5175f7c10cf436955173c2246877">CAN1_TX_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:207</div></div>
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<div class="ttc" id="struct_d_m_a___stream___type_def_html"><div class="ttname"><a href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a></div><div class="ttdoc">DMA Controller. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:698</div></div>
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<div class="ttc" id="struct_d_a_c___type_def_html"><div class="ttname"><a href="struct_d_a_c___type_def.html">DAC_TypeDef</a></div><div class="ttdoc">Digital to Analog Converter. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:645</div></div>
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<div class="ttc" id="struct_f_l_a_s_h___type_def_html"><div class="ttname"><a href="struct_f_l_a_s_h___type_def.html">FLASH_TypeDef</a></div><div class="ttdoc">FLASH Registers. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:839</div></div>
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<div class="ttc" id="struct_p_w_r___type_def_html"><div class="ttname"><a href="struct_p_w_r___type_def.html">PWR_TypeDef</a></div><div class="ttdoc">Power Control. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:1108</div></div>
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<div class="ttc" id="struct_i_w_d_g___type_def_html"><div class="ttname"><a href="struct_i_w_d_g___type_def.html">IWDG_TypeDef</a></div><div class="ttdoc">Independent WATCHDOG. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:1048</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a082cb3f7839069a0715fd76c7eacbbc9"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a082cb3f7839069a0715fd76c7eacbbc9">EXTI2_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:194</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083ab70a40106ca4486770df5d2072d9ac0e"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab70a40106ca4486770df5d2072d9ac0e">EXTI4_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:196</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a173ccc3f31df1f7e43de2ddeab3d1777"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a173ccc3f31df1f7e43de2ddeab3d1777">RTC_WKUP_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:189</div></div>
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<div class="ttc" id="group___exported__types_html_gabc715ea3779494b5a4f53173a397f7cb"><div class="ttname"><a href="group___exported__types.html#gabc715ea3779494b5a4f53173a397f7cb">uc16</a></div><div class="ttdeci">const uint16_t uc16</div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:501</div></div>
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<div class="ttc" id="struct_a_d_c___common___type_def_html"><div class="ttname"><a href="struct_a_d_c___common___type_def.html">ADC_Common_TypeDef</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:555</div></div>
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<div class="ttc" id="struct_r_c_c___type_def_html"><div class="ttname"><a href="struct_r_c_c___type_def.html">RCC_TypeDef</a></div><div class="ttdoc">Reset and Clock Control. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:1118</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083aacdff1a9c42582ed663214cbe62c1174"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aacdff1a9c42582ed663214cbe62c1174">SPI1_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:223</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a3ff8f3439f509e6e985eb960e63e1be4"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3ff8f3439f509e6e985eb960e63e1be4">DMA2_Stream3_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:247</div></div>
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<div class="ttc" id="group___exported__types_html_ga7f6037565f0caa27727c8b871daf0d56"><div class="ttname"><a href="group___exported__types.html#ga7f6037565f0caa27727c8b871daf0d56">vuc16</a></div><div class="ttdeci">__I uint16_t vuc16</div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:509</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a2ec363869f4488782dc10a60abce3b34"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a2ec363869f4488782dc10a60abce3b34">I2C1_ER_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:220</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a3a4e2095a926e4095d3c846eb1c98afa"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3a4e2095a926e4095d3c846eb1c98afa">TIM2_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:216</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a5710b22392997bac63daa5c999730f77"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a5710b22392997bac63daa5c999730f77">RCC_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:191</div></div>
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<div class="ttc" id="struct_c_a_n___filter_register___type_def_html"><div class="ttname"><a href="struct_c_a_n___filter_register___type_def.html">CAN_FilterRegister_TypeDef</a></div><div class="ttdoc">Controller Area Network FilterRegister. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:592</div></div>
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<div class="ttc" id="group___exported__types_html_ga369ae0177b957e5afa7c1e62312f97c3"><div class="ttname"><a href="group___exported__types.html#ga369ae0177b957e5afa7c1e62312f97c3">vsc16</a></div><div class="ttdeci">__I int16_t vsc16</div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:493</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083ae4badcdecdb94eb10129c4c0577c5e19"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ae4badcdecdb94eb10129c4c0577c5e19">EXTI1_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:193</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a70c9645bf48ca539510cc8f7d974f017"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a70c9645bf48ca539510cc8f7d974f017">CRYP_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:267</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083add889c84ba5de466ced209069e05d602"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083add889c84ba5de466ced209069e05d602">EXTI3_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:195</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083ac92efa72399fe58fa615d8bf8fd64a4e"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ac92efa72399fe58fa615d8bf8fd64a4e">DMA1_Stream5_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:202</div></div>
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<div class="ttc" id="struct_r_t_c___type_def_html"><div class="ttname"><a href="struct_r_t_c___type_def.html">RTC_TypeDef</a></div><div class="ttdoc">Real-Time Clock. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:1159</div></div>
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<div class="ttc" id="struct_d_c_m_i___type_def_html"><div class="ttname"><a href="struct_d_c_m_i___type_def.html">DCMI_TypeDef</a></div><div class="ttdoc">DCMI. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:679</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083aded5314b20c6e4e80cb6ab0668ffb8d5"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aded5314b20c6e4e80cb6ab0668ffb8d5">UART4_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:240</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a971089d7566ef902dfa0c80ac3a8fd52"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a971089d7566ef902dfa0c80ac3a8fd52">WWDG_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:186</div></div>
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<div class="ttc" id="struct_f_s_m_c___bank1_e___type_def_html"><div class="ttname"><a href="struct_f_s_m_c___bank1_e___type_def.html">FSMC_Bank1E_TypeDef</a></div><div class="ttdoc">Flexible Static Memory Controller Bank1E. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:864</div></div>
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<div class="ttc" id="struct_i2_c___type_def_html"><div class="ttname"><a href="struct_i2_c___type_def.html">I2C_TypeDef</a></div><div class="ttdoc">Inter-integrated Circuit Interface. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:1020</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a4d69175258ae261dd545001e810421b3"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a4d69175258ae261dd545001e810421b3">ADC_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:204</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a9ee33e72512c4cfb301b216f4fb9d68c"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9ee33e72512c4cfb301b216f4fb9d68c">DMA1_Stream0_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:197</div></div>
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<div class="ttc" id="struct_r_n_g___type_def_html"><div class="ttname"><a href="struct_r_n_g___type_def.html">RNG_TypeDef</a></div><div class="ttdoc">RNG. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:1429</div></div>
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<div class="ttc" id="struct_h_a_s_h___type_def_html"><div class="ttname"><a href="struct_h_a_s_h___type_def.html">HASH_TypeDef</a></div><div class="ttdoc">HASH. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:1404</div></div>
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<div class="ttc" id="struct_d_b_g_m_c_u___type_def_html"><div class="ttname"><a href="struct_d_b_g_m_c_u___type_def.html">DBGMCU_TypeDef</a></div><div class="ttdoc">Debug MCU. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:667</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083aed2eb3f4bb721d55fcc1003125956645"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aed2eb3f4bb721d55fcc1003125956645">TIM5_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:238</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083af312f0a21f600f9b286427e50c549ca9"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083af312f0a21f600f9b286427e50c549ca9">TIM1_CC_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:215</div></div>
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<div class="ttc" id="group___exported__types_html_ga30e6c0f6718e1b6d26dc9d94ddcf9d11"><div class="ttname"><a href="group___exported__types.html#ga30e6c0f6718e1b6d26dc9d94ddcf9d11">sc8</a></div><div class="ttdeci">const int8_t sc8</div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:486</div></div>
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<div class="ttc" id="struct_s_a_i___block___type_def_html"><div class="ttname"><a href="struct_s_a_i___block___type_def.html">SAI_Block_TypeDef</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:1213</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083aa3aa50e0353871985facf62d055faa52"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aa3aa50e0353871985facf62d055faa52">EXTI9_5_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:211</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083ac127cca7ae48bcf93924209f04e5e5a1"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ac127cca7ae48bcf93924209f04e5e5a1">TAMP_STAMP_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:188</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a9fb0ad0c850234d1983fafdb17378e2f"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a9fb0ad0c850234d1983fafdb17378e2f">EXTI15_10_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:228</div></div>
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<div class="ttc" id="struct_c_r_y_p___type_def_html"><div class="ttname"><a href="struct_c_r_y_p___type_def.html">CRYP_TypeDef</a></div><div class="ttdoc">Crypto Processor. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:1360</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a985574288f66e2a00e97387424a9a2d8"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a985574288f66e2a00e97387424a9a2d8">TIM3_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:217</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a3020193786527c47d2e4d8c92ceee804"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a3020193786527c47d2e4d8c92ceee804">I2C2_EV_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:221</div></div>
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<div class="ttc" id="group___exported__types_html_gab0ec90ac9b2c5864755998c8d37c264a"><div class="ttname"><a href="group___exported__types.html#gab0ec90ac9b2c5864755998c8d37c264a">vuc8</a></div><div class="ttdeci">__I uint8_t vuc8</div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:510</div></div>
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<div class="ttc" id="struct_s_d_i_o___type_def_html"><div class="ttname"><a href="struct_s_d_i_o___type_def.html">SDIO_TypeDef</a></div><div class="ttdoc">SD host Interface. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:1229</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a6e954232d164a6942ebc7a6bd6f7736e"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a6e954232d164a6942ebc7a6bd6f7736e">I2C3_ER_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:261</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083aad2d5e47d27fe3a02f7059b20bb729c0"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083aad2d5e47d27fe3a02f7059b20bb729c0">OTG_HS_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:265</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083ade177d9c70c89e084093024b932a4e30"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ade177d9c70c89e084093024b932a4e30">NonMaskableInt_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:177</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a5f581e9aedfaccd9b1db9ec793804b45"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a5f581e9aedfaccd9b1db9ec793804b45">TIM6_DAC_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:242</div></div>
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<div class="ttc" id="system__stm32f4xx_8h_html"><div class="ttname"><a href="system__stm32f4xx_8h.html">system_stm32f4xx.h</a></div><div class="ttdoc">CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. </div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083ab1a744bdceb8eface6ff57dd036e608e"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083ab1a744bdceb8eface6ff57dd036e608e">TIM1_TRG_COM_TIM11_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:214</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a1e5055722630fd4b12aff421964c2ebb"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a1e5055722630fd4b12aff421964c2ebb">DMA2_Stream0_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:244</div></div>
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<div class="ttc" id="struct_f_s_m_c___bank4___type_def_html"><div class="ttname"><a href="struct_f_s_m_c___bank4___type_def.html">FSMC_Bank4_TypeDef</a></div><div class="ttdoc">Flexible Static Memory Controller Bank4. </div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:901</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a6dbff8f8543325f3474cbae2446776e7"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a6dbff8f8543325f3474cbae2446776e7">SysTick_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:184</div></div>
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<div class="ttc" id="group___exported__types_html_gad97679599f3791409523fdb1c6156a28"><div class="ttname"><a href="group___exported__types.html#gad97679599f3791409523fdb1c6156a28">sc32</a></div><div class="ttdeci">const int32_t sc32</div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:484</div></div>
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