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<div class="title">core_cm4.h</div> </div>
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<div class="contents">
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<a href="core__cm4_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno"> 1</span> <span class="comment">/**************************************************************************/</span></div>
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<div class="line"><a name="l00010"></a><span class="lineno"> 10</span> <span class="comment">/* Copyright (c) 2009 - 2013 ARM LIMITED</span></div>
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<div class="line"><a name="l00011"></a><span class="lineno"> 11</span> <span class="comment"></span></div>
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<div class="line"><a name="l00012"></a><span class="lineno"> 12</span> <span class="comment"> All rights reserved.</span></div>
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<div class="line"><a name="l00013"></a><span class="lineno"> 13</span> <span class="comment"> Redistribution and use in source and binary forms, with or without</span></div>
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<div class="line"><a name="l00014"></a><span class="lineno"> 14</span> <span class="comment"> modification, are permitted provided that the following conditions are met:</span></div>
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<div class="line"><a name="l00015"></a><span class="lineno"> 15</span> <span class="comment"> - Redistributions of source code must retain the above copyright</span></div>
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<div class="line"><a name="l00016"></a><span class="lineno"> 16</span> <span class="comment"> notice, this list of conditions and the following disclaimer.</span></div>
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<div class="line"><a name="l00017"></a><span class="lineno"> 17</span> <span class="comment"> - Redistributions in binary form must reproduce the above copyright</span></div>
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<div class="line"><a name="l00018"></a><span class="lineno"> 18</span> <span class="comment"> notice, this list of conditions and the following disclaimer in the</span></div>
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<div class="line"><a name="l00019"></a><span class="lineno"> 19</span> <span class="comment"> documentation and/or other materials provided with the distribution.</span></div>
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<div class="line"><a name="l00020"></a><span class="lineno"> 20</span> <span class="comment"> - Neither the name of ARM nor the names of its contributors may be used</span></div>
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<div class="line"><a name="l00021"></a><span class="lineno"> 21</span> <span class="comment"> to endorse or promote products derived from this software without</span></div>
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<div class="line"><a name="l00022"></a><span class="lineno"> 22</span> <span class="comment"> specific prior written permission.</span></div>
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<div class="line"><a name="l00023"></a><span class="lineno"> 23</span> <span class="comment"> *</span></div>
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<div class="line"><a name="l00024"></a><span class="lineno"> 24</span> <span class="comment"> THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"</span></div>
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<div class="line"><a name="l00025"></a><span class="lineno"> 25</span> <span class="comment"> AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span></div>
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<div class="line"><a name="l00026"></a><span class="lineno"> 26</span> <span class="comment"> IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span></div>
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<div class="line"><a name="l00027"></a><span class="lineno"> 27</span> <span class="comment"> ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE</span></div>
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<div class="line"><a name="l00028"></a><span class="lineno"> 28</span> <span class="comment"> LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR</span></div>
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<div class="line"><a name="l00029"></a><span class="lineno"> 29</span> <span class="comment"> CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF</span></div>
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<div class="line"><a name="l00030"></a><span class="lineno"> 30</span> <span class="comment"> SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS</span></div>
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<div class="line"><a name="l00031"></a><span class="lineno"> 31</span> <span class="comment"> INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN</span></div>
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<div class="line"><a name="l00032"></a><span class="lineno"> 32</span> <span class="comment"> CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)</span></div>
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<div class="line"><a name="l00033"></a><span class="lineno"> 33</span> <span class="comment"> ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE</span></div>
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<div class="line"><a name="l00034"></a><span class="lineno"> 34</span> <span class="comment"> POSSIBILITY OF SUCH DAMAGE.</span></div>
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<div class="line"><a name="l00035"></a><span class="lineno"> 35</span> <span class="comment"> ---------------------------------------------------------------------------*/</span></div>
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<div class="line"><a name="l00036"></a><span class="lineno"> 36</span> </div>
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<div class="line"><a name="l00037"></a><span class="lineno"> 37</span> </div>
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<div class="line"><a name="l00038"></a><span class="lineno"> 38</span> <span class="preprocessor">#if defined ( __ICCARM__ )</span></div>
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<div class="line"><a name="l00039"></a><span class="lineno"> 39</span> <span class="preprocessor"> #pragma system_include </span><span class="comment">/* treat file as system include file for MISRA check */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00040"></a><span class="lineno"> 40</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00041"></a><span class="lineno"> 41</span> </div>
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<div class="line"><a name="l00042"></a><span class="lineno"> 42</span> <span class="preprocessor">#ifdef __cplusplus</span></div>
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<div class="line"><a name="l00043"></a><span class="lineno"> 43</span>  <span class="keyword">extern</span> <span class="stringliteral">"C"</span> {</div>
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<div class="line"><a name="l00044"></a><span class="lineno"> 44</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00045"></a><span class="lineno"> 45</span> </div>
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<div class="line"><a name="l00046"></a><span class="lineno"> 46</span> <span class="preprocessor">#ifndef __CORE_CM4_H_GENERIC</span></div>
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<div class="line"><a name="l00047"></a><span class="lineno"> 47</span> <span class="preprocessor">#define __CORE_CM4_H_GENERIC</span></div>
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<div class="line"><a name="l00048"></a><span class="lineno"> 48</span> </div>
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<div class="line"><a name="l00063"></a><span class="lineno"> 63</span> <span class="comment">/*******************************************************************************</span></div>
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<div class="line"><a name="l00064"></a><span class="lineno"> 64</span> <span class="comment"> * CMSIS definitions</span></div>
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<div class="line"><a name="l00065"></a><span class="lineno"> 65</span> <span class="comment"> ******************************************************************************/</span></div>
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<div class="line"><a name="l00070"></a><span class="lineno"> 70</span> <span class="comment">/* CMSIS CM4 definitions */</span></div>
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<div class="line"><a name="l00071"></a><span class="lineno"><a class="line" href="core__cm4_8h.html#a90ffc8179476f80347379bfe29639edc"> 71</a></span> <span class="preprocessor">#define __CM4_CMSIS_VERSION_MAIN (0x03) </span></div>
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<div class="line"><a name="l00072"></a><span class="lineno"><a class="line" href="core__cm4_8h.html#afc7392964da961a44e916fcff7add532"> 72</a></span> <span class="preprocessor">#define __CM4_CMSIS_VERSION_SUB (0x20) </span></div>
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<div class="line"><a name="l00073"></a><span class="lineno"><a class="line" href="core__cm4_8h.html#acb6f5d2c3271c95d0a02fd06723af25d"> 73</a></span> <span class="preprocessor">#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \</span></div>
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<div class="line"><a name="l00074"></a><span class="lineno"> 74</span> <span class="preprocessor"> __CM4_CMSIS_VERSION_SUB ) </span></div>
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<div class="line"><a name="l00076"></a><span class="lineno"><a class="line" href="core__cm4_8h.html#a63ea62503c88acab19fcf3d5743009e3"> 76</a></span> <span class="preprocessor">#define __CORTEX_M (0x04) </span></div>
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<div class="line"><a name="l00079"></a><span class="lineno"> 79</span> <span class="preprocessor">#if defined ( __CC_ARM )</span></div>
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<div class="line"><a name="l00080"></a><span class="lineno"> 80</span> <span class="preprocessor"> #define __ASM __asm </span></div>
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<div class="line"><a name="l00081"></a><span class="lineno"> 81</span> <span class="preprocessor"> #define __INLINE __inline </span></div>
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<div class="line"><a name="l00082"></a><span class="lineno"> 82</span> <span class="preprocessor"> #define __STATIC_INLINE static __inline</span></div>
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<div class="line"><a name="l00083"></a><span class="lineno"> 83</span> </div>
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<div class="line"><a name="l00084"></a><span class="lineno"> 84</span> <span class="preprocessor">#elif defined ( __ICCARM__ )</span></div>
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<div class="line"><a name="l00085"></a><span class="lineno"> 85</span> <span class="preprocessor"> #define __ASM __asm </span></div>
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<div class="line"><a name="l00086"></a><span class="lineno"> 86</span> <span class="preprocessor"> #define __INLINE inline </span></div>
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<div class="line"><a name="l00087"></a><span class="lineno"> 87</span> <span class="preprocessor"> #define __STATIC_INLINE static inline</span></div>
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<div class="line"><a name="l00088"></a><span class="lineno"> 88</span> </div>
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<div class="line"><a name="l00089"></a><span class="lineno"> 89</span> <span class="preprocessor">#elif defined ( __TMS470__ )</span></div>
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<div class="line"><a name="l00090"></a><span class="lineno"> 90</span> <span class="preprocessor"> #define __ASM __asm </span></div>
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<div class="line"><a name="l00091"></a><span class="lineno"> 91</span> <span class="preprocessor"> #define __STATIC_INLINE static inline</span></div>
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<div class="line"><a name="l00092"></a><span class="lineno"> 92</span> </div>
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<div class="line"><a name="l00093"></a><span class="lineno"> 93</span> <span class="preprocessor">#elif defined ( __GNUC__ )</span></div>
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<div class="line"><a name="l00094"></a><span class="lineno"> 94</span> <span class="preprocessor"> #define __ASM __asm </span></div>
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<div class="line"><a name="l00095"></a><span class="lineno"> 95</span> <span class="preprocessor"> #define __INLINE inline </span></div>
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<div class="line"><a name="l00096"></a><span class="lineno"> 96</span> <span class="preprocessor"> #define __STATIC_INLINE static inline</span></div>
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<div class="line"><a name="l00097"></a><span class="lineno"> 97</span> </div>
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<div class="line"><a name="l00098"></a><span class="lineno"> 98</span> <span class="preprocessor">#elif defined ( __TASKING__ )</span></div>
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<div class="line"><a name="l00099"></a><span class="lineno"> 99</span> <span class="preprocessor"> #define __ASM __asm </span></div>
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<div class="line"><a name="l00100"></a><span class="lineno"> 100</span> <span class="preprocessor"> #define __INLINE inline </span></div>
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<div class="line"><a name="l00101"></a><span class="lineno"> 101</span> <span class="preprocessor"> #define __STATIC_INLINE static inline</span></div>
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<div class="line"><a name="l00102"></a><span class="lineno"> 102</span> </div>
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<div class="line"><a name="l00103"></a><span class="lineno"> 103</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00104"></a><span class="lineno"> 104</span> </div>
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<div class="line"><a name="l00107"></a><span class="lineno"> 107</span> <span class="preprocessor">#if defined ( __CC_ARM )</span></div>
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<div class="line"><a name="l00108"></a><span class="lineno"> 108</span> <span class="preprocessor"> #if defined __TARGET_FPU_VFP</span></div>
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<div class="line"><a name="l00109"></a><span class="lineno"> 109</span> <span class="preprocessor"> #if (__FPU_PRESENT == 1)</span></div>
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<div class="line"><a name="l00110"></a><span class="lineno"> 110</span> <span class="preprocessor"> #define __FPU_USED 1</span></div>
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<div class="line"><a name="l00111"></a><span class="lineno"> 111</span> <span class="preprocessor"> #else</span></div>
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<div class="line"><a name="l00112"></a><span class="lineno"> 112</span> <span class="preprocessor"> #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"</span></div>
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<div class="line"><a name="l00113"></a><span class="lineno"> 113</span> <span class="preprocessor"> #define __FPU_USED 0</span></div>
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<div class="line"><a name="l00114"></a><span class="lineno"> 114</span> <span class="preprocessor"> #endif</span></div>
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<div class="line"><a name="l00115"></a><span class="lineno"> 115</span> <span class="preprocessor"> #else</span></div>
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<div class="line"><a name="l00116"></a><span class="lineno"> 116</span> <span class="preprocessor"> #define __FPU_USED 0</span></div>
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|
<div class="line"><a name="l00117"></a><span class="lineno"> 117</span> <span class="preprocessor"> #endif</span></div>
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<div class="line"><a name="l00118"></a><span class="lineno"> 118</span> </div>
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<div class="line"><a name="l00119"></a><span class="lineno"> 119</span> <span class="preprocessor">#elif defined ( __ICCARM__ )</span></div>
|
|
<div class="line"><a name="l00120"></a><span class="lineno"> 120</span> <span class="preprocessor"> #if defined __ARMVFP__</span></div>
|
|
<div class="line"><a name="l00121"></a><span class="lineno"> 121</span> <span class="preprocessor"> #if (__FPU_PRESENT == 1)</span></div>
|
|
<div class="line"><a name="l00122"></a><span class="lineno"> 122</span> <span class="preprocessor"> #define __FPU_USED 1</span></div>
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|
<div class="line"><a name="l00123"></a><span class="lineno"> 123</span> <span class="preprocessor"> #else</span></div>
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<div class="line"><a name="l00124"></a><span class="lineno"> 124</span> <span class="preprocessor"> #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"</span></div>
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|
<div class="line"><a name="l00125"></a><span class="lineno"> 125</span> <span class="preprocessor"> #define __FPU_USED 0</span></div>
|
|
<div class="line"><a name="l00126"></a><span class="lineno"> 126</span> <span class="preprocessor"> #endif</span></div>
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<div class="line"><a name="l00127"></a><span class="lineno"> 127</span> <span class="preprocessor"> #else</span></div>
|
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<div class="line"><a name="l00128"></a><span class="lineno"> 128</span> <span class="preprocessor"> #define __FPU_USED 0</span></div>
|
|
<div class="line"><a name="l00129"></a><span class="lineno"> 129</span> <span class="preprocessor"> #endif</span></div>
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<div class="line"><a name="l00130"></a><span class="lineno"> 130</span> </div>
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<div class="line"><a name="l00131"></a><span class="lineno"> 131</span> <span class="preprocessor">#elif defined ( __TMS470__ )</span></div>
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<div class="line"><a name="l00132"></a><span class="lineno"> 132</span> <span class="preprocessor"> #if defined __TI_VFP_SUPPORT__</span></div>
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<div class="line"><a name="l00133"></a><span class="lineno"> 133</span> <span class="preprocessor"> #if (__FPU_PRESENT == 1)</span></div>
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|
<div class="line"><a name="l00134"></a><span class="lineno"> 134</span> <span class="preprocessor"> #define __FPU_USED 1</span></div>
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|
<div class="line"><a name="l00135"></a><span class="lineno"> 135</span> <span class="preprocessor"> #else</span></div>
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<div class="line"><a name="l00136"></a><span class="lineno"> 136</span> <span class="preprocessor"> #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"</span></div>
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|
<div class="line"><a name="l00137"></a><span class="lineno"> 137</span> <span class="preprocessor"> #define __FPU_USED 0</span></div>
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<div class="line"><a name="l00138"></a><span class="lineno"> 138</span> <span class="preprocessor"> #endif</span></div>
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<div class="line"><a name="l00139"></a><span class="lineno"> 139</span> <span class="preprocessor"> #else</span></div>
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<div class="line"><a name="l00140"></a><span class="lineno"> 140</span> <span class="preprocessor"> #define __FPU_USED 0</span></div>
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|
<div class="line"><a name="l00141"></a><span class="lineno"> 141</span> <span class="preprocessor"> #endif</span></div>
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<div class="line"><a name="l00142"></a><span class="lineno"> 142</span> </div>
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<div class="line"><a name="l00143"></a><span class="lineno"> 143</span> <span class="preprocessor">#elif defined ( __GNUC__ )</span></div>
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<div class="line"><a name="l00144"></a><span class="lineno"> 144</span> <span class="preprocessor"> #if defined (__VFP_FP__) && !defined(__SOFTFP__)</span></div>
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<div class="line"><a name="l00145"></a><span class="lineno"> 145</span> <span class="preprocessor"> #if (__FPU_PRESENT == 1)</span></div>
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<div class="line"><a name="l00146"></a><span class="lineno"> 146</span> <span class="preprocessor"> #define __FPU_USED 1</span></div>
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<div class="line"><a name="l00147"></a><span class="lineno"> 147</span> <span class="preprocessor"> #else</span></div>
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<div class="line"><a name="l00148"></a><span class="lineno"> 148</span> <span class="preprocessor"> #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"</span></div>
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<div class="line"><a name="l00149"></a><span class="lineno"> 149</span> <span class="preprocessor"> #define __FPU_USED 0</span></div>
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<div class="line"><a name="l00150"></a><span class="lineno"> 150</span> <span class="preprocessor"> #endif</span></div>
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<div class="line"><a name="l00151"></a><span class="lineno"> 151</span> <span class="preprocessor"> #else</span></div>
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<div class="line"><a name="l00152"></a><span class="lineno"> 152</span> <span class="preprocessor"> #define __FPU_USED 0</span></div>
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<div class="line"><a name="l00153"></a><span class="lineno"> 153</span> <span class="preprocessor"> #endif</span></div>
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<div class="line"><a name="l00154"></a><span class="lineno"> 154</span> </div>
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<div class="line"><a name="l00155"></a><span class="lineno"> 155</span> <span class="preprocessor">#elif defined ( __TASKING__ )</span></div>
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<div class="line"><a name="l00156"></a><span class="lineno"> 156</span> <span class="preprocessor"> #if defined __FPU_VFP__</span></div>
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<div class="line"><a name="l00157"></a><span class="lineno"> 157</span> <span class="preprocessor"> #if (__FPU_PRESENT == 1)</span></div>
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<div class="line"><a name="l00158"></a><span class="lineno"> 158</span> <span class="preprocessor"> #define __FPU_USED 1</span></div>
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<div class="line"><a name="l00159"></a><span class="lineno"> 159</span> <span class="preprocessor"> #else</span></div>
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<div class="line"><a name="l00160"></a><span class="lineno"> 160</span> <span class="preprocessor"> #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"</span></div>
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<div class="line"><a name="l00161"></a><span class="lineno"> 161</span> <span class="preprocessor"> #define __FPU_USED 0</span></div>
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<div class="line"><a name="l00162"></a><span class="lineno"> 162</span> <span class="preprocessor"> #endif</span></div>
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<div class="line"><a name="l00163"></a><span class="lineno"> 163</span> <span class="preprocessor"> #else</span></div>
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<div class="line"><a name="l00164"></a><span class="lineno"> 164</span> <span class="preprocessor"> #define __FPU_USED 0</span></div>
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<div class="line"><a name="l00165"></a><span class="lineno"> 165</span> <span class="preprocessor"> #endif</span></div>
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<div class="line"><a name="l00166"></a><span class="lineno"> 166</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00167"></a><span class="lineno"> 167</span> </div>
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<div class="line"><a name="l00168"></a><span class="lineno"> 168</span> <span class="preprocessor">#include <stdint.h></span> <span class="comment">/* standard types definitions */</span></div>
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<div class="line"><a name="l00169"></a><span class="lineno"> 169</span> <span class="preprocessor">#include <<a class="code" href="core__cm_instr_8h.html">core_cmInstr.h</a>></span> <span class="comment">/* Core Instruction Access */</span></div>
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<div class="line"><a name="l00170"></a><span class="lineno"> 170</span> <span class="preprocessor">#include <<a class="code" href="core__cm_func_8h.html">core_cmFunc.h</a>></span> <span class="comment">/* Core Function Access */</span></div>
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<div class="line"><a name="l00171"></a><span class="lineno"> 171</span> <span class="preprocessor">#include <<a class="code" href="core__cm4__simd_8h.html">core_cm4_simd.h</a>></span> <span class="comment">/* Compiler specific SIMD Intrinsics */</span></div>
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<div class="line"><a name="l00172"></a><span class="lineno"> 172</span> </div>
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<div class="line"><a name="l00173"></a><span class="lineno"> 173</span> <span class="preprocessor">#endif </span><span class="comment">/* __CORE_CM4_H_GENERIC */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00174"></a><span class="lineno"> 174</span> </div>
|
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<div class="line"><a name="l00175"></a><span class="lineno"> 175</span> <span class="preprocessor">#ifndef __CMSIS_GENERIC</span></div>
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<div class="line"><a name="l00176"></a><span class="lineno"> 176</span> </div>
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<div class="line"><a name="l00177"></a><span class="lineno"> 177</span> <span class="preprocessor">#ifndef __CORE_CM4_H_DEPENDANT</span></div>
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<div class="line"><a name="l00178"></a><span class="lineno"><a class="line" href="core__cm4_8h.html#a65104fb6a96df4ec7f7e72781b561060"> 178</a></span> <span class="preprocessor">#define __CORE_CM4_H_DEPENDANT</span></div>
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<div class="line"><a name="l00179"></a><span class="lineno"> 179</span> </div>
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<div class="line"><a name="l00180"></a><span class="lineno"> 180</span> <span class="comment">/* check device defines and use defaults */</span></div>
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<div class="line"><a name="l00181"></a><span class="lineno"> 181</span> <span class="preprocessor">#if defined __CHECK_DEVICE_DEFINES</span></div>
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<div class="line"><a name="l00182"></a><span class="lineno"> 182</span> <span class="preprocessor"> #ifndef __CM4_REV</span></div>
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<div class="line"><a name="l00183"></a><span class="lineno"> 183</span> <span class="preprocessor"> #define __CM4_REV 0x0000</span></div>
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<div class="line"><a name="l00184"></a><span class="lineno"> 184</span> <span class="preprocessor"> #warning "__CM4_REV not defined in device header file; using default!"</span></div>
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<div class="line"><a name="l00185"></a><span class="lineno"> 185</span> <span class="preprocessor"> #endif</span></div>
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<div class="line"><a name="l00186"></a><span class="lineno"> 186</span> </div>
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<div class="line"><a name="l00187"></a><span class="lineno"> 187</span> <span class="preprocessor"> #ifndef __FPU_PRESENT</span></div>
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<div class="line"><a name="l00188"></a><span class="lineno"> 188</span> <span class="preprocessor"> #define __FPU_PRESENT 0</span></div>
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<div class="line"><a name="l00189"></a><span class="lineno"> 189</span> <span class="preprocessor"> #warning "__FPU_PRESENT not defined in device header file; using default!"</span></div>
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|
<div class="line"><a name="l00190"></a><span class="lineno"> 190</span> <span class="preprocessor"> #endif</span></div>
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<div class="line"><a name="l00191"></a><span class="lineno"> 191</span> </div>
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<div class="line"><a name="l00192"></a><span class="lineno"> 192</span> <span class="preprocessor"> #ifndef __MPU_PRESENT</span></div>
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<div class="line"><a name="l00193"></a><span class="lineno"> 193</span> <span class="preprocessor"> #define __MPU_PRESENT 0</span></div>
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|
<div class="line"><a name="l00194"></a><span class="lineno"> 194</span> <span class="preprocessor"> #warning "__MPU_PRESENT not defined in device header file; using default!"</span></div>
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|
<div class="line"><a name="l00195"></a><span class="lineno"> 195</span> <span class="preprocessor"> #endif</span></div>
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<div class="line"><a name="l00196"></a><span class="lineno"> 196</span> </div>
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<div class="line"><a name="l00197"></a><span class="lineno"> 197</span> <span class="preprocessor"> #ifndef __NVIC_PRIO_BITS</span></div>
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<div class="line"><a name="l00198"></a><span class="lineno"> 198</span> <span class="preprocessor"> #define __NVIC_PRIO_BITS 4</span></div>
|
|
<div class="line"><a name="l00199"></a><span class="lineno"> 199</span> <span class="preprocessor"> #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"</span></div>
|
|
<div class="line"><a name="l00200"></a><span class="lineno"> 200</span> <span class="preprocessor"> #endif</span></div>
|
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<div class="line"><a name="l00201"></a><span class="lineno"> 201</span> </div>
|
|
<div class="line"><a name="l00202"></a><span class="lineno"> 202</span> <span class="preprocessor"> #ifndef __Vendor_SysTickConfig</span></div>
|
|
<div class="line"><a name="l00203"></a><span class="lineno"> 203</span> <span class="preprocessor"> #define __Vendor_SysTickConfig 0</span></div>
|
|
<div class="line"><a name="l00204"></a><span class="lineno"> 204</span> <span class="preprocessor"> #warning "__Vendor_SysTickConfig not defined in device header file; using default!"</span></div>
|
|
<div class="line"><a name="l00205"></a><span class="lineno"> 205</span> <span class="preprocessor"> #endif</span></div>
|
|
<div class="line"><a name="l00206"></a><span class="lineno"> 206</span> <span class="preprocessor">#endif</span></div>
|
|
<div class="line"><a name="l00207"></a><span class="lineno"> 207</span> </div>
|
|
<div class="line"><a name="l00208"></a><span class="lineno"> 208</span> <span class="comment">/* IO definitions (access restrictions to peripheral registers) */</span></div>
|
|
<div class="line"><a name="l00216"></a><span class="lineno"> 216</span> <span class="preprocessor">#ifdef __cplusplus</span></div>
|
|
<div class="line"><a name="l00217"></a><span class="lineno"> 217</span> <span class="preprocessor"> #define __I volatile </span></div>
|
|
<div class="line"><a name="l00218"></a><span class="lineno"> 218</span> <span class="preprocessor">#else</span></div>
|
|
<div class="line"><a name="l00219"></a><span class="lineno"><a class="line" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3"> 219</a></span> <span class="preprocessor"> #define __I volatile const </span></div>
|
|
<div class="line"><a name="l00220"></a><span class="lineno"> 220</span> <span class="preprocessor">#endif</span></div>
|
|
<div class="line"><a name="l00221"></a><span class="lineno"><a class="line" href="core__cm4_8h.html#a7e25d9380f9ef903923964322e71f2f6"> 221</a></span> <span class="preprocessor">#define __O volatile </span></div>
|
|
<div class="line"><a name="l00222"></a><span class="lineno"><a class="line" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be"> 222</a></span> <span class="preprocessor">#define __IO volatile </span></div>
|
|
<div class="line"><a name="l00224"></a><span class="lineno"> 224</span> <span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00228"></a><span class="lineno"> 228</span> <span class="preprocessor"></span><span class="comment">/*******************************************************************************</span></div>
|
|
<div class="line"><a name="l00229"></a><span class="lineno"> 229</span> <span class="comment"> * Register Abstraction</span></div>
|
|
<div class="line"><a name="l00230"></a><span class="lineno"> 230</span> <span class="comment"> Core Register contain:</span></div>
|
|
<div class="line"><a name="l00231"></a><span class="lineno"> 231</span> <span class="comment"> - Core Register</span></div>
|
|
<div class="line"><a name="l00232"></a><span class="lineno"> 232</span> <span class="comment"> - Core NVIC Register</span></div>
|
|
<div class="line"><a name="l00233"></a><span class="lineno"> 233</span> <span class="comment"> - Core SCB Register</span></div>
|
|
<div class="line"><a name="l00234"></a><span class="lineno"> 234</span> <span class="comment"> - Core SysTick Register</span></div>
|
|
<div class="line"><a name="l00235"></a><span class="lineno"> 235</span> <span class="comment"> - Core Debug Register</span></div>
|
|
<div class="line"><a name="l00236"></a><span class="lineno"> 236</span> <span class="comment"> - Core MPU Register</span></div>
|
|
<div class="line"><a name="l00237"></a><span class="lineno"> 237</span> <span class="comment"> - Core FPU Register</span></div>
|
|
<div class="line"><a name="l00238"></a><span class="lineno"> 238</span> <span class="comment"> ******************************************************************************/</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l00239"></a><span class="lineno"> 239</span> </div>
|
|
<div class="line"><a name="l00251"></a><span class="lineno"><a class="line" href="union_a_p_s_r___type.html"> 251</a></span> <span class="keyword">typedef</span> <span class="keyword">union</span></div>
|
|
<div class="line"><a name="l00252"></a><span class="lineno"> 252</span> {</div>
|
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<div class="line"><a name="l00253"></a><span class="lineno"> 253</span>  <span class="keyword">struct</span></div>
|
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<div class="line"><a name="l00254"></a><span class="lineno"> 254</span>  {</div>
|
|
<div class="line"><a name="l00255"></a><span class="lineno"> 255</span> <span class="preprocessor">#if (__CORTEX_M != 0x04)</span></div>
|
|
<div class="line"><a name="l00256"></a><span class="lineno"> 256</span>  uint32_t _reserved0:27; </div>
|
|
<div class="line"><a name="l00257"></a><span class="lineno"> 257</span> <span class="preprocessor">#else</span></div>
|
|
<div class="line"><a name="l00258"></a><span class="lineno"><a class="line" href="union_a_p_s_r___type.html#afbce95646fd514c10aa85ec0a33db728"> 258</a></span>  uint32_t _reserved0:16; </div>
|
|
<div class="line"><a name="l00259"></a><span class="lineno"><a class="line" href="union_a_p_s_r___type.html#adcb98a5b9c93b0cb69cdb7af5638f32e"> 259</a></span>  uint32_t GE:4; </div>
|
|
<div class="line"><a name="l00260"></a><span class="lineno"><a class="line" href="union_a_p_s_r___type.html#ac681f266e20b3b3591b961e13633ae13"> 260</a></span>  uint32_t _reserved1:7; </div>
|
|
<div class="line"><a name="l00261"></a><span class="lineno"> 261</span> <span class="preprocessor">#endif</span></div>
|
|
<div class="line"><a name="l00262"></a><span class="lineno"><a class="line" href="union_a_p_s_r___type.html#a22d10913489d24ab08bd83457daa88de"> 262</a></span>  uint32_t Q:1; </div>
|
|
<div class="line"><a name="l00263"></a><span class="lineno"><a class="line" href="union_a_p_s_r___type.html#a8004d224aacb78ca37774c35f9156e7e"> 263</a></span>  uint32_t V:1; </div>
|
|
<div class="line"><a name="l00264"></a><span class="lineno"><a class="line" href="union_a_p_s_r___type.html#a86e2c5b891ecef1ab55b1edac0da79a6"> 264</a></span>  uint32_t C:1; </div>
|
|
<div class="line"><a name="l00265"></a><span class="lineno"><a class="line" href="union_a_p_s_r___type.html#a3b04d58738b66a28ff13f23d8b0ba7e5"> 265</a></span>  uint32_t Z:1; </div>
|
|
<div class="line"><a name="l00266"></a><span class="lineno"><a class="line" href="union_a_p_s_r___type.html#a7e7bbba9b00b0bb3283dc07f1abe37e0"> 266</a></span>  uint32_t N:1; </div>
|
|
<div class="line"><a name="l00267"></a><span class="lineno"> 267</span>  } b; </div>
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|
<div class="line"><a name="l00268"></a><span class="lineno"><a class="line" href="union_a_p_s_r___type.html#ae4c2ef8c9430d7b7bef5cbfbbaed3a94"> 268</a></span>  uint32_t <a class="code" href="union_a_p_s_r___type.html#ae4c2ef8c9430d7b7bef5cbfbbaed3a94">w</a>; </div>
|
|
<div class="line"><a name="l00269"></a><span class="lineno"> 269</span> } <a class="code" href="union_a_p_s_r___type.html">APSR_Type</a>;</div>
|
|
<div class="line"><a name="l00270"></a><span class="lineno"> 270</span> </div>
|
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<div class="line"><a name="l00271"></a><span class="lineno"> 271</span> </div>
|
|
<div class="line"><a name="l00274"></a><span class="lineno"><a class="line" href="union_i_p_s_r___type.html"> 274</a></span> <span class="keyword">typedef</span> <span class="keyword">union</span></div>
|
|
<div class="line"><a name="l00275"></a><span class="lineno"> 275</span> {</div>
|
|
<div class="line"><a name="l00276"></a><span class="lineno"> 276</span>  <span class="keyword">struct</span></div>
|
|
<div class="line"><a name="l00277"></a><span class="lineno"> 277</span>  {</div>
|
|
<div class="line"><a name="l00278"></a><span class="lineno"><a class="line" href="union_i_p_s_r___type.html#ab46e5f1b2f4d17cfb9aca4fffcbb2fa5"> 278</a></span>  uint32_t ISR:9; </div>
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<div class="line"><a name="l00279"></a><span class="lineno"><a class="line" href="union_i_p_s_r___type.html#ad2eb0a06de4f03f58874a727716aa9aa"> 279</a></span>  uint32_t _reserved0:23; </div>
|
|
<div class="line"><a name="l00280"></a><span class="lineno"> 280</span>  } b; </div>
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|
<div class="line"><a name="l00281"></a><span class="lineno"><a class="line" href="union_i_p_s_r___type.html#a4adca999d3a0bc1ae682d73ea7cfa879"> 281</a></span>  uint32_t <a class="code" href="union_i_p_s_r___type.html#a4adca999d3a0bc1ae682d73ea7cfa879">w</a>; </div>
|
|
<div class="line"><a name="l00282"></a><span class="lineno"> 282</span> } <a class="code" href="union_i_p_s_r___type.html">IPSR_Type</a>;</div>
|
|
<div class="line"><a name="l00283"></a><span class="lineno"> 283</span> </div>
|
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<div class="line"><a name="l00284"></a><span class="lineno"> 284</span> </div>
|
|
<div class="line"><a name="l00287"></a><span class="lineno"><a class="line" href="unionx_p_s_r___type.html"> 287</a></span> <span class="keyword">typedef</span> <span class="keyword">union</span></div>
|
|
<div class="line"><a name="l00288"></a><span class="lineno"> 288</span> {</div>
|
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<div class="line"><a name="l00289"></a><span class="lineno"> 289</span>  <span class="keyword">struct</span></div>
|
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<div class="line"><a name="l00290"></a><span class="lineno"> 290</span>  {</div>
|
|
<div class="line"><a name="l00291"></a><span class="lineno"><a class="line" href="unionx_p_s_r___type.html#a3e9120dcf1a829fc8d2302b4d0673970"> 291</a></span>  uint32_t ISR:9; </div>
|
|
<div class="line"><a name="l00292"></a><span class="lineno"> 292</span> <span class="preprocessor">#if (__CORTEX_M != 0x04)</span></div>
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|
<div class="line"><a name="l00293"></a><span class="lineno"> 293</span>  uint32_t _reserved0:15; </div>
|
|
<div class="line"><a name="l00294"></a><span class="lineno"> 294</span> <span class="preprocessor">#else</span></div>
|
|
<div class="line"><a name="l00295"></a><span class="lineno"><a class="line" href="unionx_p_s_r___type.html#af438e0f407357e914a70b5bd4d6a97c5"> 295</a></span>  uint32_t _reserved0:7; </div>
|
|
<div class="line"><a name="l00296"></a><span class="lineno"><a class="line" href="unionx_p_s_r___type.html#a2d0ec4ccae337c1df5658f8cf4632e76"> 296</a></span>  uint32_t GE:4; </div>
|
|
<div class="line"><a name="l00297"></a><span class="lineno"><a class="line" href="unionx_p_s_r___type.html#a790056bb6f20ea16cecc784b0dd19ad6"> 297</a></span>  uint32_t _reserved1:4; </div>
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|
<div class="line"><a name="l00298"></a><span class="lineno"> 298</span> <span class="preprocessor">#endif</span></div>
|
|
<div class="line"><a name="l00299"></a><span class="lineno"><a class="line" href="unionx_p_s_r___type.html#a7eed9fe24ae8d354cd76ae1c1110a658"> 299</a></span>  uint32_t T:1; </div>
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|
<div class="line"><a name="l00300"></a><span class="lineno"><a class="line" href="unionx_p_s_r___type.html#a3200966922a194d84425e2807a7f1328"> 300</a></span>  uint32_t IT:2; </div>
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|
<div class="line"><a name="l00301"></a><span class="lineno"><a class="line" href="unionx_p_s_r___type.html#add7cbd2b0abd8954d62cd7831796ac7c"> 301</a></span>  uint32_t Q:1; </div>
|
|
<div class="line"><a name="l00302"></a><span class="lineno"><a class="line" href="unionx_p_s_r___type.html#af14df16ea0690070c45b95f2116b7a0a"> 302</a></span>  uint32_t V:1; </div>
|
|
<div class="line"><a name="l00303"></a><span class="lineno"><a class="line" href="unionx_p_s_r___type.html#a40213a6b5620410cac83b0d89564609d"> 303</a></span>  uint32_t C:1; </div>
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|
<div class="line"><a name="l00304"></a><span class="lineno"><a class="line" href="unionx_p_s_r___type.html#a1e5d9801013d5146f2e02d9b7b3da562"> 304</a></span>  uint32_t Z:1; </div>
|
|
<div class="line"><a name="l00305"></a><span class="lineno"><a class="line" href="unionx_p_s_r___type.html#a2db9a52f6d42809627d1a7a607c5dbc5"> 305</a></span>  uint32_t N:1; </div>
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<div class="line"><a name="l00306"></a><span class="lineno"> 306</span>  } b; </div>
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<div class="line"><a name="l00307"></a><span class="lineno"><a class="line" href="unionx_p_s_r___type.html#a1a47176768f45f79076c4f5b1b534bc2"> 307</a></span>  uint32_t <a class="code" href="unionx_p_s_r___type.html#a1a47176768f45f79076c4f5b1b534bc2">w</a>; </div>
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<div class="line"><a name="l00308"></a><span class="lineno"> 308</span> } <a class="code" href="unionx_p_s_r___type.html">xPSR_Type</a>;</div>
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<div class="line"><a name="l00309"></a><span class="lineno"> 309</span> </div>
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<div class="line"><a name="l00310"></a><span class="lineno"> 310</span> </div>
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<div class="line"><a name="l00313"></a><span class="lineno"><a class="line" href="union_c_o_n_t_r_o_l___type.html"> 313</a></span> <span class="keyword">typedef</span> <span class="keyword">union</span></div>
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<div class="line"><a name="l00314"></a><span class="lineno"> 314</span> {</div>
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<div class="line"><a name="l00315"></a><span class="lineno"> 315</span>  <span class="keyword">struct</span></div>
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<div class="line"><a name="l00316"></a><span class="lineno"> 316</span>  {</div>
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<div class="line"><a name="l00317"></a><span class="lineno"><a class="line" href="union_c_o_n_t_r_o_l___type.html#a35c1732cf153b7b5c4bd321cf1de9605"> 317</a></span>  uint32_t nPRIV:1; </div>
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<div class="line"><a name="l00318"></a><span class="lineno"><a class="line" href="union_c_o_n_t_r_o_l___type.html#a8cc085fea1c50a8bd9adea63931ee8e2"> 318</a></span>  uint32_t SPSEL:1; </div>
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<div class="line"><a name="l00319"></a><span class="lineno"><a class="line" href="union_c_o_n_t_r_o_l___type.html#ac62cfff08e6f055e0101785bad7094cd"> 319</a></span>  uint32_t FPCA:1; </div>
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<div class="line"><a name="l00320"></a><span class="lineno"><a class="line" href="union_c_o_n_t_r_o_l___type.html#af8c314273a1e4970a5671bd7f8184f50"> 320</a></span>  uint32_t _reserved0:29; </div>
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<div class="line"><a name="l00321"></a><span class="lineno"> 321</span>  } b; </div>
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<div class="line"><a name="l00322"></a><span class="lineno"><a class="line" href="union_c_o_n_t_r_o_l___type.html#a6b642cca3d96da660b1198c133ca2a1f"> 322</a></span>  uint32_t <a class="code" href="union_c_o_n_t_r_o_l___type.html#a6b642cca3d96da660b1198c133ca2a1f">w</a>; </div>
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<div class="line"><a name="l00323"></a><span class="lineno"> 323</span> } <a class="code" href="union_c_o_n_t_r_o_l___type.html">CONTROL_Type</a>;</div>
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<div class="line"><a name="l00324"></a><span class="lineno"> 324</span> </div>
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<div class="line"><a name="l00336"></a><span class="lineno"><a class="line" href="struct_n_v_i_c___type.html"> 336</a></span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00337"></a><span class="lineno"> 337</span> {</div>
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<div class="line"><a name="l00338"></a><span class="lineno"><a class="line" href="struct_n_v_i_c___type.html#af90c80b7c2b48e248780b3781e0df80f"> 338</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ISER[8]; </div>
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<div class="line"><a name="l00339"></a><span class="lineno"> 339</span>  uint32_t RESERVED0[24];</div>
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<div class="line"><a name="l00340"></a><span class="lineno"><a class="line" href="struct_n_v_i_c___type.html#a1965a2e68b61d2e2009621f6949211a5"> 340</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ICER[8]; </div>
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<div class="line"><a name="l00341"></a><span class="lineno"> 341</span>  uint32_t RSERVED1[24];</div>
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<div class="line"><a name="l00342"></a><span class="lineno"><a class="line" href="struct_n_v_i_c___type.html#acf8e38fc2e97316242ddeb7ea959ab90"> 342</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ISPR[8]; </div>
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<div class="line"><a name="l00343"></a><span class="lineno"> 343</span>  uint32_t RESERVED2[24];</div>
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<div class="line"><a name="l00344"></a><span class="lineno"><a class="line" href="struct_n_v_i_c___type.html#a46241be64208436d35c9a4f8552575c5"> 344</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t ICPR[8]; </div>
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<div class="line"><a name="l00345"></a><span class="lineno"> 345</span>  uint32_t RESERVED3[24];</div>
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<div class="line"><a name="l00346"></a><span class="lineno"><a class="line" href="struct_n_v_i_c___type.html#a33e917b381e08dabe4aa5eb2881a7c11"> 346</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t IABR[8]; </div>
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<div class="line"><a name="l00347"></a><span class="lineno"> 347</span>  uint32_t RESERVED4[56];</div>
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<div class="line"><a name="l00348"></a><span class="lineno"><a class="line" href="struct_n_v_i_c___type.html#a6524789fedb94623822c3e0a47f3d06c"> 348</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint8_t IP[240]; </div>
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<div class="line"><a name="l00349"></a><span class="lineno"> 349</span>  uint32_t RESERVED5[644];</div>
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<div class="line"><a name="l00350"></a><span class="lineno"><a class="line" href="struct_n_v_i_c___type.html#a0b0d7f3131da89c659a2580249432749"> 350</a></span>  <a class="code" href="core__cm4_8h.html#a7e25d9380f9ef903923964322e71f2f6">__O</a> uint32_t <a class="code" href="struct_n_v_i_c___type.html#a0b0d7f3131da89c659a2580249432749">STIR</a>; </div>
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<div class="line"><a name="l00351"></a><span class="lineno"> 351</span> } <a class="code" href="struct_n_v_i_c___type.html">NVIC_Type</a>;</div>
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<div class="line"><a name="l00352"></a><span class="lineno"> 352</span> </div>
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<div class="line"><a name="l00353"></a><span class="lineno"> 353</span> <span class="comment">/* Software Triggered Interrupt Register Definitions */</span></div>
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<div class="line"><a name="l00354"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___n_v_i_c.html#ga9eebe495e2e48d302211108837a2b3e8"> 354</a></span> <span class="preprocessor">#define NVIC_STIR_INTID_Pos 0 </span></div>
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<div class="line"><a name="l00355"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___n_v_i_c.html#gae4060c4dfcebb08871ca4244176ce752"> 355</a></span> <span class="preprocessor">#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) </span></div>
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<div class="line"><a name="l00357"></a><span class="lineno"> 357</span> <span class="preprocessor"></span></div>
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<div class="line"><a name="l00368"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html"> 368</a></span> <span class="preprocessor">typedef struct</span></div>
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<div class="line"><a name="l00369"></a><span class="lineno"> 369</span> {</div>
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<div class="line"><a name="l00370"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#afa7a9ee34dfa1da0b60b4525da285032"> 370</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_s_c_b___type.html#afa7a9ee34dfa1da0b60b4525da285032">CPUID</a>; </div>
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<div class="line"><a name="l00371"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#a3e66570ab689d28aebefa7e84e85dc4a"> 371</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_c_b___type.html#a3e66570ab689d28aebefa7e84e85dc4a">ICSR</a>; </div>
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<div class="line"><a name="l00372"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#a0faf96f964931cadfb71cfa54e051f6f"> 372</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_c_b___type.html#a0faf96f964931cadfb71cfa54e051f6f">VTOR</a>; </div>
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<div class="line"><a name="l00373"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#a6ed3c9064013343ea9fd0a73a734f29d"> 373</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_c_b___type.html#a6ed3c9064013343ea9fd0a73a734f29d">AIRCR</a>; </div>
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<div class="line"><a name="l00374"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#abfad14e7b4534d73d329819625d77a16"> 374</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_c_b___type.html#abfad14e7b4534d73d329819625d77a16">SCR</a>; </div>
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<div class="line"><a name="l00375"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#a6d273c6b90bad15c91dfbbad0f6e92d8"> 375</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_c_b___type.html#a6d273c6b90bad15c91dfbbad0f6e92d8">CCR</a>; </div>
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<div class="line"><a name="l00376"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#af6336103f8be0cab29de51daed5a65f4"> 376</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint8_t SHP[12]; </div>
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<div class="line"><a name="l00377"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#ae9891a59abbe51b0b2067ca507ca212f"> 377</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_c_b___type.html#ae9891a59abbe51b0b2067ca507ca212f">SHCSR</a>; </div>
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<div class="line"><a name="l00378"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#a2f94bf549b16fdeb172352e22309e3c4"> 378</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_c_b___type.html#a2f94bf549b16fdeb172352e22309e3c4">CFSR</a>; </div>
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<div class="line"><a name="l00379"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#a7bed53391da4f66d8a2a236a839d4c3d"> 379</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_c_b___type.html#a7bed53391da4f66d8a2a236a839d4c3d">HFSR</a>; </div>
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<div class="line"><a name="l00380"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#ad7d61d9525fa9162579c3da0b87bff8d"> 380</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_c_b___type.html#ad7d61d9525fa9162579c3da0b87bff8d">DFSR</a>; </div>
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<div class="line"><a name="l00381"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#ac49b24b3f222508464f111772f2c44dd"> 381</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_c_b___type.html#ac49b24b3f222508464f111772f2c44dd">MMFAR</a>; </div>
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<div class="line"><a name="l00382"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#a31f79afe86c949c9862e7d5fce077c3a"> 382</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_c_b___type.html#a31f79afe86c949c9862e7d5fce077c3a">BFAR</a>; </div>
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<div class="line"><a name="l00383"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#aeb77053c84f49c261ab5b8374e8958ef"> 383</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_c_b___type.html#aeb77053c84f49c261ab5b8374e8958ef">AFSR</a>; </div>
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<div class="line"><a name="l00384"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#a3f51c43f952f3799951d0c54e76b0cb7"> 384</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t PFR[2]; </div>
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<div class="line"><a name="l00385"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#a586a5225467262b378c0f231ccc77f86"> 385</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_s_c_b___type.html#a586a5225467262b378c0f231ccc77f86">DFR</a>; </div>
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<div class="line"><a name="l00386"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#aaedf846e435ed05c68784b40d3db2bf2"> 386</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_s_c_b___type.html#aaedf846e435ed05c68784b40d3db2bf2">ADR</a>; </div>
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<div class="line"><a name="l00387"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#aec2f8283d2737c6897188568a4214976"> 387</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t MMFR[4]; </div>
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<div class="line"><a name="l00388"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#acee8e458f054aac964268f4fe647ea4f"> 388</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t ISAR[5]; </div>
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<div class="line"><a name="l00389"></a><span class="lineno"> 389</span>  uint32_t RESERVED0[5];</div>
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<div class="line"><a name="l00390"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#af460b56ce524a8e3534173f0aee78e85"> 390</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_c_b___type.html#af460b56ce524a8e3534173f0aee78e85">CPACR</a>; </div>
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<div class="line"><a name="l00391"></a><span class="lineno"> 391</span> } <a class="code" href="struct_s_c_b___type.html">SCB_Type</a>;</div>
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<div class="line"><a name="l00392"></a><span class="lineno"> 392</span> </div>
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<div class="line"><a name="l00393"></a><span class="lineno"> 393</span> <span class="comment">/* SCB CPUID Register Definitions */</span></div>
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<div class="line"><a name="l00394"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga58686b88f94f789d4e6f429fe1ff58cf"> 394</a></span> <span class="preprocessor">#define SCB_CPUID_IMPLEMENTER_Pos 24 </span></div>
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<div class="line"><a name="l00395"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga0932b31faafd47656a03ced75a31d99b"> 395</a></span> <span class="preprocessor">#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) </span></div>
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<div class="line"><a name="l00397"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga104462bd0815391b4044a70bd15d3a71"> 397</a></span> <span class="preprocessor">#define SCB_CPUID_VARIANT_Pos 20 </span></div>
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<div class="line"><a name="l00398"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gad358dfbd04300afc1824329d128b99e8"> 398</a></span> <span class="preprocessor">#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) </span></div>
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<div class="line"><a name="l00400"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaf8b3236b08fb8e840efb682645fb0e98"> 400</a></span> <span class="preprocessor">#define SCB_CPUID_ARCHITECTURE_Pos 16 </span></div>
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<div class="line"><a name="l00401"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gafae4a1f27a927338ae9dc51a0e146213"> 401</a></span> <span class="preprocessor">#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) </span></div>
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<div class="line"><a name="l00403"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga705f68eaa9afb042ca2407dc4e4629ac"> 403</a></span> <span class="preprocessor">#define SCB_CPUID_PARTNO_Pos 4 </span></div>
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<div class="line"><a name="l00404"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga98e581423ca016680c238c469aba546d"> 404</a></span> <span class="preprocessor">#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) </span></div>
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<div class="line"><a name="l00406"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga3c3d9071e574de11fb27ba57034838b1"> 406</a></span> <span class="preprocessor">#define SCB_CPUID_REVISION_Pos 0 </span></div>
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<div class="line"><a name="l00407"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga2ec0448b6483f77e7f5d08b4b81d85df"> 407</a></span> <span class="preprocessor">#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) </span></div>
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<div class="line"><a name="l00409"></a><span class="lineno"> 409</span> <span class="preprocessor"></span><span class="comment">/* SCB Interrupt Control State Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00410"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga750d4b52624a46d71356db4ea769573b"> 410</a></span> <span class="preprocessor">#define SCB_ICSR_NMIPENDSET_Pos 31 </span></div>
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<div class="line"><a name="l00411"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga340e3f79e9c3607dee9f2c048b6b22e8"> 411</a></span> <span class="preprocessor">#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) </span></div>
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<div class="line"><a name="l00413"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gab5ded23d2ab1d5ff7cc7ce746205e9fe"> 413</a></span> <span class="preprocessor">#define SCB_ICSR_PENDSVSET_Pos 28 </span></div>
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<div class="line"><a name="l00414"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga1e40d93efb402763c8c00ddcc56724ff"> 414</a></span> <span class="preprocessor">#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) </span></div>
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<div class="line"><a name="l00416"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gae218d9022288f89faf57187c4d542ecd"> 416</a></span> <span class="preprocessor">#define SCB_ICSR_PENDSVCLR_Pos 27 </span></div>
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<div class="line"><a name="l00417"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga4a901ace381d3c1c74ac82b22fae2e1e"> 417</a></span> <span class="preprocessor">#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) </span></div>
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<div class="line"><a name="l00419"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga9dbb3358c6167c9c3f85661b90fb2794"> 419</a></span> <span class="preprocessor">#define SCB_ICSR_PENDSTSET_Pos 26 </span></div>
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<div class="line"><a name="l00420"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga7325b61ea0ec323ef2d5c893b112e546"> 420</a></span> <span class="preprocessor">#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) </span></div>
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<div class="line"><a name="l00422"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gadbe25e4b333ece1341beb1a740168fdc"> 422</a></span> <span class="preprocessor">#define SCB_ICSR_PENDSTCLR_Pos 25 </span></div>
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<div class="line"><a name="l00423"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gab241827d2a793269d8cd99b9b28c2157"> 423</a></span> <span class="preprocessor">#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) </span></div>
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<div class="line"><a name="l00425"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga11cb5b1f9ce167b81f31787a77e575df"> 425</a></span> <span class="preprocessor">#define SCB_ICSR_ISRPREEMPT_Pos 23 </span></div>
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<div class="line"><a name="l00426"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaa966600396290808d596fe96e92ca2b5"> 426</a></span> <span class="preprocessor">#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) </span></div>
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<div class="line"><a name="l00428"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga10749d92b9b744094b845c2eb46d4319"> 428</a></span> <span class="preprocessor">#define SCB_ICSR_ISRPENDING_Pos 22 </span></div>
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<div class="line"><a name="l00429"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga056d74fd538e5d36d3be1f28d399c877"> 429</a></span> <span class="preprocessor">#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) </span></div>
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<div class="line"><a name="l00431"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gada60c92bf88d6fd21a8f49efa4a127b8"> 431</a></span> <span class="preprocessor">#define SCB_ICSR_VECTPENDING_Pos 12 </span></div>
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<div class="line"><a name="l00432"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gacb6992e7c7ddc27a370f62878a21ef72"> 432</a></span> <span class="preprocessor">#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) </span></div>
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<div class="line"><a name="l00434"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga403d154200242629e6d2764bfc12a7ec"> 434</a></span> <span class="preprocessor">#define SCB_ICSR_RETTOBASE_Pos 11 </span></div>
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<div class="line"><a name="l00435"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaca6fc3f79bb550f64fd7df782ed4a5f6"> 435</a></span> <span class="preprocessor">#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) </span></div>
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<div class="line"><a name="l00437"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gae4f602c7c5c895d5fb687b71b0979fc3"> 437</a></span> <span class="preprocessor">#define SCB_ICSR_VECTACTIVE_Pos 0 </span></div>
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<div class="line"><a name="l00438"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga5533791a4ecf1b9301c883047b3e8396"> 438</a></span> <span class="preprocessor">#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) </span></div>
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<div class="line"><a name="l00440"></a><span class="lineno"> 440</span> <span class="preprocessor"></span><span class="comment">/* SCB Vector Table Offset Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00441"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gac6a55451ddd38bffcff5a211d29cea78"> 441</a></span> <span class="preprocessor">#define SCB_VTOR_TBLOFF_Pos 7 </span></div>
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<div class="line"><a name="l00442"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga75e395ed74042923e8c93edf50f0996c"> 442</a></span> <span class="preprocessor">#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) </span></div>
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<div class="line"><a name="l00444"></a><span class="lineno"> 444</span> <span class="preprocessor"></span><span class="comment">/* SCB Application Interrupt and Reset Control Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00445"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaaa27c0ba600bf82c3da08c748845b640"> 445</a></span> <span class="preprocessor">#define SCB_AIRCR_VECTKEY_Pos 16 </span></div>
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<div class="line"><a name="l00446"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga90c7cf0c490e7ae55f9503a7fda1dd22"> 446</a></span> <span class="preprocessor">#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) </span></div>
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<div class="line"><a name="l00448"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaec404750ff5ca07f499a3c06b62051ef"> 448</a></span> <span class="preprocessor">#define SCB_AIRCR_VECTKEYSTAT_Pos 16 </span></div>
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<div class="line"><a name="l00449"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gabacedaefeefc73d666bbe59ece904493"> 449</a></span> <span class="preprocessor">#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) </span></div>
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<div class="line"><a name="l00451"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gad31dec98fbc0d33ace63cb1f1a927923"> 451</a></span> <span class="preprocessor">#define SCB_AIRCR_ENDIANESS_Pos 15 </span></div>
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<div class="line"><a name="l00452"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga2f571f93d3d4a6eac9a3040756d3d951"> 452</a></span> <span class="preprocessor">#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) </span></div>
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<div class="line"><a name="l00454"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaca155deccdeca0f2c76b8100d24196c8"> 454</a></span> <span class="preprocessor">#define SCB_AIRCR_PRIGROUP_Pos 8 </span></div>
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<div class="line"><a name="l00455"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga8be60fff03f48d0d345868060dc6dae7"> 455</a></span> <span class="preprocessor">#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) </span></div>
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<div class="line"><a name="l00457"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaffb2737eca1eac0fc1c282a76a40953c"> 457</a></span> <span class="preprocessor">#define SCB_AIRCR_SYSRESETREQ_Pos 2 </span></div>
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<div class="line"><a name="l00458"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaae1181119559a5bd36e62afa373fa720"> 458</a></span> <span class="preprocessor">#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) </span></div>
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<div class="line"><a name="l00460"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaa30a12e892bb696e61626d71359a9029"> 460</a></span> <span class="preprocessor">#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 </span></div>
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<div class="line"><a name="l00461"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga212c5ab1c1c82c807d30d2307aa8d218"> 461</a></span> <span class="preprocessor">#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) </span></div>
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<div class="line"><a name="l00463"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga0d483d9569cd9d1b46ec0d171b1f18d8"> 463</a></span> <span class="preprocessor">#define SCB_AIRCR_VECTRESET_Pos 0 </span></div>
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<div class="line"><a name="l00464"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga3006e31968bb9725e7b4ee0784d99f7f"> 464</a></span> <span class="preprocessor">#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) </span></div>
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<div class="line"><a name="l00466"></a><span class="lineno"> 466</span> <span class="preprocessor"></span><span class="comment">/* SCB System Control Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00467"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga3bddcec40aeaf3d3a998446100fa0e44"> 467</a></span> <span class="preprocessor">#define SCB_SCR_SEVONPEND_Pos 4 </span></div>
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<div class="line"><a name="l00468"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gafb98656644a14342e467505f69a997c9"> 468</a></span> <span class="preprocessor">#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) </span></div>
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<div class="line"><a name="l00470"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gab304f6258ec03bd9a6e7a360515c3cfe"> 470</a></span> <span class="preprocessor">#define SCB_SCR_SLEEPDEEP_Pos 2 </span></div>
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<div class="line"><a name="l00471"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga77c06a69c63f4b3f6ec1032e911e18e7"> 471</a></span> <span class="preprocessor">#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) </span></div>
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<div class="line"><a name="l00473"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga3680a15114d7fdc1e25043b881308fe9"> 473</a></span> <span class="preprocessor">#define SCB_SCR_SLEEPONEXIT_Pos 1 </span></div>
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<div class="line"><a name="l00474"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga50a243e317b9a70781b02758d45b05ee"> 474</a></span> <span class="preprocessor">#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) </span></div>
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<div class="line"><a name="l00476"></a><span class="lineno"> 476</span> <span class="preprocessor"></span><span class="comment">/* SCB Configuration Control Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00477"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gac2d20a250960a432cc74da59d20e2f86"> 477</a></span> <span class="preprocessor">#define SCB_CCR_STKALIGN_Pos 9 </span></div>
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<div class="line"><a name="l00478"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga33cf22d3d46af158a03aad25ddea1bcb"> 478</a></span> <span class="preprocessor">#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) </span></div>
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<div class="line"><a name="l00480"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga4010a4f9e2a745af1b58abe1f791ebbf"> 480</a></span> <span class="preprocessor">#define SCB_CCR_BFHFNMIGN_Pos 8 </span></div>
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<div class="line"><a name="l00481"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga89a28cc31cfc7d52d9d7a8fcc69c7eac"> 481</a></span> <span class="preprocessor">#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) </span></div>
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<div class="line"><a name="l00483"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gac8d512998bb8cd9333fb7627ddf59bba"> 483</a></span> <span class="preprocessor">#define SCB_CCR_DIV_0_TRP_Pos 4 </span></div>
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<div class="line"><a name="l00484"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gabb9aeac71b3abd8586d0297070f61dcb"> 484</a></span> <span class="preprocessor">#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) </span></div>
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<div class="line"><a name="l00486"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gac4e4928b864ea10fc24dbbc57d976229"> 486</a></span> <span class="preprocessor">#define SCB_CCR_UNALIGN_TRP_Pos 3 </span></div>
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<div class="line"><a name="l00487"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga68c96ad594af70c007923979085c99e0"> 487</a></span> <span class="preprocessor">#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) </span></div>
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<div class="line"><a name="l00489"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga789e41f45f59a8cd455fd59fa7652e5e"> 489</a></span> <span class="preprocessor">#define SCB_CCR_USERSETMPEND_Pos 1 </span></div>
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<div class="line"><a name="l00490"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga4cf59b6343ca962c80e1885710da90aa"> 490</a></span> <span class="preprocessor">#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) </span></div>
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<div class="line"><a name="l00492"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gab4615f7deb07386350365b10240a3c83"> 492</a></span> <span class="preprocessor">#define SCB_CCR_NONBASETHRDENA_Pos 0 </span></div>
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<div class="line"><a name="l00493"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gafe0f6be81b35d72d0736a0a1e3b4fbb3"> 493</a></span> <span class="preprocessor">#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) </span></div>
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<div class="line"><a name="l00495"></a><span class="lineno"> 495</span> <span class="preprocessor"></span><span class="comment">/* SCB System Handler Control and State Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00496"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gae71949507636fda388ec11d5c2d30b52"> 496</a></span> <span class="preprocessor">#define SCB_SHCSR_USGFAULTENA_Pos 18 </span></div>
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<div class="line"><a name="l00497"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga056fb6be590857bbc029bed48b21dd79"> 497</a></span> <span class="preprocessor">#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) </span></div>
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<div class="line"><a name="l00499"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga3d32edbe4a5c0335f808cfc19ec7e844"> 499</a></span> <span class="preprocessor">#define SCB_SHCSR_BUSFAULTENA_Pos 17 </span></div>
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<div class="line"><a name="l00500"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga43e8cbe619c9980e0d1aacc85d9b9e47"> 500</a></span> <span class="preprocessor">#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) </span></div>
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<div class="line"><a name="l00502"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga685b4564a8760b4506f14ec4307b7251"> 502</a></span> <span class="preprocessor">#define SCB_SHCSR_MEMFAULTENA_Pos 16 </span></div>
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<div class="line"><a name="l00503"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaf084424fa1f69bea36a1c44899d83d17"> 503</a></span> <span class="preprocessor">#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) </span></div>
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<div class="line"><a name="l00505"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga2f93ec9b243f94cdd3e94b8f0bf43641"> 505</a></span> <span class="preprocessor">#define SCB_SHCSR_SVCALLPENDED_Pos 15 </span></div>
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<div class="line"><a name="l00506"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga6095a7acfbad66f52822b1392be88652"> 506</a></span> <span class="preprocessor">#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) </span></div>
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<div class="line"><a name="l00508"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaa22551e24a72b65f1e817f7ab462203b"> 508</a></span> <span class="preprocessor">#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 </span></div>
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<div class="line"><a name="l00509"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga677c23749c4d348f30fb471d1223e783"> 509</a></span> <span class="preprocessor">#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) </span></div>
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<div class="line"><a name="l00511"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaceb60fe2d8a8cb17fcd1c1f6b5aa924f"> 511</a></span> <span class="preprocessor">#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 </span></div>
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<div class="line"><a name="l00512"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga9abc6c2e395f9e5af4ce05fc420fb04c"> 512</a></span> <span class="preprocessor">#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) </span></div>
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<div class="line"><a name="l00514"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga3cf03acf1fdc2edc3b047ddd47ebbf87"> 514</a></span> <span class="preprocessor">#define SCB_SHCSR_USGFAULTPENDED_Pos 12 </span></div>
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<div class="line"><a name="l00515"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga122b4f732732010895e438803a29d3cc"> 515</a></span> <span class="preprocessor">#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) </span></div>
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<div class="line"><a name="l00517"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaec9ca3b1213c49e2442373445e1697de"> 517</a></span> <span class="preprocessor">#define SCB_SHCSR_SYSTICKACT_Pos 11 </span></div>
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<div class="line"><a name="l00518"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gafef530088dc6d6bfc9f1893d52853684"> 518</a></span> <span class="preprocessor">#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) </span></div>
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<div class="line"><a name="l00520"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga9b9fa69ce4c5ce7fe0861dbccfb15939"> 520</a></span> <span class="preprocessor">#define SCB_SHCSR_PENDSVACT_Pos 10 </span></div>
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<div class="line"><a name="l00521"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gae0e837241a515d4cbadaaae1faa8e039"> 521</a></span> <span class="preprocessor">#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) </span></div>
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<div class="line"><a name="l00523"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga8b71cf4c61803752a41c96deb00d26af"> 523</a></span> <span class="preprocessor">#define SCB_SHCSR_MONITORACT_Pos 8 </span></div>
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<div class="line"><a name="l00524"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaad09b4bc36e9bccccc2e110d20b16e1a"> 524</a></span> <span class="preprocessor">#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) </span></div>
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<div class="line"><a name="l00526"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga977f5176be2bc8b123873861b38bc02f"> 526</a></span> <span class="preprocessor">#define SCB_SHCSR_SVCALLACT_Pos 7 </span></div>
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<div class="line"><a name="l00527"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga634c0f69a233475289023ae5cb158fdf"> 527</a></span> <span class="preprocessor">#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) </span></div>
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<div class="line"><a name="l00529"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gae06f54f5081f01ed3f6824e451ad3656"> 529</a></span> <span class="preprocessor">#define SCB_SHCSR_USGFAULTACT_Pos 3 </span></div>
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<div class="line"><a name="l00530"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gab3166103b5a5f7931d0df90949c47dfe"> 530</a></span> <span class="preprocessor">#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) </span></div>
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<div class="line"><a name="l00532"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaf272760f2df9ecdd8a5fbbd65c0b767a"> 532</a></span> <span class="preprocessor">#define SCB_SHCSR_BUSFAULTACT_Pos 1 </span></div>
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<div class="line"><a name="l00533"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga9d7a8b1054b655ad08d85c3c535d4f73"> 533</a></span> <span class="preprocessor">#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) </span></div>
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<div class="line"><a name="l00535"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga7c856f79a75dcc1d1517b19a67691803"> 535</a></span> <span class="preprocessor">#define SCB_SHCSR_MEMFAULTACT_Pos 0 </span></div>
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<div class="line"><a name="l00536"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga9147fd4e1b12394ae26eadf900a023a3"> 536</a></span> <span class="preprocessor">#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) </span></div>
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<div class="line"><a name="l00538"></a><span class="lineno"> 538</span> <span class="preprocessor"></span><span class="comment">/* SCB Configurable Fault Status Registers Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00539"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gac8e4197b295c8560e68e2d71285c7879"> 539</a></span> <span class="preprocessor">#define SCB_CFSR_USGFAULTSR_Pos 16 </span></div>
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<div class="line"><a name="l00540"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga565807b1a3f31891f1f967d0fa30d03f"> 540</a></span> <span class="preprocessor">#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) </span></div>
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<div class="line"><a name="l00542"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga555a24f4f57d199f91d1d1ab7c8c3c8a"> 542</a></span> <span class="preprocessor">#define SCB_CFSR_BUSFAULTSR_Pos 8 </span></div>
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<div class="line"><a name="l00543"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga26dc1ddfdc37a6b92597a6f7e498c1d6"> 543</a></span> <span class="preprocessor">#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) </span></div>
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<div class="line"><a name="l00545"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga91f41491cec5b5acca3fbc94efbd799e"> 545</a></span> <span class="preprocessor">#define SCB_CFSR_MEMFAULTSR_Pos 0 </span></div>
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<div class="line"><a name="l00546"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gad46716159a3808c9e7da22067d6bec98"> 546</a></span> <span class="preprocessor">#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) </span></div>
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<div class="line"><a name="l00548"></a><span class="lineno"> 548</span> <span class="preprocessor"></span><span class="comment">/* SCB Hard Fault Status Registers Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00549"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga300c90cfb7b35c82b4d44ad16c757ffb"> 549</a></span> <span class="preprocessor">#define SCB_HFSR_DEBUGEVT_Pos 31 </span></div>
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<div class="line"><a name="l00550"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gababd60e94756bb33929d5e6f25d8dba3"> 550</a></span> <span class="preprocessor">#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) </span></div>
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<div class="line"><a name="l00552"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gab361e54183a378474cb419ae2a55d6f4"> 552</a></span> <span class="preprocessor">#define SCB_HFSR_FORCED_Pos 30 </span></div>
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<div class="line"><a name="l00553"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga6560d97ed043bc01152a7247bafa3157"> 553</a></span> <span class="preprocessor">#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) </span></div>
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<div class="line"><a name="l00555"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga77993da8de35adea7bda6a4475f036ab"> 555</a></span> <span class="preprocessor">#define SCB_HFSR_VECTTBL_Pos 1 </span></div>
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<div class="line"><a name="l00556"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaac5e289211d0a63fe879a9691cb9e1a9"> 556</a></span> <span class="preprocessor">#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) </span></div>
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<div class="line"><a name="l00558"></a><span class="lineno"> 558</span> <span class="preprocessor"></span><span class="comment">/* SCB Debug Fault Status Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00559"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga13f502fb5ac673df9c287488c40b0c1d"> 559</a></span> <span class="preprocessor">#define SCB_DFSR_EXTERNAL_Pos 4 </span></div>
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<div class="line"><a name="l00560"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga3cba2ec1f588ce0b10b191d6b0d23399"> 560</a></span> <span class="preprocessor">#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) </span></div>
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<div class="line"><a name="l00562"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gad02d3eaf062ac184c18a7889c9b6de57"> 562</a></span> <span class="preprocessor">#define SCB_DFSR_VCATCH_Pos 3 </span></div>
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<div class="line"><a name="l00563"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gacbb931575c07b324ec793775b7c44d05"> 563</a></span> <span class="preprocessor">#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) </span></div>
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<div class="line"><a name="l00565"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaccf82364c6d0ed7206f1084277b7cc61"> 565</a></span> <span class="preprocessor">#define SCB_DFSR_DWTTRAP_Pos 2 </span></div>
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<div class="line"><a name="l00566"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga3f7384b8a761704655fd45396a305663"> 566</a></span> <span class="preprocessor">#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) </span></div>
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<div class="line"><a name="l00568"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaf28fdce48655f0dcefb383aebf26b050"> 568</a></span> <span class="preprocessor">#define SCB_DFSR_BKPT_Pos 1 </span></div>
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<div class="line"><a name="l00569"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga609edf8f50bc49adb51ae28bcecefe1f"> 569</a></span> <span class="preprocessor">#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) </span></div>
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<div class="line"><a name="l00571"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaef4ec28427f9f88ac70a13ae4e541378"> 571</a></span> <span class="preprocessor">#define SCB_DFSR_HALTED_Pos 0 </span></div>
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<div class="line"><a name="l00572"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga200bcf918d57443b5e29e8ce552e4bdf"> 572</a></span> <span class="preprocessor">#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) </span></div>
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<div class="line"><a name="l00574"></a><span class="lineno"> 574</span> <span class="preprocessor"></span></div>
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<div class="line"><a name="l00585"></a><span class="lineno"><a class="line" href="struct_s_cn_s_c_b___type.html"> 585</a></span> <span class="preprocessor">typedef struct</span></div>
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<div class="line"><a name="l00586"></a><span class="lineno"> 586</span> {</div>
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<div class="line"><a name="l00587"></a><span class="lineno"> 587</span>  uint32_t RESERVED0[1];</div>
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<div class="line"><a name="l00588"></a><span class="lineno"><a class="line" href="struct_s_cn_s_c_b___type.html#ad99a25f5d4c163d9005ca607c24f6a98"> 588</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_s_cn_s_c_b___type.html#ad99a25f5d4c163d9005ca607c24f6a98">ICTR</a>; </div>
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<div class="line"><a name="l00589"></a><span class="lineno"><a class="line" href="struct_s_cn_s_c_b___type.html#aacadedade30422fed705e8dfc8e6cd8d"> 589</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_s_cn_s_c_b___type.html#aacadedade30422fed705e8dfc8e6cd8d">ACTLR</a>; </div>
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<div class="line"><a name="l00590"></a><span class="lineno"> 590</span> } <a class="code" href="struct_s_cn_s_c_b___type.html">SCnSCB_Type</a>;</div>
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<div class="line"><a name="l00591"></a><span class="lineno"> 591</span> </div>
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<div class="line"><a name="l00592"></a><span class="lineno"> 592</span> <span class="comment">/* Interrupt Controller Type Register Definitions */</span></div>
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<div class="line"><a name="l00593"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_cn_s_c_b.html#ga0777ddf379af50f9ca41d40573bfffc5"> 593</a></span> <span class="preprocessor">#define SCnSCB_ICTR_INTLINESNUM_Pos 0 </span></div>
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<div class="line"><a name="l00594"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_cn_s_c_b.html#ga3efa0f5210051464e1034b19fc7b33c7"> 594</a></span> <span class="preprocessor">#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) </span></div>
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<div class="line"><a name="l00596"></a><span class="lineno"> 596</span> <span class="preprocessor"></span><span class="comment">/* Auxiliary Control Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00597"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_cn_s_c_b.html#gaff0b57464c60fea8182b903676f8de49"> 597</a></span> <span class="preprocessor">#define SCnSCB_ACTLR_DISOOFP_Pos 9 </span></div>
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<div class="line"><a name="l00598"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_cn_s_c_b.html#ga1ecd6adafa43464d7097b132c19e8640"> 598</a></span> <span class="preprocessor">#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) </span></div>
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<div class="line"><a name="l00600"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_cn_s_c_b.html#gaa194809383bc72ecf3416d85709281d7"> 600</a></span> <span class="preprocessor">#define SCnSCB_ACTLR_DISFPCA_Pos 8 </span></div>
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<div class="line"><a name="l00601"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_cn_s_c_b.html#ga10d5aa4a196dcde6f476016ece2c1b69"> 601</a></span> <span class="preprocessor">#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) </span></div>
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<div class="line"><a name="l00603"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_cn_s_c_b.html#gaab395870643a0bee78906bb15ca5bd02"> 603</a></span> <span class="preprocessor">#define SCnSCB_ACTLR_DISFOLD_Pos 2 </span></div>
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<div class="line"><a name="l00604"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_cn_s_c_b.html#gaa9dd2d4a2350499188f438d0aa9fd982"> 604</a></span> <span class="preprocessor">#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) </span></div>
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<div class="line"><a name="l00606"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_cn_s_c_b.html#gafa2eb37493c0f8dae77cde81ecf80f77"> 606</a></span> <span class="preprocessor">#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 </span></div>
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<div class="line"><a name="l00607"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_cn_s_c_b.html#ga6cda7b7219232a008ec52cc8e89d5d08"> 607</a></span> <span class="preprocessor">#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) </span></div>
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<div class="line"><a name="l00609"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_cn_s_c_b.html#gaaa3e79f5ead4a32c0ea742b2a9ffc0cd"> 609</a></span> <span class="preprocessor">#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 </span></div>
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<div class="line"><a name="l00610"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_cn_s_c_b.html#ga2a2818f0489ad10b6ea2964e899d4cbc"> 610</a></span> <span class="preprocessor">#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) </span></div>
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<div class="line"><a name="l00612"></a><span class="lineno"> 612</span> <span class="preprocessor"></span></div>
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<div class="line"><a name="l00623"></a><span class="lineno"><a class="line" href="struct_sys_tick___type.html"> 623</a></span> <span class="preprocessor">typedef struct</span></div>
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<div class="line"><a name="l00624"></a><span class="lineno"> 624</span> {</div>
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<div class="line"><a name="l00625"></a><span class="lineno"><a class="line" href="struct_sys_tick___type.html#af2ad94ac83e5d40fc6e34884bc1bec5f"> 625</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_sys_tick___type.html#af2ad94ac83e5d40fc6e34884bc1bec5f">CTRL</a>; </div>
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<div class="line"><a name="l00626"></a><span class="lineno"><a class="line" href="struct_sys_tick___type.html#ae7bc9d3eac1147f3bba8d73a8395644f"> 626</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_sys_tick___type.html#ae7bc9d3eac1147f3bba8d73a8395644f">LOAD</a>; </div>
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<div class="line"><a name="l00627"></a><span class="lineno"><a class="line" href="struct_sys_tick___type.html#a0997ff20f11817f8246e8f0edac6f4e4"> 627</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_sys_tick___type.html#a0997ff20f11817f8246e8f0edac6f4e4">VAL</a>; </div>
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<div class="line"><a name="l00628"></a><span class="lineno"><a class="line" href="struct_sys_tick___type.html#a9c9eda0ea6f6a7c904d2d75a6963e238"> 628</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_sys_tick___type.html#a9c9eda0ea6f6a7c904d2d75a6963e238">CALIB</a>; </div>
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<div class="line"><a name="l00629"></a><span class="lineno"> 629</span> } <a class="code" href="struct_sys_tick___type.html">SysTick_Type</a>;</div>
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<div class="line"><a name="l00630"></a><span class="lineno"> 630</span> </div>
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<div class="line"><a name="l00631"></a><span class="lineno"> 631</span> <span class="comment">/* SysTick Control / Status Register Definitions */</span></div>
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<div class="line"><a name="l00632"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#gadbb65d4a815759649db41df216ed4d60"> 632</a></span> <span class="preprocessor">#define SysTick_CTRL_COUNTFLAG_Pos 16 </span></div>
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<div class="line"><a name="l00633"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#ga1bf3033ecccf200f59baefe15dbb367c"> 633</a></span> <span class="preprocessor">#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) </span></div>
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<div class="line"><a name="l00635"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#ga24fbc69a5f0b78d67fda2300257baff1"> 635</a></span> <span class="preprocessor">#define SysTick_CTRL_CLKSOURCE_Pos 2 </span></div>
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<div class="line"><a name="l00636"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#gaa41d06039797423a46596bd313d57373"> 636</a></span> <span class="preprocessor">#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) </span></div>
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<div class="line"><a name="l00638"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#ga88f45bbb89ce8df3cd2b2613c7b48214"> 638</a></span> <span class="preprocessor">#define SysTick_CTRL_TICKINT_Pos 1 </span></div>
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<div class="line"><a name="l00639"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#ga95bb984266ca764024836a870238a027"> 639</a></span> <span class="preprocessor">#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) </span></div>
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<div class="line"><a name="l00641"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#ga0b48cc1e36d92a92e4bf632890314810"> 641</a></span> <span class="preprocessor">#define SysTick_CTRL_ENABLE_Pos 0 </span></div>
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<div class="line"><a name="l00642"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#ga16c9fee0ed0235524bdeb38af328fd1f"> 642</a></span> <span class="preprocessor">#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) </span></div>
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<div class="line"><a name="l00644"></a><span class="lineno"> 644</span> <span class="preprocessor"></span><span class="comment">/* SysTick Reload Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00645"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#gaf44d10df359dc5bf5752b0894ae3bad2"> 645</a></span> <span class="preprocessor">#define SysTick_LOAD_RELOAD_Pos 0 </span></div>
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<div class="line"><a name="l00646"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#ga265912a7962f0e1abd170336e579b1b1"> 646</a></span> <span class="preprocessor">#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) </span></div>
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<div class="line"><a name="l00648"></a><span class="lineno"> 648</span> <span class="preprocessor"></span><span class="comment">/* SysTick Current Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00649"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#ga3208104c3b019b5de35ae8c21d5c34dd"> 649</a></span> <span class="preprocessor">#define SysTick_VAL_CURRENT_Pos 0 </span></div>
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<div class="line"><a name="l00650"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#gafc77b56d568930b49a2474debc75ab45"> 650</a></span> <span class="preprocessor">#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) </span></div>
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<div class="line"><a name="l00652"></a><span class="lineno"> 652</span> <span class="preprocessor"></span><span class="comment">/* SysTick Calibration Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00653"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#ga534dbe414e7a46a6ce4c1eca1fbff409"> 653</a></span> <span class="preprocessor">#define SysTick_CALIB_NOREF_Pos 31 </span></div>
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<div class="line"><a name="l00654"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#ga3af0d891fdd99bcc8d8912d37830edb6"> 654</a></span> <span class="preprocessor">#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) </span></div>
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<div class="line"><a name="l00656"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#gadd0c9cd6641b9f6a0c618e7982954860"> 656</a></span> <span class="preprocessor">#define SysTick_CALIB_SKEW_Pos 30 </span></div>
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<div class="line"><a name="l00657"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#ga8a6a85a87334776f33d77fd147587431"> 657</a></span> <span class="preprocessor">#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) </span></div>
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<div class="line"><a name="l00659"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#gacae558f6e75a0bed5d826f606d8e695e"> 659</a></span> <span class="preprocessor">#define SysTick_CALIB_TENMS_Pos 0 </span></div>
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<div class="line"><a name="l00660"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#gaf1e68865c5aece2ad58971225bd3e95e"> 660</a></span> <span class="preprocessor">#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) </span></div>
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<div class="line"><a name="l00662"></a><span class="lineno"> 662</span> <span class="preprocessor"></span></div>
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<div class="line"><a name="l00673"></a><span class="lineno"><a class="line" href="struct_i_t_m___type.html"> 673</a></span> <span class="preprocessor">typedef struct</span></div>
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<div class="line"><a name="l00674"></a><span class="lineno"> 674</span> {</div>
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<div class="line"><a name="l00675"></a><span class="lineno"> 675</span>  <a class="code" href="core__cm4_8h.html#a7e25d9380f9ef903923964322e71f2f6">__O</a> <span class="keyword">union</span></div>
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<div class="line"><a name="l00676"></a><span class="lineno"> 676</span>  {</div>
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<div class="line"><a name="l00677"></a><span class="lineno"><a class="line" href="struct_i_t_m___type.html#abea77b06775d325e5f6f46203f582433"> 677</a></span>  <a class="code" href="core__cm4_8h.html#a7e25d9380f9ef903923964322e71f2f6">__O</a> uint8_t <a class="code" href="struct_i_t_m___type.html#abea77b06775d325e5f6f46203f582433">u8</a>; </div>
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<div class="line"><a name="l00678"></a><span class="lineno"><a class="line" href="struct_i_t_m___type.html#a12aa4eb4d9dcb589a5d953c836f4e8f4"> 678</a></span>  <a class="code" href="core__cm4_8h.html#a7e25d9380f9ef903923964322e71f2f6">__O</a> uint16_t <a class="code" href="struct_i_t_m___type.html#a12aa4eb4d9dcb589a5d953c836f4e8f4">u16</a>; </div>
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<div class="line"><a name="l00679"></a><span class="lineno"><a class="line" href="struct_i_t_m___type.html#a6882fa5af67ef5c5dfb433b3b68939df"> 679</a></span>  <a class="code" href="core__cm4_8h.html#a7e25d9380f9ef903923964322e71f2f6">__O</a> uint32_t <a class="code" href="struct_i_t_m___type.html#a6882fa5af67ef5c5dfb433b3b68939df">u32</a>; </div>
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<div class="line"><a name="l00680"></a><span class="lineno"> 680</span>  } PORT [32]; </div>
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<div class="line"><a name="l00681"></a><span class="lineno"> 681</span>  uint32_t RESERVED0[864];</div>
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<div class="line"><a name="l00682"></a><span class="lineno"><a class="line" href="struct_i_t_m___type.html#a91a040e1b162e1128ac1e852b4a0e589"> 682</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_i_t_m___type.html#a91a040e1b162e1128ac1e852b4a0e589">TER</a>; </div>
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<div class="line"><a name="l00683"></a><span class="lineno"> 683</span>  uint32_t RESERVED1[15];</div>
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<div class="line"><a name="l00684"></a><span class="lineno"><a class="line" href="struct_i_t_m___type.html#a93b480aac6da620bbb611212186d47fa"> 684</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_i_t_m___type.html#a93b480aac6da620bbb611212186d47fa">TPR</a>; </div>
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<div class="line"><a name="l00685"></a><span class="lineno"> 685</span>  uint32_t RESERVED2[15];</div>
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<div class="line"><a name="l00686"></a><span class="lineno"><a class="line" href="struct_i_t_m___type.html#a58f169e1aa40a9b8afb6296677c3bb45"> 686</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_i_t_m___type.html#a58f169e1aa40a9b8afb6296677c3bb45">TCR</a>; </div>
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<div class="line"><a name="l00687"></a><span class="lineno"> 687</span>  uint32_t RESERVED3[29];</div>
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<div class="line"><a name="l00688"></a><span class="lineno"><a class="line" href="struct_i_t_m___type.html#afd0e0c051acd3f6187794a4e8dc7e7ea"> 688</a></span>  <a class="code" href="core__cm4_8h.html#a7e25d9380f9ef903923964322e71f2f6">__O</a> uint32_t <a class="code" href="struct_i_t_m___type.html#afd0e0c051acd3f6187794a4e8dc7e7ea">IWR</a>; </div>
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<div class="line"><a name="l00689"></a><span class="lineno"><a class="line" href="struct_i_t_m___type.html#a212a614a8d5f2595e5eb049e5143c739"> 689</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_i_t_m___type.html#a212a614a8d5f2595e5eb049e5143c739">IRR</a>; </div>
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<div class="line"><a name="l00690"></a><span class="lineno"><a class="line" href="struct_i_t_m___type.html#ab2e87d8bb0e3ce9b8e0e4a6a6695228a"> 690</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_i_t_m___type.html#ab2e87d8bb0e3ce9b8e0e4a6a6695228a">IMCR</a>; </div>
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<div class="line"><a name="l00691"></a><span class="lineno"> 691</span>  uint32_t RESERVED4[43];</div>
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<div class="line"><a name="l00692"></a><span class="lineno"><a class="line" href="struct_i_t_m___type.html#a97840d39a9c63331e3689b5fa69175e9"> 692</a></span>  <a class="code" href="core__cm4_8h.html#a7e25d9380f9ef903923964322e71f2f6">__O</a> uint32_t <a class="code" href="struct_i_t_m___type.html#a97840d39a9c63331e3689b5fa69175e9">LAR</a>; </div>
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<div class="line"><a name="l00693"></a><span class="lineno"><a class="line" href="struct_i_t_m___type.html#aaa0515b1f6dd5e7d90b61ef67d8de77b"> 693</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_i_t_m___type.html#aaa0515b1f6dd5e7d90b61ef67d8de77b">LSR</a>; </div>
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<div class="line"><a name="l00694"></a><span class="lineno"> 694</span>  uint32_t RESERVED5[6];</div>
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<div class="line"><a name="l00695"></a><span class="lineno"><a class="line" href="struct_i_t_m___type.html#accfc7de00b0eaba0301e8f4553f70512"> 695</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_i_t_m___type.html#accfc7de00b0eaba0301e8f4553f70512">PID4</a>; </div>
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<div class="line"><a name="l00696"></a><span class="lineno"><a class="line" href="struct_i_t_m___type.html#a9353055ceb7024e07d59248e54502cb9"> 696</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_i_t_m___type.html#a9353055ceb7024e07d59248e54502cb9">PID5</a>; </div>
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<div class="line"><a name="l00697"></a><span class="lineno"><a class="line" href="struct_i_t_m___type.html#a755c0ec919e7dbb5f7ff05c8b56a3383"> 697</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_i_t_m___type.html#a755c0ec919e7dbb5f7ff05c8b56a3383">PID6</a>; </div>
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<div class="line"><a name="l00698"></a><span class="lineno"><a class="line" href="struct_i_t_m___type.html#aa31ca6bb4b749201321b23d0dbbe0704"> 698</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_i_t_m___type.html#aa31ca6bb4b749201321b23d0dbbe0704">PID7</a>; </div>
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<div class="line"><a name="l00699"></a><span class="lineno"><a class="line" href="struct_i_t_m___type.html#ab69ade751350a7758affdfe396517535"> 699</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_i_t_m___type.html#ab69ade751350a7758affdfe396517535">PID0</a>; </div>
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<div class="line"><a name="l00700"></a><span class="lineno"><a class="line" href="struct_i_t_m___type.html#a30e87ec6f93ecc9fe4f135ca8b068990"> 700</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_i_t_m___type.html#a30e87ec6f93ecc9fe4f135ca8b068990">PID1</a>; </div>
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<div class="line"><a name="l00701"></a><span class="lineno"><a class="line" href="struct_i_t_m___type.html#ae139d2e588bb382573ffcce3625a88cd"> 701</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_i_t_m___type.html#ae139d2e588bb382573ffcce3625a88cd">PID2</a>; </div>
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<div class="line"><a name="l00702"></a><span class="lineno"><a class="line" href="struct_i_t_m___type.html#af006ee26c7e61c9a3712a80ac74a6cf3"> 702</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_i_t_m___type.html#af006ee26c7e61c9a3712a80ac74a6cf3">PID3</a>; </div>
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<div class="line"><a name="l00703"></a><span class="lineno"><a class="line" href="struct_i_t_m___type.html#a413f3bb0a15222e5f38fca4baeef14f6"> 703</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_i_t_m___type.html#a413f3bb0a15222e5f38fca4baeef14f6">CID0</a>; </div>
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<div class="line"><a name="l00704"></a><span class="lineno"><a class="line" href="struct_i_t_m___type.html#a5f7d524b71f49e444ff0d1d52b3c3565"> 704</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_i_t_m___type.html#a5f7d524b71f49e444ff0d1d52b3c3565">CID1</a>; </div>
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<div class="line"><a name="l00705"></a><span class="lineno"><a class="line" href="struct_i_t_m___type.html#adee4ccce1429db8b5db3809c4539f876"> 705</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_i_t_m___type.html#adee4ccce1429db8b5db3809c4539f876">CID2</a>; </div>
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<div class="line"><a name="l00706"></a><span class="lineno"><a class="line" href="struct_i_t_m___type.html#a0e7aa199619cc7ac6baddff9600aa52e"> 706</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_i_t_m___type.html#a0e7aa199619cc7ac6baddff9600aa52e">CID3</a>; </div>
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<div class="line"><a name="l00707"></a><span class="lineno"> 707</span> } <a class="code" href="struct_i_t_m___type.html">ITM_Type</a>;</div>
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<div class="line"><a name="l00708"></a><span class="lineno"> 708</span> </div>
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<div class="line"><a name="l00709"></a><span class="lineno"> 709</span> <span class="comment">/* ITM Trace Privilege Register Definitions */</span></div>
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<div class="line"><a name="l00710"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#ga7abe5e590d1611599df87a1884a352e8"> 710</a></span> <span class="preprocessor">#define ITM_TPR_PRIVMASK_Pos 0 </span></div>
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<div class="line"><a name="l00711"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#ga168e089d882df325a387aab3a802a46b"> 711</a></span> <span class="preprocessor">#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) </span></div>
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<div class="line"><a name="l00713"></a><span class="lineno"> 713</span> <span class="preprocessor"></span><span class="comment">/* ITM Trace Control Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00714"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#ga9174ad4a36052c377cef4e6aba2ed484"> 714</a></span> <span class="preprocessor">#define ITM_TCR_BUSY_Pos 23 </span></div>
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<div class="line"><a name="l00715"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#ga43ad7cf33de12f2ef3a412d4f354c60f"> 715</a></span> <span class="preprocessor">#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) </span></div>
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<div class="line"><a name="l00717"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#gaca0281de867f33114aac0636f7ce65d3"> 717</a></span> <span class="preprocessor">#define ITM_TCR_TraceBusID_Pos 16 </span></div>
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<div class="line"><a name="l00718"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#ga60c20bd9649d1da5a2be8e656ba19a60"> 718</a></span> <span class="preprocessor">#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) </span></div>
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<div class="line"><a name="l00720"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#ga96c7c7cbc0d98426c408090b41f583f1"> 720</a></span> <span class="preprocessor">#define ITM_TCR_GTSFREQ_Pos 10 </span></div>
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<div class="line"><a name="l00721"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#gade862cf009827f7f6748fc44c541b067"> 721</a></span> <span class="preprocessor">#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) </span></div>
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<div class="line"><a name="l00723"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#gad7bc9ee1732032c6e0de035f0978e473"> 723</a></span> <span class="preprocessor">#define ITM_TCR_TSPrescale_Pos 8 </span></div>
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<div class="line"><a name="l00724"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#ga7a723f71bfb0204c264d8dbe8cc7ae52"> 724</a></span> <span class="preprocessor">#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) </span></div>
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<div class="line"><a name="l00726"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#ga7a380f0c8078f6560051406583ecd6a5"> 726</a></span> <span class="preprocessor">#define ITM_TCR_SWOENA_Pos 4 </span></div>
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<div class="line"><a name="l00727"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#ga97476cb65bab16a328b35f81fd02010a"> 727</a></span> <span class="preprocessor">#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) </span></div>
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<div class="line"><a name="l00729"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#ga30e83ebb33aa766070fe3d1f27ae820e"> 729</a></span> <span class="preprocessor">#define ITM_TCR_DWTENA_Pos 3 </span></div>
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<div class="line"><a name="l00730"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#ga98ea1c596d43d3633a202f9ee746cf70"> 730</a></span> <span class="preprocessor">#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) </span></div>
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<div class="line"><a name="l00732"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#gaa93a1147a39fc63980d299231252a30e"> 732</a></span> <span class="preprocessor">#define ITM_TCR_SYNCENA_Pos 2 </span></div>
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<div class="line"><a name="l00733"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#gac89b74a78701c25b442105d7fe2bbefb"> 733</a></span> <span class="preprocessor">#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) </span></div>
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<div class="line"><a name="l00735"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#ga5aa381845f810114ab519b90753922a1"> 735</a></span> <span class="preprocessor">#define ITM_TCR_TSENA_Pos 1 </span></div>
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<div class="line"><a name="l00736"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#ga436b2e8fa24328f48f2da31c00fc9e65"> 736</a></span> <span class="preprocessor">#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) </span></div>
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<div class="line"><a name="l00738"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#ga3286b86004bce7ffe17ee269f87f8d9d"> 738</a></span> <span class="preprocessor">#define ITM_TCR_ITMENA_Pos 0 </span></div>
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<div class="line"><a name="l00739"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#ga7dd53e3bff24ac09d94e61cb595cb2d9"> 739</a></span> <span class="preprocessor">#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) </span></div>
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<div class="line"><a name="l00741"></a><span class="lineno"> 741</span> <span class="preprocessor"></span><span class="comment">/* ITM Integration Write Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00742"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#ga04d3f842ad48f6a9127b4cecc963e1d7"> 742</a></span> <span class="preprocessor">#define ITM_IWR_ATVALIDM_Pos 0 </span></div>
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<div class="line"><a name="l00743"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#ga67b969f8f04ed15886727788f0e2ffd7"> 743</a></span> <span class="preprocessor">#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) </span></div>
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<div class="line"><a name="l00745"></a><span class="lineno"> 745</span> <span class="preprocessor"></span><span class="comment">/* ITM Integration Read Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00746"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#ga259edfd1d2e877a62e06d7a240df97f4"> 746</a></span> <span class="preprocessor">#define ITM_IRR_ATREADYM_Pos 0 </span></div>
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<div class="line"><a name="l00747"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#ga3dbc3e15f5bde2669cd8121a1fe419b9"> 747</a></span> <span class="preprocessor">#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) </span></div>
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<div class="line"><a name="l00749"></a><span class="lineno"> 749</span> <span class="preprocessor"></span><span class="comment">/* ITM Integration Mode Control Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00750"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#ga08de02bf32caf48aaa29f7c68ff5d755"> 750</a></span> <span class="preprocessor">#define ITM_IMCR_INTEGRATION_Pos 0 </span></div>
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<div class="line"><a name="l00751"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#ga8838bd3dd04c1a6be97cd946364a3fd2"> 751</a></span> <span class="preprocessor">#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) </span></div>
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<div class="line"><a name="l00753"></a><span class="lineno"> 753</span> <span class="preprocessor"></span><span class="comment">/* ITM Lock Status Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00754"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#gabfae3e570edc8759597311ed6dfb478e"> 754</a></span> <span class="preprocessor">#define ITM_LSR_ByteAcc_Pos 2 </span></div>
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<div class="line"><a name="l00755"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#ga91f492b2891bb8b7eac5b58de7b220f4"> 755</a></span> <span class="preprocessor">#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) </span></div>
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<div class="line"><a name="l00757"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#ga144a49e12b83ad9809fdd2769094fdc0"> 757</a></span> <span class="preprocessor">#define ITM_LSR_Access_Pos 1 </span></div>
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<div class="line"><a name="l00758"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#gac8ae69f11c0311da226c0c8ec40b3d37"> 758</a></span> <span class="preprocessor">#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) </span></div>
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<div class="line"><a name="l00760"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#gaf5740689cf14564d3f3fd91299b6c88d"> 760</a></span> <span class="preprocessor">#define ITM_LSR_Present_Pos 0 </span></div>
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<div class="line"><a name="l00761"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___i_t_m.html#gaa5bc2a7f5f1d69ff819531f5508bb017"> 761</a></span> <span class="preprocessor">#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) </span></div>
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<div class="line"><a name="l00763"></a><span class="lineno"> 763</span> <span class="preprocessor"> </span><span class="comment">/* end of group CMSIS_ITM */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00764"></a><span class="lineno"> 764</span> </div>
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<div class="line"><a name="l00765"></a><span class="lineno"> 765</span> </div>
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<div class="line"><a name="l00774"></a><span class="lineno"><a class="line" href="struct_d_w_t___type.html"> 774</a></span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00775"></a><span class="lineno"> 775</span> {</div>
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<div class="line"><a name="l00776"></a><span class="lineno"><a class="line" href="struct_d_w_t___type.html#a37964d64a58551b69ce4c8097210d37d"> 776</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_d_w_t___type.html#a37964d64a58551b69ce4c8097210d37d">CTRL</a>; </div>
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<div class="line"><a name="l00777"></a><span class="lineno"><a class="line" href="struct_d_w_t___type.html#a71680298e85e96e57002f87e7ab78fd4"> 777</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_d_w_t___type.html#a71680298e85e96e57002f87e7ab78fd4">CYCCNT</a>; </div>
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<div class="line"><a name="l00778"></a><span class="lineno"><a class="line" href="struct_d_w_t___type.html#a88cca2ab8eb1b5b507817656ceed89fc"> 778</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_d_w_t___type.html#a88cca2ab8eb1b5b507817656ceed89fc">CPICNT</a>; </div>
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<div class="line"><a name="l00779"></a><span class="lineno"><a class="line" href="struct_d_w_t___type.html#ac0801a2328f3431e4706fed91c828f82"> 779</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_d_w_t___type.html#ac0801a2328f3431e4706fed91c828f82">EXCCNT</a>; </div>
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<div class="line"><a name="l00780"></a><span class="lineno"><a class="line" href="struct_d_w_t___type.html#a8afd5a4bf994011748bc012fa442c74d"> 780</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_d_w_t___type.html#a8afd5a4bf994011748bc012fa442c74d">SLEEPCNT</a>; </div>
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<div class="line"><a name="l00781"></a><span class="lineno"><a class="line" href="struct_d_w_t___type.html#aeba92e6c7fd3de4ba06bfd94f47f5b35"> 781</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_d_w_t___type.html#aeba92e6c7fd3de4ba06bfd94f47f5b35">LSUCNT</a>; </div>
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<div class="line"><a name="l00782"></a><span class="lineno"><a class="line" href="struct_d_w_t___type.html#a35f2315f870a574e3e6958face6584ab"> 782</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_d_w_t___type.html#a35f2315f870a574e3e6958face6584ab">FOLDCNT</a>; </div>
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<div class="line"><a name="l00783"></a><span class="lineno"><a class="line" href="struct_d_w_t___type.html#abc5ae11d98da0ad5531a5e979a3c2ab5"> 783</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_d_w_t___type.html#abc5ae11d98da0ad5531a5e979a3c2ab5">PCSR</a>; </div>
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<div class="line"><a name="l00784"></a><span class="lineno"><a class="line" href="struct_d_w_t___type.html#a7cf71ff4b30a8362690fddd520763904"> 784</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_d_w_t___type.html#a7cf71ff4b30a8362690fddd520763904">COMP0</a>; </div>
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<div class="line"><a name="l00785"></a><span class="lineno"><a class="line" href="struct_d_w_t___type.html#a5bb1c17fc754180cc197b874d3d8673f"> 785</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_d_w_t___type.html#a5bb1c17fc754180cc197b874d3d8673f">MASK0</a>; </div>
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<div class="line"><a name="l00786"></a><span class="lineno"><a class="line" href="struct_d_w_t___type.html#a5fbd9947d110cc168941f6acadc4a729"> 786</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_d_w_t___type.html#a5fbd9947d110cc168941f6acadc4a729">FUNCTION0</a>; </div>
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<div class="line"><a name="l00787"></a><span class="lineno"> 787</span>  uint32_t RESERVED0[1];</div>
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<div class="line"><a name="l00788"></a><span class="lineno"><a class="line" href="struct_d_w_t___type.html#a4a5bb70a5ce3752bd628d5ce5658cb0c"> 788</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_d_w_t___type.html#a4a5bb70a5ce3752bd628d5ce5658cb0c">COMP1</a>; </div>
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<div class="line"><a name="l00789"></a><span class="lineno"><a class="line" href="struct_d_w_t___type.html#a0c684438a24f8c927e6e01c0e0a605ef"> 789</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_d_w_t___type.html#a0c684438a24f8c927e6e01c0e0a605ef">MASK1</a>; </div>
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<div class="line"><a name="l00790"></a><span class="lineno"><a class="line" href="struct_d_w_t___type.html#a3345a33476ee58e165447a3212e6d747"> 790</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_d_w_t___type.html#a3345a33476ee58e165447a3212e6d747">FUNCTION1</a>; </div>
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<div class="line"><a name="l00791"></a><span class="lineno"> 791</span>  uint32_t RESERVED1[1];</div>
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<div class="line"><a name="l00792"></a><span class="lineno"><a class="line" href="struct_d_w_t___type.html#a8927aedbe9fd6bdae8983088efc83332"> 792</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_d_w_t___type.html#a8927aedbe9fd6bdae8983088efc83332">COMP2</a>; </div>
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<div class="line"><a name="l00793"></a><span class="lineno"><a class="line" href="struct_d_w_t___type.html#a8ecdc8f0d917dac86b0373532a1c0e2e"> 793</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_d_w_t___type.html#a8ecdc8f0d917dac86b0373532a1c0e2e">MASK2</a>; </div>
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<div class="line"><a name="l00794"></a><span class="lineno"><a class="line" href="struct_d_w_t___type.html#acba1654190641a3617fcc558b5e3f87b"> 794</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_d_w_t___type.html#acba1654190641a3617fcc558b5e3f87b">FUNCTION2</a>; </div>
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<div class="line"><a name="l00795"></a><span class="lineno"> 795</span>  uint32_t RESERVED2[1];</div>
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<div class="line"><a name="l00796"></a><span class="lineno"><a class="line" href="struct_d_w_t___type.html#a3df15697eec279dbbb4b4e9d9ae8b62f"> 796</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_d_w_t___type.html#a3df15697eec279dbbb4b4e9d9ae8b62f">COMP3</a>; </div>
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<div class="line"><a name="l00797"></a><span class="lineno"><a class="line" href="struct_d_w_t___type.html#ae3f01137a8d28c905ddefe7333547fba"> 797</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_d_w_t___type.html#ae3f01137a8d28c905ddefe7333547fba">MASK3</a>; </div>
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<div class="line"><a name="l00798"></a><span class="lineno"><a class="line" href="struct_d_w_t___type.html#a80bd242fc05ca80f9db681ce4d82e890"> 798</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_d_w_t___type.html#a80bd242fc05ca80f9db681ce4d82e890">FUNCTION3</a>; </div>
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<div class="line"><a name="l00799"></a><span class="lineno"> 799</span> } <a class="code" href="struct_d_w_t___type.html">DWT_Type</a>;</div>
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<div class="line"><a name="l00800"></a><span class="lineno"> 800</span> </div>
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<div class="line"><a name="l00801"></a><span class="lineno"> 801</span> <span class="comment">/* DWT Control Register Definitions */</span></div>
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<div class="line"><a name="l00802"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gaac44b9b7d5391a7ffef129b7f6c84cd7"> 802</a></span> <span class="preprocessor">#define DWT_CTRL_NUMCOMP_Pos 28 </span></div>
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<div class="line"><a name="l00803"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gaa3d37d68c2ba73f2026265584c2815e7"> 803</a></span> <span class="preprocessor">#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) </span></div>
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<div class="line"><a name="l00805"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gaa82840323a2628e7f4a2b09b74fa73fd"> 805</a></span> <span class="preprocessor">#define DWT_CTRL_NOTRCPKT_Pos 27 </span></div>
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<div class="line"><a name="l00806"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga04d8bb0a065ca38e2e5f13a97e1f7073"> 806</a></span> <span class="preprocessor">#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) </span></div>
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<div class="line"><a name="l00808"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gad997b9026715d5609b5a3b144eca42d0"> 808</a></span> <span class="preprocessor">#define DWT_CTRL_NOEXTTRIG_Pos 26 </span></div>
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<div class="line"><a name="l00809"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gacc7d15edf7a27147c422099ab475953e"> 809</a></span> <span class="preprocessor">#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) </span></div>
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<div class="line"><a name="l00811"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga337f6167d960f57f12aa382ffecce522"> 811</a></span> <span class="preprocessor">#define DWT_CTRL_NOCYCCNT_Pos 25 </span></div>
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<div class="line"><a name="l00812"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gaf40c8d7a4fd978034c137e90f714c143"> 812</a></span> <span class="preprocessor">#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) </span></div>
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<div class="line"><a name="l00814"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gad52a0e5be84363ab166cc17beca0d048"> 814</a></span> <span class="preprocessor">#define DWT_CTRL_NOPRFCNT_Pos 24 </span></div>
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<div class="line"><a name="l00815"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gafd8448d7db4bc51f27f202e6e1f27823"> 815</a></span> <span class="preprocessor">#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) </span></div>
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<div class="line"><a name="l00817"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga0cb0640aaeb18a626d7823570d5c3cb6"> 817</a></span> <span class="preprocessor">#define DWT_CTRL_CYCEVTENA_Pos 22 </span></div>
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<div class="line"><a name="l00818"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga40554bd81460e39abf08810f45fac1a2"> 818</a></span> <span class="preprocessor">#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) </span></div>
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<div class="line"><a name="l00820"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga5602b0707f446ce78d88ff2a3a82bfff"> 820</a></span> <span class="preprocessor">#define DWT_CTRL_FOLDEVTENA_Pos 21 </span></div>
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<div class="line"><a name="l00821"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga717e679d775562ae09185a3776b1582f"> 821</a></span> <span class="preprocessor">#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) </span></div>
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<div class="line"><a name="l00823"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gaea5d1ee72188dc1d57b54c60a9f5233e"> 823</a></span> <span class="preprocessor">#define DWT_CTRL_LSUEVTENA_Pos 20 </span></div>
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<div class="line"><a name="l00824"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gac47427f455fbc29d4b6f8a479169f2b2"> 824</a></span> <span class="preprocessor">#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) </span></div>
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<div class="line"><a name="l00826"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga9c6d62d121164013a8e3ee372f17f3e5"> 826</a></span> <span class="preprocessor">#define DWT_CTRL_SLEEPEVTENA_Pos 19 </span></div>
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<div class="line"><a name="l00827"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga2f431b3734fb840daf5b361034856da9"> 827</a></span> <span class="preprocessor">#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) </span></div>
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<div class="line"><a name="l00829"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gaf4e73f548ae3e945ef8b1d9ff1281544"> 829</a></span> <span class="preprocessor">#define DWT_CTRL_EXCEVTENA_Pos 18 </span></div>
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<div class="line"><a name="l00830"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gab7ee0def33423b5859ca4030dff63b58"> 830</a></span> <span class="preprocessor">#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) </span></div>
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<div class="line"><a name="l00832"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga9fff0b71fb0be1499f5180c6bce1fc8f"> 832</a></span> <span class="preprocessor">#define DWT_CTRL_CPIEVTENA_Pos 17 </span></div>
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<div class="line"><a name="l00833"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga189089c30aade60b983df17ad2412f6f"> 833</a></span> <span class="preprocessor">#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) </span></div>
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<div class="line"><a name="l00835"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga05f13b547a9a1e63e003ee0bc6446d0d"> 835</a></span> <span class="preprocessor">#define DWT_CTRL_EXCTRCENA_Pos 16 </span></div>
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<div class="line"><a name="l00836"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gaf4fbb509ab3cbb768f16484c660a24c3"> 836</a></span> <span class="preprocessor">#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) </span></div>
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<div class="line"><a name="l00838"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga1e14afc7790fcb424fcf619e192554c9"> 838</a></span> <span class="preprocessor">#define DWT_CTRL_PCSAMPLENA_Pos 12 </span></div>
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<div class="line"><a name="l00839"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gafdcf1c86f43fbeaf2780ce797c9ef3d6"> 839</a></span> <span class="preprocessor">#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) </span></div>
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<div class="line"><a name="l00841"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga678ef08786edcbef964479217efb9284"> 841</a></span> <span class="preprocessor">#define DWT_CTRL_SYNCTAP_Pos 10 </span></div>
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<div class="line"><a name="l00842"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gaf1e6c3729d56ecadeb6eeff4d225968c"> 842</a></span> <span class="preprocessor">#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) </span></div>
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<div class="line"><a name="l00844"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gaf70b80936c7db60bf84fb6dadb8a3559"> 844</a></span> <span class="preprocessor">#define DWT_CTRL_CYCTAP_Pos 9 </span></div>
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<div class="line"><a name="l00845"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga6c12e2868b8989a69445646698b8c331"> 845</a></span> <span class="preprocessor">#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) </span></div>
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<div class="line"><a name="l00847"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga2868c0b28eb13be930afb819f55f6f25"> 847</a></span> <span class="preprocessor">#define DWT_CTRL_POSTINIT_Pos 5 </span></div>
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<div class="line"><a name="l00848"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gab8cbbee1e1d94d09f9a1f86379a08ee8"> 848</a></span> <span class="preprocessor">#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) </span></div>
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<div class="line"><a name="l00850"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga129bc152febfddd67a0c20c6814cba69"> 850</a></span> <span class="preprocessor">#define DWT_CTRL_POSTPRESET_Pos 1 </span></div>
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<div class="line"><a name="l00851"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga11d9e1e2a758fdd2657aa68ce61b9c9d"> 851</a></span> <span class="preprocessor">#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) </span></div>
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<div class="line"><a name="l00853"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gaa4509f5f8514a7200be61691f0e01f10"> 853</a></span> <span class="preprocessor">#define DWT_CTRL_CYCCNTENA_Pos 0 </span></div>
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<div class="line"><a name="l00854"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga4a9d209dc2a81ea6bfa0ea21331769d3"> 854</a></span> <span class="preprocessor">#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) </span></div>
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<div class="line"><a name="l00856"></a><span class="lineno"> 856</span> <span class="preprocessor"></span><span class="comment">/* DWT CPI Count Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00857"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga80e9ad8f6a9e2344af8a3cf989bebe3d"> 857</a></span> <span class="preprocessor">#define DWT_CPICNT_CPICNT_Pos 0 </span></div>
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<div class="line"><a name="l00858"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga76f39e7bca3fa86a4dbf7b8f6adb7217"> 858</a></span> <span class="preprocessor">#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) </span></div>
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<div class="line"><a name="l00860"></a><span class="lineno"> 860</span> <span class="preprocessor"></span><span class="comment">/* DWT Exception Overhead Count Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00861"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga031c693654030d4cba398b45d2925b1d"> 861</a></span> <span class="preprocessor">#define DWT_EXCCNT_EXCCNT_Pos 0 </span></div>
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<div class="line"><a name="l00862"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga057fa604a107b58a198bbbadb47e69c9"> 862</a></span> <span class="preprocessor">#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) </span></div>
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<div class="line"><a name="l00864"></a><span class="lineno"> 864</span> <span class="preprocessor"></span><span class="comment">/* DWT Sleep Count Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00865"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga0371a84a7996dc5852c56afb2676ba1c"> 865</a></span> <span class="preprocessor">#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 </span></div>
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<div class="line"><a name="l00866"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga1e340751d71413fef400a0a1d76cc828"> 866</a></span> <span class="preprocessor">#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) </span></div>
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<div class="line"><a name="l00868"></a><span class="lineno"> 868</span> <span class="preprocessor"></span><span class="comment">/* DWT LSU Count Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00869"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gab9394c7911b0b4312a096dad91d53a3d"> 869</a></span> <span class="preprocessor">#define DWT_LSUCNT_LSUCNT_Pos 0 </span></div>
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<div class="line"><a name="l00870"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga2186d7fc9317e20bad61336ee2925615"> 870</a></span> <span class="preprocessor">#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) </span></div>
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<div class="line"><a name="l00872"></a><span class="lineno"> 872</span> <span class="preprocessor"></span><span class="comment">/* DWT Folded-instruction Count Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00873"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga7f8af5ac12d178ba31a516f6ed141455"> 873</a></span> <span class="preprocessor">#define DWT_FOLDCNT_FOLDCNT_Pos 0 </span></div>
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<div class="line"><a name="l00874"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga9cb73d0342d38b14e41027d3c5c02647"> 874</a></span> <span class="preprocessor">#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) </span></div>
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<div class="line"><a name="l00876"></a><span class="lineno"> 876</span> <span class="preprocessor"></span><span class="comment">/* DWT Comparator Mask Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00877"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gaf798ae34e2b9280ea64f4d9920cd2e7d"> 877</a></span> <span class="preprocessor">#define DWT_MASK_MASK_Pos 0 </span></div>
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<div class="line"><a name="l00878"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gadd798deb0f1312feab4fb05dcddc229b"> 878</a></span> <span class="preprocessor">#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) </span></div>
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<div class="line"><a name="l00880"></a><span class="lineno"> 880</span> <span class="preprocessor"></span><span class="comment">/* DWT Comparator Function Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00881"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga22c5787493f74a6bacf6ffb103a190ba"> 881</a></span> <span class="preprocessor">#define DWT_FUNCTION_MATCHED_Pos 24 </span></div>
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<div class="line"><a name="l00882"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gac8b1a655947490280709037808eec8ac"> 882</a></span> <span class="preprocessor">#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) </span></div>
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<div class="line"><a name="l00884"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga8b75e8ab3ffd5ea2fa762d028dc30e8c"> 884</a></span> <span class="preprocessor">#define DWT_FUNCTION_DATAVADDR1_Pos 16 </span></div>
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<div class="line"><a name="l00885"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gafdbf5a8c367befe8661a4f6945c83445"> 885</a></span> <span class="preprocessor">#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) </span></div>
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<div class="line"><a name="l00887"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga9854cd8bf16f7dce0fb196a8029b018e"> 887</a></span> <span class="preprocessor">#define DWT_FUNCTION_DATAVADDR0_Pos 12 </span></div>
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<div class="line"><a name="l00888"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gafc5efbe8f9b51e04aecd00c8a4eb50fb"> 888</a></span> <span class="preprocessor">#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) </span></div>
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<div class="line"><a name="l00890"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga0517a186d4d448aa6416440f40fe7a4d"> 890</a></span> <span class="preprocessor">#define DWT_FUNCTION_DATAVSIZE_Pos 10 </span></div>
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<div class="line"><a name="l00891"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gaab42cbc1e6084c44d5de70971613ea76"> 891</a></span> <span class="preprocessor">#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) </span></div>
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<div class="line"><a name="l00893"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga89d7c48858b4d4de96cdadfac91856a1"> 893</a></span> <span class="preprocessor">#define DWT_FUNCTION_LNK1ENA_Pos 9 </span></div>
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<div class="line"><a name="l00894"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga64bd419260c3337cacf93607d1ad27ac"> 894</a></span> <span class="preprocessor">#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) </span></div>
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<div class="line"><a name="l00896"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga106f3672cd4be7c7c846e20497ebe5a6"> 896</a></span> <span class="preprocessor">#define DWT_FUNCTION_DATAVMATCH_Pos 8 </span></div>
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<div class="line"><a name="l00897"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga32af1f1c0fcd2d8d9afd1ad79cd9970e"> 897</a></span> <span class="preprocessor">#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) </span></div>
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<div class="line"><a name="l00899"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga4b65d79ca37ae8010b4a726312413efd"> 899</a></span> <span class="preprocessor">#define DWT_FUNCTION_CYCMATCH_Pos 7 </span></div>
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<div class="line"><a name="l00900"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga8e2ed09bdd33a8f7f7ce0444f5f3bb25"> 900</a></span> <span class="preprocessor">#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) </span></div>
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<div class="line"><a name="l00902"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga41d5b332216baa8d29561260a1b85659"> 902</a></span> <span class="preprocessor">#define DWT_FUNCTION_EMITRANGE_Pos 5 </span></div>
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<div class="line"><a name="l00903"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#gad46dd5aba29f2e28d4d3f50b1d291f41"> 903</a></span> <span class="preprocessor">#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) </span></div>
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<div class="line"><a name="l00905"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga5797b556edde2bbaa4d33dcdb1a891bb"> 905</a></span> <span class="preprocessor">#define DWT_FUNCTION_FUNCTION_Pos 0 </span></div>
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<div class="line"><a name="l00906"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___d_w_t.html#ga3b2cda708755ecf5f921d08b25d774d1"> 906</a></span> <span class="preprocessor">#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) </span></div>
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<div class="line"><a name="l00908"></a><span class="lineno"> 908</span> <span class="preprocessor"> </span><span class="comment">/* end of group CMSIS_DWT */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00909"></a><span class="lineno"> 909</span> </div>
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<div class="line"><a name="l00910"></a><span class="lineno"> 910</span> </div>
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<div class="line"><a name="l00919"></a><span class="lineno"><a class="line" href="struct_t_p_i___type.html"> 919</a></span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l00920"></a><span class="lineno"> 920</span> {</div>
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<div class="line"><a name="l00921"></a><span class="lineno"><a class="line" href="struct_t_p_i___type.html#a158e9d784f6ee6398f4bdcb2e4ca0912"> 921</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_t_p_i___type.html#a158e9d784f6ee6398f4bdcb2e4ca0912">SSPSR</a>; </div>
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<div class="line"><a name="l00922"></a><span class="lineno"><a class="line" href="struct_t_p_i___type.html#aa723ef3d38237aa2465779b3cc73a94a"> 922</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_t_p_i___type.html#aa723ef3d38237aa2465779b3cc73a94a">CSPSR</a>; </div>
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<div class="line"><a name="l00923"></a><span class="lineno"> 923</span>  uint32_t RESERVED0[2];</div>
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<div class="line"><a name="l00924"></a><span class="lineno"><a class="line" href="struct_t_p_i___type.html#ad75832a669eb121f6fce3c28d36b7fab"> 924</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_t_p_i___type.html#ad75832a669eb121f6fce3c28d36b7fab">ACPR</a>; </div>
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<div class="line"><a name="l00925"></a><span class="lineno"> 925</span>  uint32_t RESERVED1[55];</div>
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<div class="line"><a name="l00926"></a><span class="lineno"><a class="line" href="struct_t_p_i___type.html#a3eb655f2e45d7af358775025c1a50c8e"> 926</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_t_p_i___type.html#a3eb655f2e45d7af358775025c1a50c8e">SPPR</a>; </div>
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<div class="line"><a name="l00927"></a><span class="lineno"> 927</span>  uint32_t RESERVED2[131];</div>
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<div class="line"><a name="l00928"></a><span class="lineno"><a class="line" href="struct_t_p_i___type.html#ae67849b2c1016fe6ef9095827d16cddd"> 928</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_t_p_i___type.html#ae67849b2c1016fe6ef9095827d16cddd">FFSR</a>; </div>
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<div class="line"><a name="l00929"></a><span class="lineno"><a class="line" href="struct_t_p_i___type.html#a3eb42d69922e340037692424a69da880"> 929</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_t_p_i___type.html#a3eb42d69922e340037692424a69da880">FFCR</a>; </div>
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<div class="line"><a name="l00930"></a><span class="lineno"><a class="line" href="struct_t_p_i___type.html#a377b78fe804f327e6f8b3d0f37e7bfef"> 930</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_t_p_i___type.html#a377b78fe804f327e6f8b3d0f37e7bfef">FSCR</a>; </div>
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<div class="line"><a name="l00931"></a><span class="lineno"> 931</span>  uint32_t RESERVED3[759];</div>
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<div class="line"><a name="l00932"></a><span class="lineno"><a class="line" href="struct_t_p_i___type.html#aa4b603c71768dbda553da571eccba1fe"> 932</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_t_p_i___type.html#aa4b603c71768dbda553da571eccba1fe">TRIGGER</a>; </div>
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<div class="line"><a name="l00933"></a><span class="lineno"><a class="line" href="struct_t_p_i___type.html#ae91ff529e87d8e234343ed31bcdc4f10"> 933</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_t_p_i___type.html#ae91ff529e87d8e234343ed31bcdc4f10">FIFO0</a>; </div>
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<div class="line"><a name="l00934"></a><span class="lineno"><a class="line" href="struct_t_p_i___type.html#a176d991adb4c022bd5b982a9f8fa6a1d"> 934</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_t_p_i___type.html#a176d991adb4c022bd5b982a9f8fa6a1d">ITATBCTR2</a>; </div>
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<div class="line"><a name="l00935"></a><span class="lineno"> 935</span>  uint32_t RESERVED4[1];</div>
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<div class="line"><a name="l00936"></a><span class="lineno"><a class="line" href="struct_t_p_i___type.html#a20ca7fad4d4009c242f20a7b4a44b7d0"> 936</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_t_p_i___type.html#a20ca7fad4d4009c242f20a7b4a44b7d0">ITATBCTR0</a>; </div>
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<div class="line"><a name="l00937"></a><span class="lineno"><a class="line" href="struct_t_p_i___type.html#aebaa9b8dd27f8017dd4f92ecf32bac8e"> 937</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_t_p_i___type.html#aebaa9b8dd27f8017dd4f92ecf32bac8e">FIFO1</a>; </div>
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<div class="line"><a name="l00938"></a><span class="lineno"><a class="line" href="struct_t_p_i___type.html#ab49c2cb6b5fe082746a444e07548c198"> 938</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_t_p_i___type.html#ab49c2cb6b5fe082746a444e07548c198">ITCTRL</a>; </div>
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<div class="line"><a name="l00939"></a><span class="lineno"> 939</span>  uint32_t RESERVED5[39];</div>
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<div class="line"><a name="l00940"></a><span class="lineno"><a class="line" href="struct_t_p_i___type.html#a2e4d5a07fabd771fa942a171230a0a84"> 940</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_t_p_i___type.html#a2e4d5a07fabd771fa942a171230a0a84">CLAIMSET</a>; </div>
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<div class="line"><a name="l00941"></a><span class="lineno"><a class="line" href="struct_t_p_i___type.html#a44efa6045512c8d4da64b0623f7a43ad"> 941</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_t_p_i___type.html#a44efa6045512c8d4da64b0623f7a43ad">CLAIMCLR</a>; </div>
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<div class="line"><a name="l00942"></a><span class="lineno"> 942</span>  uint32_t RESERVED7[8];</div>
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<div class="line"><a name="l00943"></a><span class="lineno"><a class="line" href="struct_t_p_i___type.html#a4b2e0d680cf7e26728ca8966363a938d"> 943</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_t_p_i___type.html#a4b2e0d680cf7e26728ca8966363a938d">DEVID</a>; </div>
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<div class="line"><a name="l00944"></a><span class="lineno"><a class="line" href="struct_t_p_i___type.html#a16d12c5b1e12f764fa3ec4a51c5f0f35"> 944</a></span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t <a class="code" href="struct_t_p_i___type.html#a16d12c5b1e12f764fa3ec4a51c5f0f35">DEVTYPE</a>; </div>
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<div class="line"><a name="l00945"></a><span class="lineno"> 945</span> } <a class="code" href="struct_t_p_i___type.html">TPI_Type</a>;</div>
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<div class="line"><a name="l00946"></a><span class="lineno"> 946</span> </div>
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<div class="line"><a name="l00947"></a><span class="lineno"> 947</span> <span class="comment">/* TPI Asynchronous Clock Prescaler Register Definitions */</span></div>
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<div class="line"><a name="l00948"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga5a82d274eb2df8b0c92dd4ed63535928"> 948</a></span> <span class="preprocessor">#define TPI_ACPR_PRESCALER_Pos 0 </span></div>
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<div class="line"><a name="l00949"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga4fcacd27208419929921aec8457a8c13"> 949</a></span> <span class="preprocessor">#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) </span></div>
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<div class="line"><a name="l00951"></a><span class="lineno"> 951</span> <span class="preprocessor"></span><span class="comment">/* TPI Selected Pin Protocol Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00952"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga0f302797b94bb2da24052082ab630858"> 952</a></span> <span class="preprocessor">#define TPI_SPPR_TXMODE_Pos 0 </span></div>
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<div class="line"><a name="l00953"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gaca085c8a954393d70dbd7240bb02cc1f"> 953</a></span> <span class="preprocessor">#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) </span></div>
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<div class="line"><a name="l00955"></a><span class="lineno"> 955</span> <span class="preprocessor"></span><span class="comment">/* TPI Formatter and Flush Status Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00956"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga9537b8a660cc8803f57cbbee320b2fc8"> 956</a></span> <span class="preprocessor">#define TPI_FFSR_FtNonStop_Pos 3 </span></div>
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<div class="line"><a name="l00957"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gaaa313f980974a8cfc7dac68c4d805ab1"> 957</a></span> <span class="preprocessor">#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) </span></div>
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<div class="line"><a name="l00959"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gad30fde0c058da2ffb2b0a213be7a1b5c"> 959</a></span> <span class="preprocessor">#define TPI_FFSR_TCPresent_Pos 2 </span></div>
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<div class="line"><a name="l00960"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga0d6bfd263ff2fdec72d6ec9415fb1135"> 960</a></span> <span class="preprocessor">#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) </span></div>
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<div class="line"><a name="l00962"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gaedf31fd453a878021b542b644e2869d2"> 962</a></span> <span class="preprocessor">#define TPI_FFSR_FtStopped_Pos 1 </span></div>
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<div class="line"><a name="l00963"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga1ab6c3abe1cf6311ee07e7c479ce5f78"> 963</a></span> <span class="preprocessor">#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) </span></div>
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<div class="line"><a name="l00965"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga542ca74a081588273e6d5275ba5da6bf"> 965</a></span> <span class="preprocessor">#define TPI_FFSR_FlInProg_Pos 0 </span></div>
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<div class="line"><a name="l00966"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga63dfb09259893958962914fc3a9e3824"> 966</a></span> <span class="preprocessor">#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) </span></div>
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<div class="line"><a name="l00968"></a><span class="lineno"> 968</span> <span class="preprocessor"></span><span class="comment">/* TPI Formatter and Flush Control Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00969"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gaa7ea11ba6ea75b541cd82e185c725b5b"> 969</a></span> <span class="preprocessor">#define TPI_FFCR_TrigIn_Pos 8 </span></div>
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<div class="line"><a name="l00970"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga360b413bc5da61f751546a7133c3e4dd"> 970</a></span> <span class="preprocessor">#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) </span></div>
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<div class="line"><a name="l00972"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga99e58a0960b275a773b245e2b69b9a64"> 972</a></span> <span class="preprocessor">#define TPI_FFCR_EnFCont_Pos 1 </span></div>
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<div class="line"><a name="l00973"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga27d1ecf2e0ff496df03457a2a97cb2c9"> 973</a></span> <span class="preprocessor">#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) </span></div>
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<div class="line"><a name="l00975"></a><span class="lineno"> 975</span> <span class="preprocessor"></span><span class="comment">/* TPI TRIGGER Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00976"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga5517fa2ced64efbbd413720329c50b99"> 976</a></span> <span class="preprocessor">#define TPI_TRIGGER_TRIGGER_Pos 0 </span></div>
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<div class="line"><a name="l00977"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga814227af2b2665a0687bb49345e21110"> 977</a></span> <span class="preprocessor">#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) </span></div>
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<div class="line"><a name="l00979"></a><span class="lineno"> 979</span> <span class="preprocessor"></span><span class="comment">/* TPI Integration ETM Data Register Definitions (FIFO0) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00980"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gaa7e050e9eb6528241ebc6835783b6bae"> 980</a></span> <span class="preprocessor">#define TPI_FIFO0_ITM_ATVALID_Pos 29 </span></div>
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<div class="line"><a name="l00981"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga94cb2493ed35d2dab7bd4092b88a05bc"> 981</a></span> <span class="preprocessor">#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) </span></div>
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<div class="line"><a name="l00983"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gac2b6f7f13a2fa0be4aa7645a47dcac52"> 983</a></span> <span class="preprocessor">#define TPI_FIFO0_ITM_bytecount_Pos 27 </span></div>
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<div class="line"><a name="l00984"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga07bafa971b8daf0d63b3f92b9ae7fa16"> 984</a></span> <span class="preprocessor">#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) </span></div>
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<div class="line"><a name="l00986"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga7fdeb3e465ca4aa9e3b2f424ab3bbd1d"> 986</a></span> <span class="preprocessor">#define TPI_FIFO0_ETM_ATVALID_Pos 26 </span></div>
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<div class="line"><a name="l00987"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga4f0005dc420b28f2369179a935b9a9d3"> 987</a></span> <span class="preprocessor">#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) </span></div>
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<div class="line"><a name="l00989"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga2f738e45386ebf58c4d406f578e7ddaf"> 989</a></span> <span class="preprocessor">#define TPI_FIFO0_ETM_bytecount_Pos 24 </span></div>
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<div class="line"><a name="l00990"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gad2536b3a935361c68453cd068640af92"> 990</a></span> <span class="preprocessor">#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) </span></div>
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<div class="line"><a name="l00992"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga5f0037cc80c65e86d9e94e5005077a48"> 992</a></span> <span class="preprocessor">#define TPI_FIFO0_ETM2_Pos 16 </span></div>
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<div class="line"><a name="l00993"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gaa82a7b9b99c990fb12eafb3c84b68254"> 993</a></span> <span class="preprocessor">#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) </span></div>
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<div class="line"><a name="l00995"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gac5a2ef4b7f811d1f3d81ec919d794413"> 995</a></span> <span class="preprocessor">#define TPI_FIFO0_ETM1_Pos 8 </span></div>
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<div class="line"><a name="l00996"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gaad9c1a6ed34a70905005a0cc14d5f01b"> 996</a></span> <span class="preprocessor">#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) </span></div>
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<div class="line"><a name="l00998"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga48783ce3c695d8c06b1352a526110a87"> 998</a></span> <span class="preprocessor">#define TPI_FIFO0_ETM0_Pos 0 </span></div>
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<div class="line"><a name="l00999"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gaf924f7d1662f3f6c1da12052390cb118"> 999</a></span> <span class="preprocessor">#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) </span></div>
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<div class="line"><a name="l01001"></a><span class="lineno"> 1001</span> <span class="preprocessor"></span><span class="comment">/* TPI ITATBCTR2 Register Definitions */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l01002"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga6959f73d7db4a87ae9ad9cfc99844526"> 1002</a></span> <span class="preprocessor">#define TPI_ITATBCTR2_ATREADY_Pos 0 </span></div>
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<div class="line"><a name="l01003"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga1859502749709a2e5ead9a2599d998db"> 1003</a></span> <span class="preprocessor">#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) </span></div>
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<div class="line"><a name="l01005"></a><span class="lineno"> 1005</span> <span class="preprocessor"></span><span class="comment">/* TPI Integration ITM Data Register Definitions (FIFO1) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l01006"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga08edfc862b2c8c415854cc4ae2067dfb"> 1006</a></span> <span class="preprocessor">#define TPI_FIFO1_ITM_ATVALID_Pos 29 </span></div>
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<div class="line"><a name="l01007"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gabc1f6a3b6cac0099d7c01ca949b4dd08"> 1007</a></span> <span class="preprocessor">#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) </span></div>
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<div class="line"><a name="l01009"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gaa22ebf7c86e4f4b2c98cfd0b5981375a"> 1009</a></span> <span class="preprocessor">#define TPI_FIFO1_ITM_bytecount_Pos 27 </span></div>
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<div class="line"><a name="l01010"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gacba2edfc0499828019550141356b0dcb"> 1010</a></span> <span class="preprocessor">#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) </span></div>
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<div class="line"><a name="l01012"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga3177b8d815cf4a707a2d3d3d5499315d"> 1012</a></span> <span class="preprocessor">#define TPI_FIFO1_ETM_ATVALID_Pos 26 </span></div>
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|
<div class="line"><a name="l01013"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga0e8f29a1e9378d1ceb0708035edbb86d"> 1013</a></span> <span class="preprocessor">#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) </span></div>
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<div class="line"><a name="l01015"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gaab31238152b5691af633a7475eaf1f06"> 1015</a></span> <span class="preprocessor">#define TPI_FIFO1_ETM_bytecount_Pos 24 </span></div>
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|
<div class="line"><a name="l01016"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gab554305459953b80554fdb1908b73291"> 1016</a></span> <span class="preprocessor">#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) </span></div>
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|
<div class="line"><a name="l01018"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga1828c228f3940005f48fb8dd88ada35b"> 1018</a></span> <span class="preprocessor">#define TPI_FIFO1_ITM2_Pos 16 </span></div>
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|
<div class="line"><a name="l01019"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gae54512f926ebc00f2e056232aa21d335"> 1019</a></span> <span class="preprocessor">#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) </span></div>
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|
<div class="line"><a name="l01021"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gaece86ab513bc3d0e0a9dbd82258af49f"> 1021</a></span> <span class="preprocessor">#define TPI_FIFO1_ITM1_Pos 8 </span></div>
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|
<div class="line"><a name="l01022"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga3347f42828920dfe56e3130ad319a9e6"> 1022</a></span> <span class="preprocessor">#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) </span></div>
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|
<div class="line"><a name="l01024"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga2188671488417a52abb075bcd4d73440"> 1024</a></span> <span class="preprocessor">#define TPI_FIFO1_ITM0_Pos 0 </span></div>
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<div class="line"><a name="l01025"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga8ae09f544fc1a428797e2a150f14a4c9"> 1025</a></span> <span class="preprocessor">#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) </span></div>
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|
<div class="line"><a name="l01027"></a><span class="lineno"> 1027</span> <span class="preprocessor"></span><span class="comment">/* TPI ITATBCTR0 Register Definitions */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l01028"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gab1eb6866c65f02fa9c83696b49b0f346"> 1028</a></span> <span class="preprocessor">#define TPI_ITATBCTR0_ATREADY_Pos 0 </span></div>
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|
<div class="line"><a name="l01029"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gaee320b3c60f9575aa96a8742c4ff9356"> 1029</a></span> <span class="preprocessor">#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) </span></div>
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<div class="line"><a name="l01031"></a><span class="lineno"> 1031</span> <span class="preprocessor"></span><span class="comment">/* TPI Integration Mode Control Register Definitions */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l01032"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gaa847adb71a1bc811d2e3190528f495f0"> 1032</a></span> <span class="preprocessor">#define TPI_ITCTRL_Mode_Pos 0 </span></div>
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<div class="line"><a name="l01033"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gad6f87550b468ad0920d5f405bfd3f017"> 1033</a></span> <span class="preprocessor">#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) </span></div>
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<div class="line"><a name="l01035"></a><span class="lineno"> 1035</span> <span class="preprocessor"></span><span class="comment">/* TPI DEVID Register Definitions */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l01036"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga9f46cf1a1708575f56d6b827766277f4"> 1036</a></span> <span class="preprocessor">#define TPI_DEVID_NRZVALID_Pos 11 </span></div>
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|
<div class="line"><a name="l01037"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gacecc8710a8f6a23a7d1d4f5674daf02a"> 1037</a></span> <span class="preprocessor">#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) </span></div>
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|
<div class="line"><a name="l01039"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga675534579d9e25477bb38970e3ef973c"> 1039</a></span> <span class="preprocessor">#define TPI_DEVID_MANCVALID_Pos 10 </span></div>
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|
<div class="line"><a name="l01040"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga4c3ee4b1a34ad1960a6b2d6e7e0ff942"> 1040</a></span> <span class="preprocessor">#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) </span></div>
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|
<div class="line"><a name="l01042"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga974cccf4c958b4a45cb71c7b5de39b7b"> 1042</a></span> <span class="preprocessor">#define TPI_DEVID_PTINVALID_Pos 9 </span></div>
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|
<div class="line"><a name="l01043"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga1ca84d62243e475836bba02516ba6b97"> 1043</a></span> <span class="preprocessor">#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) </span></div>
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|
<div class="line"><a name="l01045"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga3f7da5de2a34be41a092e5eddd22ac4d"> 1045</a></span> <span class="preprocessor">#define TPI_DEVID_MinBufSz_Pos 6 </span></div>
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|
<div class="line"><a name="l01046"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga939e068ff3f1a65b35187ab34a342cd8"> 1046</a></span> <span class="preprocessor">#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) </span></div>
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<div class="line"><a name="l01048"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gab382b1296b5efd057be606eb8f768df8"> 1048</a></span> <span class="preprocessor">#define TPI_DEVID_AsynClkIn_Pos 5 </span></div>
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|
<div class="line"><a name="l01049"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gab67830557d2d10be882284275025a2d3"> 1049</a></span> <span class="preprocessor">#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) </span></div>
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|
<div class="line"><a name="l01051"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga80ecae7fec479e80e583f545996868ed"> 1051</a></span> <span class="preprocessor">#define TPI_DEVID_NrTraceInput_Pos 0 </span></div>
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|
<div class="line"><a name="l01052"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gabed454418d2140043cd65ec899abd97f"> 1052</a></span> <span class="preprocessor">#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) </span></div>
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|
<div class="line"><a name="l01054"></a><span class="lineno"> 1054</span> <span class="preprocessor"></span><span class="comment">/* TPI DEVTYPE Register Definitions */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l01055"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga0c799ff892af5eb3162d152abc00af7a"> 1055</a></span> <span class="preprocessor">#define TPI_DEVTYPE_SubType_Pos 0 </span></div>
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|
<div class="line"><a name="l01056"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga5b2fd7dddaf5f64855d9c0696acd65c1"> 1056</a></span> <span class="preprocessor">#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) </span></div>
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<div class="line"><a name="l01058"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#ga69c4892d332755a9f64c1680497cebdd"> 1058</a></span> <span class="preprocessor">#define TPI_DEVTYPE_MajorType_Pos 4 </span></div>
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|
<div class="line"><a name="l01059"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___t_p_i.html#gaecbceed6d08ec586403b37ad47b38c88"> 1059</a></span> <span class="preprocessor">#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) </span></div>
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|
<div class="line"><a name="l01061"></a><span class="lineno"> 1061</span> <span class="preprocessor"> </span><span class="comment">/* end of group CMSIS_TPI */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l01062"></a><span class="lineno"> 1062</span> </div>
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<div class="line"><a name="l01063"></a><span class="lineno"> 1063</span> </div>
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|
<div class="line"><a name="l01064"></a><span class="lineno"> 1064</span> <span class="preprocessor">#if (__MPU_PRESENT == 1)</span></div>
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|
<div class="line"><a name="l01065"></a><span class="lineno"> 1065</span> </div>
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|
<div class="line"><a name="l01073"></a><span class="lineno"> 1073</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l01074"></a><span class="lineno"> 1074</span> {</div>
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<div class="line"><a name="l01075"></a><span class="lineno"> 1075</span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t TYPE; </div>
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|
<div class="line"><a name="l01076"></a><span class="lineno"> 1076</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t CTRL; </div>
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<div class="line"><a name="l01077"></a><span class="lineno"> 1077</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RNR; </div>
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<div class="line"><a name="l01078"></a><span class="lineno"> 1078</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RBAR; </div>
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<div class="line"><a name="l01079"></a><span class="lineno"> 1079</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RASR; </div>
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|
<div class="line"><a name="l01080"></a><span class="lineno"> 1080</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RBAR_A1; </div>
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|
<div class="line"><a name="l01081"></a><span class="lineno"> 1081</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RASR_A1; </div>
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<div class="line"><a name="l01082"></a><span class="lineno"> 1082</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RBAR_A2; </div>
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<div class="line"><a name="l01083"></a><span class="lineno"> 1083</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RASR_A2; </div>
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<div class="line"><a name="l01084"></a><span class="lineno"> 1084</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RBAR_A3; </div>
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<div class="line"><a name="l01085"></a><span class="lineno"> 1085</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t RASR_A3; </div>
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<div class="line"><a name="l01086"></a><span class="lineno"> 1086</span> } MPU_Type;</div>
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<div class="line"><a name="l01087"></a><span class="lineno"> 1087</span> </div>
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<div class="line"><a name="l01088"></a><span class="lineno"> 1088</span> <span class="comment">/* MPU Type Register */</span></div>
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<div class="line"><a name="l01089"></a><span class="lineno"> 1089</span> <span class="preprocessor">#define MPU_TYPE_IREGION_Pos 16 </span></div>
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<div class="line"><a name="l01090"></a><span class="lineno"> 1090</span> <span class="preprocessor">#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) </span></div>
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<div class="line"><a name="l01092"></a><span class="lineno"> 1092</span> <span class="preprocessor">#define MPU_TYPE_DREGION_Pos 8 </span></div>
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<div class="line"><a name="l01093"></a><span class="lineno"> 1093</span> <span class="preprocessor">#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) </span></div>
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<div class="line"><a name="l01095"></a><span class="lineno"> 1095</span> <span class="preprocessor">#define MPU_TYPE_SEPARATE_Pos 0 </span></div>
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<div class="line"><a name="l01096"></a><span class="lineno"> 1096</span> <span class="preprocessor">#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) </span></div>
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<div class="line"><a name="l01098"></a><span class="lineno"> 1098</span> <span class="preprocessor"></span><span class="comment">/* MPU Control Register */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l01099"></a><span class="lineno"> 1099</span> <span class="preprocessor">#define MPU_CTRL_PRIVDEFENA_Pos 2 </span></div>
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<div class="line"><a name="l01100"></a><span class="lineno"> 1100</span> <span class="preprocessor">#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) </span></div>
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<div class="line"><a name="l01102"></a><span class="lineno"> 1102</span> <span class="preprocessor">#define MPU_CTRL_HFNMIENA_Pos 1 </span></div>
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<div class="line"><a name="l01103"></a><span class="lineno"> 1103</span> <span class="preprocessor">#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) </span></div>
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<div class="line"><a name="l01105"></a><span class="lineno"> 1105</span> <span class="preprocessor">#define MPU_CTRL_ENABLE_Pos 0 </span></div>
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<div class="line"><a name="l01106"></a><span class="lineno"> 1106</span> <span class="preprocessor">#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) </span></div>
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<div class="line"><a name="l01108"></a><span class="lineno"> 1108</span> <span class="preprocessor"></span><span class="comment">/* MPU Region Number Register */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l01109"></a><span class="lineno"> 1109</span> <span class="preprocessor">#define MPU_RNR_REGION_Pos 0 </span></div>
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<div class="line"><a name="l01110"></a><span class="lineno"> 1110</span> <span class="preprocessor">#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) </span></div>
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<div class="line"><a name="l01112"></a><span class="lineno"> 1112</span> <span class="preprocessor"></span><span class="comment">/* MPU Region Base Address Register */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l01113"></a><span class="lineno"> 1113</span> <span class="preprocessor">#define MPU_RBAR_ADDR_Pos 5 </span></div>
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<div class="line"><a name="l01114"></a><span class="lineno"> 1114</span> <span class="preprocessor">#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) </span></div>
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<div class="line"><a name="l01116"></a><span class="lineno"> 1116</span> <span class="preprocessor">#define MPU_RBAR_VALID_Pos 4 </span></div>
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<div class="line"><a name="l01117"></a><span class="lineno"> 1117</span> <span class="preprocessor">#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) </span></div>
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<div class="line"><a name="l01119"></a><span class="lineno"> 1119</span> <span class="preprocessor">#define MPU_RBAR_REGION_Pos 0 </span></div>
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<div class="line"><a name="l01120"></a><span class="lineno"> 1120</span> <span class="preprocessor">#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) </span></div>
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<div class="line"><a name="l01122"></a><span class="lineno"> 1122</span> <span class="preprocessor"></span><span class="comment">/* MPU Region Attribute and Size Register */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l01123"></a><span class="lineno"> 1123</span> <span class="preprocessor">#define MPU_RASR_ATTRS_Pos 16 </span></div>
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<div class="line"><a name="l01124"></a><span class="lineno"> 1124</span> <span class="preprocessor">#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) </span></div>
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<div class="line"><a name="l01126"></a><span class="lineno"> 1126</span> <span class="preprocessor">#define MPU_RASR_XN_Pos 28 </span></div>
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<div class="line"><a name="l01127"></a><span class="lineno"> 1127</span> <span class="preprocessor">#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) </span></div>
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<div class="line"><a name="l01129"></a><span class="lineno"> 1129</span> <span class="preprocessor">#define MPU_RASR_AP_Pos 24 </span></div>
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<div class="line"><a name="l01130"></a><span class="lineno"> 1130</span> <span class="preprocessor">#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) </span></div>
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<div class="line"><a name="l01132"></a><span class="lineno"> 1132</span> <span class="preprocessor">#define MPU_RASR_TEX_Pos 19 </span></div>
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<div class="line"><a name="l01133"></a><span class="lineno"> 1133</span> <span class="preprocessor">#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) </span></div>
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<div class="line"><a name="l01135"></a><span class="lineno"> 1135</span> <span class="preprocessor">#define MPU_RASR_S_Pos 18 </span></div>
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<div class="line"><a name="l01136"></a><span class="lineno"> 1136</span> <span class="preprocessor">#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) </span></div>
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<div class="line"><a name="l01138"></a><span class="lineno"> 1138</span> <span class="preprocessor">#define MPU_RASR_C_Pos 17 </span></div>
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<div class="line"><a name="l01139"></a><span class="lineno"> 1139</span> <span class="preprocessor">#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) </span></div>
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<div class="line"><a name="l01141"></a><span class="lineno"> 1141</span> <span class="preprocessor">#define MPU_RASR_B_Pos 16 </span></div>
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<div class="line"><a name="l01142"></a><span class="lineno"> 1142</span> <span class="preprocessor">#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) </span></div>
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<div class="line"><a name="l01144"></a><span class="lineno"> 1144</span> <span class="preprocessor">#define MPU_RASR_SRD_Pos 8 </span></div>
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<div class="line"><a name="l01145"></a><span class="lineno"> 1145</span> <span class="preprocessor">#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) </span></div>
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<div class="line"><a name="l01147"></a><span class="lineno"> 1147</span> <span class="preprocessor">#define MPU_RASR_SIZE_Pos 1 </span></div>
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<div class="line"><a name="l01148"></a><span class="lineno"> 1148</span> <span class="preprocessor">#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) </span></div>
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<div class="line"><a name="l01150"></a><span class="lineno"> 1150</span> <span class="preprocessor">#define MPU_RASR_ENABLE_Pos 0 </span></div>
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<div class="line"><a name="l01151"></a><span class="lineno"> 1151</span> <span class="preprocessor">#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) </span></div>
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<div class="line"><a name="l01153"></a><span class="lineno"> 1153</span> <span class="preprocessor"></span></div>
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<div class="line"><a name="l01154"></a><span class="lineno"> 1154</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l01155"></a><span class="lineno"> 1155</span> </div>
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<div class="line"><a name="l01156"></a><span class="lineno"> 1156</span> </div>
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<div class="line"><a name="l01157"></a><span class="lineno"> 1157</span> <span class="preprocessor">#if (__FPU_PRESENT == 1)</span></div>
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<div class="line"><a name="l01158"></a><span class="lineno"> 1158</span> </div>
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<div class="line"><a name="l01166"></a><span class="lineno"> 1166</span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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<div class="line"><a name="l01167"></a><span class="lineno"> 1167</span> {</div>
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<div class="line"><a name="l01168"></a><span class="lineno"> 1168</span>  uint32_t RESERVED0[1];</div>
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<div class="line"><a name="l01169"></a><span class="lineno"> 1169</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t FPCCR; </div>
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<div class="line"><a name="l01170"></a><span class="lineno"> 1170</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t FPCAR; </div>
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<div class="line"><a name="l01171"></a><span class="lineno"> 1171</span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t FPDSCR; </div>
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<div class="line"><a name="l01172"></a><span class="lineno"> 1172</span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t MVFR0; </div>
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<div class="line"><a name="l01173"></a><span class="lineno"> 1173</span>  <a class="code" href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t MVFR1; </div>
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<div class="line"><a name="l01174"></a><span class="lineno"> 1174</span> } FPU_Type;</div>
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<div class="line"><a name="l01175"></a><span class="lineno"> 1175</span> </div>
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<div class="line"><a name="l01176"></a><span class="lineno"> 1176</span> <span class="comment">/* Floating-Point Context Control Register */</span></div>
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<div class="line"><a name="l01177"></a><span class="lineno"> 1177</span> <span class="preprocessor">#define FPU_FPCCR_ASPEN_Pos 31 </span></div>
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<div class="line"><a name="l01178"></a><span class="lineno"> 1178</span> <span class="preprocessor">#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) </span></div>
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<div class="line"><a name="l01180"></a><span class="lineno"> 1180</span> <span class="preprocessor">#define FPU_FPCCR_LSPEN_Pos 30 </span></div>
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<div class="line"><a name="l01181"></a><span class="lineno"> 1181</span> <span class="preprocessor">#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) </span></div>
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<div class="line"><a name="l01183"></a><span class="lineno"> 1183</span> <span class="preprocessor">#define FPU_FPCCR_MONRDY_Pos 8 </span></div>
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<div class="line"><a name="l01184"></a><span class="lineno"> 1184</span> <span class="preprocessor">#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) </span></div>
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<div class="line"><a name="l01186"></a><span class="lineno"> 1186</span> <span class="preprocessor">#define FPU_FPCCR_BFRDY_Pos 6 </span></div>
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<div class="line"><a name="l01187"></a><span class="lineno"> 1187</span> <span class="preprocessor">#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) </span></div>
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<div class="line"><a name="l01189"></a><span class="lineno"> 1189</span> <span class="preprocessor">#define FPU_FPCCR_MMRDY_Pos 5 </span></div>
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|
<div class="line"><a name="l01190"></a><span class="lineno"> 1190</span> <span class="preprocessor">#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) </span></div>
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|
<div class="line"><a name="l01192"></a><span class="lineno"> 1192</span> <span class="preprocessor">#define FPU_FPCCR_HFRDY_Pos 4 </span></div>
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|
<div class="line"><a name="l01193"></a><span class="lineno"> 1193</span> <span class="preprocessor">#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) </span></div>
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|
<div class="line"><a name="l01195"></a><span class="lineno"> 1195</span> <span class="preprocessor">#define FPU_FPCCR_THREAD_Pos 3 </span></div>
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<div class="line"><a name="l01196"></a><span class="lineno"> 1196</span> <span class="preprocessor">#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) </span></div>
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|
<div class="line"><a name="l01198"></a><span class="lineno"> 1198</span> <span class="preprocessor">#define FPU_FPCCR_USER_Pos 1 </span></div>
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|
<div class="line"><a name="l01199"></a><span class="lineno"> 1199</span> <span class="preprocessor">#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) </span></div>
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|
<div class="line"><a name="l01201"></a><span class="lineno"> 1201</span> <span class="preprocessor">#define FPU_FPCCR_LSPACT_Pos 0 </span></div>
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|
<div class="line"><a name="l01202"></a><span class="lineno"> 1202</span> <span class="preprocessor">#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) </span></div>
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|
<div class="line"><a name="l01204"></a><span class="lineno"> 1204</span> <span class="preprocessor"></span><span class="comment">/* Floating-Point Context Address Register */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l01205"></a><span class="lineno"> 1205</span> <span class="preprocessor">#define FPU_FPCAR_ADDRESS_Pos 3 </span></div>
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|
<div class="line"><a name="l01206"></a><span class="lineno"> 1206</span> <span class="preprocessor">#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) </span></div>
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|
<div class="line"><a name="l01208"></a><span class="lineno"> 1208</span> <span class="preprocessor"></span><span class="comment">/* Floating-Point Default Status Control Register */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l01209"></a><span class="lineno"> 1209</span> <span class="preprocessor">#define FPU_FPDSCR_AHP_Pos 26 </span></div>
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|
<div class="line"><a name="l01210"></a><span class="lineno"> 1210</span> <span class="preprocessor">#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) </span></div>
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|
<div class="line"><a name="l01212"></a><span class="lineno"> 1212</span> <span class="preprocessor">#define FPU_FPDSCR_DN_Pos 25 </span></div>
|
|
<div class="line"><a name="l01213"></a><span class="lineno"> 1213</span> <span class="preprocessor">#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) </span></div>
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|
<div class="line"><a name="l01215"></a><span class="lineno"> 1215</span> <span class="preprocessor">#define FPU_FPDSCR_FZ_Pos 24 </span></div>
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|
<div class="line"><a name="l01216"></a><span class="lineno"> 1216</span> <span class="preprocessor">#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) </span></div>
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|
<div class="line"><a name="l01218"></a><span class="lineno"> 1218</span> <span class="preprocessor">#define FPU_FPDSCR_RMode_Pos 22 </span></div>
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|
<div class="line"><a name="l01219"></a><span class="lineno"> 1219</span> <span class="preprocessor">#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) </span></div>
|
|
<div class="line"><a name="l01221"></a><span class="lineno"> 1221</span> <span class="preprocessor"></span><span class="comment">/* Media and FP Feature Register 0 */</span><span class="preprocessor"></span></div>
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|
<div class="line"><a name="l01222"></a><span class="lineno"> 1222</span> <span class="preprocessor">#define FPU_MVFR0_FP_rounding_modes_Pos 28 </span></div>
|
|
<div class="line"><a name="l01223"></a><span class="lineno"> 1223</span> <span class="preprocessor">#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) </span></div>
|
|
<div class="line"><a name="l01225"></a><span class="lineno"> 1225</span> <span class="preprocessor">#define FPU_MVFR0_Short_vectors_Pos 24 </span></div>
|
|
<div class="line"><a name="l01226"></a><span class="lineno"> 1226</span> <span class="preprocessor">#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) </span></div>
|
|
<div class="line"><a name="l01228"></a><span class="lineno"> 1228</span> <span class="preprocessor">#define FPU_MVFR0_Square_root_Pos 20 </span></div>
|
|
<div class="line"><a name="l01229"></a><span class="lineno"> 1229</span> <span class="preprocessor">#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) </span></div>
|
|
<div class="line"><a name="l01231"></a><span class="lineno"> 1231</span> <span class="preprocessor">#define FPU_MVFR0_Divide_Pos 16 </span></div>
|
|
<div class="line"><a name="l01232"></a><span class="lineno"> 1232</span> <span class="preprocessor">#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) </span></div>
|
|
<div class="line"><a name="l01234"></a><span class="lineno"> 1234</span> <span class="preprocessor">#define FPU_MVFR0_FP_excep_trapping_Pos 12 </span></div>
|
|
<div class="line"><a name="l01235"></a><span class="lineno"> 1235</span> <span class="preprocessor">#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) </span></div>
|
|
<div class="line"><a name="l01237"></a><span class="lineno"> 1237</span> <span class="preprocessor">#define FPU_MVFR0_Double_precision_Pos 8 </span></div>
|
|
<div class="line"><a name="l01238"></a><span class="lineno"> 1238</span> <span class="preprocessor">#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) </span></div>
|
|
<div class="line"><a name="l01240"></a><span class="lineno"> 1240</span> <span class="preprocessor">#define FPU_MVFR0_Single_precision_Pos 4 </span></div>
|
|
<div class="line"><a name="l01241"></a><span class="lineno"> 1241</span> <span class="preprocessor">#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) </span></div>
|
|
<div class="line"><a name="l01243"></a><span class="lineno"> 1243</span> <span class="preprocessor">#define FPU_MVFR0_A_SIMD_registers_Pos 0 </span></div>
|
|
<div class="line"><a name="l01244"></a><span class="lineno"> 1244</span> <span class="preprocessor">#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) </span></div>
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|
<div class="line"><a name="l01246"></a><span class="lineno"> 1246</span> <span class="preprocessor"></span><span class="comment">/* Media and FP Feature Register 1 */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l01247"></a><span class="lineno"> 1247</span> <span class="preprocessor">#define FPU_MVFR1_FP_fused_MAC_Pos 28 </span></div>
|
|
<div class="line"><a name="l01248"></a><span class="lineno"> 1248</span> <span class="preprocessor">#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) </span></div>
|
|
<div class="line"><a name="l01250"></a><span class="lineno"> 1250</span> <span class="preprocessor">#define FPU_MVFR1_FP_HPFP_Pos 24 </span></div>
|
|
<div class="line"><a name="l01251"></a><span class="lineno"> 1251</span> <span class="preprocessor">#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) </span></div>
|
|
<div class="line"><a name="l01253"></a><span class="lineno"> 1253</span> <span class="preprocessor">#define FPU_MVFR1_D_NaN_mode_Pos 4 </span></div>
|
|
<div class="line"><a name="l01254"></a><span class="lineno"> 1254</span> <span class="preprocessor">#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) </span></div>
|
|
<div class="line"><a name="l01256"></a><span class="lineno"> 1256</span> <span class="preprocessor">#define FPU_MVFR1_FtZ_mode_Pos 0 </span></div>
|
|
<div class="line"><a name="l01257"></a><span class="lineno"> 1257</span> <span class="preprocessor">#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) </span></div>
|
|
<div class="line"><a name="l01259"></a><span class="lineno"> 1259</span> <span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l01260"></a><span class="lineno"> 1260</span> <span class="preprocessor">#endif</span></div>
|
|
<div class="line"><a name="l01261"></a><span class="lineno"> 1261</span> </div>
|
|
<div class="line"><a name="l01262"></a><span class="lineno"> 1262</span> </div>
|
|
<div class="line"><a name="l01271"></a><span class="lineno"><a class="line" href="struct_core_debug___type.html"> 1271</a></span> <span class="keyword">typedef</span> <span class="keyword">struct</span></div>
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|
<div class="line"><a name="l01272"></a><span class="lineno"> 1272</span> {</div>
|
|
<div class="line"><a name="l01273"></a><span class="lineno"><a class="line" href="struct_core_debug___type.html#a25c14c022c73a725a1736e903431095d"> 1273</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_core_debug___type.html#a25c14c022c73a725a1736e903431095d">DHCSR</a>; </div>
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|
<div class="line"><a name="l01274"></a><span class="lineno"><a class="line" href="struct_core_debug___type.html#afefa84bce7497652353a1b76d405d983"> 1274</a></span>  <a class="code" href="core__cm4_8h.html#a7e25d9380f9ef903923964322e71f2f6">__O</a> uint32_t <a class="code" href="struct_core_debug___type.html#afefa84bce7497652353a1b76d405d983">DCRSR</a>; </div>
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|
<div class="line"><a name="l01275"></a><span class="lineno"><a class="line" href="struct_core_debug___type.html#ab8f4bb076402b61f7be6308075a789c9"> 1275</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_core_debug___type.html#ab8f4bb076402b61f7be6308075a789c9">DCRDR</a>; </div>
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|
<div class="line"><a name="l01276"></a><span class="lineno"><a class="line" href="struct_core_debug___type.html#a5cdd51dbe3ebb7041880714430edd52d"> 1276</a></span>  <a class="code" href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t <a class="code" href="struct_core_debug___type.html#a5cdd51dbe3ebb7041880714430edd52d">DEMCR</a>; </div>
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|
<div class="line"><a name="l01277"></a><span class="lineno"> 1277</span> } <a class="code" href="struct_core_debug___type.html">CoreDebug_Type</a>;</div>
|
|
<div class="line"><a name="l01278"></a><span class="lineno"> 1278</span> </div>
|
|
<div class="line"><a name="l01279"></a><span class="lineno"> 1279</span> <span class="comment">/* Debug Halting Control and Status Register */</span></div>
|
|
<div class="line"><a name="l01280"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#gac91280edd0ce932665cf75a23d11d842"> 1280</a></span> <span class="preprocessor">#define CoreDebug_DHCSR_DBGKEY_Pos 16 </span></div>
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|
<div class="line"><a name="l01281"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga1ce997cee15edaafe4aed77751816ffc"> 1281</a></span> <span class="preprocessor">#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) </span></div>
|
|
<div class="line"><a name="l01283"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga6f934c5427ea057394268e541fa97753"> 1283</a></span> <span class="preprocessor">#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 </span></div>
|
|
<div class="line"><a name="l01284"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#gac474394bcceb31a8e09566c90b3f8922"> 1284</a></span> <span class="preprocessor">#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) </span></div>
|
|
<div class="line"><a name="l01286"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga2328118f8b3574c871a53605eb17e730"> 1286</a></span> <span class="preprocessor">#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 </span></div>
|
|
<div class="line"><a name="l01287"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga89dceb5325f6bcb36a0473d65fbfcfa6"> 1287</a></span> <span class="preprocessor">#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) </span></div>
|
|
<div class="line"><a name="l01289"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga2900dd56a988a4ed27ad664d5642807e"> 1289</a></span> <span class="preprocessor">#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 </span></div>
|
|
<div class="line"><a name="l01290"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga7b67e4506d7f464ef5dafd6219739756"> 1290</a></span> <span class="preprocessor">#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) </span></div>
|
|
<div class="line"><a name="l01292"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga349ccea33accc705595624c2d334fbcb"> 1292</a></span> <span class="preprocessor">#define CoreDebug_DHCSR_S_SLEEP_Pos 18 </span></div>
|
|
<div class="line"><a name="l01293"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga98d51538e645c2c1a422279cd85a0a25"> 1293</a></span> <span class="preprocessor">#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) </span></div>
|
|
<div class="line"><a name="l01295"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga760a9a0d7f39951dc3f07d01f1f64772"> 1295</a></span> <span class="preprocessor">#define CoreDebug_DHCSR_S_HALT_Pos 17 </span></div>
|
|
<div class="line"><a name="l01296"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga9f881ade3151a73bc5b02b73fe6473ca"> 1296</a></span> <span class="preprocessor">#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) </span></div>
|
|
<div class="line"><a name="l01298"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga20a71871ca8768019c51168c70c3f41d"> 1298</a></span> <span class="preprocessor">#define CoreDebug_DHCSR_S_REGRDY_Pos 16 </span></div>
|
|
<div class="line"><a name="l01299"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#gac4cd6f3178de48f473d8903e8c847c07"> 1299</a></span> <span class="preprocessor">#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) </span></div>
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<div class="line"><a name="l01301"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga85747214e2656df6b05ec72e4d22bd6d"> 1301</a></span> <span class="preprocessor">#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 </span></div>
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<div class="line"><a name="l01302"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga53aa99b2e39a67622f3b9973e079c2b4"> 1302</a></span> <span class="preprocessor">#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) </span></div>
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<div class="line"><a name="l01304"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga0d2907400eb948a4ea3886ca083ec8e3"> 1304</a></span> <span class="preprocessor">#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 </span></div>
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<div class="line"><a name="l01305"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga77fe1ef3c4a729c1c82fb62a94a51c31"> 1305</a></span> <span class="preprocessor">#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) </span></div>
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<div class="line"><a name="l01307"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#gae1fc39e80de54c0339cbb1b298a9f0f9"> 1307</a></span> <span class="preprocessor">#define CoreDebug_DHCSR_C_STEP_Pos 2 </span></div>
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<div class="line"><a name="l01308"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#gae6bda72fbd32cc5734ff3542170dc00d"> 1308</a></span> <span class="preprocessor">#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) </span></div>
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<div class="line"><a name="l01310"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#gaddf1d43f8857e4efc3dc4e6b15509692"> 1310</a></span> <span class="preprocessor">#define CoreDebug_DHCSR_C_HALT_Pos 1 </span></div>
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<div class="line"><a name="l01311"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga1d905a3aa594eb2e8bb78bcc4da05b3f"> 1311</a></span> <span class="preprocessor">#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) </span></div>
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<div class="line"><a name="l01313"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#gab557abb5b172b74d2cf44efb9d824e4e"> 1313</a></span> <span class="preprocessor">#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 </span></div>
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<div class="line"><a name="l01314"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#gab815c741a4fc2a61988cd2fb7594210b"> 1314</a></span> <span class="preprocessor">#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) </span></div>
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<div class="line"><a name="l01316"></a><span class="lineno"> 1316</span> <span class="preprocessor"></span><span class="comment">/* Debug Core Register Selector Register */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l01317"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga51e75942fc0614bc9bb2c0e96fcdda9a"> 1317</a></span> <span class="preprocessor">#define CoreDebug_DCRSR_REGWnR_Pos 16 </span></div>
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<div class="line"><a name="l01318"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga1eef4992d8f84bc6c0dffed1c87f90a5"> 1318</a></span> <span class="preprocessor">#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) </span></div>
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<div class="line"><a name="l01320"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga52182c8a9f63a52470244c0bc2064f7b"> 1320</a></span> <span class="preprocessor">#define CoreDebug_DCRSR_REGSEL_Pos 0 </span></div>
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<div class="line"><a name="l01321"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga17cafbd72b55030219ce5609baa7c01d"> 1321</a></span> <span class="preprocessor">#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) </span></div>
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<div class="line"><a name="l01323"></a><span class="lineno"> 1323</span> <span class="preprocessor"></span><span class="comment">/* Debug Exception and Monitor Control Register */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l01324"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga6ff2102b98f86540224819a1b767ba39"> 1324</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_TRCENA_Pos 24 </span></div>
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<div class="line"><a name="l01325"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga5e99652c1df93b441257389f49407834"> 1325</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) </span></div>
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<div class="line"><a name="l01327"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga341020a3b7450416d72544eaf8e57a64"> 1327</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_MON_REQ_Pos 19 </span></div>
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<div class="line"><a name="l01328"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#gae6384cbe8045051186d13ef9cdeace95"> 1328</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) </span></div>
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<div class="line"><a name="l01330"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga9ae10710684e14a1a534e785ef390e1b"> 1330</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_MON_STEP_Pos 18 </span></div>
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<div class="line"><a name="l01331"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga2ded814556de96fc369de7ae9a7ceb98"> 1331</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) </span></div>
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<div class="line"><a name="l01333"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga1e2f706a59e0d8131279af1c7e152f8d"> 1333</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_MON_PEND_Pos 17 </span></div>
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<div class="line"><a name="l01334"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga68ec55930269fab78e733dcfa32392f8"> 1334</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) </span></div>
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<div class="line"><a name="l01336"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga802829678f6871863ae9ecf60a10425c"> 1336</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_MON_EN_Pos 16 </span></div>
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<div class="line"><a name="l01337"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#gac2b46b9b65bf8d23027f255fc9641977"> 1337</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) </span></div>
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<div class="line"><a name="l01339"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#gaed9f42053031a9a30cd8054623304c0a"> 1339</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 </span></div>
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<div class="line"><a name="l01340"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga803fc98c5bb85f10f0347b23794847d1"> 1340</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) </span></div>
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<div class="line"><a name="l01342"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga22079a6e436f23b90308be97e19cf07e"> 1342</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_VC_INTERR_Pos 9 </span></div>
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|
<div class="line"><a name="l01343"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#gad6815d8e3df302d2f0ff2c2c734ed29a"> 1343</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) </span></div>
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<div class="line"><a name="l01345"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#gab8e3d8f0f9590a51bbf10f6da3ad6933"> 1345</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 </span></div>
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<div class="line"><a name="l01346"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga9d29546aefe3ca8662a7fe48dd4a5b2b"> 1346</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) </span></div>
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<div class="line"><a name="l01348"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga16f0d3d2ce1e1e8cd762d938ac56c4ac"> 1348</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_VC_STATERR_Pos 7 </span></div>
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<div class="line"><a name="l01349"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#gaa38b947d77672c48bba1280c0a642e19"> 1349</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) </span></div>
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<div class="line"><a name="l01351"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga10fc7c53bca904c128bc8e1a03072d50"> 1351</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 </span></div>
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<div class="line"><a name="l01352"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga2f98b461d19746ab2febfddebb73da6f"> 1352</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) </span></div>
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<div class="line"><a name="l01354"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#gac9d13eb2add61f610d5ced1f7ad2adf8"> 1354</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 </span></div>
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<div class="line"><a name="l01355"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga03ee58b1b02fdbf21612809034562f1c"> 1355</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) </span></div>
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<div class="line"><a name="l01357"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga444454f7c7748e76cd76c3809c887c41"> 1357</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_VC_MMERR_Pos 4 </span></div>
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<div class="line"><a name="l01358"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#gad420a9b60620584faaca6289e83d3a87"> 1358</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) </span></div>
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<div class="line"><a name="l01360"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga9fcf09666f7063a7303117aa32a85d5a"> 1360</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 </span></div>
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<div class="line"><a name="l01361"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core_debug.html#ga906476e53c1e1487c30f3a1181df9e30"> 1361</a></span> <span class="preprocessor">#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) </span></div>
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<div class="line"><a name="l01363"></a><span class="lineno"> 1363</span> <span class="preprocessor"></span></div>
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<div class="line"><a name="l01372"></a><span class="lineno"> 1372</span> <span class="preprocessor"></span><span class="comment">/* Memory mapping of Cortex-M4 Hardware */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l01373"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core__base.html#ga3c14ed93192c8d9143322bbf77ebf770"> 1373</a></span> <span class="preprocessor">#define SCS_BASE (0xE000E000UL) </span></div>
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<div class="line"><a name="l01374"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core__base.html#gadd76251e412a195ec0a8f47227a8359e"> 1374</a></span> <span class="preprocessor">#define ITM_BASE (0xE0000000UL) </span></div>
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<div class="line"><a name="l01375"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core__base.html#gafdab534f961bf8935eb456cb7700dcd2"> 1375</a></span> <span class="preprocessor">#define DWT_BASE (0xE0001000UL) </span></div>
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<div class="line"><a name="l01376"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core__base.html#ga2b1eeff850a7e418844ca847145a1a68"> 1376</a></span> <span class="preprocessor">#define TPI_BASE (0xE0040000UL) </span></div>
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<div class="line"><a name="l01377"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core__base.html#ga680604dbcda9e9b31a1639fcffe5230b"> 1377</a></span> <span class="preprocessor">#define CoreDebug_BASE (0xE000EDF0UL) </span></div>
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<div class="line"><a name="l01378"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core__base.html#ga58effaac0b93006b756d33209e814646"> 1378</a></span> <span class="preprocessor">#define SysTick_BASE (SCS_BASE + 0x0010UL) </span></div>
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<div class="line"><a name="l01379"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core__base.html#gaa0288691785a5f868238e0468b39523d"> 1379</a></span> <span class="preprocessor">#define NVIC_BASE (SCS_BASE + 0x0100UL) </span></div>
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<div class="line"><a name="l01380"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core__base.html#gad55a7ddb8d4b2398b0c1cfec76c0d9fd"> 1380</a></span> <span class="preprocessor">#define SCB_BASE (SCS_BASE + 0x0D00UL) </span></div>
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<div class="line"><a name="l01382"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core__base.html#ga9fe0cd2eef83a8adad94490d9ecca63f"> 1382</a></span> <span class="preprocessor">#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) </span></div>
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<div class="line"><a name="l01383"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core__base.html#gaaaf6477c2bde2f00f99e3c2fd1060b01"> 1383</a></span> <span class="preprocessor">#define SCB ((SCB_Type *) SCB_BASE ) </span></div>
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<div class="line"><a name="l01384"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core__base.html#gacd96c53beeaff8f603fcda425eb295de"> 1384</a></span> <span class="preprocessor">#define SysTick ((SysTick_Type *) SysTick_BASE ) </span></div>
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<div class="line"><a name="l01385"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17"> 1385</a></span> <span class="preprocessor">#define NVIC ((NVIC_Type *) NVIC_BASE ) </span></div>
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<div class="line"><a name="l01386"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core__base.html#gabae7cdf882def602cb787bb039ff6a43"> 1386</a></span> <span class="preprocessor">#define ITM ((ITM_Type *) ITM_BASE ) </span></div>
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<div class="line"><a name="l01387"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core__base.html#gabbe5a060185e1d5afa3f85b14e10a6ce"> 1387</a></span> <span class="preprocessor">#define DWT ((DWT_Type *) DWT_BASE ) </span></div>
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<div class="line"><a name="l01388"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core__base.html#ga8b4dd00016aed25a0ea54e9a9acd1239"> 1388</a></span> <span class="preprocessor">#define TPI ((TPI_Type *) TPI_BASE ) </span></div>
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<div class="line"><a name="l01389"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core__base.html#gab6e30a2b802d9021619dbb0be7f5d63d"> 1389</a></span> <span class="preprocessor">#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) </span></div>
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<div class="line"><a name="l01391"></a><span class="lineno"> 1391</span> <span class="preprocessor">#if (__MPU_PRESENT == 1)</span></div>
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<div class="line"><a name="l01392"></a><span class="lineno"> 1392</span> <span class="preprocessor"> #define MPU_BASE (SCS_BASE + 0x0D90UL) </span></div>
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<div class="line"><a name="l01393"></a><span class="lineno"> 1393</span> <span class="preprocessor"> #define MPU ((MPU_Type *) MPU_BASE ) </span></div>
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<div class="line"><a name="l01394"></a><span class="lineno"> 1394</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l01395"></a><span class="lineno"> 1395</span> </div>
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<div class="line"><a name="l01396"></a><span class="lineno"> 1396</span> <span class="preprocessor">#if (__FPU_PRESENT == 1)</span></div>
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<div class="line"><a name="l01397"></a><span class="lineno"> 1397</span> <span class="preprocessor"> #define FPU_BASE (SCS_BASE + 0x0F30UL) </span></div>
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<div class="line"><a name="l01398"></a><span class="lineno"> 1398</span> <span class="preprocessor"> #define FPU ((FPU_Type *) FPU_BASE ) </span></div>
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<div class="line"><a name="l01399"></a><span class="lineno"> 1399</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l01400"></a><span class="lineno"> 1400</span> </div>
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<div class="line"><a name="l01405"></a><span class="lineno"> 1405</span> <span class="comment">/*******************************************************************************</span></div>
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<div class="line"><a name="l01406"></a><span class="lineno"> 1406</span> <span class="comment"> * Hardware Abstraction Layer</span></div>
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<div class="line"><a name="l01407"></a><span class="lineno"> 1407</span> <span class="comment"> Core Function Interface contains:</span></div>
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<div class="line"><a name="l01408"></a><span class="lineno"> 1408</span> <span class="comment"> - Core NVIC Functions</span></div>
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<div class="line"><a name="l01409"></a><span class="lineno"> 1409</span> <span class="comment"> - Core SysTick Functions</span></div>
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<div class="line"><a name="l01410"></a><span class="lineno"> 1410</span> <span class="comment"> - Core Debug Functions</span></div>
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<div class="line"><a name="l01411"></a><span class="lineno"> 1411</span> <span class="comment"> - Core Register Access Functions</span></div>
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<div class="line"><a name="l01412"></a><span class="lineno"> 1412</span> <span class="comment"> ******************************************************************************/</span></div>
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<div class="line"><a name="l01418"></a><span class="lineno"> 1418</span> <span class="comment">/* ########################## NVIC functions #################################### */</span></div>
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<div class="line"><a name="l01435"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga77cfbb35a9d8027e392034321bed6904"> 1435</a></span> __STATIC_INLINE <span class="keywordtype">void</span> <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga77cfbb35a9d8027e392034321bed6904">NVIC_SetPriorityGrouping</a>(uint32_t PriorityGroup)</div>
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<div class="line"><a name="l01436"></a><span class="lineno"> 1436</span> {</div>
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<div class="line"><a name="l01437"></a><span class="lineno"> 1437</span>  uint32_t reg_value;</div>
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<div class="line"><a name="l01438"></a><span class="lineno"> 1438</span>  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); <span class="comment">/* only values 0..7 are used */</span></div>
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<div class="line"><a name="l01439"></a><span class="lineno"> 1439</span> </div>
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<div class="line"><a name="l01440"></a><span class="lineno"> 1440</span>  reg_value = <a class="code" href="group___c_m_s_i_s__core__base.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a>->AIRCR; <span class="comment">/* read old register configuration */</span></div>
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<div class="line"><a name="l01441"></a><span class="lineno"> 1441</span>  reg_value &= ~(<a class="code" href="group___c_m_s_i_s___s_c_b.html#ga90c7cf0c490e7ae55f9503a7fda1dd22">SCB_AIRCR_VECTKEY_Msk</a> | <a class="code" href="group___c_m_s_i_s___s_c_b.html#ga8be60fff03f48d0d345868060dc6dae7">SCB_AIRCR_PRIGROUP_Msk</a>); <span class="comment">/* clear bits to change */</span></div>
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<div class="line"><a name="l01442"></a><span class="lineno"> 1442</span>  reg_value = (reg_value |</div>
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<div class="line"><a name="l01443"></a><span class="lineno"> 1443</span>  ((uint32_t)0x5FA << <a class="code" href="group___c_m_s_i_s___s_c_b.html#gaaa27c0ba600bf82c3da08c748845b640">SCB_AIRCR_VECTKEY_Pos</a>) |</div>
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<div class="line"><a name="l01444"></a><span class="lineno"> 1444</span>  (PriorityGroupTmp << 8)); <span class="comment">/* Insert write key and priorty group */</span></div>
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<div class="line"><a name="l01445"></a><span class="lineno"> 1445</span>  <a class="code" href="group___c_m_s_i_s__core__base.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a>->AIRCR = reg_value;</div>
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<div class="line"><a name="l01446"></a><span class="lineno"> 1446</span> }</div>
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<div class="line"><a name="l01447"></a><span class="lineno"> 1447</span> </div>
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<div class="line"><a name="l01448"></a><span class="lineno"> 1448</span> </div>
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<div class="line"><a name="l01455"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga394f7ce2ca826c0da26284d17ac6524d"> 1455</a></span> __STATIC_INLINE uint32_t <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga394f7ce2ca826c0da26284d17ac6524d">NVIC_GetPriorityGrouping</a>(<span class="keywordtype">void</span>)</div>
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<div class="line"><a name="l01456"></a><span class="lineno"> 1456</span> {</div>
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<div class="line"><a name="l01457"></a><span class="lineno"> 1457</span>  <span class="keywordflow">return</span> ((<a class="code" href="group___c_m_s_i_s__core__base.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a>->AIRCR & <a class="code" href="group___c_m_s_i_s___s_c_b.html#ga8be60fff03f48d0d345868060dc6dae7">SCB_AIRCR_PRIGROUP_Msk</a>) >> <a class="code" href="group___c_m_s_i_s___s_c_b.html#gaca155deccdeca0f2c76b8100d24196c8">SCB_AIRCR_PRIGROUP_Pos</a>); <span class="comment">/* read priority grouping field */</span></div>
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<div class="line"><a name="l01458"></a><span class="lineno"> 1458</span> }</div>
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<div class="line"><a name="l01459"></a><span class="lineno"> 1459</span> </div>
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<div class="line"><a name="l01460"></a><span class="lineno"> 1460</span> </div>
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<div class="line"><a name="l01467"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga3349f2e3580d7ce22d6530b7294e5921"> 1467</a></span> __STATIC_INLINE <span class="keywordtype">void</span> <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga3349f2e3580d7ce22d6530b7294e5921">NVIC_EnableIRQ</a>(<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gac3af4a32370fb28c4ade8bf2add80251">IRQn_Type</a> <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#ga666eb0caeb12ec0e281415592ae89083">IRQn</a>)</div>
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<div class="line"><a name="l01468"></a><span class="lineno"> 1468</span> {</div>
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<div class="line"><a name="l01469"></a><span class="lineno"> 1469</span> <span class="comment">/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */</span></div>
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<div class="line"><a name="l01470"></a><span class="lineno"> 1470</span>  <a class="code" href="group___c_m_s_i_s__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>->ISER[(uint32_t)((int32_t)<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#ga666eb0caeb12ec0e281415592ae89083">IRQn</a>) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#ga666eb0caeb12ec0e281415592ae89083">IRQn</a>) & (uint32_t)0x1F)); <span class="comment">/* enable interrupt */</span></div>
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<div class="line"><a name="l01471"></a><span class="lineno"> 1471</span> }</div>
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<div class="line"><a name="l01472"></a><span class="lineno"> 1472</span> </div>
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<div class="line"><a name="l01473"></a><span class="lineno"> 1473</span> </div>
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<div class="line"><a name="l01480"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga260fba04ac8346855c57f091d4ee1e71"> 1480</a></span> __STATIC_INLINE <span class="keywordtype">void</span> <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga260fba04ac8346855c57f091d4ee1e71">NVIC_DisableIRQ</a>(<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gac3af4a32370fb28c4ade8bf2add80251">IRQn_Type</a> <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#ga666eb0caeb12ec0e281415592ae89083">IRQn</a>)</div>
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<div class="line"><a name="l01481"></a><span class="lineno"> 1481</span> {</div>
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<div class="line"><a name="l01482"></a><span class="lineno"> 1482</span>  <a class="code" href="group___c_m_s_i_s__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#ga666eb0caeb12ec0e281415592ae89083">IRQn</a>) & 0x1F)); <span class="comment">/* disable interrupt */</span></div>
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<div class="line"><a name="l01483"></a><span class="lineno"> 1483</span> }</div>
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<div class="line"><a name="l01484"></a><span class="lineno"> 1484</span> </div>
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<div class="line"><a name="l01485"></a><span class="lineno"> 1485</span> </div>
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<div class="line"><a name="l01496"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#gafec8042db64c0f8ed432b6c8386a05d8"> 1496</a></span> __STATIC_INLINE uint32_t <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#gafec8042db64c0f8ed432b6c8386a05d8">NVIC_GetPendingIRQ</a>(<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gac3af4a32370fb28c4ade8bf2add80251">IRQn_Type</a> <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#ga666eb0caeb12ec0e281415592ae89083">IRQn</a>)</div>
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<div class="line"><a name="l01497"></a><span class="lineno"> 1497</span> {</div>
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<div class="line"><a name="l01498"></a><span class="lineno"> 1498</span>  <span class="keywordflow">return</span>((uint32_t) ((<a class="code" href="group___c_m_s_i_s__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); <span class="comment">/* Return 1 if pending else 0 */</span></div>
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<div class="line"><a name="l01499"></a><span class="lineno"> 1499</span> }</div>
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<div class="line"><a name="l01500"></a><span class="lineno"> 1500</span> </div>
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<div class="line"><a name="l01501"></a><span class="lineno"> 1501</span> </div>
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<div class="line"><a name="l01508"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga3ecf446519da33e1690deffbf5be505f"> 1508</a></span> __STATIC_INLINE <span class="keywordtype">void</span> <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga3ecf446519da33e1690deffbf5be505f">NVIC_SetPendingIRQ</a>(<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gac3af4a32370fb28c4ade8bf2add80251">IRQn_Type</a> <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#ga666eb0caeb12ec0e281415592ae89083">IRQn</a>)</div>
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|
<div class="line"><a name="l01509"></a><span class="lineno"> 1509</span> {</div>
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<div class="line"><a name="l01510"></a><span class="lineno"> 1510</span>  <a class="code" href="group___c_m_s_i_s__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#ga666eb0caeb12ec0e281415592ae89083">IRQn</a>) & 0x1F)); <span class="comment">/* set interrupt pending */</span></div>
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<div class="line"><a name="l01511"></a><span class="lineno"> 1511</span> }</div>
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|
<div class="line"><a name="l01512"></a><span class="lineno"> 1512</span> </div>
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<div class="line"><a name="l01513"></a><span class="lineno"> 1513</span> </div>
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|
<div class="line"><a name="l01520"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga332e10ef9605dc6eb10b9e14511930f8"> 1520</a></span> __STATIC_INLINE <span class="keywordtype">void</span> <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga332e10ef9605dc6eb10b9e14511930f8">NVIC_ClearPendingIRQ</a>(<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gac3af4a32370fb28c4ade8bf2add80251">IRQn_Type</a> <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#ga666eb0caeb12ec0e281415592ae89083">IRQn</a>)</div>
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|
<div class="line"><a name="l01521"></a><span class="lineno"> 1521</span> {</div>
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|
<div class="line"><a name="l01522"></a><span class="lineno"> 1522</span>  <a class="code" href="group___c_m_s_i_s__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#ga666eb0caeb12ec0e281415592ae89083">IRQn</a>) & 0x1F)); <span class="comment">/* Clear pending interrupt */</span></div>
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|
<div class="line"><a name="l01523"></a><span class="lineno"> 1523</span> }</div>
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|
<div class="line"><a name="l01524"></a><span class="lineno"> 1524</span> </div>
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|
<div class="line"><a name="l01525"></a><span class="lineno"> 1525</span> </div>
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|
<div class="line"><a name="l01535"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga47a0f52794068d076c9147aa3cb8d8a6"> 1535</a></span> __STATIC_INLINE uint32_t <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga47a0f52794068d076c9147aa3cb8d8a6">NVIC_GetActive</a>(<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gac3af4a32370fb28c4ade8bf2add80251">IRQn_Type</a> <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#ga666eb0caeb12ec0e281415592ae89083">IRQn</a>)</div>
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|
<div class="line"><a name="l01536"></a><span class="lineno"> 1536</span> {</div>
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|
<div class="line"><a name="l01537"></a><span class="lineno"> 1537</span>  <span class="keywordflow">return</span>((uint32_t)((<a class="code" href="group___c_m_s_i_s__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); <span class="comment">/* Return 1 if active else 0 */</span></div>
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<div class="line"><a name="l01538"></a><span class="lineno"> 1538</span> }</div>
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<div class="line"><a name="l01539"></a><span class="lineno"> 1539</span> </div>
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<div class="line"><a name="l01540"></a><span class="lineno"> 1540</span> </div>
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|
<div class="line"><a name="l01550"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga2305cbd44aaad792e3a4e538bdaf14f9"> 1550</a></span> __STATIC_INLINE <span class="keywordtype">void</span> <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga2305cbd44aaad792e3a4e538bdaf14f9">NVIC_SetPriority</a>(<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gac3af4a32370fb28c4ade8bf2add80251">IRQn_Type</a> <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#ga666eb0caeb12ec0e281415592ae89083">IRQn</a>, uint32_t priority)</div>
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<div class="line"><a name="l01551"></a><span class="lineno"> 1551</span> {</div>
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<div class="line"><a name="l01552"></a><span class="lineno"> 1552</span>  <span class="keywordflow">if</span>(IRQn < 0) {</div>
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|
<div class="line"><a name="l01553"></a><span class="lineno"> 1553</span>  <a class="code" href="group___c_m_s_i_s__core__base.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a>->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>)) & 0xff); } <span class="comment">/* set Priority for Cortex-M System Interrupts */</span></div>
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<div class="line"><a name="l01554"></a><span class="lineno"> 1554</span>  <span class="keywordflow">else</span> {</div>
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<div class="line"><a name="l01555"></a><span class="lineno"> 1555</span>  <a class="code" href="group___c_m_s_i_s__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>->IP[(uint32_t)(IRQn)] = ((priority << (8 - <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>)) & 0xff); } <span class="comment">/* set Priority for device specific Interrupts */</span></div>
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<div class="line"><a name="l01556"></a><span class="lineno"> 1556</span> }</div>
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<div class="line"><a name="l01557"></a><span class="lineno"> 1557</span> </div>
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<div class="line"><a name="l01558"></a><span class="lineno"> 1558</span> </div>
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|
<div class="line"><a name="l01570"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga1cbaf8e6abd4aa4885828e7f24fcfeb4"> 1570</a></span> __STATIC_INLINE uint32_t <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga1cbaf8e6abd4aa4885828e7f24fcfeb4">NVIC_GetPriority</a>(<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gac3af4a32370fb28c4ade8bf2add80251">IRQn_Type</a> <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#ga666eb0caeb12ec0e281415592ae89083">IRQn</a>)</div>
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<div class="line"><a name="l01571"></a><span class="lineno"> 1571</span> {</div>
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<div class="line"><a name="l01572"></a><span class="lineno"> 1572</span> </div>
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<div class="line"><a name="l01573"></a><span class="lineno"> 1573</span>  <span class="keywordflow">if</span>(IRQn < 0) {</div>
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<div class="line"><a name="l01574"></a><span class="lineno"> 1574</span>  <span class="keywordflow">return</span>((uint32_t)(<a class="code" href="group___c_m_s_i_s__core__base.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a>->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>))); } <span class="comment">/* get priority for Cortex-M system interrupts */</span></div>
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<div class="line"><a name="l01575"></a><span class="lineno"> 1575</span>  <span class="keywordflow">else</span> {</div>
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<div class="line"><a name="l01576"></a><span class="lineno"> 1576</span>  <span class="keywordflow">return</span>((uint32_t)(<a class="code" href="group___c_m_s_i_s__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>->IP[(uint32_t)(IRQn)] >> (8 - <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>))); } <span class="comment">/* get priority for device specific interrupts */</span></div>
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<div class="line"><a name="l01577"></a><span class="lineno"> 1577</span> }</div>
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<div class="line"><a name="l01578"></a><span class="lineno"> 1578</span> </div>
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|
<div class="line"><a name="l01579"></a><span class="lineno"> 1579</span> </div>
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<div class="line"><a name="l01592"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#gadb94ac5d892b376e4f3555ae0418ebac"> 1592</a></span> __STATIC_INLINE uint32_t <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#gadb94ac5d892b376e4f3555ae0418ebac">NVIC_EncodePriority</a> (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</div>
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<div class="line"><a name="l01593"></a><span class="lineno"> 1593</span> {</div>
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<div class="line"><a name="l01594"></a><span class="lineno"> 1594</span>  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); <span class="comment">/* only values 0..7 are used */</span></div>
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|
<div class="line"><a name="l01595"></a><span class="lineno"> 1595</span>  uint32_t PreemptPriorityBits;</div>
|
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<div class="line"><a name="l01596"></a><span class="lineno"> 1596</span>  uint32_t SubPriorityBits;</div>
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|
<div class="line"><a name="l01597"></a><span class="lineno"> 1597</span> </div>
|
|
<div class="line"><a name="l01598"></a><span class="lineno"> 1598</span>  PreemptPriorityBits = ((7 - PriorityGroupTmp) > <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>) ? <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a> : 7 - PriorityGroupTmp;</div>
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|
<div class="line"><a name="l01599"></a><span class="lineno"> 1599</span>  SubPriorityBits = ((PriorityGroupTmp + <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>) < 7) ? 0 : PriorityGroupTmp - 7 + <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>;</div>
|
|
<div class="line"><a name="l01600"></a><span class="lineno"> 1600</span> </div>
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|
<div class="line"><a name="l01601"></a><span class="lineno"> 1601</span>  <span class="keywordflow">return</span> (</div>
|
|
<div class="line"><a name="l01602"></a><span class="lineno"> 1602</span>  ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |</div>
|
|
<div class="line"><a name="l01603"></a><span class="lineno"> 1603</span>  ((SubPriority & ((1 << (SubPriorityBits )) - 1)))</div>
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<div class="line"><a name="l01604"></a><span class="lineno"> 1604</span>  );</div>
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<div class="line"><a name="l01605"></a><span class="lineno"> 1605</span> }</div>
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<div class="line"><a name="l01606"></a><span class="lineno"> 1606</span> </div>
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<div class="line"><a name="l01607"></a><span class="lineno"> 1607</span> </div>
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<div class="line"><a name="l01620"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga4f23ef94633f75d3c97670a53949003c"> 1620</a></span> __STATIC_INLINE <span class="keywordtype">void</span> <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga4f23ef94633f75d3c97670a53949003c">NVIC_DecodePriority</a> (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)</div>
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<div class="line"><a name="l01621"></a><span class="lineno"> 1621</span> {</div>
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<div class="line"><a name="l01622"></a><span class="lineno"> 1622</span>  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); <span class="comment">/* only values 0..7 are used */</span></div>
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<div class="line"><a name="l01623"></a><span class="lineno"> 1623</span>  uint32_t PreemptPriorityBits;</div>
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<div class="line"><a name="l01624"></a><span class="lineno"> 1624</span>  uint32_t SubPriorityBits;</div>
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<div class="line"><a name="l01625"></a><span class="lineno"> 1625</span> </div>
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|
<div class="line"><a name="l01626"></a><span class="lineno"> 1626</span>  PreemptPriorityBits = ((7 - PriorityGroupTmp) > <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>) ? <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a> : 7 - PriorityGroupTmp;</div>
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<div class="line"><a name="l01627"></a><span class="lineno"> 1627</span>  SubPriorityBits = ((PriorityGroupTmp + <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>) < 7) ? 0 : PriorityGroupTmp - 7 + <a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>;</div>
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<div class="line"><a name="l01628"></a><span class="lineno"> 1628</span> </div>
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<div class="line"><a name="l01629"></a><span class="lineno"> 1629</span>  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);</div>
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|
<div class="line"><a name="l01630"></a><span class="lineno"> 1630</span>  *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);</div>
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|
<div class="line"><a name="l01631"></a><span class="lineno"> 1631</span> }</div>
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|
<div class="line"><a name="l01632"></a><span class="lineno"> 1632</span> </div>
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<div class="line"><a name="l01633"></a><span class="lineno"> 1633</span> </div>
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<div class="line"><a name="l01638"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga1143dec48d60a3d6f238c4798a87759c"> 1638</a></span> __STATIC_INLINE <span class="keywordtype">void</span> <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga1143dec48d60a3d6f238c4798a87759c">NVIC_SystemReset</a>(<span class="keywordtype">void</span>)</div>
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|
<div class="line"><a name="l01639"></a><span class="lineno"> 1639</span> {</div>
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|
<div class="line"><a name="l01640"></a><span class="lineno"> 1640</span>  __DSB(); <span class="comment">/* Ensure all outstanding memory accesses included</span></div>
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|
<div class="line"><a name="l01641"></a><span class="lineno"> 1641</span> <span class="comment"> buffered write are completed before reset */</span></div>
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|
<div class="line"><a name="l01642"></a><span class="lineno"> 1642</span>  <a class="code" href="group___c_m_s_i_s__core__base.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a>->AIRCR = ((0x5FA << <a class="code" href="group___c_m_s_i_s___s_c_b.html#gaaa27c0ba600bf82c3da08c748845b640">SCB_AIRCR_VECTKEY_Pos</a>) |</div>
|
|
<div class="line"><a name="l01643"></a><span class="lineno"> 1643</span>  (<a class="code" href="group___c_m_s_i_s__core__base.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a>->AIRCR & <a class="code" href="group___c_m_s_i_s___s_c_b.html#ga8be60fff03f48d0d345868060dc6dae7">SCB_AIRCR_PRIGROUP_Msk</a>) |</div>
|
|
<div class="line"><a name="l01644"></a><span class="lineno"> 1644</span>  <a class="code" href="group___c_m_s_i_s___s_c_b.html#gaae1181119559a5bd36e62afa373fa720">SCB_AIRCR_SYSRESETREQ_Msk</a>); <span class="comment">/* Keep priority group unchanged */</span></div>
|
|
<div class="line"><a name="l01645"></a><span class="lineno"> 1645</span>  __DSB(); <span class="comment">/* Ensure completion of memory access */</span></div>
|
|
<div class="line"><a name="l01646"></a><span class="lineno"> 1646</span>  <span class="keywordflow">while</span>(1); <span class="comment">/* wait until reset */</span></div>
|
|
<div class="line"><a name="l01647"></a><span class="lineno"> 1647</span> }</div>
|
|
<div class="line"><a name="l01648"></a><span class="lineno"> 1648</span> </div>
|
|
<div class="line"><a name="l01653"></a><span class="lineno"> 1653</span> <span class="comment">/* ################################## SysTick function ############################################ */</span></div>
|
|
<div class="line"><a name="l01660"></a><span class="lineno"> 1660</span> <span class="preprocessor">#if (__Vendor_SysTickConfig == 0)</span></div>
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|
<div class="line"><a name="l01661"></a><span class="lineno"> 1661</span> </div>
|
|
<div class="line"><a name="l01677"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___sys_tick_functions.html#gae4e8f0238527c69f522029b93c8e5b78"> 1677</a></span> __STATIC_INLINE uint32_t <a class="code" href="group___c_m_s_i_s___core___sys_tick_functions.html#gae4e8f0238527c69f522029b93c8e5b78">SysTick_Config</a>(uint32_t ticks)</div>
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|
<div class="line"><a name="l01678"></a><span class="lineno"> 1678</span> {</div>
|
|
<div class="line"><a name="l01679"></a><span class="lineno"> 1679</span>  <span class="keywordflow">if</span> ((ticks - 1) > <a class="code" href="group___c_m_s_i_s___sys_tick.html#ga265912a7962f0e1abd170336e579b1b1">SysTick_LOAD_RELOAD_Msk</a>) <span class="keywordflow">return</span> (1); <span class="comment">/* Reload value impossible */</span></div>
|
|
<div class="line"><a name="l01680"></a><span class="lineno"> 1680</span> </div>
|
|
<div class="line"><a name="l01681"></a><span class="lineno"> 1681</span>  <a class="code" href="group___c_m_s_i_s__core__base.html#gacd96c53beeaff8f603fcda425eb295de">SysTick</a>->LOAD = ticks - 1; <span class="comment">/* set reload register */</span></div>
|
|
<div class="line"><a name="l01682"></a><span class="lineno"> 1682</span>  <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga2305cbd44aaad792e3a4e538bdaf14f9">NVIC_SetPriority</a> (<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a6dbff8f8543325f3474cbae2446776e7">SysTick_IRQn</a>, (1<<<a class="code" href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a>) - 1); <span class="comment">/* set Priority for Systick Interrupt */</span></div>
|
|
<div class="line"><a name="l01683"></a><span class="lineno"> 1683</span>  <a class="code" href="group___c_m_s_i_s__core__base.html#gacd96c53beeaff8f603fcda425eb295de">SysTick</a>->VAL = 0; <span class="comment">/* Load the SysTick Counter Value */</span></div>
|
|
<div class="line"><a name="l01684"></a><span class="lineno"> 1684</span>  <a class="code" href="group___c_m_s_i_s__core__base.html#gacd96c53beeaff8f603fcda425eb295de">SysTick</a>->CTRL = <a class="code" href="group___c_m_s_i_s___sys_tick.html#gaa41d06039797423a46596bd313d57373">SysTick_CTRL_CLKSOURCE_Msk</a> |</div>
|
|
<div class="line"><a name="l01685"></a><span class="lineno"> 1685</span>  <a class="code" href="group___c_m_s_i_s___sys_tick.html#ga95bb984266ca764024836a870238a027">SysTick_CTRL_TICKINT_Msk</a> |</div>
|
|
<div class="line"><a name="l01686"></a><span class="lineno"> 1686</span>  <a class="code" href="group___c_m_s_i_s___sys_tick.html#ga16c9fee0ed0235524bdeb38af328fd1f">SysTick_CTRL_ENABLE_Msk</a>; <span class="comment">/* Enable SysTick IRQ and SysTick Timer */</span></div>
|
|
<div class="line"><a name="l01687"></a><span class="lineno"> 1687</span>  <span class="keywordflow">return</span> (0); <span class="comment">/* Function successful */</span></div>
|
|
<div class="line"><a name="l01688"></a><span class="lineno"> 1688</span> }</div>
|
|
<div class="line"><a name="l01689"></a><span class="lineno"> 1689</span> </div>
|
|
<div class="line"><a name="l01690"></a><span class="lineno"> 1690</span> <span class="preprocessor">#endif</span></div>
|
|
<div class="line"><a name="l01691"></a><span class="lineno"> 1691</span> </div>
|
|
<div class="line"><a name="l01696"></a><span class="lineno"> 1696</span> <span class="comment">/* ##################################### Debug In/Output function ########################################### */</span></div>
|
|
<div class="line"><a name="l01703"></a><span class="lineno"> 1703</span> <span class="keyword">extern</span> <span class="keyword">volatile</span> int32_t <a class="code" href="group___c_m_s_i_s__core___debug_functions.html#ga12e68e55a7badc271b948d6c7230b2a8">ITM_RxBuffer</a>; </div>
|
|
<div class="line"><a name="l01704"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core___debug_functions.html#gaa822cb398ee022b59e9e6c5d7bbb228a"> 1704</a></span> <span class="preprocessor">#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 </span></div>
|
|
<div class="line"><a name="l01717"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core___debug_functions.html#gac90a497bd64286b84552c2c553d3419e"> 1717</a></span> <span class="preprocessor">__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)</span></div>
|
|
<div class="line"><a name="l01718"></a><span class="lineno"> 1718</span> {</div>
|
|
<div class="line"><a name="l01719"></a><span class="lineno"> 1719</span>  <span class="keywordflow">if</span> ((<a class="code" href="group___c_m_s_i_s__core__base.html#gabae7cdf882def602cb787bb039ff6a43">ITM</a>->TCR & <a class="code" href="group___c_m_s_i_s___i_t_m.html#ga7dd53e3bff24ac09d94e61cb595cb2d9">ITM_TCR_ITMENA_Msk</a>) && <span class="comment">/* ITM enabled */</span></div>
|
|
<div class="line"><a name="l01720"></a><span class="lineno"> 1720</span>  (<a class="code" href="group___c_m_s_i_s__core__base.html#gabae7cdf882def602cb787bb039ff6a43">ITM</a>->TER & (1UL << 0) ) ) <span class="comment">/* ITM Port #0 enabled */</span></div>
|
|
<div class="line"><a name="l01721"></a><span class="lineno"> 1721</span>  {</div>
|
|
<div class="line"><a name="l01722"></a><span class="lineno"> 1722</span>  <span class="keywordflow">while</span> (<a class="code" href="group___c_m_s_i_s__core__base.html#gabae7cdf882def602cb787bb039ff6a43">ITM</a>->PORT[0].u32 == 0);</div>
|
|
<div class="line"><a name="l01723"></a><span class="lineno"> 1723</span>  <a class="code" href="group___c_m_s_i_s__core__base.html#gabae7cdf882def602cb787bb039ff6a43">ITM</a>->PORT[0].u8 = (uint8_t) ch;</div>
|
|
<div class="line"><a name="l01724"></a><span class="lineno"> 1724</span>  }</div>
|
|
<div class="line"><a name="l01725"></a><span class="lineno"> 1725</span>  <span class="keywordflow">return</span> (ch);</div>
|
|
<div class="line"><a name="l01726"></a><span class="lineno"> 1726</span> }</div>
|
|
<div class="line"><a name="l01727"></a><span class="lineno"> 1727</span> </div>
|
|
<div class="line"><a name="l01728"></a><span class="lineno"> 1728</span> </div>
|
|
<div class="line"><a name="l01736"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core___debug_functions.html#gac3ee2c30a1ac4ed34c8a866a17decd53"> 1736</a></span> __STATIC_INLINE int32_t <a class="code" href="group___c_m_s_i_s__core___debug_functions.html#gac3ee2c30a1ac4ed34c8a866a17decd53">ITM_ReceiveChar</a> (<span class="keywordtype">void</span>) {</div>
|
|
<div class="line"><a name="l01737"></a><span class="lineno"> 1737</span>  int32_t ch = -1; <span class="comment">/* no character available */</span></div>
|
|
<div class="line"><a name="l01738"></a><span class="lineno"> 1738</span> </div>
|
|
<div class="line"><a name="l01739"></a><span class="lineno"> 1739</span>  <span class="keywordflow">if</span> (ITM_RxBuffer != <a class="code" href="group___c_m_s_i_s__core___debug_functions.html#gaa822cb398ee022b59e9e6c5d7bbb228a">ITM_RXBUFFER_EMPTY</a>) {</div>
|
|
<div class="line"><a name="l01740"></a><span class="lineno"> 1740</span>  ch = <a class="code" href="group___c_m_s_i_s__core___debug_functions.html#ga12e68e55a7badc271b948d6c7230b2a8">ITM_RxBuffer</a>;</div>
|
|
<div class="line"><a name="l01741"></a><span class="lineno"> 1741</span>  ITM_RxBuffer = <a class="code" href="group___c_m_s_i_s__core___debug_functions.html#gaa822cb398ee022b59e9e6c5d7bbb228a">ITM_RXBUFFER_EMPTY</a>; <span class="comment">/* ready for next character */</span></div>
|
|
<div class="line"><a name="l01742"></a><span class="lineno"> 1742</span>  }</div>
|
|
<div class="line"><a name="l01743"></a><span class="lineno"> 1743</span> </div>
|
|
<div class="line"><a name="l01744"></a><span class="lineno"> 1744</span>  <span class="keywordflow">return</span> (ch);</div>
|
|
<div class="line"><a name="l01745"></a><span class="lineno"> 1745</span> }</div>
|
|
<div class="line"><a name="l01746"></a><span class="lineno"> 1746</span> </div>
|
|
<div class="line"><a name="l01747"></a><span class="lineno"> 1747</span> </div>
|
|
<div class="line"><a name="l01755"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core___debug_functions.html#gae61ce9ca5917735325cd93b0fb21dd29"> 1755</a></span> __STATIC_INLINE int32_t <a class="code" href="group___c_m_s_i_s__core___debug_functions.html#gae61ce9ca5917735325cd93b0fb21dd29">ITM_CheckChar</a> (<span class="keywordtype">void</span>) {</div>
|
|
<div class="line"><a name="l01756"></a><span class="lineno"> 1756</span> </div>
|
|
<div class="line"><a name="l01757"></a><span class="lineno"> 1757</span>  <span class="keywordflow">if</span> (ITM_RxBuffer == <a class="code" href="group___c_m_s_i_s__core___debug_functions.html#gaa822cb398ee022b59e9e6c5d7bbb228a">ITM_RXBUFFER_EMPTY</a>) {</div>
|
|
<div class="line"><a name="l01758"></a><span class="lineno"> 1758</span>  <span class="keywordflow">return</span> (0); <span class="comment">/* no character available */</span></div>
|
|
<div class="line"><a name="l01759"></a><span class="lineno"> 1759</span>  } <span class="keywordflow">else</span> {</div>
|
|
<div class="line"><a name="l01760"></a><span class="lineno"> 1760</span>  <span class="keywordflow">return</span> (1); <span class="comment">/* character available */</span></div>
|
|
<div class="line"><a name="l01761"></a><span class="lineno"> 1761</span>  }</div>
|
|
<div class="line"><a name="l01762"></a><span class="lineno"> 1762</span> }</div>
|
|
<div class="line"><a name="l01763"></a><span class="lineno"> 1763</span> </div>
|
|
<div class="line"><a name="l01766"></a><span class="lineno"> 1766</span> <span class="preprocessor">#endif </span><span class="comment">/* __CORE_CM4_H_DEPENDANT */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l01767"></a><span class="lineno"> 1767</span> </div>
|
|
<div class="line"><a name="l01768"></a><span class="lineno"> 1768</span> <span class="preprocessor">#endif </span><span class="comment">/* __CMSIS_GENERIC */</span><span class="preprocessor"></span></div>
|
|
<div class="line"><a name="l01769"></a><span class="lineno"> 1769</span> </div>
|
|
<div class="line"><a name="l01770"></a><span class="lineno"> 1770</span> <span class="preprocessor">#ifdef __cplusplus</span></div>
|
|
<div class="line"><a name="l01771"></a><span class="lineno"> 1771</span> }</div>
|
|
<div class="line"><a name="l01772"></a><span class="lineno"> 1772</span> <span class="preprocessor">#endif</span></div>
|
|
<div class="ttc" id="struct_sys_tick___type_html_a0997ff20f11817f8246e8f0edac6f4e4"><div class="ttname"><a href="struct_sys_tick___type.html#a0997ff20f11817f8246e8f0edac6f4e4">SysTick_Type::VAL</a></div><div class="ttdeci">__IO uint32_t VAL</div><div class="ttdef"><b>Definition:</b> core_cm4.h:627</div></div>
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<div class="ttc" id="group___c_m_s_i_s__core__base_html_gabae7cdf882def602cb787bb039ff6a43"><div class="ttname"><a href="group___c_m_s_i_s__core__base.html#gabae7cdf882def602cb787bb039ff6a43">ITM</a></div><div class="ttdeci">#define ITM</div><div class="ttdef"><b>Definition:</b> core_cm4.h:1386</div></div>
|
|
<div class="ttc" id="core__cm_func_8h_html"><div class="ttname"><a href="core__cm_func_8h.html">core_cmFunc.h</a></div><div class="ttdoc">CMSIS Cortex-M Core Function Access Header File. </div></div>
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|
<div class="ttc" id="struct_d_w_t___type_html"><div class="ttname"><a href="struct_d_w_t___type.html">DWT_Type</a></div><div class="ttdoc">Structure type to access the Data Watchpoint and Trace Register (DWT). </div><div class="ttdef"><b>Definition:</b> core_cm4.h:774</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gae3fe3587d5100c787e02102ce3944460"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a></div><div class="ttdeci">#define __NVIC_PRIO_BITS</div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:166</div></div>
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<div class="ttc" id="group___c_m_s_i_s___s_c_b_html_ga8be60fff03f48d0d345868060dc6dae7"><div class="ttname"><a href="group___c_m_s_i_s___s_c_b.html#ga8be60fff03f48d0d345868060dc6dae7">SCB_AIRCR_PRIGROUP_Msk</a></div><div class="ttdeci">#define SCB_AIRCR_PRIGROUP_Msk</div><div class="ttdef"><b>Definition:</b> core_cm4.h:455</div></div>
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|
<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_gafec8042db64c0f8ed432b6c8386a05d8"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#gafec8042db64c0f8ed432b6c8386a05d8">NVIC_GetPendingIRQ</a></div><div class="ttdeci">__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Get Pending Interrupt. </div><div class="ttdef"><b>Definition:</b> core_cm4.h:1496</div></div>
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<div class="ttc" id="struct_t_p_i___type_html_a44efa6045512c8d4da64b0623f7a43ad"><div class="ttname"><a href="struct_t_p_i___type.html#a44efa6045512c8d4da64b0623f7a43ad">TPI_Type::CLAIMCLR</a></div><div class="ttdeci">__IO uint32_t CLAIMCLR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:941</div></div>
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<div class="ttc" id="struct_i_t_m___type_html_abea77b06775d325e5f6f46203f582433"><div class="ttname"><a href="struct_i_t_m___type.html#abea77b06775d325e5f6f46203f582433">ITM_Type::u8</a></div><div class="ttdeci">__O uint8_t u8</div><div class="ttdef"><b>Definition:</b> core_cm4.h:677</div></div>
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<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_ga3ecf446519da33e1690deffbf5be505f"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga3ecf446519da33e1690deffbf5be505f">NVIC_SetPendingIRQ</a></div><div class="ttdeci">__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Set Pending Interrupt. </div><div class="ttdef"><b>Definition:</b> core_cm4.h:1508</div></div>
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<div class="ttc" id="struct_s_c_b___type_html_af460b56ce524a8e3534173f0aee78e85"><div class="ttname"><a href="struct_s_c_b___type.html#af460b56ce524a8e3534173f0aee78e85">SCB_Type::CPACR</a></div><div class="ttdeci">__IO uint32_t CPACR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:390</div></div>
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<div class="ttc" id="struct_s_c_b___type_html_a2f94bf549b16fdeb172352e22309e3c4"><div class="ttname"><a href="struct_s_c_b___type.html#a2f94bf549b16fdeb172352e22309e3c4">SCB_Type::CFSR</a></div><div class="ttdeci">__IO uint32_t CFSR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:378</div></div>
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<div class="ttc" id="struct_t_p_i___type_html_a377b78fe804f327e6f8b3d0f37e7bfef"><div class="ttname"><a href="struct_t_p_i___type.html#a377b78fe804f327e6f8b3d0f37e7bfef">TPI_Type::FSCR</a></div><div class="ttdeci">__I uint32_t FSCR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:930</div></div>
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<div class="ttc" id="struct_i_t_m___type_html_a212a614a8d5f2595e5eb049e5143c739"><div class="ttname"><a href="struct_i_t_m___type.html#a212a614a8d5f2595e5eb049e5143c739">ITM_Type::IRR</a></div><div class="ttdeci">__I uint32_t IRR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:689</div></div>
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<div class="ttc" id="struct_t_p_i___type_html_a4b2e0d680cf7e26728ca8966363a938d"><div class="ttname"><a href="struct_t_p_i___type.html#a4b2e0d680cf7e26728ca8966363a938d">TPI_Type::DEVID</a></div><div class="ttdeci">__I uint32_t DEVID</div><div class="ttdef"><b>Definition:</b> core_cm4.h:943</div></div>
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<div class="ttc" id="struct_i_t_m___type_html_a413f3bb0a15222e5f38fca4baeef14f6"><div class="ttname"><a href="struct_i_t_m___type.html#a413f3bb0a15222e5f38fca4baeef14f6">ITM_Type::CID0</a></div><div class="ttdeci">__I uint32_t CID0</div><div class="ttdef"><b>Definition:</b> core_cm4.h:703</div></div>
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<div class="ttc" id="struct_i_t_m___type_html_accfc7de00b0eaba0301e8f4553f70512"><div class="ttname"><a href="struct_i_t_m___type.html#accfc7de00b0eaba0301e8f4553f70512">ITM_Type::PID4</a></div><div class="ttdeci">__I uint32_t PID4</div><div class="ttdef"><b>Definition:</b> core_cm4.h:695</div></div>
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<div class="ttc" id="struct_t_p_i___type_html_ae91ff529e87d8e234343ed31bcdc4f10"><div class="ttname"><a href="struct_t_p_i___type.html#ae91ff529e87d8e234343ed31bcdc4f10">TPI_Type::FIFO0</a></div><div class="ttdeci">__I uint32_t FIFO0</div><div class="ttdef"><b>Definition:</b> core_cm4.h:933</div></div>
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<div class="ttc" id="core__cm4_8h_html_af63697ed9952cc71e1225efe205f6cd3"><div class="ttname"><a href="core__cm4_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a></div><div class="ttdeci">#define __I</div><div class="ttdef"><b>Definition:</b> core_cm4.h:219</div></div>
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<div class="ttc" id="struct_s_c_b___type_html_ad7d61d9525fa9162579c3da0b87bff8d"><div class="ttname"><a href="struct_s_c_b___type.html#ad7d61d9525fa9162579c3da0b87bff8d">SCB_Type::DFSR</a></div><div class="ttdeci">__IO uint32_t DFSR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:380</div></div>
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<div class="ttc" id="struct_s_c_b___type_html_ac49b24b3f222508464f111772f2c44dd"><div class="ttname"><a href="struct_s_c_b___type.html#ac49b24b3f222508464f111772f2c44dd">SCB_Type::MMFAR</a></div><div class="ttdeci">__IO uint32_t MMFAR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:381</div></div>
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<div class="ttc" id="struct_i_t_m___type_html_a91a040e1b162e1128ac1e852b4a0e589"><div class="ttname"><a href="struct_i_t_m___type.html#a91a040e1b162e1128ac1e852b4a0e589">ITM_Type::TER</a></div><div class="ttdeci">__IO uint32_t TER</div><div class="ttdef"><b>Definition:</b> core_cm4.h:682</div></div>
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<div class="ttc" id="struct_s_c_b___type_html_afa7a9ee34dfa1da0b60b4525da285032"><div class="ttname"><a href="struct_s_c_b___type.html#afa7a9ee34dfa1da0b60b4525da285032">SCB_Type::CPUID</a></div><div class="ttdeci">__I uint32_t CPUID</div><div class="ttdef"><b>Definition:</b> core_cm4.h:370</div></div>
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<div class="ttc" id="struct_s_c_b___type_html_a31f79afe86c949c9862e7d5fce077c3a"><div class="ttname"><a href="struct_s_c_b___type.html#a31f79afe86c949c9862e7d5fce077c3a">SCB_Type::BFAR</a></div><div class="ttdeci">__IO uint32_t BFAR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:382</div></div>
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<div class="ttc" id="struct_d_w_t___type_html_a4a5bb70a5ce3752bd628d5ce5658cb0c"><div class="ttname"><a href="struct_d_w_t___type.html#a4a5bb70a5ce3752bd628d5ce5658cb0c">DWT_Type::COMP1</a></div><div class="ttdeci">__IO uint32_t COMP1</div><div class="ttdef"><b>Definition:</b> core_cm4.h:788</div></div>
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<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_ga394f7ce2ca826c0da26284d17ac6524d"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga394f7ce2ca826c0da26284d17ac6524d">NVIC_GetPriorityGrouping</a></div><div class="ttdeci">__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)</div><div class="ttdoc">Get Priority Grouping. </div><div class="ttdef"><b>Definition:</b> core_cm4.h:1455</div></div>
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<div class="ttc" id="group___c_m_s_i_s___s_c_b_html_ga90c7cf0c490e7ae55f9503a7fda1dd22"><div class="ttname"><a href="group___c_m_s_i_s___s_c_b.html#ga90c7cf0c490e7ae55f9503a7fda1dd22">SCB_AIRCR_VECTKEY_Msk</a></div><div class="ttdeci">#define SCB_AIRCR_VECTKEY_Msk</div><div class="ttdef"><b>Definition:</b> core_cm4.h:446</div></div>
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<div class="ttc" id="struct_d_w_t___type_html_a7cf71ff4b30a8362690fddd520763904"><div class="ttname"><a href="struct_d_w_t___type.html#a7cf71ff4b30a8362690fddd520763904">DWT_Type::COMP0</a></div><div class="ttdeci">__IO uint32_t COMP0</div><div class="ttdef"><b>Definition:</b> core_cm4.h:784</div></div>
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<div class="ttc" id="struct_d_w_t___type_html_a8927aedbe9fd6bdae8983088efc83332"><div class="ttname"><a href="struct_d_w_t___type.html#a8927aedbe9fd6bdae8983088efc83332">DWT_Type::COMP2</a></div><div class="ttdeci">__IO uint32_t COMP2</div><div class="ttdef"><b>Definition:</b> core_cm4.h:792</div></div>
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<div class="ttc" id="struct_i_t_m___type_html_adee4ccce1429db8b5db3809c4539f876"><div class="ttname"><a href="struct_i_t_m___type.html#adee4ccce1429db8b5db3809c4539f876">ITM_Type::CID2</a></div><div class="ttdeci">__I uint32_t CID2</div><div class="ttdef"><b>Definition:</b> core_cm4.h:705</div></div>
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<div class="ttc" id="struct_s_c_b___type_html_a7bed53391da4f66d8a2a236a839d4c3d"><div class="ttname"><a href="struct_s_c_b___type.html#a7bed53391da4f66d8a2a236a839d4c3d">SCB_Type::HFSR</a></div><div class="ttdeci">__IO uint32_t HFSR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:379</div></div>
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<div class="ttc" id="group___c_m_s_i_s__core__base_html_gacd96c53beeaff8f603fcda425eb295de"><div class="ttname"><a href="group___c_m_s_i_s__core__base.html#gacd96c53beeaff8f603fcda425eb295de">SysTick</a></div><div class="ttdeci">#define SysTick</div><div class="ttdef"><b>Definition:</b> core_cm4.h:1384</div></div>
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<div class="ttc" id="group___c_m_s_i_s__core___debug_functions_html_gaa822cb398ee022b59e9e6c5d7bbb228a"><div class="ttname"><a href="group___c_m_s_i_s__core___debug_functions.html#gaa822cb398ee022b59e9e6c5d7bbb228a">ITM_RXBUFFER_EMPTY</a></div><div class="ttdeci">#define ITM_RXBUFFER_EMPTY</div><div class="ttdef"><b>Definition:</b> core_cm4.h:1704</div></div>
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<div class="ttc" id="struct_t_p_i___type_html_a3eb42d69922e340037692424a69da880"><div class="ttname"><a href="struct_t_p_i___type.html#a3eb42d69922e340037692424a69da880">TPI_Type::FFCR</a></div><div class="ttdeci">__IO uint32_t FFCR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:929</div></div>
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<div class="ttc" id="struct_i_t_m___type_html_a0e7aa199619cc7ac6baddff9600aa52e"><div class="ttname"><a href="struct_i_t_m___type.html#a0e7aa199619cc7ac6baddff9600aa52e">ITM_Type::CID3</a></div><div class="ttdeci">__I uint32_t CID3</div><div class="ttdef"><b>Definition:</b> core_cm4.h:706</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_ga666eb0caeb12ec0e281415592ae89083"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#ga666eb0caeb12ec0e281415592ae89083">IRQn</a></div><div class="ttdeci">IRQn</div><div class="ttdoc">STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...</div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:174</div></div>
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<div class="ttc" id="core__cm4_8h_html_aec43007d9998a0a0e01faede4133d6be"><div class="ttname"><a href="core__cm4_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a></div><div class="ttdeci">#define __IO</div><div class="ttdef"><b>Definition:</b> core_cm4.h:222</div></div>
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<div class="ttc" id="struct_d_w_t___type_html_aeba92e6c7fd3de4ba06bfd94f47f5b35"><div class="ttname"><a href="struct_d_w_t___type.html#aeba92e6c7fd3de4ba06bfd94f47f5b35">DWT_Type::LSUCNT</a></div><div class="ttdeci">__IO uint32_t LSUCNT</div><div class="ttdef"><b>Definition:</b> core_cm4.h:781</div></div>
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<div class="ttc" id="struct_t_p_i___type_html_ad75832a669eb121f6fce3c28d36b7fab"><div class="ttname"><a href="struct_t_p_i___type.html#ad75832a669eb121f6fce3c28d36b7fab">TPI_Type::ACPR</a></div><div class="ttdeci">__IO uint32_t ACPR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:924</div></div>
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<div class="ttc" id="struct_i_t_m___type_html_a58f169e1aa40a9b8afb6296677c3bb45"><div class="ttname"><a href="struct_i_t_m___type.html#a58f169e1aa40a9b8afb6296677c3bb45">ITM_Type::TCR</a></div><div class="ttdeci">__IO uint32_t TCR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:686</div></div>
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<div class="ttc" id="struct_s_c_b___type_html_ae9891a59abbe51b0b2067ca507ca212f"><div class="ttname"><a href="struct_s_c_b___type.html#ae9891a59abbe51b0b2067ca507ca212f">SCB_Type::SHCSR</a></div><div class="ttdeci">__IO uint32_t SHCSR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:377</div></div>
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<div class="ttc" id="struct_t_p_i___type_html_a2e4d5a07fabd771fa942a171230a0a84"><div class="ttname"><a href="struct_t_p_i___type.html#a2e4d5a07fabd771fa942a171230a0a84">TPI_Type::CLAIMSET</a></div><div class="ttdeci">__IO uint32_t CLAIMSET</div><div class="ttdef"><b>Definition:</b> core_cm4.h:940</div></div>
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<div class="ttc" id="core__cm4_8h_html_a7e25d9380f9ef903923964322e71f2f6"><div class="ttname"><a href="core__cm4_8h.html#a7e25d9380f9ef903923964322e71f2f6">__O</a></div><div class="ttdeci">#define __O</div><div class="ttdef"><b>Definition:</b> core_cm4.h:221</div></div>
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<div class="ttc" id="group___c_m_s_i_s__core___debug_functions_html_ga12e68e55a7badc271b948d6c7230b2a8"><div class="ttname"><a href="group___c_m_s_i_s__core___debug_functions.html#ga12e68e55a7badc271b948d6c7230b2a8">ITM_RxBuffer</a></div><div class="ttdeci">volatile int32_t ITM_RxBuffer</div></div>
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<div class="ttc" id="group___c_m_s_i_s__core___debug_functions_html_gac3ee2c30a1ac4ed34c8a866a17decd53"><div class="ttname"><a href="group___c_m_s_i_s__core___debug_functions.html#gac3ee2c30a1ac4ed34c8a866a17decd53">ITM_ReceiveChar</a></div><div class="ttdeci">__STATIC_INLINE int32_t ITM_ReceiveChar(void)</div><div class="ttdoc">ITM Receive Character. </div><div class="ttdef"><b>Definition:</b> core_cm4.h:1736</div></div>
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<div class="ttc" id="struct_i_t_m___type_html_a12aa4eb4d9dcb589a5d953c836f4e8f4"><div class="ttname"><a href="struct_i_t_m___type.html#a12aa4eb4d9dcb589a5d953c836f4e8f4">ITM_Type::u16</a></div><div class="ttdeci">__O uint16_t u16</div><div class="ttdef"><b>Definition:</b> core_cm4.h:678</div></div>
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<div class="ttc" id="struct_i_t_m___type_html_a6882fa5af67ef5c5dfb433b3b68939df"><div class="ttname"><a href="struct_i_t_m___type.html#a6882fa5af67ef5c5dfb433b3b68939df">ITM_Type::u32</a></div><div class="ttdeci">__O uint32_t u32</div><div class="ttdef"><b>Definition:</b> core_cm4.h:679</div></div>
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<div class="ttc" id="struct_d_w_t___type_html_a5bb1c17fc754180cc197b874d3d8673f"><div class="ttname"><a href="struct_d_w_t___type.html#a5bb1c17fc754180cc197b874d3d8673f">DWT_Type::MASK0</a></div><div class="ttdeci">__IO uint32_t MASK0</div><div class="ttdef"><b>Definition:</b> core_cm4.h:785</div></div>
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<div class="ttc" id="struct_d_w_t___type_html_a80bd242fc05ca80f9db681ce4d82e890"><div class="ttname"><a href="struct_d_w_t___type.html#a80bd242fc05ca80f9db681ce4d82e890">DWT_Type::FUNCTION3</a></div><div class="ttdeci">__IO uint32_t FUNCTION3</div><div class="ttdef"><b>Definition:</b> core_cm4.h:798</div></div>
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<div class="ttc" id="union_i_p_s_r___type_html"><div class="ttname"><a href="union_i_p_s_r___type.html">IPSR_Type</a></div><div class="ttdoc">Union type to access the Interrupt Program Status Register (IPSR). </div><div class="ttdef"><b>Definition:</b> core_cm4.h:274</div></div>
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<div class="ttc" id="struct_i_t_m___type_html_ab69ade751350a7758affdfe396517535"><div class="ttname"><a href="struct_i_t_m___type.html#ab69ade751350a7758affdfe396517535">ITM_Type::PID0</a></div><div class="ttdeci">__I uint32_t PID0</div><div class="ttdef"><b>Definition:</b> core_cm4.h:699</div></div>
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<div class="ttc" id="union_c_o_n_t_r_o_l___type_html_a6b642cca3d96da660b1198c133ca2a1f"><div class="ttname"><a href="union_c_o_n_t_r_o_l___type.html#a6b642cca3d96da660b1198c133ca2a1f">CONTROL_Type::w</a></div><div class="ttdeci">uint32_t w</div><div class="ttdef"><b>Definition:</b> core_cm4.h:322</div></div>
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<div class="ttc" id="struct_t_p_i___type_html"><div class="ttname"><a href="struct_t_p_i___type.html">TPI_Type</a></div><div class="ttdoc">Structure type to access the Trace Port Interface Register (TPI). </div><div class="ttdef"><b>Definition:</b> core_cm4.h:919</div></div>
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<div class="ttc" id="struct_s_cn_s_c_b___type_html_ad99a25f5d4c163d9005ca607c24f6a98"><div class="ttname"><a href="struct_s_cn_s_c_b___type.html#ad99a25f5d4c163d9005ca607c24f6a98">SCnSCB_Type::ICTR</a></div><div class="ttdeci">__I uint32_t ICTR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:588</div></div>
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<div class="ttc" id="struct_t_p_i___type_html_a3eb655f2e45d7af358775025c1a50c8e"><div class="ttname"><a href="struct_t_p_i___type.html#a3eb655f2e45d7af358775025c1a50c8e">TPI_Type::SPPR</a></div><div class="ttdeci">__IO uint32_t SPPR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:926</div></div>
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<div class="ttc" id="struct_t_p_i___type_html_ae67849b2c1016fe6ef9095827d16cddd"><div class="ttname"><a href="struct_t_p_i___type.html#ae67849b2c1016fe6ef9095827d16cddd">TPI_Type::FFSR</a></div><div class="ttdeci">__I uint32_t FFSR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:928</div></div>
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<div class="ttc" id="group___c_m_s_i_s__core___debug_functions_html_gae61ce9ca5917735325cd93b0fb21dd29"><div class="ttname"><a href="group___c_m_s_i_s__core___debug_functions.html#gae61ce9ca5917735325cd93b0fb21dd29">ITM_CheckChar</a></div><div class="ttdeci">__STATIC_INLINE int32_t ITM_CheckChar(void)</div><div class="ttdoc">ITM Check Character. </div><div class="ttdef"><b>Definition:</b> core_cm4.h:1755</div></div>
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<div class="ttc" id="struct_d_w_t___type_html_acba1654190641a3617fcc558b5e3f87b"><div class="ttname"><a href="struct_d_w_t___type.html#acba1654190641a3617fcc558b5e3f87b">DWT_Type::FUNCTION2</a></div><div class="ttdeci">__IO uint32_t FUNCTION2</div><div class="ttdef"><b>Definition:</b> core_cm4.h:794</div></div>
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<div class="ttc" id="struct_i_t_m___type_html_a9353055ceb7024e07d59248e54502cb9"><div class="ttname"><a href="struct_i_t_m___type.html#a9353055ceb7024e07d59248e54502cb9">ITM_Type::PID5</a></div><div class="ttdeci">__I uint32_t PID5</div><div class="ttdef"><b>Definition:</b> core_cm4.h:696</div></div>
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<div class="ttc" id="struct_s_c_b___type_html_aeb77053c84f49c261ab5b8374e8958ef"><div class="ttname"><a href="struct_s_c_b___type.html#aeb77053c84f49c261ab5b8374e8958ef">SCB_Type::AFSR</a></div><div class="ttdeci">__IO uint32_t AFSR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:383</div></div>
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<div class="ttc" id="struct_t_p_i___type_html_a158e9d784f6ee6398f4bdcb2e4ca0912"><div class="ttname"><a href="struct_t_p_i___type.html#a158e9d784f6ee6398f4bdcb2e4ca0912">TPI_Type::SSPSR</a></div><div class="ttdeci">__IO uint32_t SSPSR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:921</div></div>
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<div class="ttc" id="struct_i_t_m___type_html_ae139d2e588bb382573ffcce3625a88cd"><div class="ttname"><a href="struct_i_t_m___type.html#ae139d2e588bb382573ffcce3625a88cd">ITM_Type::PID2</a></div><div class="ttdeci">__I uint32_t PID2</div><div class="ttdef"><b>Definition:</b> core_cm4.h:701</div></div>
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<div class="ttc" id="struct_core_debug___type_html_a5cdd51dbe3ebb7041880714430edd52d"><div class="ttname"><a href="struct_core_debug___type.html#a5cdd51dbe3ebb7041880714430edd52d">CoreDebug_Type::DEMCR</a></div><div class="ttdeci">__IO uint32_t DEMCR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:1276</div></div>
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<div class="ttc" id="struct_d_w_t___type_html_ac0801a2328f3431e4706fed91c828f82"><div class="ttname"><a href="struct_d_w_t___type.html#ac0801a2328f3431e4706fed91c828f82">DWT_Type::EXCCNT</a></div><div class="ttdeci">__IO uint32_t EXCCNT</div><div class="ttdef"><b>Definition:</b> core_cm4.h:779</div></div>
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<div class="ttc" id="struct_d_w_t___type_html_a3df15697eec279dbbb4b4e9d9ae8b62f"><div class="ttname"><a href="struct_d_w_t___type.html#a3df15697eec279dbbb4b4e9d9ae8b62f">DWT_Type::COMP3</a></div><div class="ttdeci">__IO uint32_t COMP3</div><div class="ttdef"><b>Definition:</b> core_cm4.h:796</div></div>
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<div class="ttc" id="group___c_m_s_i_s__core__base_html_gac8e97e8ce56ae9f57da1363a937f8a17"><div class="ttname"><a href="group___c_m_s_i_s__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a></div><div class="ttdeci">#define NVIC</div><div class="ttdef"><b>Definition:</b> core_cm4.h:1385</div></div>
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<div class="ttc" id="struct_sys_tick___type_html_ae7bc9d3eac1147f3bba8d73a8395644f"><div class="ttname"><a href="struct_sys_tick___type.html#ae7bc9d3eac1147f3bba8d73a8395644f">SysTick_Type::LOAD</a></div><div class="ttdeci">__IO uint32_t LOAD</div><div class="ttdef"><b>Definition:</b> core_cm4.h:626</div></div>
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<div class="ttc" id="struct_s_c_b___type_html_a0faf96f964931cadfb71cfa54e051f6f"><div class="ttname"><a href="struct_s_c_b___type.html#a0faf96f964931cadfb71cfa54e051f6f">SCB_Type::VTOR</a></div><div class="ttdeci">__IO uint32_t VTOR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:372</div></div>
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<div class="ttc" id="struct_i_t_m___type_html_af006ee26c7e61c9a3712a80ac74a6cf3"><div class="ttname"><a href="struct_i_t_m___type.html#af006ee26c7e61c9a3712a80ac74a6cf3">ITM_Type::PID3</a></div><div class="ttdeci">__I uint32_t PID3</div><div class="ttdef"><b>Definition:</b> core_cm4.h:702</div></div>
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<div class="ttc" id="struct_sys_tick___type_html_af2ad94ac83e5d40fc6e34884bc1bec5f"><div class="ttname"><a href="struct_sys_tick___type.html#af2ad94ac83e5d40fc6e34884bc1bec5f">SysTick_Type::CTRL</a></div><div class="ttdeci">__IO uint32_t CTRL</div><div class="ttdef"><b>Definition:</b> core_cm4.h:625</div></div>
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<div class="ttc" id="unionx_p_s_r___type_html_a1a47176768f45f79076c4f5b1b534bc2"><div class="ttname"><a href="unionx_p_s_r___type.html#a1a47176768f45f79076c4f5b1b534bc2">xPSR_Type::w</a></div><div class="ttdeci">uint32_t w</div><div class="ttdef"><b>Definition:</b> core_cm4.h:307</div></div>
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<div class="ttc" id="struct_t_p_i___type_html_ab49c2cb6b5fe082746a444e07548c198"><div class="ttname"><a href="struct_t_p_i___type.html#ab49c2cb6b5fe082746a444e07548c198">TPI_Type::ITCTRL</a></div><div class="ttdeci">__IO uint32_t ITCTRL</div><div class="ttdef"><b>Definition:</b> core_cm4.h:938</div></div>
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<div class="ttc" id="struct_i_t_m___type_html_afd0e0c051acd3f6187794a4e8dc7e7ea"><div class="ttname"><a href="struct_i_t_m___type.html#afd0e0c051acd3f6187794a4e8dc7e7ea">ITM_Type::IWR</a></div><div class="ttdeci">__O uint32_t IWR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:688</div></div>
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<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_ga3349f2e3580d7ce22d6530b7294e5921"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga3349f2e3580d7ce22d6530b7294e5921">NVIC_EnableIRQ</a></div><div class="ttdeci">__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Enable External Interrupt. </div><div class="ttdef"><b>Definition:</b> core_cm4.h:1467</div></div>
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<div class="ttc" id="struct_d_w_t___type_html_abc5ae11d98da0ad5531a5e979a3c2ab5"><div class="ttname"><a href="struct_d_w_t___type.html#abc5ae11d98da0ad5531a5e979a3c2ab5">DWT_Type::PCSR</a></div><div class="ttdeci">__I uint32_t PCSR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:783</div></div>
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<div class="ttc" id="core__cm4__simd_8h_html"><div class="ttname"><a href="core__cm4__simd_8h.html">core_cm4_simd.h</a></div><div class="ttdoc">CMSIS Cortex-M4 SIMD Header File. </div></div>
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<div class="ttc" id="struct_core_debug___type_html"><div class="ttname"><a href="struct_core_debug___type.html">CoreDebug_Type</a></div><div class="ttdoc">Structure type to access the Core Debug Register (CoreDebug). </div><div class="ttdef"><b>Definition:</b> core_cm4.h:1271</div></div>
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<div class="ttc" id="struct_s_c_b___type_html"><div class="ttname"><a href="struct_s_c_b___type.html">SCB_Type</a></div><div class="ttdoc">Structure type to access the System Control Block (SCB). </div><div class="ttdef"><b>Definition:</b> core_cm4.h:368</div></div>
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<div class="ttc" id="group___c_m_s_i_s___i_t_m_html_ga7dd53e3bff24ac09d94e61cb595cb2d9"><div class="ttname"><a href="group___c_m_s_i_s___i_t_m.html#ga7dd53e3bff24ac09d94e61cb595cb2d9">ITM_TCR_ITMENA_Msk</a></div><div class="ttdeci">#define ITM_TCR_ITMENA_Msk</div><div class="ttdef"><b>Definition:</b> core_cm4.h:739</div></div>
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<div class="ttc" id="struct_s_c_b___type_html_a586a5225467262b378c0f231ccc77f86"><div class="ttname"><a href="struct_s_c_b___type.html#a586a5225467262b378c0f231ccc77f86">SCB_Type::DFR</a></div><div class="ttdeci">__I uint32_t DFR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:385</div></div>
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<div class="ttc" id="group___c_m_s_i_s__core__base_html_gaaaf6477c2bde2f00f99e3c2fd1060b01"><div class="ttname"><a href="group___c_m_s_i_s__core__base.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a></div><div class="ttdeci">#define SCB</div><div class="ttdef"><b>Definition:</b> core_cm4.h:1383</div></div>
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<div class="ttc" id="struct_i_t_m___type_html"><div class="ttname"><a href="struct_i_t_m___type.html">ITM_Type</a></div><div class="ttdoc">Structure type to access the Instrumentation Trace Macrocell Register (ITM). </div><div class="ttdef"><b>Definition:</b> core_cm4.h:673</div></div>
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<div class="ttc" id="union_i_p_s_r___type_html_a4adca999d3a0bc1ae682d73ea7cfa879"><div class="ttname"><a href="union_i_p_s_r___type.html#a4adca999d3a0bc1ae682d73ea7cfa879">IPSR_Type::w</a></div><div class="ttdeci">uint32_t w</div><div class="ttdef"><b>Definition:</b> core_cm4.h:281</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gac3af4a32370fb28c4ade8bf2add80251"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gac3af4a32370fb28c4ade8bf2add80251">IRQn_Type</a></div><div class="ttdeci">enum IRQn IRQn_Type</div><div class="ttdoc">STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...</div></div>
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<div class="ttc" id="struct_core_debug___type_html_afefa84bce7497652353a1b76d405d983"><div class="ttname"><a href="struct_core_debug___type.html#afefa84bce7497652353a1b76d405d983">CoreDebug_Type::DCRSR</a></div><div class="ttdeci">__O uint32_t DCRSR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:1274</div></div>
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<div class="ttc" id="struct_i_t_m___type_html_a97840d39a9c63331e3689b5fa69175e9"><div class="ttname"><a href="struct_i_t_m___type.html#a97840d39a9c63331e3689b5fa69175e9">ITM_Type::LAR</a></div><div class="ttdeci">__O uint32_t LAR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:692</div></div>
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<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_ga77cfbb35a9d8027e392034321bed6904"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga77cfbb35a9d8027e392034321bed6904">NVIC_SetPriorityGrouping</a></div><div class="ttdeci">__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)</div><div class="ttdoc">Set Priority Grouping. </div><div class="ttdef"><b>Definition:</b> core_cm4.h:1435</div></div>
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<div class="ttc" id="group___c_m_s_i_s___core___sys_tick_functions_html_gae4e8f0238527c69f522029b93c8e5b78"><div class="ttname"><a href="group___c_m_s_i_s___core___sys_tick_functions.html#gae4e8f0238527c69f522029b93c8e5b78">SysTick_Config</a></div><div class="ttdeci">__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)</div><div class="ttdoc">System Tick Configuration. </div><div class="ttdef"><b>Definition:</b> core_cm4.h:1677</div></div>
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<div class="ttc" id="struct_i_t_m___type_html_aaa0515b1f6dd5e7d90b61ef67d8de77b"><div class="ttname"><a href="struct_i_t_m___type.html#aaa0515b1f6dd5e7d90b61ef67d8de77b">ITM_Type::LSR</a></div><div class="ttdeci">__I uint32_t LSR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:693</div></div>
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<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_ga1cbaf8e6abd4aa4885828e7f24fcfeb4"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga1cbaf8e6abd4aa4885828e7f24fcfeb4">NVIC_GetPriority</a></div><div class="ttdeci">__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)</div><div class="ttdoc">Get Interrupt Priority. </div><div class="ttdef"><b>Definition:</b> core_cm4.h:1570</div></div>
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<div class="ttc" id="struct_s_c_b___type_html_abfad14e7b4534d73d329819625d77a16"><div class="ttname"><a href="struct_s_c_b___type.html#abfad14e7b4534d73d329819625d77a16">SCB_Type::SCR</a></div><div class="ttdeci">__IO uint32_t SCR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:374</div></div>
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<div class="ttc" id="union_a_p_s_r___type_html_ae4c2ef8c9430d7b7bef5cbfbbaed3a94"><div class="ttname"><a href="union_a_p_s_r___type.html#ae4c2ef8c9430d7b7bef5cbfbbaed3a94">APSR_Type::w</a></div><div class="ttdeci">uint32_t w</div><div class="ttdef"><b>Definition:</b> core_cm4.h:268</div></div>
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<div class="ttc" id="struct_d_w_t___type_html_a3345a33476ee58e165447a3212e6d747"><div class="ttname"><a href="struct_d_w_t___type.html#a3345a33476ee58e165447a3212e6d747">DWT_Type::FUNCTION1</a></div><div class="ttdeci">__IO uint32_t FUNCTION1</div><div class="ttdef"><b>Definition:</b> core_cm4.h:790</div></div>
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<div class="ttc" id="struct_d_w_t___type_html_a71680298e85e96e57002f87e7ab78fd4"><div class="ttname"><a href="struct_d_w_t___type.html#a71680298e85e96e57002f87e7ab78fd4">DWT_Type::CYCCNT</a></div><div class="ttdeci">__IO uint32_t CYCCNT</div><div class="ttdef"><b>Definition:</b> core_cm4.h:777</div></div>
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<div class="ttc" id="group___c_m_s_i_s___s_c_b_html_gaca155deccdeca0f2c76b8100d24196c8"><div class="ttname"><a href="group___c_m_s_i_s___s_c_b.html#gaca155deccdeca0f2c76b8100d24196c8">SCB_AIRCR_PRIGROUP_Pos</a></div><div class="ttdeci">#define SCB_AIRCR_PRIGROUP_Pos</div><div class="ttdef"><b>Definition:</b> core_cm4.h:454</div></div>
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<div class="ttc" id="struct_sys_tick___type_html_a9c9eda0ea6f6a7c904d2d75a6963e238"><div class="ttname"><a href="struct_sys_tick___type.html#a9c9eda0ea6f6a7c904d2d75a6963e238">SysTick_Type::CALIB</a></div><div class="ttdeci">__I uint32_t CALIB</div><div class="ttdef"><b>Definition:</b> core_cm4.h:628</div></div>
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<div class="ttc" id="struct_s_cn_s_c_b___type_html"><div class="ttname"><a href="struct_s_cn_s_c_b___type.html">SCnSCB_Type</a></div><div class="ttdoc">Structure type to access the System Control and ID Register not in the SCB. </div><div class="ttdef"><b>Definition:</b> core_cm4.h:585</div></div>
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<div class="ttc" id="struct_i_t_m___type_html_a5f7d524b71f49e444ff0d1d52b3c3565"><div class="ttname"><a href="struct_i_t_m___type.html#a5f7d524b71f49e444ff0d1d52b3c3565">ITM_Type::CID1</a></div><div class="ttdeci">__I uint32_t CID1</div><div class="ttdef"><b>Definition:</b> core_cm4.h:704</div></div>
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<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_ga2305cbd44aaad792e3a4e538bdaf14f9"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga2305cbd44aaad792e3a4e538bdaf14f9">NVIC_SetPriority</a></div><div class="ttdeci">__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)</div><div class="ttdoc">Set Interrupt Priority. </div><div class="ttdef"><b>Definition:</b> core_cm4.h:1550</div></div>
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<div class="ttc" id="struct_n_v_i_c___type_html"><div class="ttname"><a href="struct_n_v_i_c___type.html">NVIC_Type</a></div><div class="ttdoc">Structure type to access the Nested Vectored Interrupt Controller (NVIC). </div><div class="ttdef"><b>Definition:</b> core_cm4.h:336</div></div>
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<div class="ttc" id="struct_sys_tick___type_html"><div class="ttname"><a href="struct_sys_tick___type.html">SysTick_Type</a></div><div class="ttdoc">Structure type to access the System Timer (SysTick). </div><div class="ttdef"><b>Definition:</b> core_cm4.h:623</div></div>
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<div class="ttc" id="struct_i_t_m___type_html_a30e87ec6f93ecc9fe4f135ca8b068990"><div class="ttname"><a href="struct_i_t_m___type.html#a30e87ec6f93ecc9fe4f135ca8b068990">ITM_Type::PID1</a></div><div class="ttdeci">__I uint32_t PID1</div><div class="ttdef"><b>Definition:</b> core_cm4.h:700</div></div>
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<div class="ttc" id="group___c_m_s_i_s___s_c_b_html_gaaa27c0ba600bf82c3da08c748845b640"><div class="ttname"><a href="group___c_m_s_i_s___s_c_b.html#gaaa27c0ba600bf82c3da08c748845b640">SCB_AIRCR_VECTKEY_Pos</a></div><div class="ttdeci">#define SCB_AIRCR_VECTKEY_Pos</div><div class="ttdef"><b>Definition:</b> core_cm4.h:445</div></div>
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<div class="ttc" id="struct_t_p_i___type_html_aa4b603c71768dbda553da571eccba1fe"><div class="ttname"><a href="struct_t_p_i___type.html#aa4b603c71768dbda553da571eccba1fe">TPI_Type::TRIGGER</a></div><div class="ttdeci">__I uint32_t TRIGGER</div><div class="ttdef"><b>Definition:</b> core_cm4.h:932</div></div>
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<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_ga1143dec48d60a3d6f238c4798a87759c"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga1143dec48d60a3d6f238c4798a87759c">NVIC_SystemReset</a></div><div class="ttdeci">__STATIC_INLINE void NVIC_SystemReset(void)</div><div class="ttdoc">System Reset. </div><div class="ttdef"><b>Definition:</b> core_cm4.h:1638</div></div>
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<div class="ttc" id="struct_s_c_b___type_html_a6ed3c9064013343ea9fd0a73a734f29d"><div class="ttname"><a href="struct_s_c_b___type.html#a6ed3c9064013343ea9fd0a73a734f29d">SCB_Type::AIRCR</a></div><div class="ttdeci">__IO uint32_t AIRCR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:373</div></div>
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<div class="ttc" id="struct_core_debug___type_html_ab8f4bb076402b61f7be6308075a789c9"><div class="ttname"><a href="struct_core_debug___type.html#ab8f4bb076402b61f7be6308075a789c9">CoreDebug_Type::DCRDR</a></div><div class="ttdeci">__IO uint32_t DCRDR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:1275</div></div>
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<div class="ttc" id="struct_t_p_i___type_html_a16d12c5b1e12f764fa3ec4a51c5f0f35"><div class="ttname"><a href="struct_t_p_i___type.html#a16d12c5b1e12f764fa3ec4a51c5f0f35">TPI_Type::DEVTYPE</a></div><div class="ttdeci">__I uint32_t DEVTYPE</div><div class="ttdef"><b>Definition:</b> core_cm4.h:944</div></div>
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<div class="ttc" id="struct_n_v_i_c___type_html_a0b0d7f3131da89c659a2580249432749"><div class="ttname"><a href="struct_n_v_i_c___type.html#a0b0d7f3131da89c659a2580249432749">NVIC_Type::STIR</a></div><div class="ttdeci">__O uint32_t STIR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:350</div></div>
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<div class="ttc" id="group___c_m_s_i_s___s_c_b_html_gaae1181119559a5bd36e62afa373fa720"><div class="ttname"><a href="group___c_m_s_i_s___s_c_b.html#gaae1181119559a5bd36e62afa373fa720">SCB_AIRCR_SYSRESETREQ_Msk</a></div><div class="ttdeci">#define SCB_AIRCR_SYSRESETREQ_Msk</div><div class="ttdef"><b>Definition:</b> core_cm4.h:458</div></div>
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<div class="ttc" id="union_a_p_s_r___type_html"><div class="ttname"><a href="union_a_p_s_r___type.html">APSR_Type</a></div><div class="ttdoc">Union type to access the Application Program Status Register (APSR). </div><div class="ttdef"><b>Definition:</b> core_cm4.h:251</div></div>
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<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_ga4f23ef94633f75d3c97670a53949003c"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga4f23ef94633f75d3c97670a53949003c">NVIC_DecodePriority</a></div><div class="ttdeci">__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)</div><div class="ttdoc">Decode Priority. </div><div class="ttdef"><b>Definition:</b> core_cm4.h:1620</div></div>
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<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_ga260fba04ac8346855c57f091d4ee1e71"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga260fba04ac8346855c57f091d4ee1e71">NVIC_DisableIRQ</a></div><div class="ttdeci">__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Disable External Interrupt. </div><div class="ttdef"><b>Definition:</b> core_cm4.h:1480</div></div>
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<div class="ttc" id="group___c_m_s_i_s___sys_tick_html_ga265912a7962f0e1abd170336e579b1b1"><div class="ttname"><a href="group___c_m_s_i_s___sys_tick.html#ga265912a7962f0e1abd170336e579b1b1">SysTick_LOAD_RELOAD_Msk</a></div><div class="ttdeci">#define SysTick_LOAD_RELOAD_Msk</div><div class="ttdef"><b>Definition:</b> core_cm4.h:646</div></div>
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<div class="ttc" id="struct_d_w_t___type_html_ae3f01137a8d28c905ddefe7333547fba"><div class="ttname"><a href="struct_d_w_t___type.html#ae3f01137a8d28c905ddefe7333547fba">DWT_Type::MASK3</a></div><div class="ttdeci">__IO uint32_t MASK3</div><div class="ttdef"><b>Definition:</b> core_cm4.h:797</div></div>
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<div class="ttc" id="struct_d_w_t___type_html_a8ecdc8f0d917dac86b0373532a1c0e2e"><div class="ttname"><a href="struct_d_w_t___type.html#a8ecdc8f0d917dac86b0373532a1c0e2e">DWT_Type::MASK2</a></div><div class="ttdeci">__IO uint32_t MASK2</div><div class="ttdef"><b>Definition:</b> core_cm4.h:793</div></div>
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<div class="ttc" id="struct_t_p_i___type_html_a20ca7fad4d4009c242f20a7b4a44b7d0"><div class="ttname"><a href="struct_t_p_i___type.html#a20ca7fad4d4009c242f20a7b4a44b7d0">TPI_Type::ITATBCTR0</a></div><div class="ttdeci">__I uint32_t ITATBCTR0</div><div class="ttdef"><b>Definition:</b> core_cm4.h:936</div></div>
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<div class="ttc" id="struct_t_p_i___type_html_aebaa9b8dd27f8017dd4f92ecf32bac8e"><div class="ttname"><a href="struct_t_p_i___type.html#aebaa9b8dd27f8017dd4f92ecf32bac8e">TPI_Type::FIFO1</a></div><div class="ttdeci">__I uint32_t FIFO1</div><div class="ttdef"><b>Definition:</b> core_cm4.h:937</div></div>
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<div class="ttc" id="struct_s_cn_s_c_b___type_html_aacadedade30422fed705e8dfc8e6cd8d"><div class="ttname"><a href="struct_s_cn_s_c_b___type.html#aacadedade30422fed705e8dfc8e6cd8d">SCnSCB_Type::ACTLR</a></div><div class="ttdeci">__IO uint32_t ACTLR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:589</div></div>
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<div class="ttc" id="struct_d_w_t___type_html_a37964d64a58551b69ce4c8097210d37d"><div class="ttname"><a href="struct_d_w_t___type.html#a37964d64a58551b69ce4c8097210d37d">DWT_Type::CTRL</a></div><div class="ttdeci">__IO uint32_t CTRL</div><div class="ttdef"><b>Definition:</b> core_cm4.h:776</div></div>
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<div class="ttc" id="union_c_o_n_t_r_o_l___type_html"><div class="ttname"><a href="union_c_o_n_t_r_o_l___type.html">CONTROL_Type</a></div><div class="ttdoc">Union type to access the Control Registers (CONTROL). </div><div class="ttdef"><b>Definition:</b> core_cm4.h:313</div></div>
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<div class="ttc" id="group___c_m_s_i_s___sys_tick_html_gaa41d06039797423a46596bd313d57373"><div class="ttname"><a href="group___c_m_s_i_s___sys_tick.html#gaa41d06039797423a46596bd313d57373">SysTick_CTRL_CLKSOURCE_Msk</a></div><div class="ttdeci">#define SysTick_CTRL_CLKSOURCE_Msk</div><div class="ttdef"><b>Definition:</b> core_cm4.h:636</div></div>
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<div class="ttc" id="group___c_m_s_i_s___sys_tick_html_ga16c9fee0ed0235524bdeb38af328fd1f"><div class="ttname"><a href="group___c_m_s_i_s___sys_tick.html#ga16c9fee0ed0235524bdeb38af328fd1f">SysTick_CTRL_ENABLE_Msk</a></div><div class="ttdeci">#define SysTick_CTRL_ENABLE_Msk</div><div class="ttdef"><b>Definition:</b> core_cm4.h:642</div></div>
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<div class="ttc" id="struct_d_w_t___type_html_a0c684438a24f8c927e6e01c0e0a605ef"><div class="ttname"><a href="struct_d_w_t___type.html#a0c684438a24f8c927e6e01c0e0a605ef">DWT_Type::MASK1</a></div><div class="ttdeci">__IO uint32_t MASK1</div><div class="ttdef"><b>Definition:</b> core_cm4.h:789</div></div>
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<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_ga332e10ef9605dc6eb10b9e14511930f8"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga332e10ef9605dc6eb10b9e14511930f8">NVIC_ClearPendingIRQ</a></div><div class="ttdeci">__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Clear Pending Interrupt. </div><div class="ttdef"><b>Definition:</b> core_cm4.h:1520</div></div>
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<div class="ttc" id="struct_d_w_t___type_html_a35f2315f870a574e3e6958face6584ab"><div class="ttname"><a href="struct_d_w_t___type.html#a35f2315f870a574e3e6958face6584ab">DWT_Type::FOLDCNT</a></div><div class="ttdeci">__IO uint32_t FOLDCNT</div><div class="ttdef"><b>Definition:</b> core_cm4.h:782</div></div>
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<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_gadb94ac5d892b376e4f3555ae0418ebac"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#gadb94ac5d892b376e4f3555ae0418ebac">NVIC_EncodePriority</a></div><div class="ttdeci">__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</div><div class="ttdoc">Encode Priority. </div><div class="ttdef"><b>Definition:</b> core_cm4.h:1592</div></div>
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<div class="ttc" id="struct_s_c_b___type_html_a6d273c6b90bad15c91dfbbad0f6e92d8"><div class="ttname"><a href="struct_s_c_b___type.html#a6d273c6b90bad15c91dfbbad0f6e92d8">SCB_Type::CCR</a></div><div class="ttdeci">__IO uint32_t CCR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:375</div></div>
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<div class="ttc" id="core__cm_instr_8h_html"><div class="ttname"><a href="core__cm_instr_8h.html">core_cmInstr.h</a></div><div class="ttdoc">CMSIS Cortex-M Core Instruction Access Header File. </div></div>
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<div class="ttc" id="struct_core_debug___type_html_a25c14c022c73a725a1736e903431095d"><div class="ttname"><a href="struct_core_debug___type.html#a25c14c022c73a725a1736e903431095d">CoreDebug_Type::DHCSR</a></div><div class="ttdeci">__IO uint32_t DHCSR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:1273</div></div>
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<div class="ttc" id="struct_d_w_t___type_html_a5fbd9947d110cc168941f6acadc4a729"><div class="ttname"><a href="struct_d_w_t___type.html#a5fbd9947d110cc168941f6acadc4a729">DWT_Type::FUNCTION0</a></div><div class="ttdeci">__IO uint32_t FUNCTION0</div><div class="ttdef"><b>Definition:</b> core_cm4.h:786</div></div>
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<div class="ttc" id="struct_t_p_i___type_html_aa723ef3d38237aa2465779b3cc73a94a"><div class="ttname"><a href="struct_t_p_i___type.html#aa723ef3d38237aa2465779b3cc73a94a">TPI_Type::CSPSR</a></div><div class="ttdeci">__IO uint32_t CSPSR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:922</div></div>
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<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_ga47a0f52794068d076c9147aa3cb8d8a6"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga47a0f52794068d076c9147aa3cb8d8a6">NVIC_GetActive</a></div><div class="ttdeci">__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)</div><div class="ttdoc">Get Active Interrupt. </div><div class="ttdef"><b>Definition:</b> core_cm4.h:1535</div></div>
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<div class="ttc" id="struct_d_w_t___type_html_a88cca2ab8eb1b5b507817656ceed89fc"><div class="ttname"><a href="struct_d_w_t___type.html#a88cca2ab8eb1b5b507817656ceed89fc">DWT_Type::CPICNT</a></div><div class="ttdeci">__IO uint32_t CPICNT</div><div class="ttdef"><b>Definition:</b> core_cm4.h:778</div></div>
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<div class="ttc" id="unionx_p_s_r___type_html"><div class="ttname"><a href="unionx_p_s_r___type.html">xPSR_Type</a></div><div class="ttdoc">Union type to access the Special-Purpose Program Status Registers (xPSR). </div><div class="ttdef"><b>Definition:</b> core_cm4.h:287</div></div>
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<div class="ttc" id="struct_i_t_m___type_html_a93b480aac6da620bbb611212186d47fa"><div class="ttname"><a href="struct_i_t_m___type.html#a93b480aac6da620bbb611212186d47fa">ITM_Type::TPR</a></div><div class="ttdeci">__IO uint32_t TPR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:684</div></div>
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<div class="ttc" id="struct_s_c_b___type_html_a3e66570ab689d28aebefa7e84e85dc4a"><div class="ttname"><a href="struct_s_c_b___type.html#a3e66570ab689d28aebefa7e84e85dc4a">SCB_Type::ICSR</a></div><div class="ttdeci">__IO uint32_t ICSR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:371</div></div>
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<div class="ttc" id="struct_i_t_m___type_html_ab2e87d8bb0e3ce9b8e0e4a6a6695228a"><div class="ttname"><a href="struct_i_t_m___type.html#ab2e87d8bb0e3ce9b8e0e4a6a6695228a">ITM_Type::IMCR</a></div><div class="ttdeci">__IO uint32_t IMCR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:690</div></div>
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<div class="ttc" id="struct_i_t_m___type_html_aa31ca6bb4b749201321b23d0dbbe0704"><div class="ttname"><a href="struct_i_t_m___type.html#aa31ca6bb4b749201321b23d0dbbe0704">ITM_Type::PID7</a></div><div class="ttdeci">__I uint32_t PID7</div><div class="ttdef"><b>Definition:</b> core_cm4.h:698</div></div>
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<div class="ttc" id="struct_d_w_t___type_html_a8afd5a4bf994011748bc012fa442c74d"><div class="ttname"><a href="struct_d_w_t___type.html#a8afd5a4bf994011748bc012fa442c74d">DWT_Type::SLEEPCNT</a></div><div class="ttdeci">__IO uint32_t SLEEPCNT</div><div class="ttdef"><b>Definition:</b> core_cm4.h:780</div></div>
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<div class="ttc" id="group___c_m_s_i_s___sys_tick_html_ga95bb984266ca764024836a870238a027"><div class="ttname"><a href="group___c_m_s_i_s___sys_tick.html#ga95bb984266ca764024836a870238a027">SysTick_CTRL_TICKINT_Msk</a></div><div class="ttdeci">#define SysTick_CTRL_TICKINT_Msk</div><div class="ttdef"><b>Definition:</b> core_cm4.h:639</div></div>
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<div class="ttc" id="struct_t_p_i___type_html_a176d991adb4c022bd5b982a9f8fa6a1d"><div class="ttname"><a href="struct_t_p_i___type.html#a176d991adb4c022bd5b982a9f8fa6a1d">TPI_Type::ITATBCTR2</a></div><div class="ttdeci">__I uint32_t ITATBCTR2</div><div class="ttdef"><b>Definition:</b> core_cm4.h:934</div></div>
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<div class="ttc" id="struct_i_t_m___type_html_a755c0ec919e7dbb5f7ff05c8b56a3383"><div class="ttname"><a href="struct_i_t_m___type.html#a755c0ec919e7dbb5f7ff05c8b56a3383">ITM_Type::PID6</a></div><div class="ttdeci">__I uint32_t PID6</div><div class="ttdef"><b>Definition:</b> core_cm4.h:697</div></div>
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<div class="ttc" id="struct_s_c_b___type_html_aaedf846e435ed05c68784b40d3db2bf2"><div class="ttname"><a href="struct_s_c_b___type.html#aaedf846e435ed05c68784b40d3db2bf2">SCB_Type::ADR</a></div><div class="ttdeci">__I uint32_t ADR</div><div class="ttdef"><b>Definition:</b> core_cm4.h:386</div></div>
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<div class="ttc" id="group___configuration__section__for___c_m_s_i_s_html_gga666eb0caeb12ec0e281415592ae89083a6dbff8f8543325f3474cbae2446776e7"><div class="ttname"><a href="group___configuration__section__for___c_m_s_i_s.html#gga666eb0caeb12ec0e281415592ae89083a6dbff8f8543325f3474cbae2446776e7">SysTick_IRQn</a></div><div class="ttdef"><b>Definition:</b> stm32f4xx.h:184</div></div>
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