415 lines
64 KiB
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415 lines
64 KiB
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<div class="title">stm32f4xx_rcc.c File Reference</div> </div>
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<p>This file provides firmware functions to manage the following functionalities of the Reset and clock control (RCC) peripheral:
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<a href="#details">More...</a></p>
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<div class="textblock"><code>#include "<a class="el" href="stm32f4xx__rcc_8h_source.html">stm32f4xx_rcc.h</a>"</code><br />
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</div><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:ga539e07c3b3c55f1f1d47231341fb11e1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga539e07c3b3c55f1f1d47231341fb11e1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>RCC_OFFSET</b>   (RCC_BASE - <a class="el" href="group___peripheral__memory__map.html#ga9171f49478fa86d932f89e78e73b88b0">PERIPH_BASE</a>)</td></tr>
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<tr class="separator:ga539e07c3b3c55f1f1d47231341fb11e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa1d3d0ea72132df651c76fc1bdffffc"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafa1d3d0ea72132df651c76fc1bdffffc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CR_OFFSET</b>   (RCC_OFFSET + 0x00)</td></tr>
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<tr class="separator:gafa1d3d0ea72132df651c76fc1bdffffc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3d3085e491cbef815d223afbe5bf1930"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3d3085e491cbef815d223afbe5bf1930"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>HSION_BitNumber</b>   0x00</td></tr>
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<tr class="separator:ga3d3085e491cbef815d223afbe5bf1930"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac3290a833c0e35ec17d32c2d494e6133"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac3290a833c0e35ec17d32c2d494e6133"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CR_HSION_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (CR_OFFSET * 32) + (HSION_BitNumber * 4))</td></tr>
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<tr class="separator:gac3290a833c0e35ec17d32c2d494e6133"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga253fa44d87aabc55f0cd6628e77a51fd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga253fa44d87aabc55f0cd6628e77a51fd"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CSSON_BitNumber</b>   0x13</td></tr>
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<tr class="separator:ga253fa44d87aabc55f0cd6628e77a51fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaca914aed10477ae4090fea0a9639b1ea"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaca914aed10477ae4090fea0a9639b1ea"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CR_CSSON_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))</td></tr>
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<tr class="separator:gaca914aed10477ae4090fea0a9639b1ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab24d7f5f8e4b3b717fd91b54f393f6a3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab24d7f5f8e4b3b717fd91b54f393f6a3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PLLON_BitNumber</b>   0x18</td></tr>
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<tr class="separator:gab24d7f5f8e4b3b717fd91b54f393f6a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f1fb2589cb8b5ac2f7121aba1135a5f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3f1fb2589cb8b5ac2f7121aba1135a5f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CR_PLLON_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))</td></tr>
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<tr class="separator:ga3f1fb2589cb8b5ac2f7121aba1135a5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabae59c3e4200523e3aa5b6e10aee8c46"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabae59c3e4200523e3aa5b6e10aee8c46"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PLLI2SON_BitNumber</b>   0x1A</td></tr>
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<tr class="separator:gabae59c3e4200523e3aa5b6e10aee8c46"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c0fb27aba4eb660f7590252596bdfc5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0c0fb27aba4eb660f7590252596bdfc5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CR_PLLI2SON_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))</td></tr>
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<tr class="separator:ga0c0fb27aba4eb660f7590252596bdfc5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga786a15b370532d6429e03a9f9d226be7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga786a15b370532d6429e03a9f9d226be7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PLLSAION_BitNumber</b>   0x1C</td></tr>
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<tr class="separator:ga786a15b370532d6429e03a9f9d226be7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab84e7d3874237ee56e5cb3a26644cd13"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab84e7d3874237ee56e5cb3a26644cd13"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CR_PLLSAION_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))</td></tr>
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<tr class="separator:gab84e7d3874237ee56e5cb3a26644cd13"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8682298330c3b9bae1992e4f1a0af985"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8682298330c3b9bae1992e4f1a0af985"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CFGR_OFFSET</b>   (RCC_OFFSET + 0x08)</td></tr>
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<tr class="separator:ga8682298330c3b9bae1992e4f1a0af985"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9561d436b438d8f513b754f1934c3e30"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9561d436b438d8f513b754f1934c3e30"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>I2SSRC_BitNumber</b>   0x17</td></tr>
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<tr class="separator:ga9561d436b438d8f513b754f1934c3e30"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9076f5ddbb262fd45584702f5d280c9e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9076f5ddbb262fd45584702f5d280c9e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CFGR_I2SSRC_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))</td></tr>
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<tr class="separator:ga9076f5ddbb262fd45584702f5d280c9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5f8a0c3cb5f5c835bf7eef09515138ad"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga5f8a0c3cb5f5c835bf7eef09515138ad"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>BDCR_OFFSET</b>   (RCC_OFFSET + 0x70)</td></tr>
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<tr class="separator:ga5f8a0c3cb5f5c835bf7eef09515138ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9302c551752124766afc4cee65436405"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9302c551752124766afc4cee65436405"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>RTCEN_BitNumber</b>   0x0F</td></tr>
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<tr class="separator:ga9302c551752124766afc4cee65436405"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf70aaf70b0752ccb3a60307b2fb46038"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf70aaf70b0752ccb3a60307b2fb46038"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>BDCR_RTCEN_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))</td></tr>
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<tr class="memitem:gae6718158034388d8fde8caaa28ffe8b9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae6718158034388d8fde8caaa28ffe8b9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>BDRST_BitNumber</b>   0x10</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>BDCR_BDRST_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))</td></tr>
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<tr class="memitem:ga984cbe73312b6d3d355c5053763d499a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga984cbe73312b6d3d355c5053763d499a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CSR_OFFSET</b>   (RCC_OFFSET + 0x74)</td></tr>
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<tr class="memitem:ga3f9dbe50769ce2a63ae12520433b9b40"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3f9dbe50769ce2a63ae12520433b9b40"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>LSION_BitNumber</b>   0x00</td></tr>
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<tr class="separator:ga3f9dbe50769ce2a63ae12520433b9b40"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa253e36e7e5fb02998c0e4d0388abc52"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa253e36e7e5fb02998c0e4d0388abc52"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CSR_LSION_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))</td></tr>
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<tr class="separator:gaa253e36e7e5fb02998c0e4d0388abc52"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga622e592eac9f955633832687cb4aacbd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga622e592eac9f955633832687cb4aacbd"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DCKCFGR_OFFSET</b>   (RCC_OFFSET + 0x8C)</td></tr>
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<tr class="memitem:ga3e4d33566ef60a5220ce491e74a34478"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3e4d33566ef60a5220ce491e74a34478"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>TIMPRE_BitNumber</b>   0x18</td></tr>
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<tr class="memitem:gaff212f4f5168f26347acf1abbb331961"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaff212f4f5168f26347acf1abbb331961"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DCKCFGR_TIMPRE_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))</td></tr>
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<tr class="memitem:gabd7dd9cf31a9cc27fd9c0c1624f9a298"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabd7dd9cf31a9cc27fd9c0c1624f9a298"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CFGR_MCO2_RESET_MASK</b>   ((uint32_t)0x07FFFFFF)</td></tr>
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<tr class="separator:gabd7dd9cf31a9cc27fd9c0c1624f9a298"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga51f5130a66963090dc02b4ebd47e2f83"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga51f5130a66963090dc02b4ebd47e2f83"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CFGR_MCO1_RESET_MASK</b>   ((uint32_t)0xF89FFFFF)</td></tr>
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<tr class="separator:ga51f5130a66963090dc02b4ebd47e2f83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga890221cb651a3f30f6d1bca0d9b0e13d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga890221cb651a3f30f6d1bca0d9b0e13d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>FLAG_MASK</b>   ((uint8_t)0x1F)</td></tr>
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<tr class="memitem:ga9b2724575bb34217aeddcb69c41a1547"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9b2724575bb34217aeddcb69c41a1547"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CR_BYTE3_ADDRESS</b>   ((uint32_t)0x40023802)</td></tr>
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<tr class="separator:ga9b2724575bb34217aeddcb69c41a1547"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaab58c3f3f81bf1ab9a14cf3fececd8c4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaab58c3f3f81bf1ab9a14cf3fececd8c4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CIR_BYTE2_ADDRESS</b>   ((uint32_t)(RCC_BASE + 0x0C + 0x01))</td></tr>
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<tr class="separator:gaab58c3f3f81bf1ab9a14cf3fececd8c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga43f47430582c9575970901533e525bb5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga43f47430582c9575970901533e525bb5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CIR_BYTE3_ADDRESS</b>   ((uint32_t)(RCC_BASE + 0x0C + 0x02))</td></tr>
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<tr class="separator:ga43f47430582c9575970901533e525bb5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga40b5a415d697b6af7babd8a208c92435"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga40b5a415d697b6af7babd8a208c92435"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>BDCR_ADDRESS</b>   (<a class="el" href="group___peripheral__memory__map.html#ga9171f49478fa86d932f89e78e73b88b0">PERIPH_BASE</a> + BDCR_OFFSET)</td></tr>
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<tr class="separator:ga40b5a415d697b6af7babd8a208c92435"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
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Functions</h2></td></tr>
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<tr class="memitem:ga413f6422be11b1334abe60b3bff2e062"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group1.html#ga413f6422be11b1334abe60b3bff2e062">RCC_DeInit</a> (void)</td></tr>
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<tr class="memdesc:ga413f6422be11b1334abe60b3bff2e062"><td class="mdescLeft"> </td><td class="mdescRight">Resets the RCC clock configuration to the default reset state. <a href="group___r_c_c___group1.html#ga413f6422be11b1334abe60b3bff2e062">More...</a><br /></td></tr>
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<tr class="separator:ga413f6422be11b1334abe60b3bff2e062"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga523b06e73f6aa8a03e42299c855066a8"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group1.html#ga523b06e73f6aa8a03e42299c855066a8">RCC_HSEConfig</a> (uint8_t RCC_HSE)</td></tr>
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<tr class="memdesc:ga523b06e73f6aa8a03e42299c855066a8"><td class="mdescLeft"> </td><td class="mdescRight">Configures the External High Speed oscillator (HSE). <a href="group___r_c_c___group1.html#ga523b06e73f6aa8a03e42299c855066a8">More...</a><br /></td></tr>
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<tr class="separator:ga523b06e73f6aa8a03e42299c855066a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae0f15692614dd048ee4110a056f001dc"><td class="memItemLeft" align="right" valign="top">ErrorStatus </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group1.html#gae0f15692614dd048ee4110a056f001dc">RCC_WaitForHSEStartUp</a> (void)</td></tr>
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<tr class="memdesc:gae0f15692614dd048ee4110a056f001dc"><td class="mdescLeft"> </td><td class="mdescRight">Waits for HSE start-up. <a href="group___r_c_c___group1.html#gae0f15692614dd048ee4110a056f001dc">More...</a><br /></td></tr>
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<tr class="separator:gae0f15692614dd048ee4110a056f001dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa2d6a35f5c2e0f86317c3beb222677fc"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group1.html#gaa2d6a35f5c2e0f86317c3beb222677fc">RCC_AdjustHSICalibrationValue</a> (uint8_t HSICalibrationValue)</td></tr>
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<tr class="memdesc:gaa2d6a35f5c2e0f86317c3beb222677fc"><td class="mdescLeft"> </td><td class="mdescRight">Adjusts the Internal High Speed oscillator (HSI) calibration value. <a href="group___r_c_c___group1.html#gaa2d6a35f5c2e0f86317c3beb222677fc">More...</a><br /></td></tr>
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<tr class="separator:gaa2d6a35f5c2e0f86317c3beb222677fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c6772a1e43765909495f57815ef69e2"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group1.html#ga0c6772a1e43765909495f57815ef69e2">RCC_HSICmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga0c6772a1e43765909495f57815ef69e2"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the Internal High Speed oscillator (HSI). <a href="group___r_c_c___group1.html#ga0c6772a1e43765909495f57815ef69e2">More...</a><br /></td></tr>
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<tr class="separator:ga0c6772a1e43765909495f57815ef69e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga65209ab5c3589b249c7d70f978735ca6"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group1.html#ga65209ab5c3589b249c7d70f978735ca6">RCC_LSEConfig</a> (uint8_t RCC_LSE)</td></tr>
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<tr class="memdesc:ga65209ab5c3589b249c7d70f978735ca6"><td class="mdescLeft"> </td><td class="mdescRight">Configures the External Low Speed oscillator (LSE). <a href="group___r_c_c___group1.html#ga65209ab5c3589b249c7d70f978735ca6">More...</a><br /></td></tr>
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<tr class="separator:ga65209ab5c3589b249c7d70f978735ca6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga81e3ca29fd154ac2019bba6936d6d5ed"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group1.html#ga81e3ca29fd154ac2019bba6936d6d5ed">RCC_LSICmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga81e3ca29fd154ac2019bba6936d6d5ed"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the Internal Low Speed oscillator (LSI). <a href="group___r_c_c___group1.html#ga81e3ca29fd154ac2019bba6936d6d5ed">More...</a><br /></td></tr>
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<tr class="separator:ga81e3ca29fd154ac2019bba6936d6d5ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga154b93e90bfdede2a874244a1ff1002e"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group1.html#ga154b93e90bfdede2a874244a1ff1002e">RCC_PLLConfig</a> (uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)</td></tr>
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<tr class="memdesc:ga154b93e90bfdede2a874244a1ff1002e"><td class="mdescLeft"> </td><td class="mdescRight">Configures the main PLL clock source, multiplication and division factors. <a href="group___r_c_c___group1.html#ga154b93e90bfdede2a874244a1ff1002e">More...</a><br /></td></tr>
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<tr class="separator:ga154b93e90bfdede2a874244a1ff1002e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga84dee53c75e58fdb53571716593c2272"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group1.html#ga84dee53c75e58fdb53571716593c2272">RCC_PLLCmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga84dee53c75e58fdb53571716593c2272"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the main PLL. <a href="group___r_c_c___group1.html#ga84dee53c75e58fdb53571716593c2272">More...</a><br /></td></tr>
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<tr class="separator:ga84dee53c75e58fdb53571716593c2272"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2efe493a6337d5e0034bfcdfb0f541e4"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group1.html#ga2efe493a6337d5e0034bfcdfb0f541e4">RCC_PLLI2SCmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga2efe493a6337d5e0034bfcdfb0f541e4"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the PLLI2S. <a href="group___r_c_c___group1.html#ga2efe493a6337d5e0034bfcdfb0f541e4">More...</a><br /></td></tr>
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<tr class="separator:ga2efe493a6337d5e0034bfcdfb0f541e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaed7cbf4255d155c78a714a70752d14bf"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group1.html#gaed7cbf4255d155c78a714a70752d14bf">RCC_PLLSAIConfig</a> (uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR)</td></tr>
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<tr class="memdesc:gaed7cbf4255d155c78a714a70752d14bf"><td class="mdescLeft"> </td><td class="mdescRight">Configures the PLLSAI clock multiplication and division factors. <a href="group___r_c_c___group1.html#gaed7cbf4255d155c78a714a70752d14bf">More...</a><br /></td></tr>
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<tr class="separator:gaed7cbf4255d155c78a714a70752d14bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf7b2c8f7533c8321dce97196d9f77fc1"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group1.html#gaf7b2c8f7533c8321dce97196d9f77fc1">RCC_PLLSAICmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:gaf7b2c8f7533c8321dce97196d9f77fc1"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the PLLSAI. <a href="group___r_c_c___group1.html#gaf7b2c8f7533c8321dce97196d9f77fc1">More...</a><br /></td></tr>
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<tr class="separator:gaf7b2c8f7533c8321dce97196d9f77fc1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0ff1fd7b9a8a49cdda11b7d7261c3494"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group1.html#ga0ff1fd7b9a8a49cdda11b7d7261c3494">RCC_ClockSecuritySystemCmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga0ff1fd7b9a8a49cdda11b7d7261c3494"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the Clock Security System. <a href="group___r_c_c___group1.html#ga0ff1fd7b9a8a49cdda11b7d7261c3494">More...</a><br /></td></tr>
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<tr class="separator:ga0ff1fd7b9a8a49cdda11b7d7261c3494"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga15c9ecb6ef015ed008cb28e5b7a50531"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group1.html#ga15c9ecb6ef015ed008cb28e5b7a50531">RCC_MCO1Config</a> (uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)</td></tr>
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<tr class="memdesc:ga15c9ecb6ef015ed008cb28e5b7a50531"><td class="mdescLeft"> </td><td class="mdescRight">Selects the clock source to output on MCO1 pin(PA8). <a href="group___r_c_c___group1.html#ga15c9ecb6ef015ed008cb28e5b7a50531">More...</a><br /></td></tr>
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<tr class="separator:ga15c9ecb6ef015ed008cb28e5b7a50531"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf50f10675b747de60c739e44e5c22aee"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group1.html#gaf50f10675b747de60c739e44e5c22aee">RCC_MCO2Config</a> (uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)</td></tr>
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<tr class="memdesc:gaf50f10675b747de60c739e44e5c22aee"><td class="mdescLeft"> </td><td class="mdescRight">Selects the clock source to output on MCO2 pin(PC9). <a href="group___r_c_c___group1.html#gaf50f10675b747de60c739e44e5c22aee">More...</a><br /></td></tr>
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<tr class="separator:gaf50f10675b747de60c739e44e5c22aee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3551a36a8f0a3dc96a74d6b939048337"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group2.html#ga3551a36a8f0a3dc96a74d6b939048337">RCC_SYSCLKConfig</a> (uint32_t RCC_SYSCLKSource)</td></tr>
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<tr class="memdesc:ga3551a36a8f0a3dc96a74d6b939048337"><td class="mdescLeft"> </td><td class="mdescRight">Configures the system clock (SYSCLK). <a href="group___r_c_c___group2.html#ga3551a36a8f0a3dc96a74d6b939048337">More...</a><br /></td></tr>
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<tr class="separator:ga3551a36a8f0a3dc96a74d6b939048337"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaeb32311c208b2a980841c9c884a41ea"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group2.html#gaaeb32311c208b2a980841c9c884a41ea">RCC_GetSYSCLKSource</a> (void)</td></tr>
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<tr class="memdesc:gaaeb32311c208b2a980841c9c884a41ea"><td class="mdescLeft"> </td><td class="mdescRight">Returns the clock source used as system clock. <a href="group___r_c_c___group2.html#gaaeb32311c208b2a980841c9c884a41ea">More...</a><br /></td></tr>
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<tr class="separator:gaaeb32311c208b2a980841c9c884a41ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d0aec72e236c6cdf3a3a82dfb525491"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group2.html#ga9d0aec72e236c6cdf3a3a82dfb525491">RCC_HCLKConfig</a> (uint32_t RCC_SYSCLK)</td></tr>
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<tr class="memdesc:ga9d0aec72e236c6cdf3a3a82dfb525491"><td class="mdescLeft"> </td><td class="mdescRight">Configures the AHB clock (HCLK). <a href="group___r_c_c___group2.html#ga9d0aec72e236c6cdf3a3a82dfb525491">More...</a><br /></td></tr>
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<tr class="separator:ga9d0aec72e236c6cdf3a3a82dfb525491"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga448137346d4292985d4e7a61dd1a824f"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group2.html#ga448137346d4292985d4e7a61dd1a824f">RCC_PCLK1Config</a> (uint32_t RCC_HCLK)</td></tr>
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<tr class="memdesc:ga448137346d4292985d4e7a61dd1a824f"><td class="mdescLeft"> </td><td class="mdescRight">Configures the Low Speed APB clock (PCLK1). <a href="group___r_c_c___group2.html#ga448137346d4292985d4e7a61dd1a824f">More...</a><br /></td></tr>
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<tr class="separator:ga448137346d4292985d4e7a61dd1a824f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga09f9c010a4adca9e036da42c2ca6126a"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group2.html#ga09f9c010a4adca9e036da42c2ca6126a">RCC_PCLK2Config</a> (uint32_t RCC_HCLK)</td></tr>
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<tr class="memdesc:ga09f9c010a4adca9e036da42c2ca6126a"><td class="mdescLeft"> </td><td class="mdescRight">Configures the High Speed APB clock (PCLK2). <a href="group___r_c_c___group2.html#ga09f9c010a4adca9e036da42c2ca6126a">More...</a><br /></td></tr>
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<tr class="separator:ga09f9c010a4adca9e036da42c2ca6126a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3e9944fd1ed734275222bbb3e3f29993"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group2.html#ga3e9944fd1ed734275222bbb3e3f29993">RCC_GetClocksFreq</a> (<a class="el" href="struct_r_c_c___clocks_type_def.html">RCC_ClocksTypeDef</a> *RCC_Clocks)</td></tr>
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<tr class="memdesc:ga3e9944fd1ed734275222bbb3e3f29993"><td class="mdescLeft"> </td><td class="mdescRight">Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2. <a href="group___r_c_c___group2.html#ga3e9944fd1ed734275222bbb3e3f29993">More...</a><br /></td></tr>
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<tr class="separator:ga3e9944fd1ed734275222bbb3e3f29993"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1473d8a5a020642966359611c44181b0"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga1473d8a5a020642966359611c44181b0">RCC_RTCCLKConfig</a> (uint32_t RCC_RTCCLKSource)</td></tr>
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<tr class="memdesc:ga1473d8a5a020642966359611c44181b0"><td class="mdescLeft"> </td><td class="mdescRight">Configures the RTC clock (RTCCLK). <a href="group___r_c_c___group3.html#ga1473d8a5a020642966359611c44181b0">More...</a><br /></td></tr>
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<tr class="separator:ga1473d8a5a020642966359611c44181b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9802f84846df2cea8e369234ed13b159"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga9802f84846df2cea8e369234ed13b159">RCC_RTCCLKCmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga9802f84846df2cea8e369234ed13b159"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the RTC clock. <a href="group___r_c_c___group3.html#ga9802f84846df2cea8e369234ed13b159">More...</a><br /></td></tr>
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<tr class="separator:ga9802f84846df2cea8e369234ed13b159"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga636c3b72f35391e67f12a551b15fa54a"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga636c3b72f35391e67f12a551b15fa54a">RCC_BackupResetCmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga636c3b72f35391e67f12a551b15fa54a"><td class="mdescLeft"> </td><td class="mdescRight">Forces or releases the Backup domain reset. <a href="group___r_c_c___group3.html#ga636c3b72f35391e67f12a551b15fa54a">More...</a><br /></td></tr>
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<tr class="separator:ga636c3b72f35391e67f12a551b15fa54a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c56f8529988fcc8f4dbffbc1bab27d0"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga6c56f8529988fcc8f4dbffbc1bab27d0">RCC_I2SCLKConfig</a> (uint32_t RCC_I2SCLKSource)</td></tr>
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<tr class="memdesc:ga6c56f8529988fcc8f4dbffbc1bab27d0"><td class="mdescLeft"> </td><td class="mdescRight">Configures the I2S clock source (I2SCLK). <a href="group___r_c_c___group3.html#ga6c56f8529988fcc8f4dbffbc1bab27d0">More...</a><br /></td></tr>
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<tr class="separator:ga6c56f8529988fcc8f4dbffbc1bab27d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga71a887e0e7ef3d49ff87f2cbc435b099"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga71a887e0e7ef3d49ff87f2cbc435b099">RCC_SAIPLLI2SClkDivConfig</a> (uint32_t RCC_PLLI2SDivQ)</td></tr>
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<tr class="memdesc:ga71a887e0e7ef3d49ff87f2cbc435b099"><td class="mdescLeft"> </td><td class="mdescRight">Configures the SAI clock Divider coming from PLLI2S. <a href="group___r_c_c___group3.html#ga71a887e0e7ef3d49ff87f2cbc435b099">More...</a><br /></td></tr>
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<tr class="separator:ga71a887e0e7ef3d49ff87f2cbc435b099"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabefc354915bd57804329349ec3f33fab"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#gabefc354915bd57804329349ec3f33fab">RCC_SAIPLLSAIClkDivConfig</a> (uint32_t RCC_PLLSAIDivQ)</td></tr>
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<tr class="memdesc:gabefc354915bd57804329349ec3f33fab"><td class="mdescLeft"> </td><td class="mdescRight">Configures the SAI clock Divider coming from PLLSAI. <a href="group___r_c_c___group3.html#gabefc354915bd57804329349ec3f33fab">More...</a><br /></td></tr>
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<tr class="separator:gabefc354915bd57804329349ec3f33fab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6cb4739d834adbf4009112357e1b1099"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga6cb4739d834adbf4009112357e1b1099">RCC_SAIBlockACLKConfig</a> (uint32_t RCC_SAIBlockACLKSource)</td></tr>
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<tr class="memdesc:ga6cb4739d834adbf4009112357e1b1099"><td class="mdescLeft"> </td><td class="mdescRight">Configures SAI1BlockA clock source selection. <a href="group___r_c_c___group3.html#ga6cb4739d834adbf4009112357e1b1099">More...</a><br /></td></tr>
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<tr class="separator:ga6cb4739d834adbf4009112357e1b1099"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d1fb5c9a743d7f36713c9c76d386557"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga4d1fb5c9a743d7f36713c9c76d386557">RCC_SAIBlockBCLKConfig</a> (uint32_t RCC_SAIBlockBCLKSource)</td></tr>
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<tr class="memdesc:ga4d1fb5c9a743d7f36713c9c76d386557"><td class="mdescLeft"> </td><td class="mdescRight">Configures SAI1BlockB clock source selection. <a href="group___r_c_c___group3.html#ga4d1fb5c9a743d7f36713c9c76d386557">More...</a><br /></td></tr>
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<tr class="separator:ga4d1fb5c9a743d7f36713c9c76d386557"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac04a91996aefd2a517cf90c2a44830d2"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#gac04a91996aefd2a517cf90c2a44830d2">RCC_LTDCCLKDivConfig</a> (uint32_t RCC_PLLSAIDivR)</td></tr>
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<tr class="memdesc:gac04a91996aefd2a517cf90c2a44830d2"><td class="mdescLeft"> </td><td class="mdescRight">Configures the LTDC clock Divider coming from PLLSAI. <a href="group___r_c_c___group3.html#gac04a91996aefd2a517cf90c2a44830d2">More...</a><br /></td></tr>
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<tr class="separator:gac04a91996aefd2a517cf90c2a44830d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0599100e7afdf8ed988e351a899e922"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#gaf0599100e7afdf8ed988e351a899e922">RCC_TIMCLKPresConfig</a> (uint32_t RCC_TIMCLKPrescaler)</td></tr>
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<tr class="memdesc:gaf0599100e7afdf8ed988e351a899e922"><td class="mdescLeft"> </td><td class="mdescRight">Configures the Timers clocks prescalers selection. <a href="group___r_c_c___group3.html#gaf0599100e7afdf8ed988e351a899e922">More...</a><br /></td></tr>
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<tr class="separator:gaf0599100e7afdf8ed988e351a899e922"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80c89116820d48bb38db2e7d5e5a49b9"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga80c89116820d48bb38db2e7d5e5a49b9">RCC_AHB1PeriphClockCmd</a> (uint32_t RCC_AHB1Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga80c89116820d48bb38db2e7d5e5a49b9"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the AHB1 peripheral clock. <a href="group___r_c_c___group3.html#ga80c89116820d48bb38db2e7d5e5a49b9">More...</a><br /></td></tr>
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<tr class="separator:ga80c89116820d48bb38db2e7d5e5a49b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaadffedbd87e796f01d9776b8ee01ff5e"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#gaadffedbd87e796f01d9776b8ee01ff5e">RCC_AHB2PeriphClockCmd</a> (uint32_t RCC_AHB2Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:gaadffedbd87e796f01d9776b8ee01ff5e"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the AHB2 peripheral clock. <a href="group___r_c_c___group3.html#gaadffedbd87e796f01d9776b8ee01ff5e">More...</a><br /></td></tr>
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<tr class="separator:gaadffedbd87e796f01d9776b8ee01ff5e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4eb8c119f2e9bf2bd2e042d27f151338"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga4eb8c119f2e9bf2bd2e042d27f151338">RCC_AHB3PeriphClockCmd</a> (uint32_t RCC_AHB3Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga4eb8c119f2e9bf2bd2e042d27f151338"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the AHB3 peripheral clock. <a href="group___r_c_c___group3.html#ga4eb8c119f2e9bf2bd2e042d27f151338">More...</a><br /></td></tr>
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<tr class="separator:ga4eb8c119f2e9bf2bd2e042d27f151338"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee7cc5d73af7fe1986fceff8afd3973e"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#gaee7cc5d73af7fe1986fceff8afd3973e">RCC_APB1PeriphClockCmd</a> (uint32_t RCC_APB1Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:gaee7cc5d73af7fe1986fceff8afd3973e"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the Low Speed APB (APB1) peripheral clock. <a href="group___r_c_c___group3.html#gaee7cc5d73af7fe1986fceff8afd3973e">More...</a><br /></td></tr>
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<tr class="separator:gaee7cc5d73af7fe1986fceff8afd3973e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56ff55caf8d835351916b40dd030bc87"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga56ff55caf8d835351916b40dd030bc87">RCC_APB2PeriphClockCmd</a> (uint32_t RCC_APB2Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga56ff55caf8d835351916b40dd030bc87"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the High Speed APB (APB2) peripheral clock. <a href="group___r_c_c___group3.html#ga56ff55caf8d835351916b40dd030bc87">More...</a><br /></td></tr>
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<tr class="separator:ga56ff55caf8d835351916b40dd030bc87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7c450567f4731d4f0615f63586cad86"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#gaa7c450567f4731d4f0615f63586cad86">RCC_AHB1PeriphResetCmd</a> (uint32_t RCC_AHB1Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:gaa7c450567f4731d4f0615f63586cad86"><td class="mdescLeft"> </td><td class="mdescRight">Forces or releases AHB1 peripheral reset. <a href="group___r_c_c___group3.html#gaa7c450567f4731d4f0615f63586cad86">More...</a><br /></td></tr>
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<tr class="separator:gaa7c450567f4731d4f0615f63586cad86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb119d6d1955d1b8c361e8140845ac5a"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#gafb119d6d1955d1b8c361e8140845ac5a">RCC_AHB2PeriphResetCmd</a> (uint32_t RCC_AHB2Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:gafb119d6d1955d1b8c361e8140845ac5a"><td class="mdescLeft"> </td><td class="mdescRight">Forces or releases AHB2 peripheral reset. <a href="group___r_c_c___group3.html#gafb119d6d1955d1b8c361e8140845ac5a">More...</a><br /></td></tr>
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<tr class="separator:gafb119d6d1955d1b8c361e8140845ac5a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee44f159a1ca9ebdd7117bff387cd592"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#gaee44f159a1ca9ebdd7117bff387cd592">RCC_AHB3PeriphResetCmd</a> (uint32_t RCC_AHB3Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:gaee44f159a1ca9ebdd7117bff387cd592"><td class="mdescLeft"> </td><td class="mdescRight">Forces or releases AHB3 peripheral reset. <a href="group___r_c_c___group3.html#gaee44f159a1ca9ebdd7117bff387cd592">More...</a><br /></td></tr>
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<tr class="separator:gaee44f159a1ca9ebdd7117bff387cd592"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab197ae4369c10b92640a733b40ed2801"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#gab197ae4369c10b92640a733b40ed2801">RCC_APB1PeriphResetCmd</a> (uint32_t RCC_APB1Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:gab197ae4369c10b92640a733b40ed2801"><td class="mdescLeft"> </td><td class="mdescRight">Forces or releases Low Speed APB (APB1) peripheral reset. <a href="group___r_c_c___group3.html#gab197ae4369c10b92640a733b40ed2801">More...</a><br /></td></tr>
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<tr class="separator:gab197ae4369c10b92640a733b40ed2801"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad94553850ac07106a27ee85fec37efdf"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#gad94553850ac07106a27ee85fec37efdf">RCC_APB2PeriphResetCmd</a> (uint32_t RCC_APB2Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:gad94553850ac07106a27ee85fec37efdf"><td class="mdescLeft"> </td><td class="mdescRight">Forces or releases High Speed APB (APB2) peripheral reset. <a href="group___r_c_c___group3.html#gad94553850ac07106a27ee85fec37efdf">More...</a><br /></td></tr>
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<tr class="separator:gad94553850ac07106a27ee85fec37efdf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5cd0d5adbc7496d7005b208bd19ce255"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga5cd0d5adbc7496d7005b208bd19ce255">RCC_AHB1PeriphClockLPModeCmd</a> (uint32_t RCC_AHB1Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga5cd0d5adbc7496d7005b208bd19ce255"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. <a href="group___r_c_c___group3.html#ga5cd0d5adbc7496d7005b208bd19ce255">More...</a><br /></td></tr>
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<tr class="separator:ga5cd0d5adbc7496d7005b208bd19ce255"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ac5bb9676ae9b48e50d6a95de922ce3"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga1ac5bb9676ae9b48e50d6a95de922ce3">RCC_AHB2PeriphClockLPModeCmd</a> (uint32_t RCC_AHB2Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga1ac5bb9676ae9b48e50d6a95de922ce3"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. <a href="group___r_c_c___group3.html#ga1ac5bb9676ae9b48e50d6a95de922ce3">More...</a><br /></td></tr>
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<tr class="separator:ga1ac5bb9676ae9b48e50d6a95de922ce3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e1df07cdfd81c068902d9d35fcc3911"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga4e1df07cdfd81c068902d9d35fcc3911">RCC_AHB3PeriphClockLPModeCmd</a> (uint32_t RCC_AHB3Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga4e1df07cdfd81c068902d9d35fcc3911"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. <a href="group___r_c_c___group3.html#ga4e1df07cdfd81c068902d9d35fcc3911">More...</a><br /></td></tr>
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<tr class="separator:ga4e1df07cdfd81c068902d9d35fcc3911"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga84dd64badb84768cbcf19e241cadff50"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga84dd64badb84768cbcf19e241cadff50">RCC_APB1PeriphClockLPModeCmd</a> (uint32_t RCC_APB1Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga84dd64badb84768cbcf19e241cadff50"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. <a href="group___r_c_c___group3.html#ga84dd64badb84768cbcf19e241cadff50">More...</a><br /></td></tr>
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<tr class="separator:ga84dd64badb84768cbcf19e241cadff50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga30365b9e0b4c5d7e98c2675c862ddd7e"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga30365b9e0b4c5d7e98c2675c862ddd7e">RCC_APB2PeriphClockLPModeCmd</a> (uint32_t RCC_APB2Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga30365b9e0b4c5d7e98c2675c862ddd7e"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. <a href="group___r_c_c___group3.html#ga30365b9e0b4c5d7e98c2675c862ddd7e">More...</a><br /></td></tr>
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<tr class="separator:ga30365b9e0b4c5d7e98c2675c862ddd7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1337eb44ba2fce5b3e8ccd92cd01bde4"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga1337eb44ba2fce5b3e8ccd92cd01bde4">RCC_LSEModeConfig</a> (uint8_t Mode)</td></tr>
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<tr class="memdesc:ga1337eb44ba2fce5b3e8ccd92cd01bde4"><td class="mdescLeft"> </td><td class="mdescRight">Configures the External Low Speed oscillator mode (LSE mode). <a href="group___r_c_c___group3.html#ga1337eb44ba2fce5b3e8ccd92cd01bde4">More...</a><br /></td></tr>
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<tr class="separator:ga1337eb44ba2fce5b3e8ccd92cd01bde4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa953aa226e9ce45300d535941e4dfe2f"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group4.html#gaa953aa226e9ce45300d535941e4dfe2f">RCC_ITConfig</a> (uint8_t RCC_IT, FunctionalState NewState)</td></tr>
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<tr class="memdesc:gaa953aa226e9ce45300d535941e4dfe2f"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the specified RCC interrupts. <a href="group___r_c_c___group4.html#gaa953aa226e9ce45300d535941e4dfe2f">More...</a><br /></td></tr>
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<tr class="separator:gaa953aa226e9ce45300d535941e4dfe2f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2897bdc52f272031c44fb1f72205d295"><td class="memItemLeft" align="right" valign="top">FlagStatus </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group4.html#ga2897bdc52f272031c44fb1f72205d295">RCC_GetFlagStatus</a> (uint8_t RCC_FLAG)</td></tr>
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<tr class="memdesc:ga2897bdc52f272031c44fb1f72205d295"><td class="mdescLeft"> </td><td class="mdescRight">Checks whether the specified RCC flag is set or not. <a href="group___r_c_c___group4.html#ga2897bdc52f272031c44fb1f72205d295">More...</a><br /></td></tr>
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<tr class="separator:ga2897bdc52f272031c44fb1f72205d295"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga53f909dbb15a54124419084ebda97d72"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group4.html#ga53f909dbb15a54124419084ebda97d72">RCC_ClearFlag</a> (void)</td></tr>
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<tr class="memdesc:ga53f909dbb15a54124419084ebda97d72"><td class="mdescLeft"> </td><td class="mdescRight">Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST. <a href="group___r_c_c___group4.html#ga53f909dbb15a54124419084ebda97d72">More...</a><br /></td></tr>
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<tr class="separator:ga53f909dbb15a54124419084ebda97d72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6126c99f398ee4be410ad76ae3aee18f"><td class="memItemLeft" align="right" valign="top">ITStatus </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group4.html#ga6126c99f398ee4be410ad76ae3aee18f">RCC_GetITStatus</a> (uint8_t RCC_IT)</td></tr>
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<tr class="memdesc:ga6126c99f398ee4be410ad76ae3aee18f"><td class="mdescLeft"> </td><td class="mdescRight">Checks whether the specified RCC interrupt has occurred or not. <a href="group___r_c_c___group4.html#ga6126c99f398ee4be410ad76ae3aee18f">More...</a><br /></td></tr>
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<tr class="separator:ga6126c99f398ee4be410ad76ae3aee18f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga529842d165910f8f87e26115da36089b"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group4.html#ga529842d165910f8f87e26115da36089b">RCC_ClearITPendingBit</a> (uint8_t RCC_IT)</td></tr>
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<tr class="memdesc:ga529842d165910f8f87e26115da36089b"><td class="mdescLeft"> </td><td class="mdescRight">Clears the RCC's interrupt pending bits. <a href="group___r_c_c___group4.html#ga529842d165910f8f87e26115da36089b">More...</a><br /></td></tr>
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<tr class="separator:ga529842d165910f8f87e26115da36089b"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>This file provides firmware functions to manage the following functionalities of the Reset and clock control (RCC) peripheral: </p>
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<dl class="section author"><dt>Author</dt><dd>MCD Application Team </dd></dl>
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<dl class="section version"><dt>Version</dt><dd>V1.4.0 </dd></dl>
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<dl class="section date"><dt>Date</dt><dd>04-August-2014<ul>
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<li>Internal/external clocks, PLL, CSS and MCO configuration</li>
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<li>System, AHB and APB busses clocks configuration</li>
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<li>Peripheral clocks configuration</li>
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<li>Interrupts and flags management</li>
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</ul>
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</dd></dl>
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<pre class="fragment">===============================================================================
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##### RCC specific features #####
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===============================================================================
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[..]
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After reset the device is running from Internal High Speed oscillator
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(HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
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and I-Cache are disabled, and all peripherals are off except internal
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SRAM, Flash and JTAG.
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(+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
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all peripherals mapped on these busses are running at HSI speed.
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(+) The clock for all peripherals is switched off, except the SRAM and FLASH.
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(+) All GPIOs are in input floating state, except the JTAG pins which
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are assigned to be used for debug purpose.
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[..]
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Once the device started from reset, the user application has to:
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(+) Configure the clock source to be used to drive the System clock
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(if the application needs higher frequency/performance)
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(+) Configure the System clock frequency and Flash settings
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(+) Configure the AHB and APB busses prescalers
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(+) Enable the clock for the peripheral(s) to be used
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(+) Configure the clock source(s) for peripherals which clocks are not
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derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
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</pre><dl class="section attention"><dt>Attention</dt><dd></dd></dl>
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<h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
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<p>Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at: </p><pre class="fragment"> http://www.st.com/software_license_agreement_liberty_v2
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</pre><p>Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. </p>
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