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<a href="#func-members">Functions</a> </div>
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<div class="title">Interrupts and flags management functions<div class="ingroups"><a class="el" href="group___s_t_m32_f4xx___std_periph___driver.html">STM32F4xx_StdPeriph_Driver</a> » <a class="el" href="group___d_m_a.html">DMA</a> » <a class="el" href="group___d_m_a___private___functions.html">DMA_Private_Functions</a></div></div> </div>
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<p>Interrupts and flags management functions.
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<a href="#details">More...</a></p>
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Collaboration diagram for Interrupts and flags management functions:</div>
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</div>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
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Functions</h2></td></tr>
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<tr class="memitem:gaa4d631cdd6cd020106435f30c0c6fb15"><td class="memItemLeft" align="right" valign="top">FunctionalState </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_m_a___group4.html#gaa4d631cdd6cd020106435f30c0c6fb15">DMA_GetCmdStatus</a> (<a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *DMAy_Streamx)</td></tr>
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<tr class="memdesc:gaa4d631cdd6cd020106435f30c0c6fb15"><td class="mdescLeft"> </td><td class="mdescRight">Returns the status of EN bit for the specified DMAy Streamx. <a href="#gaa4d631cdd6cd020106435f30c0c6fb15">More...</a><br /></td></tr>
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<tr class="separator:gaa4d631cdd6cd020106435f30c0c6fb15"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9893809a7067861ec111f7d712ebf28d"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_m_a___group4.html#ga9893809a7067861ec111f7d712ebf28d">DMA_GetFIFOStatus</a> (<a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *DMAy_Streamx)</td></tr>
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<tr class="memdesc:ga9893809a7067861ec111f7d712ebf28d"><td class="mdescLeft"> </td><td class="mdescRight">Returns the current DMAy Streamx FIFO filled level. <a href="#ga9893809a7067861ec111f7d712ebf28d">More...</a><br /></td></tr>
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<tr class="separator:ga9893809a7067861ec111f7d712ebf28d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga10cfc0fe31d64a1fd8fb3efb4ae2a411"><td class="memItemLeft" align="right" valign="top">FlagStatus </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_m_a___group4.html#ga10cfc0fe31d64a1fd8fb3efb4ae2a411">DMA_GetFlagStatus</a> (<a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *DMAy_Streamx, uint32_t DMA_FLAG)</td></tr>
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<tr class="memdesc:ga10cfc0fe31d64a1fd8fb3efb4ae2a411"><td class="mdescLeft"> </td><td class="mdescRight">Checks whether the specified DMAy Streamx flag is set or not. <a href="#ga10cfc0fe31d64a1fd8fb3efb4ae2a411">More...</a><br /></td></tr>
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<tr class="separator:ga10cfc0fe31d64a1fd8fb3efb4ae2a411"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga510d62b4051f5a5de164e84b266b851d"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_m_a___group4.html#ga510d62b4051f5a5de164e84b266b851d">DMA_ClearFlag</a> (<a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *DMAy_Streamx, uint32_t DMA_FLAG)</td></tr>
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<tr class="memdesc:ga510d62b4051f5a5de164e84b266b851d"><td class="mdescLeft"> </td><td class="mdescRight">Clears the DMAy Streamx's pending flags. <a href="#ga510d62b4051f5a5de164e84b266b851d">More...</a><br /></td></tr>
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<tr class="separator:ga510d62b4051f5a5de164e84b266b851d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab9c469a3f5d4aca5c97dee798ffc2f05"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_m_a___group4.html#gab9c469a3f5d4aca5c97dee798ffc2f05">DMA_ITConfig</a> (<a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState)</td></tr>
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<tr class="memdesc:gab9c469a3f5d4aca5c97dee798ffc2f05"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the specified DMAy Streamx interrupts. <a href="#gab9c469a3f5d4aca5c97dee798ffc2f05">More...</a><br /></td></tr>
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<tr class="separator:gab9c469a3f5d4aca5c97dee798ffc2f05"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad0ccf5f6548bd7cf8f2cae30393bb716"><td class="memItemLeft" align="right" valign="top">ITStatus </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_m_a___group4.html#gad0ccf5f6548bd7cf8f2cae30393bb716">DMA_GetITStatus</a> (<a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *DMAy_Streamx, uint32_t DMA_IT)</td></tr>
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<tr class="memdesc:gad0ccf5f6548bd7cf8f2cae30393bb716"><td class="mdescLeft"> </td><td class="mdescRight">Checks whether the specified DMAy Streamx interrupt has occurred or not. <a href="#gad0ccf5f6548bd7cf8f2cae30393bb716">More...</a><br /></td></tr>
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<tr class="separator:gad0ccf5f6548bd7cf8f2cae30393bb716"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad5433018889cd36140d98bb380c4e76e"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_m_a___group4.html#gad5433018889cd36140d98bb380c4e76e">DMA_ClearITPendingBit</a> (<a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *DMAy_Streamx, uint32_t DMA_IT)</td></tr>
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<tr class="memdesc:gad5433018889cd36140d98bb380c4e76e"><td class="mdescLeft"> </td><td class="mdescRight">Clears the DMAy Streamx's interrupt pending bits. <a href="#gad5433018889cd36140d98bb380c4e76e">More...</a><br /></td></tr>
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<tr class="separator:gad5433018889cd36140d98bb380c4e76e"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<p>Interrupts and flags management functions. </p>
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<pre class="fragment"> ===============================================================================
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##### Interrupts and flags management functions #####
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===============================================================================
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[..]
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This subsection provides functions allowing to
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(+) Check the DMA enable status
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(+) Check the FIFO status
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(+) Configure the DMA Interrupts sources and check or clear the flags or
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pending bits status.
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[..]
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(#) DMA Enable status:
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After configuring the DMA Stream (DMA_Init() function) and enabling
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the stream, it is recommended to check (or wait until) the DMA Stream
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is effectively enabled. A Stream may remain disabled if a configuration
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parameter is wrong. After disabling a DMA Stream, it is also recommended
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to check (or wait until) the DMA Stream is effectively disabled.
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If a Stream is disabled while a data transfer is ongoing, the current
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data will be transferred and the Stream will be effectively disabled
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only after this data transfer completion.
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To monitor this state it is possible to use the following function:
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(++) FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx);
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(#) FIFO Status:
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It is possible to monitor the FIFO status when a transfer is ongoing
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using the following function:
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(++) uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx);
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(#) DMA Interrupts and Flags:
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The user should identify which mode will be used in his application
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to manage the DMA controller events: Polling mode or Interrupt mode.
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*** Polling Mode ***
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====================
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[..]
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Each DMA stream can be managed through 4 event Flags:
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(x : DMA Stream number )
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(#) DMA_FLAG_FEIFx : to indicate that a FIFO Mode Transfer Error event occurred.
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(#) DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred.
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(#) DMA_FLAG_TEIFx : to indicate that a Transfer Error event occurred.
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(#) DMA_FLAG_HTIFx : to indicate that a Half-Transfer Complete event occurred.
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(#) DMA_FLAG_TCIFx : to indicate that a Transfer Complete event occurred .
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[..]
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In this Mode it is advised to use the following functions:
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(+) FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
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(+) void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
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*** Interrupt Mode ***
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======================
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[..]
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Each DMA Stream can be managed through 4 Interrupts:
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*** Interrupt Source ***
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========================
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[..]
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(#) DMA_IT_FEIFx : specifies the interrupt source for the FIFO Mode Transfer Error event.
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(#) DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event.
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(#) DMA_IT_TEIFx : specifies the interrupt source for the Transfer Error event.
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(#) DMA_IT_HTIFx : specifies the interrupt source for the Half-Transfer Complete event.
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(#) DMA_IT_TCIFx : specifies the interrupt source for the a Transfer Complete event.
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[..]
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In this Mode it is advised to use the following functions:
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(+) void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
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(+) ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
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(+) void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);</pre> <h2 class="groupheader">Function Documentation</h2>
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<a class="anchor" id="ga510d62b4051f5a5de164e84b266b851d"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void DMA_ClearFlag </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> * </td>
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<td class="paramname"><em>DMAy_Streamx</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>DMA_FLAG</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Clears the DMAy Streamx's pending flags. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">DMAy_Streamx</td><td>where y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream. </td></tr>
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<tr><td class="paramname">DMA_FLAG</td><td>specifies the flag to clear. This parameter can be any combination of the following values: <ul>
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<li>DMA_FLAG_TCIFx: Streamx transfer complete flag </li>
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<li>DMA_FLAG_HTIFx: Streamx half transfer complete flag </li>
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<li>DMA_FLAG_TEIFx: Streamx transfer error flag </li>
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<li>DMA_FLAG_DMEIFx: Streamx direct mode error flag </li>
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<li>DMA_FLAG_FEIFx: Streamx FIFO error flag Where x can be 0 to 7 to select the DMA Stream. </li>
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</ul>
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</td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
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<table class="retval">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="gad5433018889cd36140d98bb380c4e76e"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void DMA_ClearITPendingBit </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> * </td>
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<td class="paramname"><em>DMAy_Streamx</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>DMA_IT</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Clears the DMAy Streamx's interrupt pending bits. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">DMAy_Streamx</td><td>where y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream. </td></tr>
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<tr><td class="paramname">DMA_IT</td><td>specifies the DMA interrupt pending bit to clear. This parameter can be any combination of the following values: <ul>
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<li>DMA_IT_TCIFx: Streamx transfer complete interrupt </li>
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<li>DMA_IT_HTIFx: Streamx half transfer complete interrupt </li>
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<li>DMA_IT_TEIFx: Streamx transfer error interrupt </li>
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<li>DMA_IT_DMEIFx: Streamx direct mode error interrupt </li>
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<li>DMA_IT_FEIFx: Streamx FIFO error interrupt Where x can be 0 to 7 to select the DMA Stream. </li>
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</ul>
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</td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
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<table class="retval">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="gaa4d631cdd6cd020106435f30c0c6fb15"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">FunctionalState DMA_GetCmdStatus </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> * </td>
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<td class="paramname"><em>DMAy_Streamx</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Returns the status of EN bit for the specified DMAy Streamx. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">DMAy_Streamx</td><td>where y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream.</td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section note"><dt>Note</dt><dd>After configuring the DMA Stream (<a class="el" href="group___d_m_a___group1.html#gaced8a4149acfb0a50b50e63273a87148" title="Initializes the DMAy Streamx according to the specified parameters in the DMA_InitStruct structure...">DMA_Init()</a> function) and enabling the stream, it is recommended to check (or wait until) the DMA Stream is effectively enabled. A Stream may remain disabled if a configuration parameter is wrong. After disabling a DMA Stream, it is also recommended to check (or wait until) the DMA Stream is effectively disabled. If a Stream is disabled while a data transfer is ongoing, the current data will be transferred and the Stream will be effectively disabled only after the transfer of this single data is finished.</dd></dl>
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<dl class="retval"><dt>Return values</dt><dd>
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<table class="retval">
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<tr><td class="paramname">Current</td><td>state of the DMAy Streamx (ENABLE or DISABLE). </td></tr>
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</table>
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</dd>
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</dl>
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</div>
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<a class="anchor" id="ga9893809a7067861ec111f7d712ebf28d"></a>
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<div class="memitem">
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<table class="memname">
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<tr>
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<td class="memname">uint32_t DMA_GetFIFOStatus </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> * </td>
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<td class="paramname"><em>DMAy_Streamx</em></td><td>)</td>
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<td></td>
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</tr>
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</div><div class="memdoc">
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<p>Returns the current DMAy Streamx FIFO filled level. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">DMAy_Streamx</td><td>where y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
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<table class="retval">
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<tr><td class="paramname">The</td><td>FIFO filling state.<ul>
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<li>DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full and not empty.</li>
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<li>DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.</li>
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<li>DMA_FIFOStatus_HalfFull: if more than 1 half-full.</li>
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<li>DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.</li>
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<li>DMA_FIFOStatus_Empty: when FIFO is empty</li>
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<li>DMA_FIFOStatus_Full: when FIFO is full </li>
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</ul>
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</td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="ga10cfc0fe31d64a1fd8fb3efb4ae2a411"></a>
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<div class="memitem">
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<tr>
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<td class="memname">FlagStatus DMA_GetFlagStatus </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> * </td>
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<td class="paramname"><em>DMAy_Streamx</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>DMA_FLAG</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Checks whether the specified DMAy Streamx flag is set or not. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">DMAy_Streamx</td><td>where y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream. </td></tr>
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<tr><td class="paramname">DMA_FLAG</td><td>specifies the flag to check. This parameter can be one of the following values: <ul>
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<li>DMA_FLAG_TCIFx: Streamx transfer complete flag </li>
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<li>DMA_FLAG_HTIFx: Streamx half transfer complete flag </li>
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<li>DMA_FLAG_TEIFx: Streamx transfer error flag </li>
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<li>DMA_FLAG_DMEIFx: Streamx direct mode error flag </li>
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<li>DMA_FLAG_FEIFx: Streamx FIFO error flag Where x can be 0 to 7 to select the DMA Stream. </li>
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</ul>
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</td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
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<table class="retval">
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<tr><td class="paramname">The</td><td>new state of DMA_FLAG (SET or RESET). </td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="gad0ccf5f6548bd7cf8f2cae30393bb716"></a>
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<div class="memitem">
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<td class="memname">ITStatus DMA_GetITStatus </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> * </td>
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<td class="paramname"><em>DMAy_Streamx</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>DMA_IT</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Checks whether the specified DMAy Streamx interrupt has occurred or not. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">DMAy_Streamx</td><td>where y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream. </td></tr>
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<tr><td class="paramname">DMA_IT</td><td>specifies the DMA interrupt source to check. This parameter can be one of the following values: <ul>
|
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<li>DMA_IT_TCIFx: Streamx transfer complete interrupt </li>
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<li>DMA_IT_HTIFx: Streamx half transfer complete interrupt </li>
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<li>DMA_IT_TEIFx: Streamx transfer error interrupt </li>
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<li>DMA_IT_DMEIFx: Streamx direct mode error interrupt </li>
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<li>DMA_IT_FEIFx: Streamx FIFO error interrupt Where x can be 0 to 7 to select the DMA Stream. </li>
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</ul>
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</td></tr>
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</table>
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</dd>
|
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
|
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<table class="retval">
|
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<tr><td class="paramname">The</td><td>new state of DMA_IT (SET or RESET). </td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="gab9c469a3f5d4aca5c97dee798ffc2f05"></a>
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<div class="memitem">
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<div class="memproto">
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<tr>
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<td class="memname">void DMA_ITConfig </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> * </td>
|
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<td class="paramname"><em>DMAy_Streamx</em>, </td>
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</tr>
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<tr>
|
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<td class="paramkey"></td>
|
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<td></td>
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<td class="paramtype">uint32_t </td>
|
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<td class="paramname"><em>DMA_IT</em>, </td>
|
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</tr>
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<tr>
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<td class="paramkey"></td>
|
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<td></td>
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<td class="paramtype">FunctionalState </td>
|
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<td class="paramname"><em>NewState</em> </td>
|
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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|
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<p>Enables or disables the specified DMAy Streamx interrupts. </p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">DMAy_Streamx</td><td>where y can be 1 or 2 to select the DMA and x can be 0 to 7 to select the DMA Stream. </td></tr>
|
|
<tr><td class="paramname">DMA_IT</td><td>specifies the DMA interrupt sources to be enabled or disabled. This parameter can be any combination of the following values: <ul>
|
|
<li>DMA_IT_TC: Transfer complete interrupt mask </li>
|
|
<li>DMA_IT_HT: Half transfer complete interrupt mask </li>
|
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<li>DMA_IT_TE: Transfer error interrupt mask </li>
|
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<li>DMA_IT_FE: FIFO error interrupt mask </li>
|
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</ul>
|
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</td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified DMA interrupts. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
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</dd>
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</dl>
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</div>
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</div>
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