61 #define CLEAR_HC_INT(HC_REGS, intr) \
63 USB_OTG_HCINTn_TypeDef hcint_clear; \
64 hcint_clear.d32 = 0; \
65 hcint_clear.b.intr = 1; \
66 USB_OTG_WRITE_REG32(&((HC_REGS)->HCINT), hcint_clear.d32);\
69 #define MASK_HOST_INT_CHH(hc_num) { USB_OTG_HCGINTMSK_TypeDef GINTMSK; \
70 GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \
71 GINTMSK.b.chhltd = 0; \
72 USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);}
74 #define UNMASK_HOST_INT_CHH(hc_num) { USB_OTG_HCGINTMSK_TypeDef GINTMSK; \
75 GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \
76 GINTMSK.b.chhltd = 1; \
77 USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);}
79 #define MASK_HOST_INT_ACK(hc_num) { USB_OTG_HCGINTMSK_TypeDef GINTMSK; \
80 GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \
82 USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);}
84 #define UNMASK_HOST_INT_ACK(hc_num) { USB_OTG_HCGINTMSK_TypeDef GINTMSK; \
85 GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \
87 USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);}
115 #endif //__HCD_INT_H__
Definition: usb_core.h:287
uint32_t USBH_OTG_ISR_Handler(USB_OTG_CORE_HANDLE *pdev)
HOST_Handle_ISR This function handles all USB Host Interrupts.
Definition: usb_hcd_int.c:114