discoverpixy
stm32f4xx_rcc.h
Go to the documentation of this file.
1 
28 /* Define to prevent recursive inclusion -------------------------------------*/
29 #ifndef __STM32F4xx_RCC_H
30 #define __STM32F4xx_RCC_H
31 
32 #ifdef __cplusplus
33  extern "C" {
34 #endif
35 
36 /* Includes ------------------------------------------------------------------*/
37 #include "stm32f4xx.h"
38 
47 /* Exported types ------------------------------------------------------------*/
48 typedef struct
49 {
50  uint32_t SYSCLK_Frequency;
51  uint32_t HCLK_Frequency;
52  uint32_t PCLK1_Frequency;
53  uint32_t PCLK2_Frequency;
54 }RCC_ClocksTypeDef;
55 
56 /* Exported constants --------------------------------------------------------*/
57 
65 #define RCC_HSE_OFF ((uint8_t)0x00)
66 #define RCC_HSE_ON ((uint8_t)0x01)
67 #define RCC_HSE_Bypass ((uint8_t)0x05)
68 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
69  ((HSE) == RCC_HSE_Bypass))
70 
77 #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
78 #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
79 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \
80  ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
81 
88 #define RCC_PLLSource_HSI ((uint32_t)0x00000000)
89 #define RCC_PLLSource_HSE ((uint32_t)0x00400000)
90 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
91  ((SOURCE) == RCC_PLLSource_HSE))
92 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
93 #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
94 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
95 #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
96 
97 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
98 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
99 #define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
100 
101 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
102 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
103 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
104 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
105 
106 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
107 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
108 
109 #define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000)
110 #define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000)
111 #define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000)
112 #define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000)
113 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\
114  ((VALUE) == RCC_PLLSAIDivR_Div4) ||\
115  ((VALUE) == RCC_PLLSAIDivR_Div8) ||\
116  ((VALUE) == RCC_PLLSAIDivR_Div16))
117 
125 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
126 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
127 #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
128 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
129  ((SOURCE) == RCC_SYSCLKSource_HSE) || \
130  ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
131 
138 #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
139 #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
140 #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
141 #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
142 #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
143 #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
144 #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
145 #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
146 #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
147 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
148  ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
149  ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
150  ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
151  ((HCLK) == RCC_SYSCLK_Div512))
152 
159 #define RCC_HCLK_Div1 ((uint32_t)0x00000000)
160 #define RCC_HCLK_Div2 ((uint32_t)0x00001000)
161 #define RCC_HCLK_Div4 ((uint32_t)0x00001400)
162 #define RCC_HCLK_Div8 ((uint32_t)0x00001800)
163 #define RCC_HCLK_Div16 ((uint32_t)0x00001C00)
164 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
165  ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
166  ((PCLK) == RCC_HCLK_Div16))
167 
174 #define RCC_IT_LSIRDY ((uint8_t)0x01)
175 #define RCC_IT_LSERDY ((uint8_t)0x02)
176 #define RCC_IT_HSIRDY ((uint8_t)0x04)
177 #define RCC_IT_HSERDY ((uint8_t)0x08)
178 #define RCC_IT_PLLRDY ((uint8_t)0x10)
179 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
180 #define RCC_IT_PLLSAIRDY ((uint8_t)0x40)
181 #define RCC_IT_CSS ((uint8_t)0x80)
182 
183 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
184 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
185  ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
186  ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
187  ((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY))
188 #define IS_RCC_CLEAR_IT(IT)((IT) != 0x00)
189 
197 #define RCC_LSE_OFF ((uint8_t)0x00)
198 #define RCC_LSE_ON ((uint8_t)0x01)
199 #define RCC_LSE_Bypass ((uint8_t)0x04)
200 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
201  ((LSE) == RCC_LSE_Bypass))
202 
209 #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
210 #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
211 #define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300)
212 #define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300)
213 #define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300)
214 #define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300)
215 #define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300)
216 #define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300)
217 #define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300)
218 #define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300)
219 #define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300)
220 #define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300)
221 #define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300)
222 #define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300)
223 #define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300)
224 #define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300)
225 #define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300)
226 #define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300)
227 #define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300)
228 #define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300)
229 #define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300)
230 #define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300)
231 #define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300)
232 #define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300)
233 #define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300)
234 #define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300)
235 #define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300)
236 #define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300)
237 #define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300)
238 #define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300)
239 #define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300)
240 #define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300)
241 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
242  ((SOURCE) == RCC_RTCCLKSource_LSI) || \
243  ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
244  ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
245  ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
246  ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \
247  ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
248  ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
249  ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
250  ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \
251  ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
252  ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
253  ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
254  ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \
255  ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
256  ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
257  ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
258  ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
259  ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \
260  ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
261  ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
262  ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
263  ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
264  ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
265  ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
266  ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
267  ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
268  ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
269  ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \
270  ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \
271  ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
272  ((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
273 
280 #define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00)
281 #define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
282 
283 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
284 
291 #define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000)
292 #define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000)
293 #define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000)
294 
295 #define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\
296  ((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\
297  ((SOURCE) == RCC_SAIACLKSource_Ext))
298 
305 #define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000)
306 #define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000)
307 #define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000)
308 
309 #define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\
310  ((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\
311  ((SOURCE) == RCC_SAIBCLKSource_Ext))
312 
319 #define RCC_TIMPrescDesactivated ((uint8_t)0x00)
320 #define RCC_TIMPrescActivated ((uint8_t)0x01)
321 
322 #define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated))
323 
330 #define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001)
331 #define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002)
332 #define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)
333 #define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)
334 #define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010)
335 #define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)
336 #define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)
337 #define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)
338 #define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
339 #define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200)
340 #define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400)
341 #define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)
342 #define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000)
343 #define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)
344 #define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000)
345 #define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)
346 #define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000)
347 #define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)
348 #define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)
349 #define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)
350 #define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000)
351 #define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)
352 #define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)
353 #define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000)
354 #define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)
355 #define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)
356 #define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)
357 
358 #define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x810BE800) == 0x00) && ((PERIPH) != 0x00))
359 #define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD1FE800) == 0x00) && ((PERIPH) != 0x00))
360 #define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81106800) == 0x00) && ((PERIPH) != 0x00))
361 
369 #define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001)
370 #define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010)
371 #define RCC_AHB2Periph_HASH ((uint32_t)0x00000020)
372 #define RCC_AHB2Periph_RNG ((uint32_t)0x00000040)
373 #define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)
374 #define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
375 
382 #if defined (STM32F40_41xxx)
383 #define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
384 #endif /* STM32F40_41xxx */
385 
386 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
387 #define RCC_AHB3Periph_FMC ((uint32_t)0x00000001)
388 #endif /* STM32F427_437xx || STM32F429_439xx */
389 
390 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
391 
398 #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
399 #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
400 #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
401 #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
402 #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
403 #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
404 #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
405 #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
406 #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
407 #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
408 #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
409 #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
410 #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
411 #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
412 #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
413 #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
414 #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
415 #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
416 #define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)
417 #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
418 #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
419 #define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
420 #define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
421 #define RCC_APB1Periph_UART7 ((uint32_t)0x40000000)
422 #define RCC_APB1Periph_UART8 ((uint32_t)0x80000000)
423 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x09013600) == 0x00) && ((PERIPH) != 0x00))
424 
431 #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001)
432 #define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002)
433 #define RCC_APB2Periph_USART1 ((uint32_t)0x00000010)
434 #define RCC_APB2Periph_USART6 ((uint32_t)0x00000020)
435 #define RCC_APB2Periph_ADC ((uint32_t)0x00000100)
436 #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100)
437 #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200)
438 #define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400)
439 #define RCC_APB2Periph_SDIO ((uint32_t)0x00000800)
440 #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
441 #define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000)
442 #define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)
443 #define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000)
444 #define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)
445 #define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)
446 #define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000)
447 #define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000)
448 #define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000)
449 #define RCC_APB2Periph_LTDC ((uint32_t)0x04000000)
450 
451 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFB8880CC) == 0x00) && ((PERIPH) != 0x00))
452 #define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFB8886CC) == 0x00) && ((PERIPH) != 0x00))
453 
461 #define RCC_MCO1Source_HSI ((uint32_t)0x00000000)
462 #define RCC_MCO1Source_LSE ((uint32_t)0x00200000)
463 #define RCC_MCO1Source_HSE ((uint32_t)0x00400000)
464 #define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000)
465 #define RCC_MCO1Div_1 ((uint32_t)0x00000000)
466 #define RCC_MCO1Div_2 ((uint32_t)0x04000000)
467 #define RCC_MCO1Div_3 ((uint32_t)0x05000000)
468 #define RCC_MCO1Div_4 ((uint32_t)0x06000000)
469 #define RCC_MCO1Div_5 ((uint32_t)0x07000000)
470 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
471  ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
472 
473 #define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
474  ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
475  ((DIV) == RCC_MCO1Div_5))
476 
483 #define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000)
484 #define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000)
485 #define RCC_MCO2Source_HSE ((uint32_t)0x80000000)
486 #define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000)
487 #define RCC_MCO2Div_1 ((uint32_t)0x00000000)
488 #define RCC_MCO2Div_2 ((uint32_t)0x20000000)
489 #define RCC_MCO2Div_3 ((uint32_t)0x28000000)
490 #define RCC_MCO2Div_4 ((uint32_t)0x30000000)
491 #define RCC_MCO2Div_5 ((uint32_t)0x38000000)
492 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
493  ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
494 
495 #define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
496  ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
497  ((DIV) == RCC_MCO2Div_5))
498 
505 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
506 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
507 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
508 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
509 #define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D)
510 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
511 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
512 #define RCC_FLAG_BORRST ((uint8_t)0x79)
513 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
514 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
515 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
516 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
517 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
518 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
519 
520 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
521  ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
522  ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
523  ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
524  ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
525  ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \
526  ((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY))
527 
528 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
529 
537 /* Exported macro ------------------------------------------------------------*/
538 /* Exported functions --------------------------------------------------------*/
539 
540 /* Function used to set the RCC clock configuration to the default reset state */
541 void RCC_DeInit(void);
542 
543 /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
544 void RCC_HSEConfig(uint8_t RCC_HSE);
545 ErrorStatus RCC_WaitForHSEStartUp(void);
546 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
547 void RCC_HSICmd(FunctionalState NewState);
548 void RCC_LSEConfig(uint8_t RCC_LSE);
549 void RCC_LSICmd(FunctionalState NewState);
550 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
551 void RCC_PLLCmd(FunctionalState NewState);
552 
553 #if defined (STM32F40_41xxx) || defined (STM32F401xx)
554 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
555 #elif defined (STM32F411xE)
556 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM);
557 #elif defined (STM32F427_437xx) || defined (STM32F429_439xx)
558 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR);
559 #else
560 #endif /* STM32F40_41xxx || STM32F401xx */
561 
562 void RCC_PLLI2SCmd(FunctionalState NewState);
563 void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR);
564 void RCC_PLLSAICmd(FunctionalState NewState);
565 void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
566 void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
567 void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
568 
569 /* System, AHB and APB busses clocks configuration functions ******************/
570 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
571 uint8_t RCC_GetSYSCLKSource(void);
572 void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
573 void RCC_PCLK1Config(uint32_t RCC_HCLK);
574 void RCC_PCLK2Config(uint32_t RCC_HCLK);
575 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
576 
577 /* Peripheral clocks configuration functions **********************************/
578 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
579 void RCC_RTCCLKCmd(FunctionalState NewState);
580 void RCC_BackupResetCmd(FunctionalState NewState);
581 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
582 void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ);
583 void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ);
584 void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource);
585 void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource);
586 void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR);
587 void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);
588 
589 void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
590 void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
591 void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
592 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
593 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
594 
595 void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
596 void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
597 void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
598 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
599 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
600 
601 void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
602 void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
603 void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
604 void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
605 void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
606 
607 void RCC_LSEModeConfig(uint8_t Mode);
608 
609 /* Interrupts and flags management functions **********************************/
610 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
611 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
612 void RCC_ClearFlag(void);
613 ITStatus RCC_GetITStatus(uint8_t RCC_IT);
614 void RCC_ClearITPendingBit(uint8_t RCC_IT);
615 
616 #ifdef __cplusplus
617 }
618 #endif
619 
620 #endif /* __STM32F4xx_RCC_H */
621 
630 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RCC_ClocksTypeDef::HCLK_Frequency
uint32_t HCLK_Frequency
Definition: stm32f4xx_rcc.h:51
RCC_AHB3PeriphClockCmd
void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
Enables or disables the AHB3 peripheral clock.
Definition: stm32f4xx_rcc.c:1586
RCC_ClearFlag
void RCC_ClearFlag(void)
Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
Definition: stm32f4xx_rcc.c:2227
RCC_PCLK1Config
void RCC_PCLK1Config(uint32_t RCC_HCLK)
Configures the Low Speed APB clock (PCLK1).
Definition: stm32f4xx_rcc.c:1014
RCC_GetITStatus
ITStatus RCC_GetITStatus(uint8_t RCC_IT)
Checks whether the specified RCC interrupt has occurred or not.
Definition: stm32f4xx_rcc.c:2247
RCC_ClearITPendingBit
void RCC_ClearITPendingBit(uint8_t RCC_IT)
Clears the RCC's interrupt pending bits.
Definition: stm32f4xx_rcc.c:2281
RCC_ClockSecuritySystemCmd
void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
Enables or disables the Clock Security System.
Definition: stm32f4xx_rcc.c:671
RCC_APB2PeriphClockCmd
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the High Speed APB (APB2) peripheral clock.
Definition: stm32f4xx_rcc.c:1683
RCC_GetFlagStatus
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
Checks whether the specified RCC flag is set or not.
Definition: stm32f4xx_rcc.c:2182
RCC_DeInit
void RCC_DeInit(void)
Resets the RCC clock configuration to the default reset state.
Definition: stm32f4xx_rcc.c:213
RCC_ClocksTypeDef::SYSCLK_Frequency
uint32_t SYSCLK_Frequency
Definition: stm32f4xx_rcc.h:50
RCC_AHB2PeriphClockCmd
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
Enables or disables the AHB2 peripheral clock.
Definition: stm32f4xx_rcc.c:1558
RCC_AHB3PeriphClockLPModeCmd
void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
Definition: stm32f4xx_rcc.c:1978
RCC_AHB2PeriphClockLPModeCmd
void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.
Definition: stm32f4xx_rcc.c:1950
RCC_HSICmd
void RCC_HSICmd(FunctionalState NewState)
Enables or disables the Internal High Speed oscillator (HSI).
Definition: stm32f4xx_rcc.c:354
stm32f4xx.h
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
RCC_RTCCLKConfig
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
Configures the RTC clock (RTCCLK).
Definition: stm32f4xx_rcc.c:1222
RCC_SAIPLLI2SClkDivConfig
void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ)
Configures the SAI clock Divider coming from PLLI2S.
Definition: stm32f4xx_rcc.c:1309
RCC_APB1PeriphClockLPModeCmd
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
Definition: stm32f4xx_rcc.c:2030
RCC_LSICmd
void RCC_LSICmd(FunctionalState NewState)
Enables or disables the Internal Low Speed oscillator (LSI).
Definition: stm32f4xx_rcc.c:419
RCC_PLLI2SCmd
void RCC_PLLI2SCmd(FunctionalState NewState)
Enables or disables the PLLI2S.
Definition: stm32f4xx_rcc.c:606
RCC_PLLSAICmd
void RCC_PLLSAICmd(FunctionalState NewState)
Enables or disables the PLLSAI.
Definition: stm32f4xx_rcc.c:653
RCC_ITConfig
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
Enables or disables the specified RCC interrupts.
Definition: stm32f4xx_rcc.c:2145
RCC_PCLK2Config
void RCC_PCLK2Config(uint32_t RCC_HCLK)
Configures the High Speed APB clock (PCLK2).
Definition: stm32f4xx_rcc.c:1045
RCC_RTCCLKCmd
void RCC_RTCCLKCmd(FunctionalState NewState)
Enables or disables the RTC clock.
Definition: stm32f4xx_rcc.c:1254
RCC_LSEModeConfig
void RCC_LSEModeConfig(uint8_t Mode)
Configures the External Low Speed oscillator mode (LSE mode).
Definition: stm32f4xx_rcc.c:2099
RCC_AHB3PeriphResetCmd
void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
Forces or releases AHB3 peripheral reset.
Definition: stm32f4xx_rcc.c:1779
RCC_AdjustHSICalibrationValue
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
Adjusts the Internal High Speed oscillator (HSI) calibration value.
Definition: stm32f4xx_rcc.c:318
RCC_AHB1PeriphClockLPModeCmd
void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
Definition: stm32f4xx_rcc.c:1918
RCC_PLLSAIConfig
void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR)
Configures the PLLSAI clock multiplication and division factors.
Definition: stm32f4xx_rcc.c:635
RCC_PLLConfig
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
Configures the main PLL clock source, multiplication and division factors.
Definition: stm32f4xx_rcc.c:462
RCC_MCO1Config
void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
Selects the clock source to output on MCO1 pin(PA8).
Definition: stm32f4xx_rcc.c:696
RCC_LTDCCLKDivConfig
void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR)
Configures the LTDC clock Divider coming from PLLSAI.
Definition: stm32f4xx_rcc.c:1446
RCC_TIMCLKPresConfig
void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler)
Configures the Timers clocks prescalers selection.
Definition: stm32f4xx_rcc.c:1483
RCC_SAIBlockACLKConfig
void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource)
Configures SAI1BlockA clock source selection.
Definition: stm32f4xx_rcc.c:1377
RCC_AHB1PeriphClockCmd
void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
Enables or disables the AHB1 peripheral clock.
Definition: stm32f4xx_rcc.c:1526
RCC_MCO2Config
void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
Selects the clock source to output on MCO2 pin(PC9).
Definition: stm32f4xx_rcc.c:734
RCC_WaitForHSEStartUp
ErrorStatus RCC_WaitForHSEStartUp(void)
Waits for HSE start-up.
Definition: stm32f4xx_rcc.c:287
RCC_APB2PeriphClockLPModeCmd
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
Definition: stm32f4xx_rcc.c:2075
RCC_I2SCLKConfig
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
Configures the I2S clock source (I2SCLK).
Definition: stm32f4xx_rcc.c:1288
RCC_AHB2PeriphResetCmd
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
Forces or releases AHB2 peripheral reset.
Definition: stm32f4xx_rcc.c:1754
RCC_ClocksTypeDef::PCLK1_Frequency
uint32_t PCLK1_Frequency
Definition: stm32f4xx_rcc.h:52
RCC_HCLKConfig
void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
Configures the AHB clock (HCLK).
Definition: stm32f4xx_rcc.c:982
RCC_GetSYSCLKSource
uint8_t RCC_GetSYSCLKSource(void)
Returns the clock source used as system clock.
Definition: stm32f4xx_rcc.c:957
RCC_APB1PeriphClockCmd
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the Low Speed APB (APB1) peripheral clock.
Definition: stm32f4xx_rcc.c:1638
RCC_HSEConfig
void RCC_HSEConfig(uint8_t RCC_HSE)
Configures the External High Speed oscillator (HSE).
Definition: stm32f4xx_rcc.c:263
RCC_AHB1PeriphResetCmd
void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
Forces or releases AHB1 peripheral reset.
Definition: stm32f4xx_rcc.c:1725
RCC_APB1PeriphResetCmd
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
Definition: stm32f4xx_rcc.c:1828
RCC_ClocksTypeDef::PCLK2_Frequency
uint32_t PCLK2_Frequency
Definition: stm32f4xx_rcc.h:53
RCC_GetClocksFreq
void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks)
Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2.
Definition: stm32f4xx_rcc.c:1097
RCC_SAIBlockBCLKConfig
void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource)
Configures SAI1BlockB clock source selection.
Definition: stm32f4xx_rcc.c:1413
RCC_APB2PeriphResetCmd
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
Definition: stm32f4xx_rcc.c:1869
RCC_SYSCLKConfig
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
Configures the system clock (SYSCLK).
Definition: stm32f4xx_rcc.c:929
RCC_LSEConfig
void RCC_LSEConfig(uint8_t RCC_LSE)
Configures the External Low Speed oscillator (LSE).
Definition: stm32f4xx_rcc.c:379
RCC_SAIPLLSAIClkDivConfig
void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ)
Configures the SAI clock Divider coming from PLLSAI.
Definition: stm32f4xx_rcc.c:1341
RCC_ClocksTypeDef
Definition: stm32f4xx_rcc.h:48
RCC_BackupResetCmd
void RCC_BackupResetCmd(FunctionalState NewState)
Forces or releases the Backup domain reset.
Definition: stm32f4xx_rcc.c:1271
RCC_PLLCmd
void RCC_PLLCmd(FunctionalState NewState)
Enables or disables the main PLL.
Definition: stm32f4xx_rcc.c:485
Generated on Sun May 10 2015 15:15:17 for discoverpixy by   doxygen 1.8.9.1