discoverpixy
stm32f4xx.h
Go to the documentation of this file.
1 
53 #ifndef __STM32F4xx_H
54 #define __STM32F4xx_H
55 
56 #ifdef __cplusplus
57  extern "C" {
58 #endif /* __cplusplus */
59 
64 /* Uncomment the line below according to the target STM32 device used in your
65  application
66  */
67 
68 #if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) && !defined (STM32F411xE)
69  #define STM32F40_41xxx
73  /* #define STM32F427_437xx */
76  /* #define STM32F429_439xx */
81  /* #define STM32F401xx */
84  /* #define STM32F411xE */
85 #endif
86 
87 /* Old STM32F40XX definition, maintained for legacy purpose */
88 #ifdef STM32F40XX
89  #define STM32F40_41xxx
90 #endif /* STM32F40XX */
91 
92 /* Old STM32F427X definition, maintained for legacy purpose */
93 #ifdef STM32F427X
94  #define STM32F427_437xx
95 #endif /* STM32F427X */
96 
97 /* Tip: To avoid modifying this file each time you need to switch between these
98  devices, you can define the device in your toolchain compiler preprocessor.
99  */
100 
101 #if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) && !defined (STM32F411xE)
102  #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
103 #endif
104 
105 #if !defined (USE_STDPERIPH_DRIVER)
106 
111  #define USE_STDPERIPH_DRIVER
112 #endif /* USE_STDPERIPH_DRIVER */
113 
122 #if !defined (HSE_VALUE)
123  //#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
124  #define HSE_VALUE ((uint32_t)8000000)
125 #endif /* HSE_VALUE */
126 
131 #if !defined (HSE_STARTUP_TIMEOUT)
132  #define HSE_STARTUP_TIMEOUT ((uint16_t)0x05000)
133 #endif /* HSE_STARTUP_TIMEOUT */
134 
135 #if !defined (HSI_VALUE)
136  #define HSI_VALUE ((uint32_t)16000000)
137 #endif /* HSI_VALUE */
138 
142 #define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01)
143 #define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x04)
144 #define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00)
145 #define __STM32F4XX_STDPERIPH_VERSION_RC (0x00)
146 #define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\
147  |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\
148  |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\
149  |(__STM32F4XX_STDPERIPH_VERSION_RC))
150 
162 #define __CM4_REV 0x0001
163 #define __MPU_PRESENT 1
164 #define __NVIC_PRIO_BITS 4
165 #define __Vendor_SysTickConfig 0
166 #define __FPU_PRESENT 1
172 typedef enum IRQn
173 {
174 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
175  NonMaskableInt_IRQn = -14,
176  MemoryManagement_IRQn = -12,
177  BusFault_IRQn = -11,
178  UsageFault_IRQn = -10,
179  SVCall_IRQn = -5,
180  DebugMonitor_IRQn = -4,
181  PendSV_IRQn = -2,
182  SysTick_IRQn = -1,
183 /****** STM32 specific Interrupt Numbers **********************************************************************/
184  WWDG_IRQn = 0,
185  PVD_IRQn = 1,
186  TAMP_STAMP_IRQn = 2,
187  RTC_WKUP_IRQn = 3,
188  FLASH_IRQn = 4,
189  RCC_IRQn = 5,
190  EXTI0_IRQn = 6,
191  EXTI1_IRQn = 7,
192  EXTI2_IRQn = 8,
193  EXTI3_IRQn = 9,
194  EXTI4_IRQn = 10,
195  DMA1_Stream0_IRQn = 11,
196  DMA1_Stream1_IRQn = 12,
197  DMA1_Stream2_IRQn = 13,
198  DMA1_Stream3_IRQn = 14,
199  DMA1_Stream4_IRQn = 15,
200  DMA1_Stream5_IRQn = 16,
201  DMA1_Stream6_IRQn = 17,
202  ADC_IRQn = 18,
204 #if defined (STM32F40_41xxx)
205  CAN1_TX_IRQn = 19,
206  CAN1_RX0_IRQn = 20,
207  CAN1_RX1_IRQn = 21,
208  CAN1_SCE_IRQn = 22,
209  EXTI9_5_IRQn = 23,
210  TIM1_BRK_TIM9_IRQn = 24,
211  TIM1_UP_TIM10_IRQn = 25,
212  TIM1_TRG_COM_TIM11_IRQn = 26,
213  TIM1_CC_IRQn = 27,
214  TIM2_IRQn = 28,
215  TIM3_IRQn = 29,
216  TIM4_IRQn = 30,
217  I2C1_EV_IRQn = 31,
218  I2C1_ER_IRQn = 32,
219  I2C2_EV_IRQn = 33,
220  I2C2_ER_IRQn = 34,
221  SPI1_IRQn = 35,
222  SPI2_IRQn = 36,
223  USART1_IRQn = 37,
224  USART2_IRQn = 38,
225  USART3_IRQn = 39,
226  EXTI15_10_IRQn = 40,
227  RTC_Alarm_IRQn = 41,
228  OTG_FS_WKUP_IRQn = 42,
229  TIM8_BRK_TIM12_IRQn = 43,
230  TIM8_UP_TIM13_IRQn = 44,
231  TIM8_TRG_COM_TIM14_IRQn = 45,
232  TIM8_CC_IRQn = 46,
233  DMA1_Stream7_IRQn = 47,
234  FSMC_IRQn = 48,
235  SDIO_IRQn = 49,
236  TIM5_IRQn = 50,
237  SPI3_IRQn = 51,
238  UART4_IRQn = 52,
239  UART5_IRQn = 53,
240  TIM6_DAC_IRQn = 54,
241  TIM7_IRQn = 55,
242  DMA2_Stream0_IRQn = 56,
243  DMA2_Stream1_IRQn = 57,
244  DMA2_Stream2_IRQn = 58,
245  DMA2_Stream3_IRQn = 59,
246  DMA2_Stream4_IRQn = 60,
247  ETH_IRQn = 61,
248  ETH_WKUP_IRQn = 62,
249  CAN2_TX_IRQn = 63,
250  CAN2_RX0_IRQn = 64,
251  CAN2_RX1_IRQn = 65,
252  CAN2_SCE_IRQn = 66,
253  OTG_FS_IRQn = 67,
254  DMA2_Stream5_IRQn = 68,
255  DMA2_Stream6_IRQn = 69,
256  DMA2_Stream7_IRQn = 70,
257  USART6_IRQn = 71,
258  I2C3_EV_IRQn = 72,
259  I2C3_ER_IRQn = 73,
260  OTG_HS_EP1_OUT_IRQn = 74,
261  OTG_HS_EP1_IN_IRQn = 75,
262  OTG_HS_WKUP_IRQn = 76,
263  OTG_HS_IRQn = 77,
264  DCMI_IRQn = 78,
265  CRYP_IRQn = 79,
266  HASH_RNG_IRQn = 80,
267  FPU_IRQn = 81
268 #endif /* STM32F40_41xxx */
269 
270 #if defined (STM32F427_437xx)
271  CAN1_TX_IRQn = 19,
272  CAN1_RX0_IRQn = 20,
273  CAN1_RX1_IRQn = 21,
274  CAN1_SCE_IRQn = 22,
275  EXTI9_5_IRQn = 23,
276  TIM1_BRK_TIM9_IRQn = 24,
277  TIM1_UP_TIM10_IRQn = 25,
278  TIM1_TRG_COM_TIM11_IRQn = 26,
279  TIM1_CC_IRQn = 27,
280  TIM2_IRQn = 28,
281  TIM3_IRQn = 29,
282  TIM4_IRQn = 30,
283  I2C1_EV_IRQn = 31,
284  I2C1_ER_IRQn = 32,
285  I2C2_EV_IRQn = 33,
286  I2C2_ER_IRQn = 34,
287  SPI1_IRQn = 35,
288  SPI2_IRQn = 36,
289  USART1_IRQn = 37,
290  USART2_IRQn = 38,
291  USART3_IRQn = 39,
292  EXTI15_10_IRQn = 40,
293  RTC_Alarm_IRQn = 41,
294  OTG_FS_WKUP_IRQn = 42,
295  TIM8_BRK_TIM12_IRQn = 43,
296  TIM8_UP_TIM13_IRQn = 44,
297  TIM8_TRG_COM_TIM14_IRQn = 45,
298  TIM8_CC_IRQn = 46,
299  DMA1_Stream7_IRQn = 47,
300  FMC_IRQn = 48,
301  SDIO_IRQn = 49,
302  TIM5_IRQn = 50,
303  SPI3_IRQn = 51,
304  UART4_IRQn = 52,
305  UART5_IRQn = 53,
306  TIM6_DAC_IRQn = 54,
307  TIM7_IRQn = 55,
308  DMA2_Stream0_IRQn = 56,
309  DMA2_Stream1_IRQn = 57,
310  DMA2_Stream2_IRQn = 58,
311  DMA2_Stream3_IRQn = 59,
312  DMA2_Stream4_IRQn = 60,
313  ETH_IRQn = 61,
314  ETH_WKUP_IRQn = 62,
315  CAN2_TX_IRQn = 63,
316  CAN2_RX0_IRQn = 64,
317  CAN2_RX1_IRQn = 65,
318  CAN2_SCE_IRQn = 66,
319  OTG_FS_IRQn = 67,
320  DMA2_Stream5_IRQn = 68,
321  DMA2_Stream6_IRQn = 69,
322  DMA2_Stream7_IRQn = 70,
323  USART6_IRQn = 71,
324  I2C3_EV_IRQn = 72,
325  I2C3_ER_IRQn = 73,
326  OTG_HS_EP1_OUT_IRQn = 74,
327  OTG_HS_EP1_IN_IRQn = 75,
328  OTG_HS_WKUP_IRQn = 76,
329  OTG_HS_IRQn = 77,
330  DCMI_IRQn = 78,
331  CRYP_IRQn = 79,
332  HASH_RNG_IRQn = 80,
333  FPU_IRQn = 81,
334  UART7_IRQn = 82,
335  UART8_IRQn = 83,
336  SPI4_IRQn = 84,
337  SPI5_IRQn = 85,
338  SPI6_IRQn = 86,
339  SAI1_IRQn = 87,
340  DMA2D_IRQn = 90
341 #endif /* STM32F427_437xx */
342 
343 #if defined (STM32F429_439xx)
344  CAN1_TX_IRQn = 19,
345  CAN1_RX0_IRQn = 20,
346  CAN1_RX1_IRQn = 21,
347  CAN1_SCE_IRQn = 22,
348  EXTI9_5_IRQn = 23,
349  TIM1_BRK_TIM9_IRQn = 24,
350  TIM1_UP_TIM10_IRQn = 25,
351  TIM1_TRG_COM_TIM11_IRQn = 26,
352  TIM1_CC_IRQn = 27,
353  TIM2_IRQn = 28,
354  TIM3_IRQn = 29,
355  TIM4_IRQn = 30,
356  I2C1_EV_IRQn = 31,
357  I2C1_ER_IRQn = 32,
358  I2C2_EV_IRQn = 33,
359  I2C2_ER_IRQn = 34,
360  SPI1_IRQn = 35,
361  SPI2_IRQn = 36,
362  USART1_IRQn = 37,
363  USART2_IRQn = 38,
364  USART3_IRQn = 39,
365  EXTI15_10_IRQn = 40,
366  RTC_Alarm_IRQn = 41,
367  OTG_FS_WKUP_IRQn = 42,
368  TIM8_BRK_TIM12_IRQn = 43,
369  TIM8_UP_TIM13_IRQn = 44,
370  TIM8_TRG_COM_TIM14_IRQn = 45,
371  TIM8_CC_IRQn = 46,
372  DMA1_Stream7_IRQn = 47,
373  FMC_IRQn = 48,
374  SDIO_IRQn = 49,
375  TIM5_IRQn = 50,
376  SPI3_IRQn = 51,
377  UART4_IRQn = 52,
378  UART5_IRQn = 53,
379  TIM6_DAC_IRQn = 54,
380  TIM7_IRQn = 55,
381  DMA2_Stream0_IRQn = 56,
382  DMA2_Stream1_IRQn = 57,
383  DMA2_Stream2_IRQn = 58,
384  DMA2_Stream3_IRQn = 59,
385  DMA2_Stream4_IRQn = 60,
386  ETH_IRQn = 61,
387  ETH_WKUP_IRQn = 62,
388  CAN2_TX_IRQn = 63,
389  CAN2_RX0_IRQn = 64,
390  CAN2_RX1_IRQn = 65,
391  CAN2_SCE_IRQn = 66,
392  OTG_FS_IRQn = 67,
393  DMA2_Stream5_IRQn = 68,
394  DMA2_Stream6_IRQn = 69,
395  DMA2_Stream7_IRQn = 70,
396  USART6_IRQn = 71,
397  I2C3_EV_IRQn = 72,
398  I2C3_ER_IRQn = 73,
399  OTG_HS_EP1_OUT_IRQn = 74,
400  OTG_HS_EP1_IN_IRQn = 75,
401  OTG_HS_WKUP_IRQn = 76,
402  OTG_HS_IRQn = 77,
403  DCMI_IRQn = 78,
404  CRYP_IRQn = 79,
405  HASH_RNG_IRQn = 80,
406  FPU_IRQn = 81,
407  UART7_IRQn = 82,
408  UART8_IRQn = 83,
409  SPI4_IRQn = 84,
410  SPI5_IRQn = 85,
411  SPI6_IRQn = 86,
412  SAI1_IRQn = 87,
413  LTDC_IRQn = 88,
414  LTDC_ER_IRQn = 89,
415  DMA2D_IRQn = 90
416 #endif /* STM32F429_439xx */
417 
418 #if defined (STM32F401xx) || defined (STM32F411xE)
419  EXTI9_5_IRQn = 23,
420  TIM1_BRK_TIM9_IRQn = 24,
421  TIM1_UP_TIM10_IRQn = 25,
422  TIM1_TRG_COM_TIM11_IRQn = 26,
423  TIM1_CC_IRQn = 27,
424  TIM2_IRQn = 28,
425  TIM3_IRQn = 29,
426  TIM4_IRQn = 30,
427  I2C1_EV_IRQn = 31,
428  I2C1_ER_IRQn = 32,
429  I2C2_EV_IRQn = 33,
430  I2C2_ER_IRQn = 34,
431  SPI1_IRQn = 35,
432  SPI2_IRQn = 36,
433  USART1_IRQn = 37,
434  USART2_IRQn = 38,
435  EXTI15_10_IRQn = 40,
436  RTC_Alarm_IRQn = 41,
437  OTG_FS_WKUP_IRQn = 42,
438  DMA1_Stream7_IRQn = 47,
439  SDIO_IRQn = 49,
440  TIM5_IRQn = 50,
441  SPI3_IRQn = 51,
442  DMA2_Stream0_IRQn = 56,
443  DMA2_Stream1_IRQn = 57,
444  DMA2_Stream2_IRQn = 58,
445  DMA2_Stream3_IRQn = 59,
446  DMA2_Stream4_IRQn = 60,
447  OTG_FS_IRQn = 67,
448  DMA2_Stream5_IRQn = 68,
449  DMA2_Stream6_IRQn = 69,
450  DMA2_Stream7_IRQn = 70,
451  USART6_IRQn = 71,
452  I2C3_EV_IRQn = 72,
453  I2C3_ER_IRQn = 73,
454  FPU_IRQn = 81,
455 #if defined (STM32F401xx)
456  SPI4_IRQn = 84
457 #endif /* STM32F411xE */
458 #if defined (STM32F411xE)
459  SPI4_IRQn = 84,
460  SPI5_IRQn = 85
461 #endif /* STM32F411xE */
462 #endif /* STM32F401xx || STM32F411xE */
463 
464 } IRQn_Type;
465 
470 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
471 #include "system_stm32f4xx.h"
472 #include <stdint.h>
473 
478 typedef int32_t s32;
479 typedef int16_t s16;
480 typedef int8_t s8;
481 
482 typedef const int32_t sc32;
483 typedef const int16_t sc16;
484 typedef const int8_t sc8;
486 typedef __IO int32_t vs32;
487 typedef __IO int16_t vs16;
488 typedef __IO int8_t vs8;
489 
490 typedef __I int32_t vsc32;
491 typedef __I int16_t vsc16;
492 typedef __I int8_t vsc8;
494 typedef uint32_t u32;
495 typedef uint16_t u16;
496 typedef uint8_t u8;
497 
498 typedef const uint32_t uc32;
499 typedef const uint16_t uc16;
500 typedef const uint8_t uc8;
502 typedef __IO uint32_t vu32;
503 typedef __IO uint16_t vu16;
504 typedef __IO uint8_t vu8;
505 
506 typedef __I uint32_t vuc32;
507 typedef __I uint16_t vuc16;
508 typedef __I uint8_t vuc8;
510 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
511 
512 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
513 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
514 
515 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
516 
529 typedef struct
530 {
531  __IO uint32_t SR;
532  __IO uint32_t CR1;
533  __IO uint32_t CR2;
534  __IO uint32_t SMPR1;
535  __IO uint32_t SMPR2;
536  __IO uint32_t JOFR1;
537  __IO uint32_t JOFR2;
538  __IO uint32_t JOFR3;
539  __IO uint32_t JOFR4;
540  __IO uint32_t HTR;
541  __IO uint32_t LTR;
542  __IO uint32_t SQR1;
543  __IO uint32_t SQR2;
544  __IO uint32_t SQR3;
545  __IO uint32_t JSQR;
546  __IO uint32_t JDR1;
547  __IO uint32_t JDR2;
548  __IO uint32_t JDR3;
549  __IO uint32_t JDR4;
550  __IO uint32_t DR;
551 } ADC_TypeDef;
552 
553 typedef struct
554 {
555  __IO uint32_t CSR;
556  __IO uint32_t CCR;
557  __IO uint32_t CDR;
559 } ADC_Common_TypeDef;
560 
561 
566 typedef struct
567 {
568  __IO uint32_t TIR;
569  __IO uint32_t TDTR;
570  __IO uint32_t TDLR;
571  __IO uint32_t TDHR;
572 } CAN_TxMailBox_TypeDef;
573 
578 typedef struct
579 {
580  __IO uint32_t RIR;
581  __IO uint32_t RDTR;
582  __IO uint32_t RDLR;
583  __IO uint32_t RDHR;
584 } CAN_FIFOMailBox_TypeDef;
585 
590 typedef struct
591 {
592  __IO uint32_t FR1;
593  __IO uint32_t FR2;
594 } CAN_FilterRegister_TypeDef;
595 
600 typedef struct
601 {
602  __IO uint32_t MCR;
603  __IO uint32_t MSR;
604  __IO uint32_t TSR;
605  __IO uint32_t RF0R;
606  __IO uint32_t RF1R;
607  __IO uint32_t IER;
608  __IO uint32_t ESR;
609  __IO uint32_t BTR;
610  uint32_t RESERVED0[88];
611  CAN_TxMailBox_TypeDef sTxMailBox[3];
612  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
613  uint32_t RESERVED1[12];
614  __IO uint32_t FMR;
615  __IO uint32_t FM1R;
616  uint32_t RESERVED2;
617  __IO uint32_t FS1R;
618  uint32_t RESERVED3;
619  __IO uint32_t FFA1R;
620  uint32_t RESERVED4;
621  __IO uint32_t FA1R;
622  uint32_t RESERVED5[8];
623  CAN_FilterRegister_TypeDef sFilterRegister[28];
624 } CAN_TypeDef;
625 
630 typedef struct
631 {
632  __IO uint32_t DR;
633  __IO uint8_t IDR;
634  uint8_t RESERVED0;
635  uint16_t RESERVED1;
636  __IO uint32_t CR;
637 } CRC_TypeDef;
638 
643 typedef struct
644 {
645  __IO uint32_t CR;
646  __IO uint32_t SWTRIGR;
647  __IO uint32_t DHR12R1;
648  __IO uint32_t DHR12L1;
649  __IO uint32_t DHR8R1;
650  __IO uint32_t DHR12R2;
651  __IO uint32_t DHR12L2;
652  __IO uint32_t DHR8R2;
653  __IO uint32_t DHR12RD;
654  __IO uint32_t DHR12LD;
655  __IO uint32_t DHR8RD;
656  __IO uint32_t DOR1;
657  __IO uint32_t DOR2;
658  __IO uint32_t SR;
659 } DAC_TypeDef;
660 
665 typedef struct
666 {
667  __IO uint32_t IDCODE;
668  __IO uint32_t CR;
669  __IO uint32_t APB1FZ;
670  __IO uint32_t APB2FZ;
671 }DBGMCU_TypeDef;
672 
677 typedef struct
678 {
679  __IO uint32_t CR;
680  __IO uint32_t SR;
681  __IO uint32_t RISR;
682  __IO uint32_t IER;
683  __IO uint32_t MISR;
684  __IO uint32_t ICR;
685  __IO uint32_t ESCR;
686  __IO uint32_t ESUR;
687  __IO uint32_t CWSTRTR;
688  __IO uint32_t CWSIZER;
689  __IO uint32_t DR;
690 } DCMI_TypeDef;
691 
696 typedef struct
697 {
698  __IO uint32_t CR;
699  __IO uint32_t NDTR;
700  __IO uint32_t PAR;
701  __IO uint32_t M0AR;
702  __IO uint32_t M1AR;
703  __IO uint32_t FCR;
704 } DMA_Stream_TypeDef;
705 
706 typedef struct
707 {
708  __IO uint32_t LISR;
709  __IO uint32_t HISR;
710  __IO uint32_t LIFCR;
711  __IO uint32_t HIFCR;
712 } DMA_TypeDef;
713 
718 typedef struct
719 {
720  __IO uint32_t CR;
721  __IO uint32_t ISR;
722  __IO uint32_t IFCR;
723  __IO uint32_t FGMAR;
724  __IO uint32_t FGOR;
725  __IO uint32_t BGMAR;
726  __IO uint32_t BGOR;
727  __IO uint32_t FGPFCCR;
728  __IO uint32_t FGCOLR;
729  __IO uint32_t BGPFCCR;
730  __IO uint32_t BGCOLR;
731  __IO uint32_t FGCMAR;
732  __IO uint32_t BGCMAR;
733  __IO uint32_t OPFCCR;
734  __IO uint32_t OCOLR;
735  __IO uint32_t OMAR;
736  __IO uint32_t OOR;
737  __IO uint32_t NLR;
738  __IO uint32_t LWR;
739  __IO uint32_t AMTCR;
740  uint32_t RESERVED[236];
741  __IO uint32_t FGCLUT[256];
742  __IO uint32_t BGCLUT[256];
743 } DMA2D_TypeDef;
744 
749 typedef struct
750 {
751  __IO uint32_t MACCR;
752  __IO uint32_t MACFFR;
753  __IO uint32_t MACHTHR;
754  __IO uint32_t MACHTLR;
755  __IO uint32_t MACMIIAR;
756  __IO uint32_t MACMIIDR;
757  __IO uint32_t MACFCR;
758  __IO uint32_t MACVLANTR; /* 8 */
759  uint32_t RESERVED0[2];
760  __IO uint32_t MACRWUFFR; /* 11 */
761  __IO uint32_t MACPMTCSR;
762  uint32_t RESERVED1[2];
763  __IO uint32_t MACSR; /* 15 */
764  __IO uint32_t MACIMR;
765  __IO uint32_t MACA0HR;
766  __IO uint32_t MACA0LR;
767  __IO uint32_t MACA1HR;
768  __IO uint32_t MACA1LR;
769  __IO uint32_t MACA2HR;
770  __IO uint32_t MACA2LR;
771  __IO uint32_t MACA3HR;
772  __IO uint32_t MACA3LR; /* 24 */
773  uint32_t RESERVED2[40];
774  __IO uint32_t MMCCR; /* 65 */
775  __IO uint32_t MMCRIR;
776  __IO uint32_t MMCTIR;
777  __IO uint32_t MMCRIMR;
778  __IO uint32_t MMCTIMR; /* 69 */
779  uint32_t RESERVED3[14];
780  __IO uint32_t MMCTGFSCCR; /* 84 */
781  __IO uint32_t MMCTGFMSCCR;
782  uint32_t RESERVED4[5];
783  __IO uint32_t MMCTGFCR;
784  uint32_t RESERVED5[10];
785  __IO uint32_t MMCRFCECR;
786  __IO uint32_t MMCRFAECR;
787  uint32_t RESERVED6[10];
788  __IO uint32_t MMCRGUFCR;
789  uint32_t RESERVED7[334];
790  __IO uint32_t PTPTSCR;
791  __IO uint32_t PTPSSIR;
792  __IO uint32_t PTPTSHR;
793  __IO uint32_t PTPTSLR;
794  __IO uint32_t PTPTSHUR;
795  __IO uint32_t PTPTSLUR;
796  __IO uint32_t PTPTSAR;
797  __IO uint32_t PTPTTHR;
798  __IO uint32_t PTPTTLR;
799  __IO uint32_t RESERVED8;
800  __IO uint32_t PTPTSSR;
801  uint32_t RESERVED9[565];
802  __IO uint32_t DMABMR;
803  __IO uint32_t DMATPDR;
804  __IO uint32_t DMARPDR;
805  __IO uint32_t DMARDLAR;
806  __IO uint32_t DMATDLAR;
807  __IO uint32_t DMASR;
808  __IO uint32_t DMAOMR;
809  __IO uint32_t DMAIER;
810  __IO uint32_t DMAMFBOCR;
811  __IO uint32_t DMARSWTR;
812  uint32_t RESERVED10[8];
813  __IO uint32_t DMACHTDR;
814  __IO uint32_t DMACHRDR;
815  __IO uint32_t DMACHTBAR;
816  __IO uint32_t DMACHRBAR;
817 } ETH_TypeDef;
818 
823 typedef struct
824 {
825  __IO uint32_t IMR;
826  __IO uint32_t EMR;
827  __IO uint32_t RTSR;
828  __IO uint32_t FTSR;
829  __IO uint32_t SWIER;
830  __IO uint32_t PR;
831 } EXTI_TypeDef;
832 
837 typedef struct
838 {
839  __IO uint32_t ACR;
840  __IO uint32_t KEYR;
841  __IO uint32_t OPTKEYR;
842  __IO uint32_t SR;
843  __IO uint32_t CR;
844  __IO uint32_t OPTCR;
845  __IO uint32_t OPTCR1;
846 } FLASH_TypeDef;
847 
848 #if defined (STM32F40_41xxx)
849 
853 typedef struct
854 {
855  __IO uint32_t BTCR[8];
856 } FSMC_Bank1_TypeDef;
857 
862 typedef struct
863 {
864  __IO uint32_t BWTR[7];
865 } FSMC_Bank1E_TypeDef;
866 
871 typedef struct
872 {
873  __IO uint32_t PCR2;
874  __IO uint32_t SR2;
875  __IO uint32_t PMEM2;
876  __IO uint32_t PATT2;
877  uint32_t RESERVED0;
878  __IO uint32_t ECCR2;
879 } FSMC_Bank2_TypeDef;
880 
885 typedef struct
886 {
887  __IO uint32_t PCR3;
888  __IO uint32_t SR3;
889  __IO uint32_t PMEM3;
890  __IO uint32_t PATT3;
891  uint32_t RESERVED0;
892  __IO uint32_t ECCR3;
893 } FSMC_Bank3_TypeDef;
894 
899 typedef struct
900 {
901  __IO uint32_t PCR4;
902  __IO uint32_t SR4;
903  __IO uint32_t PMEM4;
904  __IO uint32_t PATT4;
905  __IO uint32_t PIO4;
906 } FSMC_Bank4_TypeDef;
907 #endif /* STM32F40_41xxx */
908 
909 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
910 
914 typedef struct
915 {
916  __IO uint32_t BTCR[8];
917 } FMC_Bank1_TypeDef;
918 
923 typedef struct
924 {
925  __IO uint32_t BWTR[7];
926 } FMC_Bank1E_TypeDef;
927 
932 typedef struct
933 {
934  __IO uint32_t PCR2;
935  __IO uint32_t SR2;
936  __IO uint32_t PMEM2;
937  __IO uint32_t PATT2;
938  uint32_t RESERVED0;
939  __IO uint32_t ECCR2;
940 } FMC_Bank2_TypeDef;
941 
946 typedef struct
947 {
948  __IO uint32_t PCR3;
949  __IO uint32_t SR3;
950  __IO uint32_t PMEM3;
951  __IO uint32_t PATT3;
952  uint32_t RESERVED0;
953  __IO uint32_t ECCR3;
954 } FMC_Bank3_TypeDef;
955 
960 typedef struct
961 {
962  __IO uint32_t PCR4;
963  __IO uint32_t SR4;
964  __IO uint32_t PMEM4;
965  __IO uint32_t PATT4;
966  __IO uint32_t PIO4;
967 } FMC_Bank4_TypeDef;
968 
973 typedef struct
974 {
975  __IO uint32_t SDCR[2];
976  __IO uint32_t SDTR[2];
977  __IO uint32_t SDCMR;
978  __IO uint32_t SDRTR;
979  __IO uint32_t SDSR;
980 } FMC_Bank5_6_TypeDef;
981 #endif /* STM32F427_437xx || STM32F429_439xx */
982 
987 typedef struct
988 {
989  __IO uint32_t MODER;
990  __IO uint32_t OTYPER;
991  __IO uint32_t OSPEEDR;
992  __IO uint32_t PUPDR;
993  __IO uint32_t IDR;
994  __IO uint32_t ODR;
995  __IO uint16_t BSRRL;
996  __IO uint16_t BSRRH;
997  __IO uint32_t LCKR;
998  __IO uint32_t AFR[2];
999 } GPIO_TypeDef;
1000 
1005 typedef struct
1006 {
1007  __IO uint32_t MEMRMP;
1008  __IO uint32_t PMC;
1009  __IO uint32_t EXTICR[4];
1010  uint32_t RESERVED[2];
1011  __IO uint32_t CMPCR;
1012 } SYSCFG_TypeDef;
1013 
1018 typedef struct
1019 {
1020  __IO uint16_t CR1;
1021  uint16_t RESERVED0;
1022  __IO uint16_t CR2;
1023  uint16_t RESERVED1;
1024  __IO uint16_t OAR1;
1025  uint16_t RESERVED2;
1026  __IO uint16_t OAR2;
1027  uint16_t RESERVED3;
1028  __IO uint16_t DR;
1029  uint16_t RESERVED4;
1030  __IO uint16_t SR1;
1031  uint16_t RESERVED5;
1032  __IO uint16_t SR2;
1033  uint16_t RESERVED6;
1034  __IO uint16_t CCR;
1035  uint16_t RESERVED7;
1036  __IO uint16_t TRISE;
1037  uint16_t RESERVED8;
1038  __IO uint16_t FLTR;
1039  uint16_t RESERVED9;
1040 } I2C_TypeDef;
1041 
1046 typedef struct
1047 {
1048  __IO uint32_t KR;
1049  __IO uint32_t PR;
1050  __IO uint32_t RLR;
1051  __IO uint32_t SR;
1052 } IWDG_TypeDef;
1053 
1058 typedef struct
1059 {
1060  uint32_t RESERVED0[2];
1061  __IO uint32_t SSCR;
1062  __IO uint32_t BPCR;
1063  __IO uint32_t AWCR;
1064  __IO uint32_t TWCR;
1065  __IO uint32_t GCR;
1066  uint32_t RESERVED1[2];
1067  __IO uint32_t SRCR;
1068  uint32_t RESERVED2[1];
1069  __IO uint32_t BCCR;
1070  uint32_t RESERVED3[1];
1071  __IO uint32_t IER;
1072  __IO uint32_t ISR;
1073  __IO uint32_t ICR;
1074  __IO uint32_t LIPCR;
1075  __IO uint32_t CPSR;
1076  __IO uint32_t CDSR;
1077 } LTDC_TypeDef;
1078 
1083 typedef struct
1084 {
1085  __IO uint32_t CR;
1086  __IO uint32_t WHPCR;
1087  __IO uint32_t WVPCR;
1088  __IO uint32_t CKCR;
1089  __IO uint32_t PFCR;
1090  __IO uint32_t CACR;
1091  __IO uint32_t DCCR;
1092  __IO uint32_t BFCR;
1093  uint32_t RESERVED0[2];
1094  __IO uint32_t CFBAR;
1095  __IO uint32_t CFBLR;
1096  __IO uint32_t CFBLNR;
1097  uint32_t RESERVED1[3];
1098  __IO uint32_t CLUTWR;
1100 } LTDC_Layer_TypeDef;
1101 
1106 typedef struct
1107 {
1108  __IO uint32_t CR;
1109  __IO uint32_t CSR;
1110 } PWR_TypeDef;
1111 
1116 typedef struct
1117 {
1118  __IO uint32_t CR;
1119  __IO uint32_t PLLCFGR;
1120  __IO uint32_t CFGR;
1121  __IO uint32_t CIR;
1122  __IO uint32_t AHB1RSTR;
1123  __IO uint32_t AHB2RSTR;
1124  __IO uint32_t AHB3RSTR;
1125  uint32_t RESERVED0;
1126  __IO uint32_t APB1RSTR;
1127  __IO uint32_t APB2RSTR;
1128  uint32_t RESERVED1[2];
1129  __IO uint32_t AHB1ENR;
1130  __IO uint32_t AHB2ENR;
1131  __IO uint32_t AHB3ENR;
1132  uint32_t RESERVED2;
1133  __IO uint32_t APB1ENR;
1134  __IO uint32_t APB2ENR;
1135  uint32_t RESERVED3[2];
1136  __IO uint32_t AHB1LPENR;
1137  __IO uint32_t AHB2LPENR;
1138  __IO uint32_t AHB3LPENR;
1139  uint32_t RESERVED4;
1140  __IO uint32_t APB1LPENR;
1141  __IO uint32_t APB2LPENR;
1142  uint32_t RESERVED5[2];
1143  __IO uint32_t BDCR;
1144  __IO uint32_t CSR;
1145  uint32_t RESERVED6[2];
1146  __IO uint32_t SSCGR;
1147  __IO uint32_t PLLI2SCFGR;
1148  __IO uint32_t PLLSAICFGR;
1149  __IO uint32_t DCKCFGR;
1151 } RCC_TypeDef;
1152 
1157 typedef struct
1158 {
1159  __IO uint32_t TR;
1160  __IO uint32_t DR;
1161  __IO uint32_t CR;
1162  __IO uint32_t ISR;
1163  __IO uint32_t PRER;
1164  __IO uint32_t WUTR;
1165  __IO uint32_t CALIBR;
1166  __IO uint32_t ALRMAR;
1167  __IO uint32_t ALRMBR;
1168  __IO uint32_t WPR;
1169  __IO uint32_t SSR;
1170  __IO uint32_t SHIFTR;
1171  __IO uint32_t TSTR;
1172  __IO uint32_t TSDR;
1173  __IO uint32_t TSSSR;
1174  __IO uint32_t CALR;
1175  __IO uint32_t TAFCR;
1176  __IO uint32_t ALRMASSR;
1177  __IO uint32_t ALRMBSSR;
1178  uint32_t RESERVED7;
1179  __IO uint32_t BKP0R;
1180  __IO uint32_t BKP1R;
1181  __IO uint32_t BKP2R;
1182  __IO uint32_t BKP3R;
1183  __IO uint32_t BKP4R;
1184  __IO uint32_t BKP5R;
1185  __IO uint32_t BKP6R;
1186  __IO uint32_t BKP7R;
1187  __IO uint32_t BKP8R;
1188  __IO uint32_t BKP9R;
1189  __IO uint32_t BKP10R;
1190  __IO uint32_t BKP11R;
1191  __IO uint32_t BKP12R;
1192  __IO uint32_t BKP13R;
1193  __IO uint32_t BKP14R;
1194  __IO uint32_t BKP15R;
1195  __IO uint32_t BKP16R;
1196  __IO uint32_t BKP17R;
1197  __IO uint32_t BKP18R;
1198  __IO uint32_t BKP19R;
1199 } RTC_TypeDef;
1200 
1201 
1206 typedef struct
1207 {
1208  __IO uint32_t GCR;
1209 } SAI_TypeDef;
1210 
1211 typedef struct
1212 {
1213  __IO uint32_t CR1;
1214  __IO uint32_t CR2;
1215  __IO uint32_t FRCR;
1216  __IO uint32_t SLOTR;
1217  __IO uint32_t IMR;
1218  __IO uint32_t SR;
1219  __IO uint32_t CLRFR;
1220  __IO uint32_t DR;
1221 } SAI_Block_TypeDef;
1222 
1227 typedef struct
1228 {
1229  __IO uint32_t POWER;
1230  __IO uint32_t CLKCR;
1231  __IO uint32_t ARG;
1232  __IO uint32_t CMD;
1233  __I uint32_t RESPCMD;
1234  __I uint32_t RESP1;
1235  __I uint32_t RESP2;
1236  __I uint32_t RESP3;
1237  __I uint32_t RESP4;
1238  __IO uint32_t DTIMER;
1239  __IO uint32_t DLEN;
1240  __IO uint32_t DCTRL;
1241  __I uint32_t DCOUNT;
1242  __I uint32_t STA;
1243  __IO uint32_t ICR;
1244  __IO uint32_t MASK;
1245  uint32_t RESERVED0[2];
1246  __I uint32_t FIFOCNT;
1247  uint32_t RESERVED1[13];
1248  __IO uint32_t FIFO;
1249 } SDIO_TypeDef;
1250 
1255 typedef struct
1256 {
1257  __IO uint16_t CR1;
1258  uint16_t RESERVED0;
1259  __IO uint16_t CR2;
1260  uint16_t RESERVED1;
1261  __IO uint16_t SR;
1262  uint16_t RESERVED2;
1263  __IO uint16_t DR;
1264  uint16_t RESERVED3;
1265  __IO uint16_t CRCPR;
1266  uint16_t RESERVED4;
1267  __IO uint16_t RXCRCR;
1268  uint16_t RESERVED5;
1269  __IO uint16_t TXCRCR;
1270  uint16_t RESERVED6;
1271  __IO uint16_t I2SCFGR;
1272  uint16_t RESERVED7;
1273  __IO uint16_t I2SPR;
1274  uint16_t RESERVED8;
1275 } SPI_TypeDef;
1276 
1281 typedef struct
1282 {
1283  __IO uint16_t CR1;
1284  uint16_t RESERVED0;
1285  __IO uint16_t CR2;
1286  uint16_t RESERVED1;
1287  __IO uint16_t SMCR;
1288  uint16_t RESERVED2;
1289  __IO uint16_t DIER;
1290  uint16_t RESERVED3;
1291  __IO uint16_t SR;
1292  uint16_t RESERVED4;
1293  __IO uint16_t EGR;
1294  uint16_t RESERVED5;
1295  __IO uint16_t CCMR1;
1296  uint16_t RESERVED6;
1297  __IO uint16_t CCMR2;
1298  uint16_t RESERVED7;
1299  __IO uint16_t CCER;
1300  uint16_t RESERVED8;
1301  __IO uint32_t CNT;
1302  __IO uint16_t PSC;
1303  uint16_t RESERVED9;
1304  __IO uint32_t ARR;
1305  __IO uint16_t RCR;
1306  uint16_t RESERVED10;
1307  __IO uint32_t CCR1;
1308  __IO uint32_t CCR2;
1309  __IO uint32_t CCR3;
1310  __IO uint32_t CCR4;
1311  __IO uint16_t BDTR;
1312  uint16_t RESERVED11;
1313  __IO uint16_t DCR;
1314  uint16_t RESERVED12;
1315  __IO uint16_t DMAR;
1316  uint16_t RESERVED13;
1317  __IO uint16_t OR;
1318  uint16_t RESERVED14;
1319 } TIM_TypeDef;
1320 
1325 typedef struct
1326 {
1327  __IO uint16_t SR;
1328  uint16_t RESERVED0;
1329  __IO uint16_t DR;
1330  uint16_t RESERVED1;
1331  __IO uint16_t BRR;
1332  uint16_t RESERVED2;
1333  __IO uint16_t CR1;
1334  uint16_t RESERVED3;
1335  __IO uint16_t CR2;
1336  uint16_t RESERVED4;
1337  __IO uint16_t CR3;
1338  uint16_t RESERVED5;
1339  __IO uint16_t GTPR;
1340  uint16_t RESERVED6;
1341 } USART_TypeDef;
1342 
1347 typedef struct
1348 {
1349  __IO uint32_t CR;
1350  __IO uint32_t CFR;
1351  __IO uint32_t SR;
1352 } WWDG_TypeDef;
1353 
1358 typedef struct
1359 {
1360  __IO uint32_t CR;
1361  __IO uint32_t SR;
1362  __IO uint32_t DR;
1363  __IO uint32_t DOUT;
1364  __IO uint32_t DMACR;
1365  __IO uint32_t IMSCR;
1366  __IO uint32_t RISR;
1367  __IO uint32_t MISR;
1368  __IO uint32_t K0LR;
1369  __IO uint32_t K0RR;
1370  __IO uint32_t K1LR;
1371  __IO uint32_t K1RR;
1372  __IO uint32_t K2LR;
1373  __IO uint32_t K2RR;
1374  __IO uint32_t K3LR;
1375  __IO uint32_t K3RR;
1376  __IO uint32_t IV0LR;
1377  __IO uint32_t IV0RR;
1378  __IO uint32_t IV1LR;
1379  __IO uint32_t IV1RR;
1380  __IO uint32_t CSGCMCCM0R;
1381  __IO uint32_t CSGCMCCM1R;
1382  __IO uint32_t CSGCMCCM2R;
1383  __IO uint32_t CSGCMCCM3R;
1384  __IO uint32_t CSGCMCCM4R;
1385  __IO uint32_t CSGCMCCM5R;
1386  __IO uint32_t CSGCMCCM6R;
1387  __IO uint32_t CSGCMCCM7R;
1388  __IO uint32_t CSGCM0R;
1389  __IO uint32_t CSGCM1R;
1390  __IO uint32_t CSGCM2R;
1391  __IO uint32_t CSGCM3R;
1392  __IO uint32_t CSGCM4R;
1393  __IO uint32_t CSGCM5R;
1394  __IO uint32_t CSGCM6R;
1395  __IO uint32_t CSGCM7R;
1396 } CRYP_TypeDef;
1397 
1402 typedef struct
1403 {
1404  __IO uint32_t CR;
1405  __IO uint32_t DIN;
1406  __IO uint32_t STR;
1407  __IO uint32_t HR[5];
1408  __IO uint32_t IMR;
1409  __IO uint32_t SR;
1410  uint32_t RESERVED[52];
1411  __IO uint32_t CSR[54];
1412 } HASH_TypeDef;
1413 
1418 typedef struct
1419 {
1420  __IO uint32_t HR[8];
1421 } HASH_DIGEST_TypeDef;
1422 
1427 typedef struct
1428 {
1429  __IO uint32_t CR;
1430  __IO uint32_t SR;
1431  __IO uint32_t DR;
1432 } RNG_TypeDef;
1433 
1441 #define FLASH_BASE ((uint32_t)0x08000000)
1442 #define CCMDATARAM_BASE ((uint32_t)0x10000000)
1443 #define SRAM1_BASE ((uint32_t)0x20000000)
1444 #define SRAM2_BASE ((uint32_t)0x2001C000)
1445 #define SRAM3_BASE ((uint32_t)0x20020000)
1446 #define PERIPH_BASE ((uint32_t)0x40000000)
1447 #define BKPSRAM_BASE ((uint32_t)0x40024000)
1449 #if defined (STM32F40_41xxx)
1450 #define FSMC_R_BASE ((uint32_t)0xA0000000)
1451 #endif /* STM32F40_41xxx */
1452 
1453 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
1454 #define FMC_R_BASE ((uint32_t)0xA0000000)
1455 #endif /* STM32F427_437xx || STM32F429_439xx */
1456 
1457 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000)
1458 #define SRAM1_BB_BASE ((uint32_t)0x22000000)
1459 #define SRAM2_BB_BASE ((uint32_t)0x2201C000)
1460 #define SRAM3_BB_BASE ((uint32_t)0x22400000)
1461 #define PERIPH_BB_BASE ((uint32_t)0x42000000)
1462 #define BKPSRAM_BB_BASE ((uint32_t)0x42024000)
1464 /* Legacy defines */
1465 #define SRAM_BASE SRAM1_BASE
1466 #define SRAM_BB_BASE SRAM1_BB_BASE
1467 
1468 
1470 #define APB1PERIPH_BASE PERIPH_BASE
1471 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
1472 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
1473 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
1474 
1476 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
1477 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
1478 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
1479 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
1480 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
1481 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
1482 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
1483 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
1484 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
1485 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
1486 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
1487 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
1488 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
1489 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
1490 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
1491 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
1492 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
1493 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
1494 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
1495 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
1496 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
1497 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
1498 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
1499 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
1500 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
1501 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
1502 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
1503 #define UART7_BASE (APB1PERIPH_BASE + 0x7800)
1504 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
1505 
1507 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
1508 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
1509 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
1510 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
1511 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
1512 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
1513 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
1514 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
1515 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
1516 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
1517 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
1518 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
1519 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
1520 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
1521 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
1522 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
1523 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
1524 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
1525 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
1526 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
1527 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
1528 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800)
1529 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
1530 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
1531 
1533 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
1534 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
1535 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
1536 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
1537 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
1538 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
1539 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
1540 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
1541 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
1542 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)
1543 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)
1544 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
1545 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
1546 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
1547 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
1548 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
1549 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
1550 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
1551 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
1552 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
1553 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
1554 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
1555 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
1556 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
1557 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
1558 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
1559 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
1560 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
1561 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
1562 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
1563 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
1564 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
1565 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
1566 #define ETH_MAC_BASE (ETH_BASE)
1567 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
1568 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
1569 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
1570 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)
1571 
1573 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
1574 #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)
1575 #define HASH_BASE (AHB2PERIPH_BASE + 0x60400)
1576 #define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710)
1577 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
1578 
1579 #if defined (STM32F40_41xxx)
1580 
1581 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
1582 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
1583 #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
1584 #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
1585 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
1586 #endif /* STM32F40_41xxx */
1587 
1588 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
1589 
1590 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
1591 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
1592 #define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060)
1593 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
1594 #define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
1595 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
1596 #endif /* STM32F427_437xx || STM32F429_439xx */
1597 
1598 /* Debug MCU registers base address */
1599 #define DBGMCU_BASE ((uint32_t )0xE0042000)
1600 
1608 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1609 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1610 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1611 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1612 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1613 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1614 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1615 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1616 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1617 #define RTC ((RTC_TypeDef *) RTC_BASE)
1618 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1619 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1620 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1621 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1622 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1623 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1624 #define USART2 ((USART_TypeDef *) USART2_BASE)
1625 #define USART3 ((USART_TypeDef *) USART3_BASE)
1626 #define UART4 ((USART_TypeDef *) UART4_BASE)
1627 #define UART5 ((USART_TypeDef *) UART5_BASE)
1628 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1629 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1630 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1631 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1632 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1633 #define PWR ((PWR_TypeDef *) PWR_BASE)
1634 #define DAC ((DAC_TypeDef *) DAC_BASE)
1635 #define UART7 ((USART_TypeDef *) UART7_BASE)
1636 #define UART8 ((USART_TypeDef *) UART8_BASE)
1637 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1638 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1639 #define USART1 ((USART_TypeDef *) USART1_BASE)
1640 #define USART6 ((USART_TypeDef *) USART6_BASE)
1641 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1642 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1643 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1644 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1645 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1646 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1647 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1648 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1649 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1650 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1651 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1652 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1653 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1654 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1655 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1656 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1657 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1658 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
1659 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1660 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1661 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1662 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1663 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1664 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1665 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1666 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1667 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1668 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1669 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1670 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1671 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1672 #define CRC ((CRC_TypeDef *) CRC_BASE)
1673 #define RCC ((RCC_TypeDef *) RCC_BASE)
1674 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1675 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1676 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1677 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1678 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1679 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1680 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1681 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1682 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1683 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1684 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1685 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1686 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1687 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1688 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1689 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1690 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1691 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1692 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1693 #define ETH ((ETH_TypeDef *) ETH_BASE)
1694 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1695 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1696 #define CRYP ((CRYP_TypeDef *) CRYP_BASE)
1697 #define HASH ((HASH_TypeDef *) HASH_BASE)
1698 #define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
1699 #define RNG ((RNG_TypeDef *) RNG_BASE)
1700 
1701 #if defined (STM32F40_41xxx)
1702 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1703 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1704 #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
1705 #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
1706 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
1707 #endif /* STM32F40_41xxx */
1708 
1709 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
1710 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1711 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1712 #define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
1713 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1714 #define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
1715 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1716 #endif /* STM32F427_437xx || STM32F429_439xx */
1717 
1718 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1719 
1732 /******************************************************************************/
1733 /* Peripheral Registers_Bits_Definition */
1734 /******************************************************************************/
1735 
1736 /******************************************************************************/
1737 /* */
1738 /* Analog to Digital Converter */
1739 /* */
1740 /******************************************************************************/
1741 /******************** Bit definition for ADC_SR register ********************/
1742 #define ADC_SR_AWD ((uint8_t)0x01)
1743 #define ADC_SR_EOC ((uint8_t)0x02)
1744 #define ADC_SR_JEOC ((uint8_t)0x04)
1745 #define ADC_SR_JSTRT ((uint8_t)0x08)
1746 #define ADC_SR_STRT ((uint8_t)0x10)
1747 #define ADC_SR_OVR ((uint8_t)0x20)
1749 /******************* Bit definition for ADC_CR1 register ********************/
1750 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F)
1751 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001)
1752 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002)
1753 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004)
1754 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008)
1755 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010)
1756 #define ADC_CR1_EOCIE ((uint32_t)0x00000020)
1757 #define ADC_CR1_AWDIE ((uint32_t)0x00000040)
1758 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080)
1759 #define ADC_CR1_SCAN ((uint32_t)0x00000100)
1760 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200)
1761 #define ADC_CR1_JAUTO ((uint32_t)0x00000400)
1762 #define ADC_CR1_DISCEN ((uint32_t)0x00000800)
1763 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000)
1764 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000)
1765 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000)
1766 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000)
1767 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000)
1768 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000)
1769 #define ADC_CR1_AWDEN ((uint32_t)0x00800000)
1770 #define ADC_CR1_RES ((uint32_t)0x03000000)
1771 #define ADC_CR1_RES_0 ((uint32_t)0x01000000)
1772 #define ADC_CR1_RES_1 ((uint32_t)0x02000000)
1773 #define ADC_CR1_OVRIE ((uint32_t)0x04000000)
1775 /******************* Bit definition for ADC_CR2 register ********************/
1776 #define ADC_CR2_ADON ((uint32_t)0x00000001)
1777 #define ADC_CR2_CONT ((uint32_t)0x00000002)
1778 #define ADC_CR2_DMA ((uint32_t)0x00000100)
1779 #define ADC_CR2_DDS ((uint32_t)0x00000200)
1780 #define ADC_CR2_EOCS ((uint32_t)0x00000400)
1781 #define ADC_CR2_ALIGN ((uint32_t)0x00000800)
1782 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000)
1783 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000)
1784 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000)
1785 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000)
1786 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000)
1787 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000)
1788 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000)
1789 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000)
1790 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000)
1791 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000)
1792 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000)
1793 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000)
1794 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000)
1795 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000)
1796 #define ADC_CR2_EXTEN ((uint32_t)0x30000000)
1797 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000)
1798 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000)
1799 #define ADC_CR2_SWSTART ((uint32_t)0x40000000)
1801 /****************** Bit definition for ADC_SMPR1 register *******************/
1802 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007)
1803 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001)
1804 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002)
1805 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004)
1806 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038)
1807 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008)
1808 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010)
1809 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020)
1810 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0)
1811 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040)
1812 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080)
1813 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100)
1814 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00)
1815 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200)
1816 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400)
1817 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800)
1818 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000)
1819 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000)
1820 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000)
1821 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000)
1822 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000)
1823 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000)
1824 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000)
1825 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000)
1826 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000)
1827 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000)
1828 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000)
1829 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000)
1830 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000)
1831 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000)
1832 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000)
1833 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000)
1834 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000)
1835 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000)
1836 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000)
1837 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000)
1839 /****************** Bit definition for ADC_SMPR2 register *******************/
1840 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007)
1841 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001)
1842 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002)
1843 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004)
1844 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038)
1845 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008)
1846 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010)
1847 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020)
1848 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0)
1849 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040)
1850 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080)
1851 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100)
1852 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00)
1853 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200)
1854 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400)
1855 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800)
1856 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000)
1857 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000)
1858 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000)
1859 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000)
1860 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000)
1861 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000)
1862 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000)
1863 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000)
1864 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000)
1865 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000)
1866 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000)
1867 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000)
1868 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000)
1869 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000)
1870 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000)
1871 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000)
1872 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000)
1873 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000)
1874 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000)
1875 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000)
1876 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000)
1877 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000)
1878 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000)
1879 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000)
1881 /****************** Bit definition for ADC_JOFR1 register *******************/
1882 #define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF)
1884 /****************** Bit definition for ADC_JOFR2 register *******************/
1885 #define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF)
1887 /****************** Bit definition for ADC_JOFR3 register *******************/
1888 #define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF)
1890 /****************** Bit definition for ADC_JOFR4 register *******************/
1891 #define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF)
1893 /******************* Bit definition for ADC_HTR register ********************/
1894 #define ADC_HTR_HT ((uint16_t)0x0FFF)
1896 /******************* Bit definition for ADC_LTR register ********************/
1897 #define ADC_LTR_LT ((uint16_t)0x0FFF)
1899 /******************* Bit definition for ADC_SQR1 register *******************/
1900 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F)
1901 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001)
1902 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002)
1903 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004)
1904 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008)
1905 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010)
1906 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0)
1907 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020)
1908 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040)
1909 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080)
1910 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100)
1911 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200)
1912 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00)
1913 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400)
1914 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800)
1915 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000)
1916 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000)
1917 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000)
1918 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000)
1919 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000)
1920 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000)
1921 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000)
1922 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000)
1923 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000)
1924 #define ADC_SQR1_L ((uint32_t)0x00F00000)
1925 #define ADC_SQR1_L_0 ((uint32_t)0x00100000)
1926 #define ADC_SQR1_L_1 ((uint32_t)0x00200000)
1927 #define ADC_SQR1_L_2 ((uint32_t)0x00400000)
1928 #define ADC_SQR1_L_3 ((uint32_t)0x00800000)
1930 /******************* Bit definition for ADC_SQR2 register *******************/
1931 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F)
1932 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001)
1933 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002)
1934 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004)
1935 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008)
1936 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010)
1937 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0)
1938 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020)
1939 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040)
1940 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080)
1941 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100)
1942 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200)
1943 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00)
1944 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400)
1945 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800)
1946 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000)
1947 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000)
1948 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000)
1949 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000)
1950 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000)
1951 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000)
1952 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000)
1953 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000)
1954 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000)
1955 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000)
1956 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000)
1957 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000)
1958 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000)
1959 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000)
1960 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000)
1961 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000)
1962 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000)
1963 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000)
1964 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000)
1965 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000)
1966 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000)
1968 /******************* Bit definition for ADC_SQR3 register *******************/
1969 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F)
1970 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001)
1971 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002)
1972 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004)
1973 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008)
1974 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010)
1975 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0)
1976 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020)
1977 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040)
1978 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080)
1979 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100)
1980 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200)
1981 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00)
1982 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400)
1983 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800)
1984 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000)
1985 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000)
1986 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000)
1987 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000)
1988 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000)
1989 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000)
1990 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000)
1991 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000)
1992 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000)
1993 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000)
1994 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000)
1995 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000)
1996 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000)
1997 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000)
1998 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000)
1999 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000)
2000 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000)
2001 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000)
2002 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000)
2003 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000)
2004 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000)
2006 /******************* Bit definition for ADC_JSQR register *******************/
2007 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F)
2008 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001)
2009 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002)
2010 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004)
2011 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008)
2012 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010)
2013 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0)
2014 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020)
2015 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040)
2016 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080)
2017 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100)
2018 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200)
2019 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00)
2020 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400)
2021 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800)
2022 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000)
2023 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000)
2024 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000)
2025 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000)
2026 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000)
2027 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000)
2028 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000)
2029 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000)
2030 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000)
2031 #define ADC_JSQR_JL ((uint32_t)0x00300000)
2032 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000)
2033 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000)
2035 /******************* Bit definition for ADC_JDR1 register *******************/
2036 #define ADC_JDR1_JDATA ((uint16_t)0xFFFF)
2038 /******************* Bit definition for ADC_JDR2 register *******************/
2039 #define ADC_JDR2_JDATA ((uint16_t)0xFFFF)
2041 /******************* Bit definition for ADC_JDR3 register *******************/
2042 #define ADC_JDR3_JDATA ((uint16_t)0xFFFF)
2044 /******************* Bit definition for ADC_JDR4 register *******************/
2045 #define ADC_JDR4_JDATA ((uint16_t)0xFFFF)
2047 /******************** Bit definition for ADC_DR register ********************/
2048 #define ADC_DR_DATA ((uint32_t)0x0000FFFF)
2049 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000)
2051 /******************* Bit definition for ADC_CSR register ********************/
2052 #define ADC_CSR_AWD1 ((uint32_t)0x00000001)
2053 #define ADC_CSR_EOC1 ((uint32_t)0x00000002)
2054 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004)
2055 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008)
2056 #define ADC_CSR_STRT1 ((uint32_t)0x00000010)
2057 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020)
2058 #define ADC_CSR_AWD2 ((uint32_t)0x00000100)
2059 #define ADC_CSR_EOC2 ((uint32_t)0x00000200)
2060 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400)
2061 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800)
2062 #define ADC_CSR_STRT2 ((uint32_t)0x00001000)
2063 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000)
2064 #define ADC_CSR_AWD3 ((uint32_t)0x00010000)
2065 #define ADC_CSR_EOC3 ((uint32_t)0x00020000)
2066 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000)
2067 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000)
2068 #define ADC_CSR_STRT3 ((uint32_t)0x00100000)
2069 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000)
2071 /******************* Bit definition for ADC_CCR register ********************/
2072 #define ADC_CCR_MULTI ((uint32_t)0x0000001F)
2073 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001)
2074 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002)
2075 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004)
2076 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008)
2077 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010)
2078 #define ADC_CCR_DELAY ((uint32_t)0x00000F00)
2079 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100)
2080 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200)
2081 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400)
2082 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800)
2083 #define ADC_CCR_DDS ((uint32_t)0x00002000)
2084 #define ADC_CCR_DMA ((uint32_t)0x0000C000)
2085 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000)
2086 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000)
2087 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000)
2088 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000)
2089 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000)
2090 #define ADC_CCR_VBATE ((uint32_t)0x00400000)
2091 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000)
2093 /******************* Bit definition for ADC_CDR register ********************/
2094 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF)
2095 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000)
2097 /******************************************************************************/
2098 /* */
2099 /* Controller Area Network */
2100 /* */
2101 /******************************************************************************/
2103 /******************* Bit definition for CAN_MCR register ********************/
2104 #define CAN_MCR_INRQ ((uint16_t)0x0001)
2105 #define CAN_MCR_SLEEP ((uint16_t)0x0002)
2106 #define CAN_MCR_TXFP ((uint16_t)0x0004)
2107 #define CAN_MCR_RFLM ((uint16_t)0x0008)
2108 #define CAN_MCR_NART ((uint16_t)0x0010)
2109 #define CAN_MCR_AWUM ((uint16_t)0x0020)
2110 #define CAN_MCR_ABOM ((uint16_t)0x0040)
2111 #define CAN_MCR_TTCM ((uint16_t)0x0080)
2112 #define CAN_MCR_RESET ((uint16_t)0x8000)
2114 /******************* Bit definition for CAN_MSR register ********************/
2115 #define CAN_MSR_INAK ((uint16_t)0x0001)
2116 #define CAN_MSR_SLAK ((uint16_t)0x0002)
2117 #define CAN_MSR_ERRI ((uint16_t)0x0004)
2118 #define CAN_MSR_WKUI ((uint16_t)0x0008)
2119 #define CAN_MSR_SLAKI ((uint16_t)0x0010)
2120 #define CAN_MSR_TXM ((uint16_t)0x0100)
2121 #define CAN_MSR_RXM ((uint16_t)0x0200)
2122 #define CAN_MSR_SAMP ((uint16_t)0x0400)
2123 #define CAN_MSR_RX ((uint16_t)0x0800)
2125 /******************* Bit definition for CAN_TSR register ********************/
2126 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001)
2127 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002)
2128 #define CAN_TSR_ALST0 ((uint32_t)0x00000004)
2129 #define CAN_TSR_TERR0 ((uint32_t)0x00000008)
2130 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080)
2131 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100)
2132 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200)
2133 #define CAN_TSR_ALST1 ((uint32_t)0x00000400)
2134 #define CAN_TSR_TERR1 ((uint32_t)0x00000800)
2135 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000)
2136 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000)
2137 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000)
2138 #define CAN_TSR_ALST2 ((uint32_t)0x00040000)
2139 #define CAN_TSR_TERR2 ((uint32_t)0x00080000)
2140 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000)
2141 #define CAN_TSR_CODE ((uint32_t)0x03000000)
2143 #define CAN_TSR_TME ((uint32_t)0x1C000000)
2144 #define CAN_TSR_TME0 ((uint32_t)0x04000000)
2145 #define CAN_TSR_TME1 ((uint32_t)0x08000000)
2146 #define CAN_TSR_TME2 ((uint32_t)0x10000000)
2148 #define CAN_TSR_LOW ((uint32_t)0xE0000000)
2149 #define CAN_TSR_LOW0 ((uint32_t)0x20000000)
2150 #define CAN_TSR_LOW1 ((uint32_t)0x40000000)
2151 #define CAN_TSR_LOW2 ((uint32_t)0x80000000)
2153 /******************* Bit definition for CAN_RF0R register *******************/
2154 #define CAN_RF0R_FMP0 ((uint8_t)0x03)
2155 #define CAN_RF0R_FULL0 ((uint8_t)0x08)
2156 #define CAN_RF0R_FOVR0 ((uint8_t)0x10)
2157 #define CAN_RF0R_RFOM0 ((uint8_t)0x20)
2159 /******************* Bit definition for CAN_RF1R register *******************/
2160 #define CAN_RF1R_FMP1 ((uint8_t)0x03)
2161 #define CAN_RF1R_FULL1 ((uint8_t)0x08)
2162 #define CAN_RF1R_FOVR1 ((uint8_t)0x10)
2163 #define CAN_RF1R_RFOM1 ((uint8_t)0x20)
2165 /******************** Bit definition for CAN_IER register *******************/
2166 #define CAN_IER_TMEIE ((uint32_t)0x00000001)
2167 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002)
2168 #define CAN_IER_FFIE0 ((uint32_t)0x00000004)
2169 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008)
2170 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010)
2171 #define CAN_IER_FFIE1 ((uint32_t)0x00000020)
2172 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040)
2173 #define CAN_IER_EWGIE ((uint32_t)0x00000100)
2174 #define CAN_IER_EPVIE ((uint32_t)0x00000200)
2175 #define CAN_IER_BOFIE ((uint32_t)0x00000400)
2176 #define CAN_IER_LECIE ((uint32_t)0x00000800)
2177 #define CAN_IER_ERRIE ((uint32_t)0x00008000)
2178 #define CAN_IER_WKUIE ((uint32_t)0x00010000)
2179 #define CAN_IER_SLKIE ((uint32_t)0x00020000)
2181 /******************** Bit definition for CAN_ESR register *******************/
2182 #define CAN_ESR_EWGF ((uint32_t)0x00000001)
2183 #define CAN_ESR_EPVF ((uint32_t)0x00000002)
2184 #define CAN_ESR_BOFF ((uint32_t)0x00000004)
2186 #define CAN_ESR_LEC ((uint32_t)0x00000070)
2187 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010)
2188 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020)
2189 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040)
2191 #define CAN_ESR_TEC ((uint32_t)0x00FF0000)
2192 #define CAN_ESR_REC ((uint32_t)0xFF000000)
2194 /******************* Bit definition for CAN_BTR register ********************/
2195 #define CAN_BTR_BRP ((uint32_t)0x000003FF)
2196 #define CAN_BTR_TS1 ((uint32_t)0x000F0000)
2197 #define CAN_BTR_TS2 ((uint32_t)0x00700000)
2198 #define CAN_BTR_SJW ((uint32_t)0x03000000)
2199 #define CAN_BTR_LBKM ((uint32_t)0x40000000)
2200 #define CAN_BTR_SILM ((uint32_t)0x80000000)
2203 /****************** Bit definition for CAN_TI0R register ********************/
2204 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001)
2205 #define CAN_TI0R_RTR ((uint32_t)0x00000002)
2206 #define CAN_TI0R_IDE ((uint32_t)0x00000004)
2207 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8)
2208 #define CAN_TI0R_STID ((uint32_t)0xFFE00000)
2210 /****************** Bit definition for CAN_TDT0R register *******************/
2211 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F)
2212 #define CAN_TDT0R_TGT ((uint32_t)0x00000100)
2213 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000)
2215 /****************** Bit definition for CAN_TDL0R register *******************/
2216 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF)
2217 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00)
2218 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000)
2219 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000)
2221 /****************** Bit definition for CAN_TDH0R register *******************/
2222 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF)
2223 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00)
2224 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000)
2225 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000)
2227 /******************* Bit definition for CAN_TI1R register *******************/
2228 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001)
2229 #define CAN_TI1R_RTR ((uint32_t)0x00000002)
2230 #define CAN_TI1R_IDE ((uint32_t)0x00000004)
2231 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8)
2232 #define CAN_TI1R_STID ((uint32_t)0xFFE00000)
2234 /******************* Bit definition for CAN_TDT1R register ******************/
2235 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F)
2236 #define CAN_TDT1R_TGT ((uint32_t)0x00000100)
2237 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000)
2239 /******************* Bit definition for CAN_TDL1R register ******************/
2240 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF)
2241 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00)
2242 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000)
2243 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000)
2245 /******************* Bit definition for CAN_TDH1R register ******************/
2246 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF)
2247 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00)
2248 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000)
2249 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000)
2251 /******************* Bit definition for CAN_TI2R register *******************/
2252 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001)
2253 #define CAN_TI2R_RTR ((uint32_t)0x00000002)
2254 #define CAN_TI2R_IDE ((uint32_t)0x00000004)
2255 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8)
2256 #define CAN_TI2R_STID ((uint32_t)0xFFE00000)
2258 /******************* Bit definition for CAN_TDT2R register ******************/
2259 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F)
2260 #define CAN_TDT2R_TGT ((uint32_t)0x00000100)
2261 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000)
2263 /******************* Bit definition for CAN_TDL2R register ******************/
2264 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF)
2265 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00)
2266 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000)
2267 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000)
2269 /******************* Bit definition for CAN_TDH2R register ******************/
2270 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF)
2271 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00)
2272 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000)
2273 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000)
2275 /******************* Bit definition for CAN_RI0R register *******************/
2276 #define CAN_RI0R_RTR ((uint32_t)0x00000002)
2277 #define CAN_RI0R_IDE ((uint32_t)0x00000004)
2278 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8)
2279 #define CAN_RI0R_STID ((uint32_t)0xFFE00000)
2281 /******************* Bit definition for CAN_RDT0R register ******************/
2282 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F)
2283 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00)
2284 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000)
2286 /******************* Bit definition for CAN_RDL0R register ******************/
2287 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF)
2288 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00)
2289 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000)
2290 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000)
2292 /******************* Bit definition for CAN_RDH0R register ******************/
2293 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF)
2294 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00)
2295 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000)
2296 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000)
2298 /******************* Bit definition for CAN_RI1R register *******************/
2299 #define CAN_RI1R_RTR ((uint32_t)0x00000002)
2300 #define CAN_RI1R_IDE ((uint32_t)0x00000004)
2301 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8)
2302 #define CAN_RI1R_STID ((uint32_t)0xFFE00000)
2304 /******************* Bit definition for CAN_RDT1R register ******************/
2305 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F)
2306 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00)
2307 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000)
2309 /******************* Bit definition for CAN_RDL1R register ******************/
2310 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF)
2311 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00)
2312 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000)
2313 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000)
2315 /******************* Bit definition for CAN_RDH1R register ******************/
2316 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF)
2317 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00)
2318 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000)
2319 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000)
2322 /******************* Bit definition for CAN_FMR register ********************/
2323 #define CAN_FMR_FINIT ((uint8_t)0x01)
2325 /******************* Bit definition for CAN_FM1R register *******************/
2326 #define CAN_FM1R_FBM ((uint16_t)0x3FFF)
2327 #define CAN_FM1R_FBM0 ((uint16_t)0x0001)
2328 #define CAN_FM1R_FBM1 ((uint16_t)0x0002)
2329 #define CAN_FM1R_FBM2 ((uint16_t)0x0004)
2330 #define CAN_FM1R_FBM3 ((uint16_t)0x0008)
2331 #define CAN_FM1R_FBM4 ((uint16_t)0x0010)
2332 #define CAN_FM1R_FBM5 ((uint16_t)0x0020)
2333 #define CAN_FM1R_FBM6 ((uint16_t)0x0040)
2334 #define CAN_FM1R_FBM7 ((uint16_t)0x0080)
2335 #define CAN_FM1R_FBM8 ((uint16_t)0x0100)
2336 #define CAN_FM1R_FBM9 ((uint16_t)0x0200)
2337 #define CAN_FM1R_FBM10 ((uint16_t)0x0400)
2338 #define CAN_FM1R_FBM11 ((uint16_t)0x0800)
2339 #define CAN_FM1R_FBM12 ((uint16_t)0x1000)
2340 #define CAN_FM1R_FBM13 ((uint16_t)0x2000)
2342 /******************* Bit definition for CAN_FS1R register *******************/
2343 #define CAN_FS1R_FSC ((uint16_t)0x3FFF)
2344 #define CAN_FS1R_FSC0 ((uint16_t)0x0001)
2345 #define CAN_FS1R_FSC1 ((uint16_t)0x0002)
2346 #define CAN_FS1R_FSC2 ((uint16_t)0x0004)
2347 #define CAN_FS1R_FSC3 ((uint16_t)0x0008)
2348 #define CAN_FS1R_FSC4 ((uint16_t)0x0010)
2349 #define CAN_FS1R_FSC5 ((uint16_t)0x0020)
2350 #define CAN_FS1R_FSC6 ((uint16_t)0x0040)
2351 #define CAN_FS1R_FSC7 ((uint16_t)0x0080)
2352 #define CAN_FS1R_FSC8 ((uint16_t)0x0100)
2353 #define CAN_FS1R_FSC9 ((uint16_t)0x0200)
2354 #define CAN_FS1R_FSC10 ((uint16_t)0x0400)
2355 #define CAN_FS1R_FSC11 ((uint16_t)0x0800)
2356 #define CAN_FS1R_FSC12 ((uint16_t)0x1000)
2357 #define CAN_FS1R_FSC13 ((uint16_t)0x2000)
2359 /****************** Bit definition for CAN_FFA1R register *******************/
2360 #define CAN_FFA1R_FFA ((uint16_t)0x3FFF)
2361 #define CAN_FFA1R_FFA0 ((uint16_t)0x0001)
2362 #define CAN_FFA1R_FFA1 ((uint16_t)0x0002)
2363 #define CAN_FFA1R_FFA2 ((uint16_t)0x0004)
2364 #define CAN_FFA1R_FFA3 ((uint16_t)0x0008)
2365 #define CAN_FFA1R_FFA4 ((uint16_t)0x0010)
2366 #define CAN_FFA1R_FFA5 ((uint16_t)0x0020)
2367 #define CAN_FFA1R_FFA6 ((uint16_t)0x0040)
2368 #define CAN_FFA1R_FFA7 ((uint16_t)0x0080)
2369 #define CAN_FFA1R_FFA8 ((uint16_t)0x0100)
2370 #define CAN_FFA1R_FFA9 ((uint16_t)0x0200)
2371 #define CAN_FFA1R_FFA10 ((uint16_t)0x0400)
2372 #define CAN_FFA1R_FFA11 ((uint16_t)0x0800)
2373 #define CAN_FFA1R_FFA12 ((uint16_t)0x1000)
2374 #define CAN_FFA1R_FFA13 ((uint16_t)0x2000)
2376 /******************* Bit definition for CAN_FA1R register *******************/
2377 #define CAN_FA1R_FACT ((uint16_t)0x3FFF)
2378 #define CAN_FA1R_FACT0 ((uint16_t)0x0001)
2379 #define CAN_FA1R_FACT1 ((uint16_t)0x0002)
2380 #define CAN_FA1R_FACT2 ((uint16_t)0x0004)
2381 #define CAN_FA1R_FACT3 ((uint16_t)0x0008)
2382 #define CAN_FA1R_FACT4 ((uint16_t)0x0010)
2383 #define CAN_FA1R_FACT5 ((uint16_t)0x0020)
2384 #define CAN_FA1R_FACT6 ((uint16_t)0x0040)
2385 #define CAN_FA1R_FACT7 ((uint16_t)0x0080)
2386 #define CAN_FA1R_FACT8 ((uint16_t)0x0100)
2387 #define CAN_FA1R_FACT9 ((uint16_t)0x0200)
2388 #define CAN_FA1R_FACT10 ((uint16_t)0x0400)
2389 #define CAN_FA1R_FACT11 ((uint16_t)0x0800)
2390 #define CAN_FA1R_FACT12 ((uint16_t)0x1000)
2391 #define CAN_FA1R_FACT13 ((uint16_t)0x2000)
2393 /******************* Bit definition for CAN_F0R1 register *******************/
2394 #define CAN_F0R1_FB0 ((uint32_t)0x00000001)
2395 #define CAN_F0R1_FB1 ((uint32_t)0x00000002)
2396 #define CAN_F0R1_FB2 ((uint32_t)0x00000004)
2397 #define CAN_F0R1_FB3 ((uint32_t)0x00000008)
2398 #define CAN_F0R1_FB4 ((uint32_t)0x00000010)
2399 #define CAN_F0R1_FB5 ((uint32_t)0x00000020)
2400 #define CAN_F0R1_FB6 ((uint32_t)0x00000040)
2401 #define CAN_F0R1_FB7 ((uint32_t)0x00000080)
2402 #define CAN_F0R1_FB8 ((uint32_t)0x00000100)
2403 #define CAN_F0R1_FB9 ((uint32_t)0x00000200)
2404 #define CAN_F0R1_FB10 ((uint32_t)0x00000400)
2405 #define CAN_F0R1_FB11 ((uint32_t)0x00000800)
2406 #define CAN_F0R1_FB12 ((uint32_t)0x00001000)
2407 #define CAN_F0R1_FB13 ((uint32_t)0x00002000)
2408 #define CAN_F0R1_FB14 ((uint32_t)0x00004000)
2409 #define CAN_F0R1_FB15 ((uint32_t)0x00008000)
2410 #define CAN_F0R1_FB16 ((uint32_t)0x00010000)
2411 #define CAN_F0R1_FB17 ((uint32_t)0x00020000)
2412 #define CAN_F0R1_FB18 ((uint32_t)0x00040000)
2413 #define CAN_F0R1_FB19 ((uint32_t)0x00080000)
2414 #define CAN_F0R1_FB20 ((uint32_t)0x00100000)
2415 #define CAN_F0R1_FB21 ((uint32_t)0x00200000)
2416 #define CAN_F0R1_FB22 ((uint32_t)0x00400000)
2417 #define CAN_F0R1_FB23 ((uint32_t)0x00800000)
2418 #define CAN_F0R1_FB24 ((uint32_t)0x01000000)
2419 #define CAN_F0R1_FB25 ((uint32_t)0x02000000)
2420 #define CAN_F0R1_FB26 ((uint32_t)0x04000000)
2421 #define CAN_F0R1_FB27 ((uint32_t)0x08000000)
2422 #define CAN_F0R1_FB28 ((uint32_t)0x10000000)
2423 #define CAN_F0R1_FB29 ((uint32_t)0x20000000)
2424 #define CAN_F0R1_FB30 ((uint32_t)0x40000000)
2425 #define CAN_F0R1_FB31 ((uint32_t)0x80000000)
2427 /******************* Bit definition for CAN_F1R1 register *******************/
2428 #define CAN_F1R1_FB0 ((uint32_t)0x00000001)
2429 #define CAN_F1R1_FB1 ((uint32_t)0x00000002)
2430 #define CAN_F1R1_FB2 ((uint32_t)0x00000004)
2431 #define CAN_F1R1_FB3 ((uint32_t)0x00000008)
2432 #define CAN_F1R1_FB4 ((uint32_t)0x00000010)
2433 #define CAN_F1R1_FB5 ((uint32_t)0x00000020)
2434 #define CAN_F1R1_FB6 ((uint32_t)0x00000040)
2435 #define CAN_F1R1_FB7 ((uint32_t)0x00000080)
2436 #define CAN_F1R1_FB8 ((uint32_t)0x00000100)
2437 #define CAN_F1R1_FB9 ((uint32_t)0x00000200)
2438 #define CAN_F1R1_FB10 ((uint32_t)0x00000400)
2439 #define CAN_F1R1_FB11 ((uint32_t)0x00000800)
2440 #define CAN_F1R1_FB12 ((uint32_t)0x00001000)
2441 #define CAN_F1R1_FB13 ((uint32_t)0x00002000)
2442 #define CAN_F1R1_FB14 ((uint32_t)0x00004000)
2443 #define CAN_F1R1_FB15 ((uint32_t)0x00008000)
2444 #define CAN_F1R1_FB16 ((uint32_t)0x00010000)
2445 #define CAN_F1R1_FB17 ((uint32_t)0x00020000)
2446 #define CAN_F1R1_FB18 ((uint32_t)0x00040000)
2447 #define CAN_F1R1_FB19 ((uint32_t)0x00080000)
2448 #define CAN_F1R1_FB20 ((uint32_t)0x00100000)
2449 #define CAN_F1R1_FB21 ((uint32_t)0x00200000)
2450 #define CAN_F1R1_FB22 ((uint32_t)0x00400000)
2451 #define CAN_F1R1_FB23 ((uint32_t)0x00800000)
2452 #define CAN_F1R1_FB24 ((uint32_t)0x01000000)
2453 #define CAN_F1R1_FB25 ((uint32_t)0x02000000)
2454 #define CAN_F1R1_FB26 ((uint32_t)0x04000000)
2455 #define CAN_F1R1_FB27 ((uint32_t)0x08000000)
2456 #define CAN_F1R1_FB28 ((uint32_t)0x10000000)
2457 #define CAN_F1R1_FB29 ((uint32_t)0x20000000)
2458 #define CAN_F1R1_FB30 ((uint32_t)0x40000000)
2459 #define CAN_F1R1_FB31 ((uint32_t)0x80000000)
2461 /******************* Bit definition for CAN_F2R1 register *******************/
2462 #define CAN_F2R1_FB0 ((uint32_t)0x00000001)
2463 #define CAN_F2R1_FB1 ((uint32_t)0x00000002)
2464 #define CAN_F2R1_FB2 ((uint32_t)0x00000004)
2465 #define CAN_F2R1_FB3 ((uint32_t)0x00000008)
2466 #define CAN_F2R1_FB4 ((uint32_t)0x00000010)
2467 #define CAN_F2R1_FB5 ((uint32_t)0x00000020)
2468 #define CAN_F2R1_FB6 ((uint32_t)0x00000040)
2469 #define CAN_F2R1_FB7 ((uint32_t)0x00000080)
2470 #define CAN_F2R1_FB8 ((uint32_t)0x00000100)
2471 #define CAN_F2R1_FB9 ((uint32_t)0x00000200)
2472 #define CAN_F2R1_FB10 ((uint32_t)0x00000400)
2473 #define CAN_F2R1_FB11 ((uint32_t)0x00000800)
2474 #define CAN_F2R1_FB12 ((uint32_t)0x00001000)
2475 #define CAN_F2R1_FB13 ((uint32_t)0x00002000)
2476 #define CAN_F2R1_FB14 ((uint32_t)0x00004000)
2477 #define CAN_F2R1_FB15 ((uint32_t)0x00008000)
2478 #define CAN_F2R1_FB16 ((uint32_t)0x00010000)
2479 #define CAN_F2R1_FB17 ((uint32_t)0x00020000)
2480 #define CAN_F2R1_FB18 ((uint32_t)0x00040000)
2481 #define CAN_F2R1_FB19 ((uint32_t)0x00080000)
2482 #define CAN_F2R1_FB20 ((uint32_t)0x00100000)
2483 #define CAN_F2R1_FB21 ((uint32_t)0x00200000)
2484 #define CAN_F2R1_FB22 ((uint32_t)0x00400000)
2485 #define CAN_F2R1_FB23 ((uint32_t)0x00800000)
2486 #define CAN_F2R1_FB24 ((uint32_t)0x01000000)
2487 #define CAN_F2R1_FB25 ((uint32_t)0x02000000)
2488 #define CAN_F2R1_FB26 ((uint32_t)0x04000000)
2489 #define CAN_F2R1_FB27 ((uint32_t)0x08000000)
2490 #define CAN_F2R1_FB28 ((uint32_t)0x10000000)
2491 #define CAN_F2R1_FB29 ((uint32_t)0x20000000)
2492 #define CAN_F2R1_FB30 ((uint32_t)0x40000000)
2493 #define CAN_F2R1_FB31 ((uint32_t)0x80000000)
2495 /******************* Bit definition for CAN_F3R1 register *******************/
2496 #define CAN_F3R1_FB0 ((uint32_t)0x00000001)
2497 #define CAN_F3R1_FB1 ((uint32_t)0x00000002)
2498 #define CAN_F3R1_FB2 ((uint32_t)0x00000004)
2499 #define CAN_F3R1_FB3 ((uint32_t)0x00000008)
2500 #define CAN_F3R1_FB4 ((uint32_t)0x00000010)
2501 #define CAN_F3R1_FB5 ((uint32_t)0x00000020)
2502 #define CAN_F3R1_FB6 ((uint32_t)0x00000040)
2503 #define CAN_F3R1_FB7 ((uint32_t)0x00000080)
2504 #define CAN_F3R1_FB8 ((uint32_t)0x00000100)
2505 #define CAN_F3R1_FB9 ((uint32_t)0x00000200)
2506 #define CAN_F3R1_FB10 ((uint32_t)0x00000400)
2507 #define CAN_F3R1_FB11 ((uint32_t)0x00000800)
2508 #define CAN_F3R1_FB12 ((uint32_t)0x00001000)
2509 #define CAN_F3R1_FB13 ((uint32_t)0x00002000)
2510 #define CAN_F3R1_FB14 ((uint32_t)0x00004000)
2511 #define CAN_F3R1_FB15 ((uint32_t)0x00008000)
2512 #define CAN_F3R1_FB16 ((uint32_t)0x00010000)
2513 #define CAN_F3R1_FB17 ((uint32_t)0x00020000)
2514 #define CAN_F3R1_FB18 ((uint32_t)0x00040000)
2515 #define CAN_F3R1_FB19 ((uint32_t)0x00080000)
2516 #define CAN_F3R1_FB20 ((uint32_t)0x00100000)
2517 #define CAN_F3R1_FB21 ((uint32_t)0x00200000)
2518 #define CAN_F3R1_FB22 ((uint32_t)0x00400000)
2519 #define CAN_F3R1_FB23 ((uint32_t)0x00800000)
2520 #define CAN_F3R1_FB24 ((uint32_t)0x01000000)
2521 #define CAN_F3R1_FB25 ((uint32_t)0x02000000)
2522 #define CAN_F3R1_FB26 ((uint32_t)0x04000000)
2523 #define CAN_F3R1_FB27 ((uint32_t)0x08000000)
2524 #define CAN_F3R1_FB28 ((uint32_t)0x10000000)
2525 #define CAN_F3R1_FB29 ((uint32_t)0x20000000)
2526 #define CAN_F3R1_FB30 ((uint32_t)0x40000000)
2527 #define CAN_F3R1_FB31 ((uint32_t)0x80000000)
2529 /******************* Bit definition for CAN_F4R1 register *******************/
2530 #define CAN_F4R1_FB0 ((uint32_t)0x00000001)
2531 #define CAN_F4R1_FB1 ((uint32_t)0x00000002)
2532 #define CAN_F4R1_FB2 ((uint32_t)0x00000004)
2533 #define CAN_F4R1_FB3 ((uint32_t)0x00000008)
2534 #define CAN_F4R1_FB4 ((uint32_t)0x00000010)
2535 #define CAN_F4R1_FB5 ((uint32_t)0x00000020)
2536 #define CAN_F4R1_FB6 ((uint32_t)0x00000040)
2537 #define CAN_F4R1_FB7 ((uint32_t)0x00000080)
2538 #define CAN_F4R1_FB8 ((uint32_t)0x00000100)
2539 #define CAN_F4R1_FB9 ((uint32_t)0x00000200)
2540 #define CAN_F4R1_FB10 ((uint32_t)0x00000400)
2541 #define CAN_F4R1_FB11 ((uint32_t)0x00000800)
2542 #define CAN_F4R1_FB12 ((uint32_t)0x00001000)
2543 #define CAN_F4R1_FB13 ((uint32_t)0x00002000)
2544 #define CAN_F4R1_FB14 ((uint32_t)0x00004000)
2545 #define CAN_F4R1_FB15 ((uint32_t)0x00008000)
2546 #define CAN_F4R1_FB16 ((uint32_t)0x00010000)
2547 #define CAN_F4R1_FB17 ((uint32_t)0x00020000)
2548 #define CAN_F4R1_FB18 ((uint32_t)0x00040000)
2549 #define CAN_F4R1_FB19 ((uint32_t)0x00080000)
2550 #define CAN_F4R1_FB20 ((uint32_t)0x00100000)
2551 #define CAN_F4R1_FB21 ((uint32_t)0x00200000)
2552 #define CAN_F4R1_FB22 ((uint32_t)0x00400000)
2553 #define CAN_F4R1_FB23 ((uint32_t)0x00800000)
2554 #define CAN_F4R1_FB24 ((uint32_t)0x01000000)
2555 #define CAN_F4R1_FB25 ((uint32_t)0x02000000)
2556 #define CAN_F4R1_FB26 ((uint32_t)0x04000000)
2557 #define CAN_F4R1_FB27 ((uint32_t)0x08000000)
2558 #define CAN_F4R1_FB28 ((uint32_t)0x10000000)
2559 #define CAN_F4R1_FB29 ((uint32_t)0x20000000)
2560 #define CAN_F4R1_FB30 ((uint32_t)0x40000000)
2561 #define CAN_F4R1_FB31 ((uint32_t)0x80000000)
2563 /******************* Bit definition for CAN_F5R1 register *******************/
2564 #define CAN_F5R1_FB0 ((uint32_t)0x00000001)
2565 #define CAN_F5R1_FB1 ((uint32_t)0x00000002)
2566 #define CAN_F5R1_FB2 ((uint32_t)0x00000004)
2567 #define CAN_F5R1_FB3 ((uint32_t)0x00000008)
2568 #define CAN_F5R1_FB4 ((uint32_t)0x00000010)
2569 #define CAN_F5R1_FB5 ((uint32_t)0x00000020)
2570 #define CAN_F5R1_FB6 ((uint32_t)0x00000040)
2571 #define CAN_F5R1_FB7 ((uint32_t)0x00000080)
2572 #define CAN_F5R1_FB8 ((uint32_t)0x00000100)
2573 #define CAN_F5R1_FB9 ((uint32_t)0x00000200)
2574 #define CAN_F5R1_FB10 ((uint32_t)0x00000400)
2575 #define CAN_F5R1_FB11 ((uint32_t)0x00000800)
2576 #define CAN_F5R1_FB12 ((uint32_t)0x00001000)
2577 #define CAN_F5R1_FB13 ((uint32_t)0x00002000)
2578 #define CAN_F5R1_FB14 ((uint32_t)0x00004000)
2579 #define CAN_F5R1_FB15 ((uint32_t)0x00008000)
2580 #define CAN_F5R1_FB16 ((uint32_t)0x00010000)
2581 #define CAN_F5R1_FB17 ((uint32_t)0x00020000)
2582 #define CAN_F5R1_FB18 ((uint32_t)0x00040000)
2583 #define CAN_F5R1_FB19 ((uint32_t)0x00080000)
2584 #define CAN_F5R1_FB20 ((uint32_t)0x00100000)
2585 #define CAN_F5R1_FB21 ((uint32_t)0x00200000)
2586 #define CAN_F5R1_FB22 ((uint32_t)0x00400000)
2587 #define CAN_F5R1_FB23 ((uint32_t)0x00800000)
2588 #define CAN_F5R1_FB24 ((uint32_t)0x01000000)
2589 #define CAN_F5R1_FB25 ((uint32_t)0x02000000)
2590 #define CAN_F5R1_FB26 ((uint32_t)0x04000000)
2591 #define CAN_F5R1_FB27 ((uint32_t)0x08000000)
2592 #define CAN_F5R1_FB28 ((uint32_t)0x10000000)
2593 #define CAN_F5R1_FB29 ((uint32_t)0x20000000)
2594 #define CAN_F5R1_FB30 ((uint32_t)0x40000000)
2595 #define CAN_F5R1_FB31 ((uint32_t)0x80000000)
2597 /******************* Bit definition for CAN_F6R1 register *******************/
2598 #define CAN_F6R1_FB0 ((uint32_t)0x00000001)
2599 #define CAN_F6R1_FB1 ((uint32_t)0x00000002)
2600 #define CAN_F6R1_FB2 ((uint32_t)0x00000004)
2601 #define CAN_F6R1_FB3 ((uint32_t)0x00000008)
2602 #define CAN_F6R1_FB4 ((uint32_t)0x00000010)
2603 #define CAN_F6R1_FB5 ((uint32_t)0x00000020)
2604 #define CAN_F6R1_FB6 ((uint32_t)0x00000040)
2605 #define CAN_F6R1_FB7 ((uint32_t)0x00000080)
2606 #define CAN_F6R1_FB8 ((uint32_t)0x00000100)
2607 #define CAN_F6R1_FB9 ((uint32_t)0x00000200)
2608 #define CAN_F6R1_FB10 ((uint32_t)0x00000400)
2609 #define CAN_F6R1_FB11 ((uint32_t)0x00000800)
2610 #define CAN_F6R1_FB12 ((uint32_t)0x00001000)
2611 #define CAN_F6R1_FB13 ((uint32_t)0x00002000)
2612 #define CAN_F6R1_FB14 ((uint32_t)0x00004000)
2613 #define CAN_F6R1_FB15 ((uint32_t)0x00008000)
2614 #define CAN_F6R1_FB16 ((uint32_t)0x00010000)
2615 #define CAN_F6R1_FB17 ((uint32_t)0x00020000)
2616 #define CAN_F6R1_FB18 ((uint32_t)0x00040000)
2617 #define CAN_F6R1_FB19 ((uint32_t)0x00080000)
2618 #define CAN_F6R1_FB20 ((uint32_t)0x00100000)
2619 #define CAN_F6R1_FB21 ((uint32_t)0x00200000)
2620 #define CAN_F6R1_FB22 ((uint32_t)0x00400000)
2621 #define CAN_F6R1_FB23 ((uint32_t)0x00800000)
2622 #define CAN_F6R1_FB24 ((uint32_t)0x01000000)
2623 #define CAN_F6R1_FB25 ((uint32_t)0x02000000)
2624 #define CAN_F6R1_FB26 ((uint32_t)0x04000000)
2625 #define CAN_F6R1_FB27 ((uint32_t)0x08000000)
2626 #define CAN_F6R1_FB28 ((uint32_t)0x10000000)
2627 #define CAN_F6R1_FB29 ((uint32_t)0x20000000)
2628 #define CAN_F6R1_FB30 ((uint32_t)0x40000000)
2629 #define CAN_F6R1_FB31 ((uint32_t)0x80000000)
2631 /******************* Bit definition for CAN_F7R1 register *******************/
2632 #define CAN_F7R1_FB0 ((uint32_t)0x00000001)
2633 #define CAN_F7R1_FB1 ((uint32_t)0x00000002)
2634 #define CAN_F7R1_FB2 ((uint32_t)0x00000004)
2635 #define CAN_F7R1_FB3 ((uint32_t)0x00000008)
2636 #define CAN_F7R1_FB4 ((uint32_t)0x00000010)
2637 #define CAN_F7R1_FB5 ((uint32_t)0x00000020)
2638 #define CAN_F7R1_FB6 ((uint32_t)0x00000040)
2639 #define CAN_F7R1_FB7 ((uint32_t)0x00000080)
2640 #define CAN_F7R1_FB8 ((uint32_t)0x00000100)
2641 #define CAN_F7R1_FB9 ((uint32_t)0x00000200)
2642 #define CAN_F7R1_FB10 ((uint32_t)0x00000400)
2643 #define CAN_F7R1_FB11 ((uint32_t)0x00000800)
2644 #define CAN_F7R1_FB12 ((uint32_t)0x00001000)
2645 #define CAN_F7R1_FB13 ((uint32_t)0x00002000)
2646 #define CAN_F7R1_FB14 ((uint32_t)0x00004000)
2647 #define CAN_F7R1_FB15 ((uint32_t)0x00008000)
2648 #define CAN_F7R1_FB16 ((uint32_t)0x00010000)
2649 #define CAN_F7R1_FB17 ((uint32_t)0x00020000)
2650 #define CAN_F7R1_FB18 ((uint32_t)0x00040000)
2651 #define CAN_F7R1_FB19 ((uint32_t)0x00080000)
2652 #define CAN_F7R1_FB20 ((uint32_t)0x00100000)
2653 #define CAN_F7R1_FB21 ((uint32_t)0x00200000)
2654 #define CAN_F7R1_FB22 ((uint32_t)0x00400000)
2655 #define CAN_F7R1_FB23 ((uint32_t)0x00800000)
2656 #define CAN_F7R1_FB24 ((uint32_t)0x01000000)
2657 #define CAN_F7R1_FB25 ((uint32_t)0x02000000)
2658 #define CAN_F7R1_FB26 ((uint32_t)0x04000000)
2659 #define CAN_F7R1_FB27 ((uint32_t)0x08000000)
2660 #define CAN_F7R1_FB28 ((uint32_t)0x10000000)
2661 #define CAN_F7R1_FB29 ((uint32_t)0x20000000)
2662 #define CAN_F7R1_FB30 ((uint32_t)0x40000000)
2663 #define CAN_F7R1_FB31 ((uint32_t)0x80000000)
2665 /******************* Bit definition for CAN_F8R1 register *******************/
2666 #define CAN_F8R1_FB0 ((uint32_t)0x00000001)
2667 #define CAN_F8R1_FB1 ((uint32_t)0x00000002)
2668 #define CAN_F8R1_FB2 ((uint32_t)0x00000004)
2669 #define CAN_F8R1_FB3 ((uint32_t)0x00000008)
2670 #define CAN_F8R1_FB4 ((uint32_t)0x00000010)
2671 #define CAN_F8R1_FB5 ((uint32_t)0x00000020)
2672 #define CAN_F8R1_FB6 ((uint32_t)0x00000040)
2673 #define CAN_F8R1_FB7 ((uint32_t)0x00000080)
2674 #define CAN_F8R1_FB8 ((uint32_t)0x00000100)
2675 #define CAN_F8R1_FB9 ((uint32_t)0x00000200)
2676 #define CAN_F8R1_FB10 ((uint32_t)0x00000400)
2677 #define CAN_F8R1_FB11 ((uint32_t)0x00000800)
2678 #define CAN_F8R1_FB12 ((uint32_t)0x00001000)
2679 #define CAN_F8R1_FB13 ((uint32_t)0x00002000)
2680 #define CAN_F8R1_FB14 ((uint32_t)0x00004000)
2681 #define CAN_F8R1_FB15 ((uint32_t)0x00008000)
2682 #define CAN_F8R1_FB16 ((uint32_t)0x00010000)
2683 #define CAN_F8R1_FB17 ((uint32_t)0x00020000)
2684 #define CAN_F8R1_FB18 ((uint32_t)0x00040000)
2685 #define CAN_F8R1_FB19 ((uint32_t)0x00080000)
2686 #define CAN_F8R1_FB20 ((uint32_t)0x00100000)
2687 #define CAN_F8R1_FB21 ((uint32_t)0x00200000)
2688 #define CAN_F8R1_FB22 ((uint32_t)0x00400000)
2689 #define CAN_F8R1_FB23 ((uint32_t)0x00800000)
2690 #define CAN_F8R1_FB24 ((uint32_t)0x01000000)
2691 #define CAN_F8R1_FB25 ((uint32_t)0x02000000)
2692 #define CAN_F8R1_FB26 ((uint32_t)0x04000000)
2693 #define CAN_F8R1_FB27 ((uint32_t)0x08000000)
2694 #define CAN_F8R1_FB28 ((uint32_t)0x10000000)
2695 #define CAN_F8R1_FB29 ((uint32_t)0x20000000)
2696 #define CAN_F8R1_FB30 ((uint32_t)0x40000000)
2697 #define CAN_F8R1_FB31 ((uint32_t)0x80000000)
2699 /******************* Bit definition for CAN_F9R1 register *******************/
2700 #define CAN_F9R1_FB0 ((uint32_t)0x00000001)
2701 #define CAN_F9R1_FB1 ((uint32_t)0x00000002)
2702 #define CAN_F9R1_FB2 ((uint32_t)0x00000004)
2703 #define CAN_F9R1_FB3 ((uint32_t)0x00000008)
2704 #define CAN_F9R1_FB4 ((uint32_t)0x00000010)
2705 #define CAN_F9R1_FB5 ((uint32_t)0x00000020)
2706 #define CAN_F9R1_FB6 ((uint32_t)0x00000040)
2707 #define CAN_F9R1_FB7 ((uint32_t)0x00000080)
2708 #define CAN_F9R1_FB8 ((uint32_t)0x00000100)
2709 #define CAN_F9R1_FB9 ((uint32_t)0x00000200)
2710 #define CAN_F9R1_FB10 ((uint32_t)0x00000400)
2711 #define CAN_F9R1_FB11 ((uint32_t)0x00000800)
2712 #define CAN_F9R1_FB12 ((uint32_t)0x00001000)
2713 #define CAN_F9R1_FB13 ((uint32_t)0x00002000)
2714 #define CAN_F9R1_FB14 ((uint32_t)0x00004000)
2715 #define CAN_F9R1_FB15 ((uint32_t)0x00008000)
2716 #define CAN_F9R1_FB16 ((uint32_t)0x00010000)
2717 #define CAN_F9R1_FB17 ((uint32_t)0x00020000)
2718 #define CAN_F9R1_FB18 ((uint32_t)0x00040000)
2719 #define CAN_F9R1_FB19 ((uint32_t)0x00080000)
2720 #define CAN_F9R1_FB20 ((uint32_t)0x00100000)
2721 #define CAN_F9R1_FB21 ((uint32_t)0x00200000)
2722 #define CAN_F9R1_FB22 ((uint32_t)0x00400000)
2723 #define CAN_F9R1_FB23 ((uint32_t)0x00800000)
2724 #define CAN_F9R1_FB24 ((uint32_t)0x01000000)
2725 #define CAN_F9R1_FB25 ((uint32_t)0x02000000)
2726 #define CAN_F9R1_FB26 ((uint32_t)0x04000000)
2727 #define CAN_F9R1_FB27 ((uint32_t)0x08000000)
2728 #define CAN_F9R1_FB28 ((uint32_t)0x10000000)
2729 #define CAN_F9R1_FB29 ((uint32_t)0x20000000)
2730 #define CAN_F9R1_FB30 ((uint32_t)0x40000000)
2731 #define CAN_F9R1_FB31 ((uint32_t)0x80000000)
2733 /******************* Bit definition for CAN_F10R1 register ******************/
2734 #define CAN_F10R1_FB0 ((uint32_t)0x00000001)
2735 #define CAN_F10R1_FB1 ((uint32_t)0x00000002)
2736 #define CAN_F10R1_FB2 ((uint32_t)0x00000004)
2737 #define CAN_F10R1_FB3 ((uint32_t)0x00000008)
2738 #define CAN_F10R1_FB4 ((uint32_t)0x00000010)
2739 #define CAN_F10R1_FB5 ((uint32_t)0x00000020)
2740 #define CAN_F10R1_FB6 ((uint32_t)0x00000040)
2741 #define CAN_F10R1_FB7 ((uint32_t)0x00000080)
2742 #define CAN_F10R1_FB8 ((uint32_t)0x00000100)
2743 #define CAN_F10R1_FB9 ((uint32_t)0x00000200)
2744 #define CAN_F10R1_FB10 ((uint32_t)0x00000400)
2745 #define CAN_F10R1_FB11 ((uint32_t)0x00000800)
2746 #define CAN_F10R1_FB12 ((uint32_t)0x00001000)
2747 #define CAN_F10R1_FB13 ((uint32_t)0x00002000)
2748 #define CAN_F10R1_FB14 ((uint32_t)0x00004000)
2749 #define CAN_F10R1_FB15 ((uint32_t)0x00008000)
2750 #define CAN_F10R1_FB16 ((uint32_t)0x00010000)
2751 #define CAN_F10R1_FB17 ((uint32_t)0x00020000)
2752 #define CAN_F10R1_FB18 ((uint32_t)0x00040000)
2753 #define CAN_F10R1_FB19 ((uint32_t)0x00080000)
2754 #define CAN_F10R1_FB20 ((uint32_t)0x00100000)
2755 #define CAN_F10R1_FB21 ((uint32_t)0x00200000)
2756 #define CAN_F10R1_FB22 ((uint32_t)0x00400000)
2757 #define CAN_F10R1_FB23 ((uint32_t)0x00800000)
2758 #define CAN_F10R1_FB24 ((uint32_t)0x01000000)
2759 #define CAN_F10R1_FB25 ((uint32_t)0x02000000)
2760 #define CAN_F10R1_FB26 ((uint32_t)0x04000000)
2761 #define CAN_F10R1_FB27 ((uint32_t)0x08000000)
2762 #define CAN_F10R1_FB28 ((uint32_t)0x10000000)
2763 #define CAN_F10R1_FB29 ((uint32_t)0x20000000)
2764 #define CAN_F10R1_FB30 ((uint32_t)0x40000000)
2765 #define CAN_F10R1_FB31 ((uint32_t)0x80000000)
2767 /******************* Bit definition for CAN_F11R1 register ******************/
2768 #define CAN_F11R1_FB0 ((uint32_t)0x00000001)
2769 #define CAN_F11R1_FB1 ((uint32_t)0x00000002)
2770 #define CAN_F11R1_FB2 ((uint32_t)0x00000004)
2771 #define CAN_F11R1_FB3 ((uint32_t)0x00000008)
2772 #define CAN_F11R1_FB4 ((uint32_t)0x00000010)
2773 #define CAN_F11R1_FB5 ((uint32_t)0x00000020)
2774 #define CAN_F11R1_FB6 ((uint32_t)0x00000040)
2775 #define CAN_F11R1_FB7 ((uint32_t)0x00000080)
2776 #define CAN_F11R1_FB8 ((uint32_t)0x00000100)
2777 #define CAN_F11R1_FB9 ((uint32_t)0x00000200)
2778 #define CAN_F11R1_FB10 ((uint32_t)0x00000400)
2779 #define CAN_F11R1_FB11 ((uint32_t)0x00000800)
2780 #define CAN_F11R1_FB12 ((uint32_t)0x00001000)
2781 #define CAN_F11R1_FB13 ((uint32_t)0x00002000)
2782 #define CAN_F11R1_FB14 ((uint32_t)0x00004000)
2783 #define CAN_F11R1_FB15 ((uint32_t)0x00008000)
2784 #define CAN_F11R1_FB16 ((uint32_t)0x00010000)
2785 #define CAN_F11R1_FB17 ((uint32_t)0x00020000)
2786 #define CAN_F11R1_FB18 ((uint32_t)0x00040000)
2787 #define CAN_F11R1_FB19 ((uint32_t)0x00080000)
2788 #define CAN_F11R1_FB20 ((uint32_t)0x00100000)
2789 #define CAN_F11R1_FB21 ((uint32_t)0x00200000)
2790 #define CAN_F11R1_FB22 ((uint32_t)0x00400000)
2791 #define CAN_F11R1_FB23 ((uint32_t)0x00800000)
2792 #define CAN_F11R1_FB24 ((uint32_t)0x01000000)
2793 #define CAN_F11R1_FB25 ((uint32_t)0x02000000)
2794 #define CAN_F11R1_FB26 ((uint32_t)0x04000000)
2795 #define CAN_F11R1_FB27 ((uint32_t)0x08000000)
2796 #define CAN_F11R1_FB28 ((uint32_t)0x10000000)
2797 #define CAN_F11R1_FB29 ((uint32_t)0x20000000)
2798 #define CAN_F11R1_FB30 ((uint32_t)0x40000000)
2799 #define CAN_F11R1_FB31 ((uint32_t)0x80000000)
2801 /******************* Bit definition for CAN_F12R1 register ******************/
2802 #define CAN_F12R1_FB0 ((uint32_t)0x00000001)
2803 #define CAN_F12R1_FB1 ((uint32_t)0x00000002)
2804 #define CAN_F12R1_FB2 ((uint32_t)0x00000004)
2805 #define CAN_F12R1_FB3 ((uint32_t)0x00000008)
2806 #define CAN_F12R1_FB4 ((uint32_t)0x00000010)
2807 #define CAN_F12R1_FB5 ((uint32_t)0x00000020)
2808 #define CAN_F12R1_FB6 ((uint32_t)0x00000040)
2809 #define CAN_F12R1_FB7 ((uint32_t)0x00000080)
2810 #define CAN_F12R1_FB8 ((uint32_t)0x00000100)
2811 #define CAN_F12R1_FB9 ((uint32_t)0x00000200)
2812 #define CAN_F12R1_FB10 ((uint32_t)0x00000400)
2813 #define CAN_F12R1_FB11 ((uint32_t)0x00000800)
2814 #define CAN_F12R1_FB12 ((uint32_t)0x00001000)
2815 #define CAN_F12R1_FB13 ((uint32_t)0x00002000)
2816 #define CAN_F12R1_FB14 ((uint32_t)0x00004000)
2817 #define CAN_F12R1_FB15 ((uint32_t)0x00008000)
2818 #define CAN_F12R1_FB16 ((uint32_t)0x00010000)
2819 #define CAN_F12R1_FB17 ((uint32_t)0x00020000)
2820 #define CAN_F12R1_FB18 ((uint32_t)0x00040000)
2821 #define CAN_F12R1_FB19 ((uint32_t)0x00080000)
2822 #define CAN_F12R1_FB20 ((uint32_t)0x00100000)
2823 #define CAN_F12R1_FB21 ((uint32_t)0x00200000)
2824 #define CAN_F12R1_FB22 ((uint32_t)0x00400000)
2825 #define CAN_F12R1_FB23 ((uint32_t)0x00800000)
2826 #define CAN_F12R1_FB24 ((uint32_t)0x01000000)
2827 #define CAN_F12R1_FB25 ((uint32_t)0x02000000)
2828 #define CAN_F12R1_FB26 ((uint32_t)0x04000000)
2829 #define CAN_F12R1_FB27 ((uint32_t)0x08000000)
2830 #define CAN_F12R1_FB28 ((uint32_t)0x10000000)
2831 #define CAN_F12R1_FB29 ((uint32_t)0x20000000)
2832 #define CAN_F12R1_FB30 ((uint32_t)0x40000000)
2833 #define CAN_F12R1_FB31 ((uint32_t)0x80000000)
2835 /******************* Bit definition for CAN_F13R1 register ******************/
2836 #define CAN_F13R1_FB0 ((uint32_t)0x00000001)
2837 #define CAN_F13R1_FB1 ((uint32_t)0x00000002)
2838 #define CAN_F13R1_FB2 ((uint32_t)0x00000004)
2839 #define CAN_F13R1_FB3 ((uint32_t)0x00000008)
2840 #define CAN_F13R1_FB4 ((uint32_t)0x00000010)
2841 #define CAN_F13R1_FB5 ((uint32_t)0x00000020)
2842 #define CAN_F13R1_FB6 ((uint32_t)0x00000040)
2843 #define CAN_F13R1_FB7 ((uint32_t)0x00000080)
2844 #define CAN_F13R1_FB8 ((uint32_t)0x00000100)
2845 #define CAN_F13R1_FB9 ((uint32_t)0x00000200)
2846 #define CAN_F13R1_FB10 ((uint32_t)0x00000400)
2847 #define CAN_F13R1_FB11 ((uint32_t)0x00000800)
2848 #define CAN_F13R1_FB12 ((uint32_t)0x00001000)
2849 #define CAN_F13R1_FB13 ((uint32_t)0x00002000)
2850 #define CAN_F13R1_FB14 ((uint32_t)0x00004000)
2851 #define CAN_F13R1_FB15 ((uint32_t)0x00008000)
2852 #define CAN_F13R1_FB16 ((uint32_t)0x00010000)
2853 #define CAN_F13R1_FB17 ((uint32_t)0x00020000)
2854 #define CAN_F13R1_FB18 ((uint32_t)0x00040000)
2855 #define CAN_F13R1_FB19 ((uint32_t)0x00080000)
2856 #define CAN_F13R1_FB20 ((uint32_t)0x00100000)
2857 #define CAN_F13R1_FB21 ((uint32_t)0x00200000)
2858 #define CAN_F13R1_FB22 ((uint32_t)0x00400000)
2859 #define CAN_F13R1_FB23 ((uint32_t)0x00800000)
2860 #define CAN_F13R1_FB24 ((uint32_t)0x01000000)
2861 #define CAN_F13R1_FB25 ((uint32_t)0x02000000)
2862 #define CAN_F13R1_FB26 ((uint32_t)0x04000000)
2863 #define CAN_F13R1_FB27 ((uint32_t)0x08000000)
2864 #define CAN_F13R1_FB28 ((uint32_t)0x10000000)
2865 #define CAN_F13R1_FB29 ((uint32_t)0x20000000)
2866 #define CAN_F13R1_FB30 ((uint32_t)0x40000000)
2867 #define CAN_F13R1_FB31 ((uint32_t)0x80000000)
2869 /******************* Bit definition for CAN_F0R2 register *******************/
2870 #define CAN_F0R2_FB0 ((uint32_t)0x00000001)
2871 #define CAN_F0R2_FB1 ((uint32_t)0x00000002)
2872 #define CAN_F0R2_FB2 ((uint32_t)0x00000004)
2873 #define CAN_F0R2_FB3 ((uint32_t)0x00000008)
2874 #define CAN_F0R2_FB4 ((uint32_t)0x00000010)
2875 #define CAN_F0R2_FB5 ((uint32_t)0x00000020)
2876 #define CAN_F0R2_FB6 ((uint32_t)0x00000040)
2877 #define CAN_F0R2_FB7 ((uint32_t)0x00000080)
2878 #define CAN_F0R2_FB8 ((uint32_t)0x00000100)
2879 #define CAN_F0R2_FB9 ((uint32_t)0x00000200)
2880 #define CAN_F0R2_FB10 ((uint32_t)0x00000400)
2881 #define CAN_F0R2_FB11 ((uint32_t)0x00000800)
2882 #define CAN_F0R2_FB12 ((uint32_t)0x00001000)
2883 #define CAN_F0R2_FB13 ((uint32_t)0x00002000)
2884 #define CAN_F0R2_FB14 ((uint32_t)0x00004000)
2885 #define CAN_F0R2_FB15 ((uint32_t)0x00008000)
2886 #define CAN_F0R2_FB16 ((uint32_t)0x00010000)
2887 #define CAN_F0R2_FB17 ((uint32_t)0x00020000)
2888 #define CAN_F0R2_FB18 ((uint32_t)0x00040000)
2889 #define CAN_F0R2_FB19 ((uint32_t)0x00080000)
2890 #define CAN_F0R2_FB20 ((uint32_t)0x00100000)
2891 #define CAN_F0R2_FB21 ((uint32_t)0x00200000)
2892 #define CAN_F0R2_FB22 ((uint32_t)0x00400000)
2893 #define CAN_F0R2_FB23 ((uint32_t)0x00800000)
2894 #define CAN_F0R2_FB24 ((uint32_t)0x01000000)
2895 #define CAN_F0R2_FB25 ((uint32_t)0x02000000)
2896 #define CAN_F0R2_FB26 ((uint32_t)0x04000000)
2897 #define CAN_F0R2_FB27 ((uint32_t)0x08000000)
2898 #define CAN_F0R2_FB28 ((uint32_t)0x10000000)
2899 #define CAN_F0R2_FB29 ((uint32_t)0x20000000)
2900 #define CAN_F0R2_FB30 ((uint32_t)0x40000000)
2901 #define CAN_F0R2_FB31 ((uint32_t)0x80000000)
2903 /******************* Bit definition for CAN_F1R2 register *******************/
2904 #define CAN_F1R2_FB0 ((uint32_t)0x00000001)
2905 #define CAN_F1R2_FB1 ((uint32_t)0x00000002)
2906 #define CAN_F1R2_FB2 ((uint32_t)0x00000004)
2907 #define CAN_F1R2_FB3 ((uint32_t)0x00000008)
2908 #define CAN_F1R2_FB4 ((uint32_t)0x00000010)
2909 #define CAN_F1R2_FB5 ((uint32_t)0x00000020)
2910 #define CAN_F1R2_FB6 ((uint32_t)0x00000040)
2911 #define CAN_F1R2_FB7 ((uint32_t)0x00000080)
2912 #define CAN_F1R2_FB8 ((uint32_t)0x00000100)
2913 #define CAN_F1R2_FB9 ((uint32_t)0x00000200)
2914 #define CAN_F1R2_FB10 ((uint32_t)0x00000400)
2915 #define CAN_F1R2_FB11 ((uint32_t)0x00000800)
2916 #define CAN_F1R2_FB12 ((uint32_t)0x00001000)
2917 #define CAN_F1R2_FB13 ((uint32_t)0x00002000)
2918 #define CAN_F1R2_FB14 ((uint32_t)0x00004000)
2919 #define CAN_F1R2_FB15 ((uint32_t)0x00008000)
2920 #define CAN_F1R2_FB16 ((uint32_t)0x00010000)
2921 #define CAN_F1R2_FB17 ((uint32_t)0x00020000)
2922 #define CAN_F1R2_FB18 ((uint32_t)0x00040000)
2923 #define CAN_F1R2_FB19 ((uint32_t)0x00080000)
2924 #define CAN_F1R2_FB20 ((uint32_t)0x00100000)
2925 #define CAN_F1R2_FB21 ((uint32_t)0x00200000)
2926 #define CAN_F1R2_FB22 ((uint32_t)0x00400000)
2927 #define CAN_F1R2_FB23 ((uint32_t)0x00800000)
2928 #define CAN_F1R2_FB24 ((uint32_t)0x01000000)
2929 #define CAN_F1R2_FB25 ((uint32_t)0x02000000)
2930 #define CAN_F1R2_FB26 ((uint32_t)0x04000000)
2931 #define CAN_F1R2_FB27 ((uint32_t)0x08000000)
2932 #define CAN_F1R2_FB28 ((uint32_t)0x10000000)
2933 #define CAN_F1R2_FB29 ((uint32_t)0x20000000)
2934 #define CAN_F1R2_FB30 ((uint32_t)0x40000000)
2935 #define CAN_F1R2_FB31 ((uint32_t)0x80000000)
2937 /******************* Bit definition for CAN_F2R2 register *******************/
2938 #define CAN_F2R2_FB0 ((uint32_t)0x00000001)
2939 #define CAN_F2R2_FB1 ((uint32_t)0x00000002)
2940 #define CAN_F2R2_FB2 ((uint32_t)0x00000004)
2941 #define CAN_F2R2_FB3 ((uint32_t)0x00000008)
2942 #define CAN_F2R2_FB4 ((uint32_t)0x00000010)
2943 #define CAN_F2R2_FB5 ((uint32_t)0x00000020)
2944 #define CAN_F2R2_FB6 ((uint32_t)0x00000040)
2945 #define CAN_F2R2_FB7 ((uint32_t)0x00000080)
2946 #define CAN_F2R2_FB8 ((uint32_t)0x00000100)
2947 #define CAN_F2R2_FB9 ((uint32_t)0x00000200)
2948 #define CAN_F2R2_FB10 ((uint32_t)0x00000400)
2949 #define CAN_F2R2_FB11 ((uint32_t)0x00000800)
2950 #define CAN_F2R2_FB12 ((uint32_t)0x00001000)
2951 #define CAN_F2R2_FB13 ((uint32_t)0x00002000)
2952 #define CAN_F2R2_FB14 ((uint32_t)0x00004000)
2953 #define CAN_F2R2_FB15 ((uint32_t)0x00008000)
2954 #define CAN_F2R2_FB16 ((uint32_t)0x00010000)
2955 #define CAN_F2R2_FB17 ((uint32_t)0x00020000)
2956 #define CAN_F2R2_FB18 ((uint32_t)0x00040000)
2957 #define CAN_F2R2_FB19 ((uint32_t)0x00080000)
2958 #define CAN_F2R2_FB20 ((uint32_t)0x00100000)
2959 #define CAN_F2R2_FB21 ((uint32_t)0x00200000)
2960 #define CAN_F2R2_FB22 ((uint32_t)0x00400000)
2961 #define CAN_F2R2_FB23 ((uint32_t)0x00800000)
2962 #define CAN_F2R2_FB24 ((uint32_t)0x01000000)
2963 #define CAN_F2R2_FB25 ((uint32_t)0x02000000)
2964 #define CAN_F2R2_FB26 ((uint32_t)0x04000000)
2965 #define CAN_F2R2_FB27 ((uint32_t)0x08000000)
2966 #define CAN_F2R2_FB28 ((uint32_t)0x10000000)
2967 #define CAN_F2R2_FB29 ((uint32_t)0x20000000)
2968 #define CAN_F2R2_FB30 ((uint32_t)0x40000000)
2969 #define CAN_F2R2_FB31 ((uint32_t)0x80000000)
2971 /******************* Bit definition for CAN_F3R2 register *******************/
2972 #define CAN_F3R2_FB0 ((uint32_t)0x00000001)
2973 #define CAN_F3R2_FB1 ((uint32_t)0x00000002)
2974 #define CAN_F3R2_FB2 ((uint32_t)0x00000004)
2975 #define CAN_F3R2_FB3 ((uint32_t)0x00000008)
2976 #define CAN_F3R2_FB4 ((uint32_t)0x00000010)
2977 #define CAN_F3R2_FB5 ((uint32_t)0x00000020)
2978 #define CAN_F3R2_FB6 ((uint32_t)0x00000040)
2979 #define CAN_F3R2_FB7 ((uint32_t)0x00000080)
2980 #define CAN_F3R2_FB8 ((uint32_t)0x00000100)
2981 #define CAN_F3R2_FB9 ((uint32_t)0x00000200)
2982 #define CAN_F3R2_FB10 ((uint32_t)0x00000400)
2983 #define CAN_F3R2_FB11 ((uint32_t)0x00000800)
2984 #define CAN_F3R2_FB12 ((uint32_t)0x00001000)
2985 #define CAN_F3R2_FB13 ((uint32_t)0x00002000)
2986 #define CAN_F3R2_FB14 ((uint32_t)0x00004000)
2987 #define CAN_F3R2_FB15 ((uint32_t)0x00008000)
2988 #define CAN_F3R2_FB16 ((uint32_t)0x00010000)
2989 #define CAN_F3R2_FB17 ((uint32_t)0x00020000)
2990 #define CAN_F3R2_FB18 ((uint32_t)0x00040000)
2991 #define CAN_F3R2_FB19 ((uint32_t)0x00080000)
2992 #define CAN_F3R2_FB20 ((uint32_t)0x00100000)
2993 #define CAN_F3R2_FB21 ((uint32_t)0x00200000)
2994 #define CAN_F3R2_FB22 ((uint32_t)0x00400000)
2995 #define CAN_F3R2_FB23 ((uint32_t)0x00800000)
2996 #define CAN_F3R2_FB24 ((uint32_t)0x01000000)
2997 #define CAN_F3R2_FB25 ((uint32_t)0x02000000)
2998 #define CAN_F3R2_FB26 ((uint32_t)0x04000000)
2999 #define CAN_F3R2_FB27 ((uint32_t)0x08000000)
3000 #define CAN_F3R2_FB28 ((uint32_t)0x10000000)
3001 #define CAN_F3R2_FB29 ((uint32_t)0x20000000)
3002 #define CAN_F3R2_FB30 ((uint32_t)0x40000000)
3003 #define CAN_F3R2_FB31 ((uint32_t)0x80000000)
3005 /******************* Bit definition for CAN_F4R2 register *******************/
3006 #define CAN_F4R2_FB0 ((uint32_t)0x00000001)
3007 #define CAN_F4R2_FB1 ((uint32_t)0x00000002)
3008 #define CAN_F4R2_FB2 ((uint32_t)0x00000004)
3009 #define CAN_F4R2_FB3 ((uint32_t)0x00000008)
3010 #define CAN_F4R2_FB4 ((uint32_t)0x00000010)
3011 #define CAN_F4R2_FB5 ((uint32_t)0x00000020)
3012 #define CAN_F4R2_FB6 ((uint32_t)0x00000040)
3013 #define CAN_F4R2_FB7 ((uint32_t)0x00000080)
3014 #define CAN_F4R2_FB8 ((uint32_t)0x00000100)
3015 #define CAN_F4R2_FB9 ((uint32_t)0x00000200)
3016 #define CAN_F4R2_FB10 ((uint32_t)0x00000400)
3017 #define CAN_F4R2_FB11 ((uint32_t)0x00000800)
3018 #define CAN_F4R2_FB12 ((uint32_t)0x00001000)
3019 #define CAN_F4R2_FB13 ((uint32_t)0x00002000)
3020 #define CAN_F4R2_FB14 ((uint32_t)0x00004000)
3021 #define CAN_F4R2_FB15 ((uint32_t)0x00008000)
3022 #define CAN_F4R2_FB16 ((uint32_t)0x00010000)
3023 #define CAN_F4R2_FB17 ((uint32_t)0x00020000)
3024 #define CAN_F4R2_FB18 ((uint32_t)0x00040000)
3025 #define CAN_F4R2_FB19 ((uint32_t)0x00080000)
3026 #define CAN_F4R2_FB20 ((uint32_t)0x00100000)
3027 #define CAN_F4R2_FB21 ((uint32_t)0x00200000)
3028 #define CAN_F4R2_FB22 ((uint32_t)0x00400000)
3029 #define CAN_F4R2_FB23 ((uint32_t)0x00800000)
3030 #define CAN_F4R2_FB24 ((uint32_t)0x01000000)
3031 #define CAN_F4R2_FB25 ((uint32_t)0x02000000)
3032 #define CAN_F4R2_FB26 ((uint32_t)0x04000000)
3033 #define CAN_F4R2_FB27 ((uint32_t)0x08000000)
3034 #define CAN_F4R2_FB28 ((uint32_t)0x10000000)
3035 #define CAN_F4R2_FB29 ((uint32_t)0x20000000)
3036 #define CAN_F4R2_FB30 ((uint32_t)0x40000000)
3037 #define CAN_F4R2_FB31 ((uint32_t)0x80000000)
3039 /******************* Bit definition for CAN_F5R2 register *******************/
3040 #define CAN_F5R2_FB0 ((uint32_t)0x00000001)
3041 #define CAN_F5R2_FB1 ((uint32_t)0x00000002)
3042 #define CAN_F5R2_FB2 ((uint32_t)0x00000004)
3043 #define CAN_F5R2_FB3 ((uint32_t)0x00000008)
3044 #define CAN_F5R2_FB4 ((uint32_t)0x00000010)
3045 #define CAN_F5R2_FB5 ((uint32_t)0x00000020)
3046 #define CAN_F5R2_FB6 ((uint32_t)0x00000040)
3047 #define CAN_F5R2_FB7 ((uint32_t)0x00000080)
3048 #define CAN_F5R2_FB8 ((uint32_t)0x00000100)
3049 #define CAN_F5R2_FB9 ((uint32_t)0x00000200)
3050 #define CAN_F5R2_FB10 ((uint32_t)0x00000400)
3051 #define CAN_F5R2_FB11 ((uint32_t)0x00000800)
3052 #define CAN_F5R2_FB12 ((uint32_t)0x00001000)
3053 #define CAN_F5R2_FB13 ((uint32_t)0x00002000)
3054 #define CAN_F5R2_FB14 ((uint32_t)0x00004000)
3055 #define CAN_F5R2_FB15 ((uint32_t)0x00008000)
3056 #define CAN_F5R2_FB16 ((uint32_t)0x00010000)
3057 #define CAN_F5R2_FB17 ((uint32_t)0x00020000)
3058 #define CAN_F5R2_FB18 ((uint32_t)0x00040000)
3059 #define CAN_F5R2_FB19 ((uint32_t)0x00080000)
3060 #define CAN_F5R2_FB20 ((uint32_t)0x00100000)
3061 #define CAN_F5R2_FB21 ((uint32_t)0x00200000)
3062 #define CAN_F5R2_FB22 ((uint32_t)0x00400000)
3063 #define CAN_F5R2_FB23 ((uint32_t)0x00800000)
3064 #define CAN_F5R2_FB24 ((uint32_t)0x01000000)
3065 #define CAN_F5R2_FB25 ((uint32_t)0x02000000)
3066 #define CAN_F5R2_FB26 ((uint32_t)0x04000000)
3067 #define CAN_F5R2_FB27 ((uint32_t)0x08000000)
3068 #define CAN_F5R2_FB28 ((uint32_t)0x10000000)
3069 #define CAN_F5R2_FB29 ((uint32_t)0x20000000)
3070 #define CAN_F5R2_FB30 ((uint32_t)0x40000000)
3071 #define CAN_F5R2_FB31 ((uint32_t)0x80000000)
3073 /******************* Bit definition for CAN_F6R2 register *******************/
3074 #define CAN_F6R2_FB0 ((uint32_t)0x00000001)
3075 #define CAN_F6R2_FB1 ((uint32_t)0x00000002)
3076 #define CAN_F6R2_FB2 ((uint32_t)0x00000004)
3077 #define CAN_F6R2_FB3 ((uint32_t)0x00000008)
3078 #define CAN_F6R2_FB4 ((uint32_t)0x00000010)
3079 #define CAN_F6R2_FB5 ((uint32_t)0x00000020)
3080 #define CAN_F6R2_FB6 ((uint32_t)0x00000040)
3081 #define CAN_F6R2_FB7 ((uint32_t)0x00000080)
3082 #define CAN_F6R2_FB8 ((uint32_t)0x00000100)
3083 #define CAN_F6R2_FB9 ((uint32_t)0x00000200)
3084 #define CAN_F6R2_FB10 ((uint32_t)0x00000400)
3085 #define CAN_F6R2_FB11 ((uint32_t)0x00000800)
3086 #define CAN_F6R2_FB12 ((uint32_t)0x00001000)
3087 #define CAN_F6R2_FB13 ((uint32_t)0x00002000)
3088 #define CAN_F6R2_FB14 ((uint32_t)0x00004000)
3089 #define CAN_F6R2_FB15 ((uint32_t)0x00008000)
3090 #define CAN_F6R2_FB16 ((uint32_t)0x00010000)
3091 #define CAN_F6R2_FB17 ((uint32_t)0x00020000)
3092 #define CAN_F6R2_FB18 ((uint32_t)0x00040000)
3093 #define CAN_F6R2_FB19 ((uint32_t)0x00080000)
3094 #define CAN_F6R2_FB20 ((uint32_t)0x00100000)
3095 #define CAN_F6R2_FB21 ((uint32_t)0x00200000)
3096 #define CAN_F6R2_FB22 ((uint32_t)0x00400000)
3097 #define CAN_F6R2_FB23 ((uint32_t)0x00800000)
3098 #define CAN_F6R2_FB24 ((uint32_t)0x01000000)
3099 #define CAN_F6R2_FB25 ((uint32_t)0x02000000)
3100 #define CAN_F6R2_FB26 ((uint32_t)0x04000000)
3101 #define CAN_F6R2_FB27 ((uint32_t)0x08000000)
3102 #define CAN_F6R2_FB28 ((uint32_t)0x10000000)
3103 #define CAN_F6R2_FB29 ((uint32_t)0x20000000)
3104 #define CAN_F6R2_FB30 ((uint32_t)0x40000000)
3105 #define CAN_F6R2_FB31 ((uint32_t)0x80000000)
3107 /******************* Bit definition for CAN_F7R2 register *******************/
3108 #define CAN_F7R2_FB0 ((uint32_t)0x00000001)
3109 #define CAN_F7R2_FB1 ((uint32_t)0x00000002)
3110 #define CAN_F7R2_FB2 ((uint32_t)0x00000004)
3111 #define CAN_F7R2_FB3 ((uint32_t)0x00000008)
3112 #define CAN_F7R2_FB4 ((uint32_t)0x00000010)
3113 #define CAN_F7R2_FB5 ((uint32_t)0x00000020)
3114 #define CAN_F7R2_FB6 ((uint32_t)0x00000040)
3115 #define CAN_F7R2_FB7 ((uint32_t)0x00000080)
3116 #define CAN_F7R2_FB8 ((uint32_t)0x00000100)
3117 #define CAN_F7R2_FB9 ((uint32_t)0x00000200)
3118 #define CAN_F7R2_FB10 ((uint32_t)0x00000400)
3119 #define CAN_F7R2_FB11 ((uint32_t)0x00000800)
3120 #define CAN_F7R2_FB12 ((uint32_t)0x00001000)
3121 #define CAN_F7R2_FB13 ((uint32_t)0x00002000)
3122 #define CAN_F7R2_FB14 ((uint32_t)0x00004000)
3123 #define CAN_F7R2_FB15 ((uint32_t)0x00008000)
3124 #define CAN_F7R2_FB16 ((uint32_t)0x00010000)
3125 #define CAN_F7R2_FB17 ((uint32_t)0x00020000)
3126 #define CAN_F7R2_FB18 ((uint32_t)0x00040000)
3127 #define CAN_F7R2_FB19 ((uint32_t)0x00080000)
3128 #define CAN_F7R2_FB20 ((uint32_t)0x00100000)
3129 #define CAN_F7R2_FB21 ((uint32_t)0x00200000)
3130 #define CAN_F7R2_FB22 ((uint32_t)0x00400000)
3131 #define CAN_F7R2_FB23 ((uint32_t)0x00800000)
3132 #define CAN_F7R2_FB24 ((uint32_t)0x01000000)
3133 #define CAN_F7R2_FB25 ((uint32_t)0x02000000)
3134 #define CAN_F7R2_FB26 ((uint32_t)0x04000000)
3135 #define CAN_F7R2_FB27 ((uint32_t)0x08000000)
3136 #define CAN_F7R2_FB28 ((uint32_t)0x10000000)
3137 #define CAN_F7R2_FB29 ((uint32_t)0x20000000)
3138 #define CAN_F7R2_FB30 ((uint32_t)0x40000000)
3139 #define CAN_F7R2_FB31 ((uint32_t)0x80000000)
3141 /******************* Bit definition for CAN_F8R2 register *******************/
3142 #define CAN_F8R2_FB0 ((uint32_t)0x00000001)
3143 #define CAN_F8R2_FB1 ((uint32_t)0x00000002)
3144 #define CAN_F8R2_FB2 ((uint32_t)0x00000004)
3145 #define CAN_F8R2_FB3 ((uint32_t)0x00000008)
3146 #define CAN_F8R2_FB4 ((uint32_t)0x00000010)
3147 #define CAN_F8R2_FB5 ((uint32_t)0x00000020)
3148 #define CAN_F8R2_FB6 ((uint32_t)0x00000040)
3149 #define CAN_F8R2_FB7 ((uint32_t)0x00000080)
3150 #define CAN_F8R2_FB8 ((uint32_t)0x00000100)
3151 #define CAN_F8R2_FB9 ((uint32_t)0x00000200)
3152 #define CAN_F8R2_FB10 ((uint32_t)0x00000400)
3153 #define CAN_F8R2_FB11 ((uint32_t)0x00000800)
3154 #define CAN_F8R2_FB12 ((uint32_t)0x00001000)
3155 #define CAN_F8R2_FB13 ((uint32_t)0x00002000)
3156 #define CAN_F8R2_FB14 ((uint32_t)0x00004000)
3157 #define CAN_F8R2_FB15 ((uint32_t)0x00008000)
3158 #define CAN_F8R2_FB16 ((uint32_t)0x00010000)
3159 #define CAN_F8R2_FB17 ((uint32_t)0x00020000)
3160 #define CAN_F8R2_FB18 ((uint32_t)0x00040000)
3161 #define CAN_F8R2_FB19 ((uint32_t)0x00080000)
3162 #define CAN_F8R2_FB20 ((uint32_t)0x00100000)
3163 #define CAN_F8R2_FB21 ((uint32_t)0x00200000)
3164 #define CAN_F8R2_FB22 ((uint32_t)0x00400000)
3165 #define CAN_F8R2_FB23 ((uint32_t)0x00800000)
3166 #define CAN_F8R2_FB24 ((uint32_t)0x01000000)
3167 #define CAN_F8R2_FB25 ((uint32_t)0x02000000)
3168 #define CAN_F8R2_FB26 ((uint32_t)0x04000000)
3169 #define CAN_F8R2_FB27 ((uint32_t)0x08000000)
3170 #define CAN_F8R2_FB28 ((uint32_t)0x10000000)
3171 #define CAN_F8R2_FB29 ((uint32_t)0x20000000)
3172 #define CAN_F8R2_FB30 ((uint32_t)0x40000000)
3173 #define CAN_F8R2_FB31 ((uint32_t)0x80000000)
3175 /******************* Bit definition for CAN_F9R2 register *******************/
3176 #define CAN_F9R2_FB0 ((uint32_t)0x00000001)
3177 #define CAN_F9R2_FB1 ((uint32_t)0x00000002)
3178 #define CAN_F9R2_FB2 ((uint32_t)0x00000004)
3179 #define CAN_F9R2_FB3 ((uint32_t)0x00000008)
3180 #define CAN_F9R2_FB4 ((uint32_t)0x00000010)
3181 #define CAN_F9R2_FB5 ((uint32_t)0x00000020)
3182 #define CAN_F9R2_FB6 ((uint32_t)0x00000040)
3183 #define CAN_F9R2_FB7 ((uint32_t)0x00000080)
3184 #define CAN_F9R2_FB8 ((uint32_t)0x00000100)
3185 #define CAN_F9R2_FB9 ((uint32_t)0x00000200)
3186 #define CAN_F9R2_FB10 ((uint32_t)0x00000400)
3187 #define CAN_F9R2_FB11 ((uint32_t)0x00000800)
3188 #define CAN_F9R2_FB12 ((uint32_t)0x00001000)
3189 #define CAN_F9R2_FB13 ((uint32_t)0x00002000)
3190 #define CAN_F9R2_FB14 ((uint32_t)0x00004000)
3191 #define CAN_F9R2_FB15 ((uint32_t)0x00008000)
3192 #define CAN_F9R2_FB16 ((uint32_t)0x00010000)
3193 #define CAN_F9R2_FB17 ((uint32_t)0x00020000)
3194 #define CAN_F9R2_FB18 ((uint32_t)0x00040000)
3195 #define CAN_F9R2_FB19 ((uint32_t)0x00080000)
3196 #define CAN_F9R2_FB20 ((uint32_t)0x00100000)
3197 #define CAN_F9R2_FB21 ((uint32_t)0x00200000)
3198 #define CAN_F9R2_FB22 ((uint32_t)0x00400000)
3199 #define CAN_F9R2_FB23 ((uint32_t)0x00800000)
3200 #define CAN_F9R2_FB24 ((uint32_t)0x01000000)
3201 #define CAN_F9R2_FB25 ((uint32_t)0x02000000)
3202 #define CAN_F9R2_FB26 ((uint32_t)0x04000000)
3203 #define CAN_F9R2_FB27 ((uint32_t)0x08000000)
3204 #define CAN_F9R2_FB28 ((uint32_t)0x10000000)
3205 #define CAN_F9R2_FB29 ((uint32_t)0x20000000)
3206 #define CAN_F9R2_FB30 ((uint32_t)0x40000000)
3207 #define CAN_F9R2_FB31 ((uint32_t)0x80000000)
3209 /******************* Bit definition for CAN_F10R2 register ******************/
3210 #define CAN_F10R2_FB0 ((uint32_t)0x00000001)
3211 #define CAN_F10R2_FB1 ((uint32_t)0x00000002)
3212 #define CAN_F10R2_FB2 ((uint32_t)0x00000004)
3213 #define CAN_F10R2_FB3 ((uint32_t)0x00000008)
3214 #define CAN_F10R2_FB4 ((uint32_t)0x00000010)
3215 #define CAN_F10R2_FB5 ((uint32_t)0x00000020)
3216 #define CAN_F10R2_FB6 ((uint32_t)0x00000040)
3217 #define CAN_F10R2_FB7 ((uint32_t)0x00000080)
3218 #define CAN_F10R2_FB8 ((uint32_t)0x00000100)
3219 #define CAN_F10R2_FB9 ((uint32_t)0x00000200)
3220 #define CAN_F10R2_FB10 ((uint32_t)0x00000400)
3221 #define CAN_F10R2_FB11 ((uint32_t)0x00000800)
3222 #define CAN_F10R2_FB12 ((uint32_t)0x00001000)
3223 #define CAN_F10R2_FB13 ((uint32_t)0x00002000)
3224 #define CAN_F10R2_FB14 ((uint32_t)0x00004000)
3225 #define CAN_F10R2_FB15 ((uint32_t)0x00008000)
3226 #define CAN_F10R2_FB16 ((uint32_t)0x00010000)
3227 #define CAN_F10R2_FB17 ((uint32_t)0x00020000)
3228 #define CAN_F10R2_FB18 ((uint32_t)0x00040000)
3229 #define CAN_F10R2_FB19 ((uint32_t)0x00080000)
3230 #define CAN_F10R2_FB20 ((uint32_t)0x00100000)
3231 #define CAN_F10R2_FB21 ((uint32_t)0x00200000)
3232 #define CAN_F10R2_FB22 ((uint32_t)0x00400000)
3233 #define CAN_F10R2_FB23 ((uint32_t)0x00800000)
3234 #define CAN_F10R2_FB24 ((uint32_t)0x01000000)
3235 #define CAN_F10R2_FB25 ((uint32_t)0x02000000)
3236 #define CAN_F10R2_FB26 ((uint32_t)0x04000000)
3237 #define CAN_F10R2_FB27 ((uint32_t)0x08000000)
3238 #define CAN_F10R2_FB28 ((uint32_t)0x10000000)
3239 #define CAN_F10R2_FB29 ((uint32_t)0x20000000)
3240 #define CAN_F10R2_FB30 ((uint32_t)0x40000000)
3241 #define CAN_F10R2_FB31 ((uint32_t)0x80000000)
3243 /******************* Bit definition for CAN_F11R2 register ******************/
3244 #define CAN_F11R2_FB0 ((uint32_t)0x00000001)
3245 #define CAN_F11R2_FB1 ((uint32_t)0x00000002)
3246 #define CAN_F11R2_FB2 ((uint32_t)0x00000004)
3247 #define CAN_F11R2_FB3 ((uint32_t)0x00000008)
3248 #define CAN_F11R2_FB4 ((uint32_t)0x00000010)
3249 #define CAN_F11R2_FB5 ((uint32_t)0x00000020)
3250 #define CAN_F11R2_FB6 ((uint32_t)0x00000040)
3251 #define CAN_F11R2_FB7 ((uint32_t)0x00000080)
3252 #define CAN_F11R2_FB8 ((uint32_t)0x00000100)
3253 #define CAN_F11R2_FB9 ((uint32_t)0x00000200)
3254 #define CAN_F11R2_FB10 ((uint32_t)0x00000400)
3255 #define CAN_F11R2_FB11 ((uint32_t)0x00000800)
3256 #define CAN_F11R2_FB12 ((uint32_t)0x00001000)
3257 #define CAN_F11R2_FB13 ((uint32_t)0x00002000)
3258 #define CAN_F11R2_FB14 ((uint32_t)0x00004000)
3259 #define CAN_F11R2_FB15 ((uint32_t)0x00008000)
3260 #define CAN_F11R2_FB16 ((uint32_t)0x00010000)
3261 #define CAN_F11R2_FB17 ((uint32_t)0x00020000)
3262 #define CAN_F11R2_FB18 ((uint32_t)0x00040000)
3263 #define CAN_F11R2_FB19 ((uint32_t)0x00080000)
3264 #define CAN_F11R2_FB20 ((uint32_t)0x00100000)
3265 #define CAN_F11R2_FB21 ((uint32_t)0x00200000)
3266 #define CAN_F11R2_FB22 ((uint32_t)0x00400000)
3267 #define CAN_F11R2_FB23 ((uint32_t)0x00800000)
3268 #define CAN_F11R2_FB24 ((uint32_t)0x01000000)
3269 #define CAN_F11R2_FB25 ((uint32_t)0x02000000)
3270 #define CAN_F11R2_FB26 ((uint32_t)0x04000000)
3271 #define CAN_F11R2_FB27 ((uint32_t)0x08000000)
3272 #define CAN_F11R2_FB28 ((uint32_t)0x10000000)
3273 #define CAN_F11R2_FB29 ((uint32_t)0x20000000)
3274 #define CAN_F11R2_FB30 ((uint32_t)0x40000000)
3275 #define CAN_F11R2_FB31 ((uint32_t)0x80000000)
3277 /******************* Bit definition for CAN_F12R2 register ******************/
3278 #define CAN_F12R2_FB0 ((uint32_t)0x00000001)
3279 #define CAN_F12R2_FB1 ((uint32_t)0x00000002)
3280 #define CAN_F12R2_FB2 ((uint32_t)0x00000004)
3281 #define CAN_F12R2_FB3 ((uint32_t)0x00000008)
3282 #define CAN_F12R2_FB4 ((uint32_t)0x00000010)
3283 #define CAN_F12R2_FB5 ((uint32_t)0x00000020)
3284 #define CAN_F12R2_FB6 ((uint32_t)0x00000040)
3285 #define CAN_F12R2_FB7 ((uint32_t)0x00000080)
3286 #define CAN_F12R2_FB8 ((uint32_t)0x00000100)
3287 #define CAN_F12R2_FB9 ((uint32_t)0x00000200)
3288 #define CAN_F12R2_FB10 ((uint32_t)0x00000400)
3289 #define CAN_F12R2_FB11 ((uint32_t)0x00000800)
3290 #define CAN_F12R2_FB12 ((uint32_t)0x00001000)
3291 #define CAN_F12R2_FB13 ((uint32_t)0x00002000)
3292 #define CAN_F12R2_FB14 ((uint32_t)0x00004000)
3293 #define CAN_F12R2_FB15 ((uint32_t)0x00008000)
3294 #define CAN_F12R2_FB16 ((uint32_t)0x00010000)
3295 #define CAN_F12R2_FB17 ((uint32_t)0x00020000)
3296 #define CAN_F12R2_FB18 ((uint32_t)0x00040000)
3297 #define CAN_F12R2_FB19 ((uint32_t)0x00080000)
3298 #define CAN_F12R2_FB20 ((uint32_t)0x00100000)
3299 #define CAN_F12R2_FB21 ((uint32_t)0x00200000)
3300 #define CAN_F12R2_FB22 ((uint32_t)0x00400000)
3301 #define CAN_F12R2_FB23 ((uint32_t)0x00800000)
3302 #define CAN_F12R2_FB24 ((uint32_t)0x01000000)
3303 #define CAN_F12R2_FB25 ((uint32_t)0x02000000)
3304 #define CAN_F12R2_FB26 ((uint32_t)0x04000000)
3305 #define CAN_F12R2_FB27 ((uint32_t)0x08000000)
3306 #define CAN_F12R2_FB28 ((uint32_t)0x10000000)
3307 #define CAN_F12R2_FB29 ((uint32_t)0x20000000)
3308 #define CAN_F12R2_FB30 ((uint32_t)0x40000000)
3309 #define CAN_F12R2_FB31 ((uint32_t)0x80000000)
3311 /******************* Bit definition for CAN_F13R2 register ******************/
3312 #define CAN_F13R2_FB0 ((uint32_t)0x00000001)
3313 #define CAN_F13R2_FB1 ((uint32_t)0x00000002)
3314 #define CAN_F13R2_FB2 ((uint32_t)0x00000004)
3315 #define CAN_F13R2_FB3 ((uint32_t)0x00000008)
3316 #define CAN_F13R2_FB4 ((uint32_t)0x00000010)
3317 #define CAN_F13R2_FB5 ((uint32_t)0x00000020)
3318 #define CAN_F13R2_FB6 ((uint32_t)0x00000040)
3319 #define CAN_F13R2_FB7 ((uint32_t)0x00000080)
3320 #define CAN_F13R2_FB8 ((uint32_t)0x00000100)
3321 #define CAN_F13R2_FB9 ((uint32_t)0x00000200)
3322 #define CAN_F13R2_FB10 ((uint32_t)0x00000400)
3323 #define CAN_F13R2_FB11 ((uint32_t)0x00000800)
3324 #define CAN_F13R2_FB12 ((uint32_t)0x00001000)
3325 #define CAN_F13R2_FB13 ((uint32_t)0x00002000)
3326 #define CAN_F13R2_FB14 ((uint32_t)0x00004000)
3327 #define CAN_F13R2_FB15 ((uint32_t)0x00008000)
3328 #define CAN_F13R2_FB16 ((uint32_t)0x00010000)
3329 #define CAN_F13R2_FB17 ((uint32_t)0x00020000)
3330 #define CAN_F13R2_FB18 ((uint32_t)0x00040000)
3331 #define CAN_F13R2_FB19 ((uint32_t)0x00080000)
3332 #define CAN_F13R2_FB20 ((uint32_t)0x00100000)
3333 #define CAN_F13R2_FB21 ((uint32_t)0x00200000)
3334 #define CAN_F13R2_FB22 ((uint32_t)0x00400000)
3335 #define CAN_F13R2_FB23 ((uint32_t)0x00800000)
3336 #define CAN_F13R2_FB24 ((uint32_t)0x01000000)
3337 #define CAN_F13R2_FB25 ((uint32_t)0x02000000)
3338 #define CAN_F13R2_FB26 ((uint32_t)0x04000000)
3339 #define CAN_F13R2_FB27 ((uint32_t)0x08000000)
3340 #define CAN_F13R2_FB28 ((uint32_t)0x10000000)
3341 #define CAN_F13R2_FB29 ((uint32_t)0x20000000)
3342 #define CAN_F13R2_FB30 ((uint32_t)0x40000000)
3343 #define CAN_F13R2_FB31 ((uint32_t)0x80000000)
3345 /******************************************************************************/
3346 /* */
3347 /* CRC calculation unit */
3348 /* */
3349 /******************************************************************************/
3350 /******************* Bit definition for CRC_DR register *********************/
3351 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF)
3354 /******************* Bit definition for CRC_IDR register ********************/
3355 #define CRC_IDR_IDR ((uint8_t)0xFF)
3358 /******************** Bit definition for CRC_CR register ********************/
3359 #define CRC_CR_RESET ((uint8_t)0x01)
3361 /******************************************************************************/
3362 /* */
3363 /* Crypto Processor */
3364 /* */
3365 /******************************************************************************/
3366 /******************* Bits definition for CRYP_CR register ********************/
3367 #define CRYP_CR_ALGODIR ((uint32_t)0x00000004)
3368 
3369 #define CRYP_CR_ALGOMODE ((uint32_t)0x00080038)
3370 #define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008)
3371 #define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010)
3372 #define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020)
3373 #define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
3374 #define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008)
3375 #define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010)
3376 #define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018)
3377 #define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020)
3378 #define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028)
3379 #define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030)
3380 #define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038)
3381 
3382 #define CRYP_CR_DATATYPE ((uint32_t)0x000000C0)
3383 #define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040)
3384 #define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080)
3385 #define CRYP_CR_KEYSIZE ((uint32_t)0x00000300)
3386 #define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100)
3387 #define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200)
3388 #define CRYP_CR_FFLUSH ((uint32_t)0x00004000)
3389 #define CRYP_CR_CRYPEN ((uint32_t)0x00008000)
3390 
3391 #define CRYP_CR_GCM_CCMPH ((uint32_t)0x00030000)
3392 #define CRYP_CR_GCM_CCMPH_0 ((uint32_t)0x00010000)
3393 #define CRYP_CR_GCM_CCMPH_1 ((uint32_t)0x00020000)
3394 #define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
3395 
3396 /****************** Bits definition for CRYP_SR register *********************/
3397 #define CRYP_SR_IFEM ((uint32_t)0x00000001)
3398 #define CRYP_SR_IFNF ((uint32_t)0x00000002)
3399 #define CRYP_SR_OFNE ((uint32_t)0x00000004)
3400 #define CRYP_SR_OFFU ((uint32_t)0x00000008)
3401 #define CRYP_SR_BUSY ((uint32_t)0x00000010)
3402 /****************** Bits definition for CRYP_DMACR register ******************/
3403 #define CRYP_DMACR_DIEN ((uint32_t)0x00000001)
3404 #define CRYP_DMACR_DOEN ((uint32_t)0x00000002)
3405 /***************** Bits definition for CRYP_IMSCR register ******************/
3406 #define CRYP_IMSCR_INIM ((uint32_t)0x00000001)
3407 #define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002)
3408 /****************** Bits definition for CRYP_RISR register *******************/
3409 #define CRYP_RISR_OUTRIS ((uint32_t)0x00000001)
3410 #define CRYP_RISR_INRIS ((uint32_t)0x00000002)
3411 /****************** Bits definition for CRYP_MISR register *******************/
3412 #define CRYP_MISR_INMIS ((uint32_t)0x00000001)
3413 #define CRYP_MISR_OUTMIS ((uint32_t)0x00000002)
3414 
3415 /******************************************************************************/
3416 /* */
3417 /* Digital to Analog Converter */
3418 /* */
3419 /******************************************************************************/
3420 /******************** Bit definition for DAC_CR register ********************/
3421 #define DAC_CR_EN1 ((uint32_t)0x00000001)
3422 #define DAC_CR_BOFF1 ((uint32_t)0x00000002)
3423 #define DAC_CR_TEN1 ((uint32_t)0x00000004)
3425 #define DAC_CR_TSEL1 ((uint32_t)0x00000038)
3426 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008)
3427 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010)
3428 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020)
3430 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0)
3431 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040)
3432 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080)
3434 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00)
3435 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100)
3436 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200)
3437 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400)
3438 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800)
3440 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000)
3441 #define DAC_CR_EN2 ((uint32_t)0x00010000)
3442 #define DAC_CR_BOFF2 ((uint32_t)0x00020000)
3443 #define DAC_CR_TEN2 ((uint32_t)0x00040000)
3445 #define DAC_CR_TSEL2 ((uint32_t)0x00380000)
3446 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000)
3447 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000)
3448 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000)
3450 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000)
3451 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000)
3452 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000)
3454 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000)
3455 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000)
3456 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000)
3457 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000)
3458 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000)
3460 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000)
3462 /***************** Bit definition for DAC_SWTRIGR register ******************/
3463 #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01)
3464 #define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02)
3466 /***************** Bit definition for DAC_DHR12R1 register ******************/
3467 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF)
3469 /***************** Bit definition for DAC_DHR12L1 register ******************/
3470 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0)
3472 /****************** Bit definition for DAC_DHR8R1 register ******************/
3473 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF)
3475 /***************** Bit definition for DAC_DHR12R2 register ******************/
3476 #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF)
3478 /***************** Bit definition for DAC_DHR12L2 register ******************/
3479 #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0)
3481 /****************** Bit definition for DAC_DHR8R2 register ******************/
3482 #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF)
3484 /***************** Bit definition for DAC_DHR12RD register ******************/
3485 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF)
3486 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000)
3488 /***************** Bit definition for DAC_DHR12LD register ******************/
3489 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0)
3490 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000)
3492 /****************** Bit definition for DAC_DHR8RD register ******************/
3493 #define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF)
3494 #define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00)
3496 /******************* Bit definition for DAC_DOR1 register *******************/
3497 #define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF)
3499 /******************* Bit definition for DAC_DOR2 register *******************/
3500 #define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF)
3502 /******************** Bit definition for DAC_SR register ********************/
3503 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000)
3504 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000)
3506 /******************************************************************************/
3507 /* */
3508 /* Debug MCU */
3509 /* */
3510 /******************************************************************************/
3511 
3512 /******************************************************************************/
3513 /* */
3514 /* DCMI */
3515 /* */
3516 /******************************************************************************/
3517 /******************** Bits definition for DCMI_CR register ******************/
3518 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
3519 #define DCMI_CR_CM ((uint32_t)0x00000002)
3520 #define DCMI_CR_CROP ((uint32_t)0x00000004)
3521 #define DCMI_CR_JPEG ((uint32_t)0x00000008)
3522 #define DCMI_CR_ESS ((uint32_t)0x00000010)
3523 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
3524 #define DCMI_CR_HSPOL ((uint32_t)0x00000040)
3525 #define DCMI_CR_VSPOL ((uint32_t)0x00000080)
3526 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
3527 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
3528 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
3529 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
3530 #define DCMI_CR_CRE ((uint32_t)0x00001000)
3531 #define DCMI_CR_ENABLE ((uint32_t)0x00004000)
3532 
3533 /******************** Bits definition for DCMI_SR register ******************/
3534 #define DCMI_SR_HSYNC ((uint32_t)0x00000001)
3535 #define DCMI_SR_VSYNC ((uint32_t)0x00000002)
3536 #define DCMI_SR_FNE ((uint32_t)0x00000004)
3537 
3538 /******************** Bits definition for DCMI_RISR register ****************/
3539 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
3540 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
3541 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
3542 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
3543 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
3544 
3545 /******************** Bits definition for DCMI_IER register *****************/
3546 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
3547 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
3548 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
3549 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
3550 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
3551 
3552 /******************** Bits definition for DCMI_MISR register ****************/
3553 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
3554 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
3555 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
3556 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
3557 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
3558 
3559 /******************** Bits definition for DCMI_ICR register *****************/
3560 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
3561 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
3562 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
3563 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
3564 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
3565 
3566 /******************************************************************************/
3567 /* */
3568 /* DMA Controller */
3569 /* */
3570 /******************************************************************************/
3571 /******************** Bits definition for DMA_SxCR register *****************/
3572 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
3573 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
3574 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
3575 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
3576 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
3577 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
3578 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
3579 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
3580 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
3581 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
3582 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
3583 #define DMA_SxCR_CT ((uint32_t)0x00080000)
3584 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
3585 #define DMA_SxCR_PL ((uint32_t)0x00030000)
3586 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
3587 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
3588 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
3589 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
3590 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
3591 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
3592 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
3593 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
3594 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
3595 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
3596 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
3597 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
3598 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
3599 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
3600 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
3601 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
3602 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
3603 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
3604 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
3605 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
3606 #define DMA_SxCR_EN ((uint32_t)0x00000001)
3607 
3608 /******************** Bits definition for DMA_SxCNDTR register **************/
3609 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
3610 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
3611 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
3612 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
3613 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
3614 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
3615 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
3616 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
3617 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
3618 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
3619 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
3620 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
3621 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
3622 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
3623 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
3624 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
3625 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
3626 
3627 /******************** Bits definition for DMA_SxFCR register ****************/
3628 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
3629 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
3630 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
3631 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
3632 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
3633 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
3634 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
3635 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
3636 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
3637 
3638 /******************** Bits definition for DMA_LISR register *****************/
3639 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
3640 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
3641 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
3642 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
3643 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
3644 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
3645 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
3646 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
3647 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
3648 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
3649 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
3650 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
3651 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
3652 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
3653 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
3654 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
3655 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
3656 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
3657 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
3658 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
3659 
3660 /******************** Bits definition for DMA_HISR register *****************/
3661 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
3662 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
3663 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
3664 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
3665 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
3666 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
3667 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
3668 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
3669 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
3670 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
3671 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
3672 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
3673 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
3674 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
3675 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
3676 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
3677 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
3678 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
3679 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
3680 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
3681 
3682 /******************** Bits definition for DMA_LIFCR register ****************/
3683 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
3684 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
3685 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
3686 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
3687 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
3688 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
3689 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
3690 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
3691 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
3692 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
3693 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
3694 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
3695 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
3696 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
3697 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
3698 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
3699 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
3700 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
3701 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
3702 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
3703 
3704 /******************** Bits definition for DMA_HIFCR register ****************/
3705 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
3706 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
3707 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
3708 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
3709 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
3710 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
3711 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
3712 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
3713 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
3714 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
3715 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
3716 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
3717 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
3718 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
3719 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
3720 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
3721 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
3722 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
3723 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
3724 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
3725 
3726 /******************************************************************************/
3727 /* */
3728 /* AHB Master DMA2D Controller (DMA2D) */
3729 /* */
3730 /******************************************************************************/
3731 
3732 /******************** Bit definition for DMA2D_CR register ******************/
3733 
3734 #define DMA2D_CR_START ((uint32_t)0x00000001)
3735 #define DMA2D_CR_SUSP ((uint32_t)0x00000002)
3736 #define DMA2D_CR_ABORT ((uint32_t)0x00000004)
3737 #define DMA2D_CR_TEIE ((uint32_t)0x00000100)
3738 #define DMA2D_CR_TCIE ((uint32_t)0x00000200)
3739 #define DMA2D_CR_TWIE ((uint32_t)0x00000400)
3740 #define DMA2D_CR_CAEIE ((uint32_t)0x00000800)
3741 #define DMA2D_CR_CTCIE ((uint32_t)0x00001000)
3742 #define DMA2D_CR_CEIE ((uint32_t)0x00002000)
3743 #define DMA2D_CR_MODE ((uint32_t)0x00030000)
3745 /******************** Bit definition for DMA2D_ISR register *****************/
3746 
3747 #define DMA2D_ISR_TEIF ((uint32_t)0x00000001)
3748 #define DMA2D_ISR_TCIF ((uint32_t)0x00000002)
3749 #define DMA2D_ISR_TWIF ((uint32_t)0x00000004)
3750 #define DMA2D_ISR_CAEIF ((uint32_t)0x00000008)
3751 #define DMA2D_ISR_CTCIF ((uint32_t)0x00000010)
3752 #define DMA2D_ISR_CEIF ((uint32_t)0x00000020)
3754 /******************** Bit definition for DMA2D_IFSR register ****************/
3755 
3756 #define DMA2D_IFSR_CTEIF ((uint32_t)0x00000001)
3757 #define DMA2D_IFSR_CTCIF ((uint32_t)0x00000002)
3758 #define DMA2D_IFSR_CTWIF ((uint32_t)0x00000004)
3759 #define DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008)
3760 #define DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010)
3761 #define DMA2D_IFSR_CCEIF ((uint32_t)0x00000020)
3763 /******************** Bit definition for DMA2D_FGMAR register ***************/
3764 
3765 #define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF)
3767 /******************** Bit definition for DMA2D_FGOR register ****************/
3768 
3769 #define DMA2D_FGOR_LO ((uint32_t)0x00003FFF)
3771 /******************** Bit definition for DMA2D_BGMAR register ***************/
3772 
3773 #define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF)
3775 /******************** Bit definition for DMA2D_BGOR register ****************/
3776 
3777 #define DMA2D_BGOR_LO ((uint32_t)0x00003FFF)
3779 /******************** Bit definition for DMA2D_FGPFCCR register *************/
3780 
3781 #define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F)
3782 #define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010)
3783 #define DMA2D_FGPFCCR_START ((uint32_t)0x00000020)
3784 #define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00)
3785 #define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000)
3786 #define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000)
3788 /******************** Bit definition for DMA2D_FGCOLR register **************/
3789 
3790 #define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF)
3791 #define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00)
3792 #define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000)
3794 /******************** Bit definition for DMA2D_BGPFCCR register *************/
3795 
3796 #define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F)
3797 #define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010)
3798 #define DMA2D_BGPFCCR_START ((uint32_t)0x00000020)
3799 #define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00)
3800 #define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000)
3801 #define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000)
3803 /******************** Bit definition for DMA2D_BGCOLR register **************/
3804 
3805 #define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF)
3806 #define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00)
3807 #define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000)
3809 /******************** Bit definition for DMA2D_FGCMAR register **************/
3810 
3811 #define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF)
3813 /******************** Bit definition for DMA2D_BGCMAR register **************/
3814 
3815 #define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF)
3817 /******************** Bit definition for DMA2D_OPFCCR register **************/
3818 
3819 #define DMA2D_OPFCCR_CM ((uint32_t)0x00000007)
3821 /******************** Bit definition for DMA2D_OCOLR register ***************/
3822 
3825 #define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF)
3826 #define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00)
3827 #define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000)
3828 #define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000)
3831 #define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F)
3832 #define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0)
3833 #define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800)
3836 #define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F)
3837 #define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0)
3838 #define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00)
3839 #define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000)
3842 #define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F)
3843 #define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0)
3844 #define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00)
3845 #define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000)
3847 /******************** Bit definition for DMA2D_OMAR register ****************/
3848 
3849 #define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF)
3851 /******************** Bit definition for DMA2D_OOR register *****************/
3852 
3853 #define DMA2D_OOR_LO ((uint32_t)0x00003FFF)
3855 /******************** Bit definition for DMA2D_NLR register *****************/
3856 
3857 #define DMA2D_NLR_NL ((uint32_t)0x0000FFFF)
3858 #define DMA2D_NLR_PL ((uint32_t)0x3FFF0000)
3860 /******************** Bit definition for DMA2D_LWR register *****************/
3861 
3862 #define DMA2D_LWR_LW ((uint32_t)0x0000FFFF)
3864 /******************** Bit definition for DMA2D_AMTCR register ***************/
3865 
3866 #define DMA2D_AMTCR_EN ((uint32_t)0x00000001)
3867 #define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00)
3871 /******************** Bit definition for DMA2D_FGCLUT register **************/
3872 
3873 /******************** Bit definition for DMA2D_BGCLUT register **************/
3874 
3875 
3876 /******************************************************************************/
3877 /* */
3878 /* External Interrupt/Event Controller */
3879 /* */
3880 /******************************************************************************/
3881 /******************* Bit definition for EXTI_IMR register *******************/
3882 #define EXTI_IMR_MR0 ((uint32_t)0x00000001)
3883 #define EXTI_IMR_MR1 ((uint32_t)0x00000002)
3884 #define EXTI_IMR_MR2 ((uint32_t)0x00000004)
3885 #define EXTI_IMR_MR3 ((uint32_t)0x00000008)
3886 #define EXTI_IMR_MR4 ((uint32_t)0x00000010)
3887 #define EXTI_IMR_MR5 ((uint32_t)0x00000020)
3888 #define EXTI_IMR_MR6 ((uint32_t)0x00000040)
3889 #define EXTI_IMR_MR7 ((uint32_t)0x00000080)
3890 #define EXTI_IMR_MR8 ((uint32_t)0x00000100)
3891 #define EXTI_IMR_MR9 ((uint32_t)0x00000200)
3892 #define EXTI_IMR_MR10 ((uint32_t)0x00000400)
3893 #define EXTI_IMR_MR11 ((uint32_t)0x00000800)
3894 #define EXTI_IMR_MR12 ((uint32_t)0x00001000)
3895 #define EXTI_IMR_MR13 ((uint32_t)0x00002000)
3896 #define EXTI_IMR_MR14 ((uint32_t)0x00004000)
3897 #define EXTI_IMR_MR15 ((uint32_t)0x00008000)
3898 #define EXTI_IMR_MR16 ((uint32_t)0x00010000)
3899 #define EXTI_IMR_MR17 ((uint32_t)0x00020000)
3900 #define EXTI_IMR_MR18 ((uint32_t)0x00040000)
3901 #define EXTI_IMR_MR19 ((uint32_t)0x00080000)
3903 /******************* Bit definition for EXTI_EMR register *******************/
3904 #define EXTI_EMR_MR0 ((uint32_t)0x00000001)
3905 #define EXTI_EMR_MR1 ((uint32_t)0x00000002)
3906 #define EXTI_EMR_MR2 ((uint32_t)0x00000004)
3907 #define EXTI_EMR_MR3 ((uint32_t)0x00000008)
3908 #define EXTI_EMR_MR4 ((uint32_t)0x00000010)
3909 #define EXTI_EMR_MR5 ((uint32_t)0x00000020)
3910 #define EXTI_EMR_MR6 ((uint32_t)0x00000040)
3911 #define EXTI_EMR_MR7 ((uint32_t)0x00000080)
3912 #define EXTI_EMR_MR8 ((uint32_t)0x00000100)
3913 #define EXTI_EMR_MR9 ((uint32_t)0x00000200)
3914 #define EXTI_EMR_MR10 ((uint32_t)0x00000400)
3915 #define EXTI_EMR_MR11 ((uint32_t)0x00000800)
3916 #define EXTI_EMR_MR12 ((uint32_t)0x00001000)
3917 #define EXTI_EMR_MR13 ((uint32_t)0x00002000)
3918 #define EXTI_EMR_MR14 ((uint32_t)0x00004000)
3919 #define EXTI_EMR_MR15 ((uint32_t)0x00008000)
3920 #define EXTI_EMR_MR16 ((uint32_t)0x00010000)
3921 #define EXTI_EMR_MR17 ((uint32_t)0x00020000)
3922 #define EXTI_EMR_MR18 ((uint32_t)0x00040000)
3923 #define EXTI_EMR_MR19 ((uint32_t)0x00080000)
3925 /****************** Bit definition for EXTI_RTSR register *******************/
3926 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001)
3927 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002)
3928 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004)
3929 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008)
3930 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010)
3931 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020)
3932 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040)
3933 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080)
3934 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100)
3935 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200)
3936 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400)
3937 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800)
3938 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000)
3939 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000)
3940 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000)
3941 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000)
3942 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000)
3943 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000)
3944 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000)
3945 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000)
3947 /****************** Bit definition for EXTI_FTSR register *******************/
3948 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001)
3949 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002)
3950 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004)
3951 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008)
3952 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010)
3953 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020)
3954 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040)
3955 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080)
3956 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100)
3957 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200)
3958 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400)
3959 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800)
3960 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000)
3961 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000)
3962 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000)
3963 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000)
3964 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000)
3965 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000)
3966 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000)
3967 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000)
3969 /****************** Bit definition for EXTI_SWIER register ******************/
3970 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001)
3971 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002)
3972 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004)
3973 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008)
3974 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010)
3975 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020)
3976 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040)
3977 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080)
3978 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100)
3979 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200)
3980 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400)
3981 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800)
3982 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000)
3983 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000)
3984 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000)
3985 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000)
3986 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000)
3987 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000)
3988 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000)
3989 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000)
3991 /******************* Bit definition for EXTI_PR register ********************/
3992 #define EXTI_PR_PR0 ((uint32_t)0x00000001)
3993 #define EXTI_PR_PR1 ((uint32_t)0x00000002)
3994 #define EXTI_PR_PR2 ((uint32_t)0x00000004)
3995 #define EXTI_PR_PR3 ((uint32_t)0x00000008)
3996 #define EXTI_PR_PR4 ((uint32_t)0x00000010)
3997 #define EXTI_PR_PR5 ((uint32_t)0x00000020)
3998 #define EXTI_PR_PR6 ((uint32_t)0x00000040)
3999 #define EXTI_PR_PR7 ((uint32_t)0x00000080)
4000 #define EXTI_PR_PR8 ((uint32_t)0x00000100)
4001 #define EXTI_PR_PR9 ((uint32_t)0x00000200)
4002 #define EXTI_PR_PR10 ((uint32_t)0x00000400)
4003 #define EXTI_PR_PR11 ((uint32_t)0x00000800)
4004 #define EXTI_PR_PR12 ((uint32_t)0x00001000)
4005 #define EXTI_PR_PR13 ((uint32_t)0x00002000)
4006 #define EXTI_PR_PR14 ((uint32_t)0x00004000)
4007 #define EXTI_PR_PR15 ((uint32_t)0x00008000)
4008 #define EXTI_PR_PR16 ((uint32_t)0x00010000)
4009 #define EXTI_PR_PR17 ((uint32_t)0x00020000)
4010 #define EXTI_PR_PR18 ((uint32_t)0x00040000)
4011 #define EXTI_PR_PR19 ((uint32_t)0x00080000)
4013 /******************************************************************************/
4014 /* */
4015 /* FLASH */
4016 /* */
4017 /******************************************************************************/
4018 /******************* Bits definition for FLASH_ACR register *****************/
4019 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
4020 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
4021 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
4022 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
4023 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
4024 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
4025 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
4026 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
4027 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
4028 #define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)
4029 #define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)
4030 #define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)
4031 #define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)
4032 #define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)
4033 #define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)
4034 #define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)
4035 #define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)
4036 
4037 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
4038 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
4039 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
4040 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
4041 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
4042 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
4043 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
4044 
4045 /******************* Bits definition for FLASH_SR register ******************/
4046 #define FLASH_SR_EOP ((uint32_t)0x00000001)
4047 #define FLASH_SR_SOP ((uint32_t)0x00000002)
4048 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
4049 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
4050 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
4051 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
4052 #define FLASH_SR_BSY ((uint32_t)0x00010000)
4053 
4054 /******************* Bits definition for FLASH_CR register ******************/
4055 #define FLASH_CR_PG ((uint32_t)0x00000001)
4056 #define FLASH_CR_SER ((uint32_t)0x00000002)
4057 #define FLASH_CR_MER ((uint32_t)0x00000004)
4058 #define FLASH_CR_MER1 FLASH_CR_MER
4059 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
4060 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
4061 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
4062 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
4063 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
4064 #define FLASH_CR_SNB_4 ((uint32_t)0x00000040)
4065 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
4066 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
4067 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
4068 #define FLASH_CR_MER2 ((uint32_t)0x00008000)
4069 #define FLASH_CR_STRT ((uint32_t)0x00010000)
4070 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
4071 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
4072 
4073 /******************* Bits definition for FLASH_OPTCR register ***************/
4074 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
4075 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
4076 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
4077 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
4078 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
4079 #define FLASH_OPTCR_BFB2 ((uint32_t)0x00000010)
4080 
4081 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
4082 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
4083 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
4084 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
4085 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
4086 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
4087 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
4088 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
4089 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
4090 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
4091 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
4092 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
4093 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
4094 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
4095 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
4096 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
4097 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
4098 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
4099 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
4100 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
4101 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
4102 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
4103 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
4104 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
4105 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
4106 
4107 #define FLASH_OPTCR_DB1M ((uint32_t)0x40000000)
4108 #define FLASH_OPTCR_SPRMOD ((uint32_t)0x80000000)
4109 
4110 /****************** Bits definition for FLASH_OPTCR1 register ***************/
4111 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
4112 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
4113 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
4114 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
4115 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
4116 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
4117 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
4118 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
4119 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
4120 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
4121 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
4122 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
4123 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
4124 
4125 #if defined (STM32F40_41xxx)
4126 /******************************************************************************/
4127 /* */
4128 /* Flexible Static Memory Controller */
4129 /* */
4130 /******************************************************************************/
4131 /****************** Bit definition for FSMC_BCR1 register *******************/
4132 #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001)
4133 #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002)
4135 #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C)
4136 #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004)
4137 #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008)
4139 #define FSMC_BCR1_MWID ((uint32_t)0x00000030)
4140 #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010)
4141 #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020)
4143 #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040)
4144 #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100)
4145 #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200)
4146 #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400)
4147 #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800)
4148 #define FSMC_BCR1_WREN ((uint32_t)0x00001000)
4149 #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000)
4150 #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000)
4151 #define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000)
4152 #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000)
4154 /****************** Bit definition for FSMC_BCR2 register *******************/
4155 #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001)
4156 #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002)
4158 #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C)
4159 #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004)
4160 #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008)
4162 #define FSMC_BCR2_MWID ((uint32_t)0x00000030)
4163 #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010)
4164 #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020)
4166 #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040)
4167 #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100)
4168 #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200)
4169 #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400)
4170 #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800)
4171 #define FSMC_BCR2_WREN ((uint32_t)0x00001000)
4172 #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000)
4173 #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000)
4174 #define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000)
4175 #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000)
4177 /****************** Bit definition for FSMC_BCR3 register *******************/
4178 #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001)
4179 #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002)
4181 #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C)
4182 #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004)
4183 #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008)
4185 #define FSMC_BCR3_MWID ((uint32_t)0x00000030)
4186 #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010)
4187 #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020)
4189 #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040)
4190 #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100)
4191 #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200)
4192 #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400)
4193 #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800)
4194 #define FSMC_BCR3_WREN ((uint32_t)0x00001000)
4195 #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000)
4196 #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000)
4197 #define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000)
4198 #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000)
4200 /****************** Bit definition for FSMC_BCR4 register *******************/
4201 #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001)
4202 #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002)
4204 #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C)
4205 #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004)
4206 #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008)
4208 #define FSMC_BCR4_MWID ((uint32_t)0x00000030)
4209 #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010)
4210 #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020)
4212 #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040)
4213 #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100)
4214 #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200)
4215 #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400)
4216 #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800)
4217 #define FSMC_BCR4_WREN ((uint32_t)0x00001000)
4218 #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000)
4219 #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000)
4220 #define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000)
4221 #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000)
4223 /****************** Bit definition for FSMC_BTR1 register ******************/
4224 #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F)
4225 #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001)
4226 #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002)
4227 #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004)
4228 #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008)
4230 #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0)
4231 #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010)
4232 #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020)
4233 #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040)
4234 #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080)
4236 #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00)
4237 #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100)
4238 #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200)
4239 #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400)
4240 #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800)
4242 #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000)
4243 #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000)
4244 #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000)
4245 #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000)
4246 #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000)
4248 #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000)
4249 #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000)
4250 #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000)
4251 #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000)
4252 #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000)
4254 #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000)
4255 #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000)
4256 #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000)
4257 #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000)
4258 #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000)
4260 #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000)
4261 #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000)
4262 #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000)
4264 /****************** Bit definition for FSMC_BTR2 register *******************/
4265 #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F)
4266 #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001)
4267 #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002)
4268 #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004)
4269 #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008)
4271 #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0)
4272 #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010)
4273 #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020)
4274 #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040)
4275 #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080)
4277 #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00)
4278 #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100)
4279 #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200)
4280 #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400)
4281 #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800)
4283 #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000)
4284 #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000)
4285 #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000)
4286 #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000)
4287 #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000)
4289 #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000)
4290 #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000)
4291 #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000)
4292 #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000)
4293 #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000)
4295 #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000)
4296 #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000)
4297 #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000)
4298 #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000)
4299 #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000)
4301 #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000)
4302 #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000)
4303 #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000)
4305 /******************* Bit definition for FSMC_BTR3 register *******************/
4306 #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F)
4307 #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001)
4308 #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002)
4309 #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004)
4310 #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008)
4312 #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0)
4313 #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010)
4314 #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020)
4315 #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040)
4316 #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080)
4318 #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00)
4319 #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100)
4320 #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200)
4321 #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400)
4322 #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800)
4324 #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000)
4325 #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000)
4326 #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000)
4327 #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000)
4328 #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000)
4330 #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000)
4331 #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000)
4332 #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000)
4333 #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000)
4334 #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000)
4336 #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000)
4337 #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000)
4338 #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000)
4339 #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000)
4340 #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000)
4342 #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000)
4343 #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000)
4344 #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000)
4346 /****************** Bit definition for FSMC_BTR4 register *******************/
4347 #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F)
4348 #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001)
4349 #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002)
4350 #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004)
4351 #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008)
4353 #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0)
4354 #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010)
4355 #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020)
4356 #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040)
4357 #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080)
4359 #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00)
4360 #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100)
4361 #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200)
4362 #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400)
4363 #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800)
4365 #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000)
4366 #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000)
4367 #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000)
4368 #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000)
4369 #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000)
4371 #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000)
4372 #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000)
4373 #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000)
4374 #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000)
4375 #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000)
4377 #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000)
4378 #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000)
4379 #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000)
4380 #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000)
4381 #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000)
4383 #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000)
4384 #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000)
4385 #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000)
4387 /****************** Bit definition for FSMC_BWTR1 register ******************/
4388 #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F)
4389 #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001)
4390 #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002)
4391 #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004)
4392 #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008)
4394 #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0)
4395 #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010)
4396 #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020)
4397 #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040)
4398 #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080)
4400 #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00)
4401 #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100)
4402 #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200)
4403 #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400)
4404 #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800)
4406 #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000)
4407 #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000)
4408 #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000)
4409 #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000)
4410 #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000)
4412 #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000)
4413 #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000)
4414 #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000)
4415 #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000)
4416 #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000)
4418 #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000)
4419 #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000)
4420 #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000)
4422 /****************** Bit definition for FSMC_BWTR2 register ******************/
4423 #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F)
4424 #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001)
4425 #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002)
4426 #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004)
4427 #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008)
4429 #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0)
4430 #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010)
4431 #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020)
4432 #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040)
4433 #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080)
4435 #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00)
4436 #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100)
4437 #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200)
4438 #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400)
4439 #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800)
4441 #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000)
4442 #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000)
4443 #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000)
4444 #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000)
4445 #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000)
4447 #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000)
4448 #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000)
4449 #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000)
4450 #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000)
4451 #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000)
4453 #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000)
4454 #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000)
4455 #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000)
4457 /****************** Bit definition for FSMC_BWTR3 register ******************/
4458 #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F)
4459 #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001)
4460 #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002)
4461 #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004)
4462 #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008)
4464 #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0)
4465 #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010)
4466 #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020)
4467 #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040)
4468 #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080)
4470 #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00)
4471 #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100)
4472 #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200)
4473 #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400)
4474 #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800)
4476 #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000)
4477 #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000)
4478 #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000)
4479 #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000)
4480 #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000)
4482 #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000)
4483 #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000)
4484 #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000)
4485 #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000)
4486 #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000)
4488 #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000)
4489 #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000)
4490 #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000)
4492 /****************** Bit definition for FSMC_BWTR4 register ******************/
4493 #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F)
4494 #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001)
4495 #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002)
4496 #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004)
4497 #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008)
4499 #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0)
4500 #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010)
4501 #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020)
4502 #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040)
4503 #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080)
4505 #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00)
4506 #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100)
4507 #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200)
4508 #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400)
4509 #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800)
4511 #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000)
4512 #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000)
4513 #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000)
4514 #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000)
4515 #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000)
4517 #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000)
4518 #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000)
4519 #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000)
4520 #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000)
4521 #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000)
4523 #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000)
4524 #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000)
4525 #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000)
4527 /****************** Bit definition for FSMC_PCR2 register *******************/
4528 #define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002)
4529 #define FSMC_PCR2_PBKEN ((uint32_t)0x00000004)
4530 #define FSMC_PCR2_PTYP ((uint32_t)0x00000008)
4532 #define FSMC_PCR2_PWID ((uint32_t)0x00000030)
4533 #define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010)
4534 #define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020)
4536 #define FSMC_PCR2_ECCEN ((uint32_t)0x00000040)
4538 #define FSMC_PCR2_TCLR ((uint32_t)0x00001E00)
4539 #define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200)
4540 #define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400)
4541 #define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800)
4542 #define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000)
4544 #define FSMC_PCR2_TAR ((uint32_t)0x0001E000)
4545 #define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000)
4546 #define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000)
4547 #define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000)
4548 #define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000)
4550 #define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000)
4551 #define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000)
4552 #define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000)
4553 #define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000)
4555 /****************** Bit definition for FSMC_PCR3 register *******************/
4556 #define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002)
4557 #define FSMC_PCR3_PBKEN ((uint32_t)0x00000004)
4558 #define FSMC_PCR3_PTYP ((uint32_t)0x00000008)
4560 #define FSMC_PCR3_PWID ((uint32_t)0x00000030)
4561 #define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010)
4562 #define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020)
4564 #define FSMC_PCR3_ECCEN ((uint32_t)0x00000040)
4566 #define FSMC_PCR3_TCLR ((uint32_t)0x00001E00)
4567 #define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200)
4568 #define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400)
4569 #define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800)
4570 #define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000)
4572 #define FSMC_PCR3_TAR ((uint32_t)0x0001E000)
4573 #define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000)
4574 #define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000)
4575 #define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000)
4576 #define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000)
4578 #define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000)
4579 #define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000)
4580 #define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000)
4581 #define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000)
4583 /****************** Bit definition for FSMC_PCR4 register *******************/
4584 #define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002)
4585 #define FSMC_PCR4_PBKEN ((uint32_t)0x00000004)
4586 #define FSMC_PCR4_PTYP ((uint32_t)0x00000008)
4588 #define FSMC_PCR4_PWID ((uint32_t)0x00000030)
4589 #define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010)
4590 #define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020)
4592 #define FSMC_PCR4_ECCEN ((uint32_t)0x00000040)
4594 #define FSMC_PCR4_TCLR ((uint32_t)0x00001E00)
4595 #define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200)
4596 #define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400)
4597 #define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800)
4598 #define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000)
4600 #define FSMC_PCR4_TAR ((uint32_t)0x0001E000)
4601 #define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000)
4602 #define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000)
4603 #define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000)
4604 #define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000)
4606 #define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000)
4607 #define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000)
4608 #define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000)
4609 #define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000)
4611 /******************* Bit definition for FSMC_SR2 register *******************/
4612 #define FSMC_SR2_IRS ((uint8_t)0x01)
4613 #define FSMC_SR2_ILS ((uint8_t)0x02)
4614 #define FSMC_SR2_IFS ((uint8_t)0x04)
4615 #define FSMC_SR2_IREN ((uint8_t)0x08)
4616 #define FSMC_SR2_ILEN ((uint8_t)0x10)
4617 #define FSMC_SR2_IFEN ((uint8_t)0x20)
4618 #define FSMC_SR2_FEMPT ((uint8_t)0x40)
4620 /******************* Bit definition for FSMC_SR3 register *******************/
4621 #define FSMC_SR3_IRS ((uint8_t)0x01)
4622 #define FSMC_SR3_ILS ((uint8_t)0x02)
4623 #define FSMC_SR3_IFS ((uint8_t)0x04)
4624 #define FSMC_SR3_IREN ((uint8_t)0x08)
4625 #define FSMC_SR3_ILEN ((uint8_t)0x10)
4626 #define FSMC_SR3_IFEN ((uint8_t)0x20)
4627 #define FSMC_SR3_FEMPT ((uint8_t)0x40)
4629 /******************* Bit definition for FSMC_SR4 register *******************/
4630 #define FSMC_SR4_IRS ((uint8_t)0x01)
4631 #define FSMC_SR4_ILS ((uint8_t)0x02)
4632 #define FSMC_SR4_IFS ((uint8_t)0x04)
4633 #define FSMC_SR4_IREN ((uint8_t)0x08)
4634 #define FSMC_SR4_ILEN ((uint8_t)0x10)
4635 #define FSMC_SR4_IFEN ((uint8_t)0x20)
4636 #define FSMC_SR4_FEMPT ((uint8_t)0x40)
4638 /****************** Bit definition for FSMC_PMEM2 register ******************/
4639 #define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF)
4640 #define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001)
4641 #define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002)
4642 #define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004)
4643 #define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008)
4644 #define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010)
4645 #define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020)
4646 #define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040)
4647 #define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080)
4649 #define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00)
4650 #define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100)
4651 #define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200)
4652 #define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400)
4653 #define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800)
4654 #define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000)
4655 #define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000)
4656 #define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000)
4657 #define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000)
4659 #define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000)
4660 #define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000)
4661 #define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000)
4662 #define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000)
4663 #define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000)
4664 #define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000)
4665 #define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000)
4666 #define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000)
4667 #define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000)
4669 #define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000)
4670 #define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000)
4671 #define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000)
4672 #define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000)
4673 #define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000)
4674 #define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000)
4675 #define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000)
4676 #define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000)
4677 #define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000)
4679 /****************** Bit definition for FSMC_PMEM3 register ******************/
4680 #define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF)
4681 #define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001)
4682 #define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002)
4683 #define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004)
4684 #define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008)
4685 #define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010)
4686 #define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020)
4687 #define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040)
4688 #define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080)
4690 #define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00)
4691 #define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100)
4692 #define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200)
4693 #define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400)
4694 #define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800)
4695 #define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000)
4696 #define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000)
4697 #define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000)
4698 #define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000)
4700 #define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000)
4701 #define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000)
4702 #define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000)
4703 #define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000)
4704 #define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000)
4705 #define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000)
4706 #define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000)
4707 #define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000)
4708 #define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000)
4710 #define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000)
4711 #define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000)
4712 #define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000)
4713 #define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000)
4714 #define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000)
4715 #define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000)
4716 #define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000)
4717 #define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000)
4718 #define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000)
4720 /****************** Bit definition for FSMC_PMEM4 register ******************/
4721 #define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF)
4722 #define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001)
4723 #define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002)
4724 #define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004)
4725 #define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008)
4726 #define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010)
4727 #define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020)
4728 #define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040)
4729 #define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080)
4731 #define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00)
4732 #define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100)
4733 #define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200)
4734 #define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400)
4735 #define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800)
4736 #define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000)
4737 #define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000)
4738 #define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000)
4739 #define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000)
4741 #define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000)
4742 #define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000)
4743 #define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000)
4744 #define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000)
4745 #define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000)
4746 #define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000)
4747 #define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000)
4748 #define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000)
4749 #define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000)
4751 #define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000)
4752 #define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000)
4753 #define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000)
4754 #define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000)
4755 #define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000)
4756 #define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000)
4757 #define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000)
4758 #define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000)
4759 #define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000)
4761 /****************** Bit definition for FSMC_PATT2 register ******************/
4762 #define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF)
4763 #define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001)
4764 #define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002)
4765 #define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004)
4766 #define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008)
4767 #define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010)
4768 #define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020)
4769 #define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040)
4770 #define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080)
4772 #define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00)
4773 #define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100)
4774 #define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200)
4775 #define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400)
4776 #define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800)
4777 #define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000)
4778 #define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000)
4779 #define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000)
4780 #define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000)
4782 #define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000)
4783 #define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000)
4784 #define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000)
4785 #define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000)
4786 #define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000)
4787 #define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000)
4788 #define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000)
4789 #define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000)
4790 #define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000)
4792 #define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000)
4793 #define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000)
4794 #define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000)
4795 #define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000)
4796 #define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000)
4797 #define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000)
4798 #define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000)
4799 #define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000)
4800 #define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000)
4802 /****************** Bit definition for FSMC_PATT3 register ******************/
4803 #define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF)
4804 #define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001)
4805 #define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002)
4806 #define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004)
4807 #define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008)
4808 #define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010)
4809 #define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020)
4810 #define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040)
4811 #define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080)
4813 #define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00)
4814 #define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100)
4815 #define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200)
4816 #define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400)
4817 #define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800)
4818 #define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000)
4819 #define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000)
4820 #define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000)
4821 #define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000)
4823 #define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000)
4824 #define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000)
4825 #define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000)
4826 #define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000)
4827 #define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000)
4828 #define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000)
4829 #define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000)
4830 #define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000)
4831 #define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000)
4833 #define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000)
4834 #define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000)
4835 #define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000)
4836 #define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000)
4837 #define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000)
4838 #define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000)
4839 #define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000)
4840 #define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000)
4841 #define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000)
4843 /****************** Bit definition for FSMC_PATT4 register ******************/
4844 #define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF)
4845 #define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001)
4846 #define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002)
4847 #define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004)
4848 #define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008)
4849 #define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010)
4850 #define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020)
4851 #define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040)
4852 #define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080)
4854 #define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00)
4855 #define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100)
4856 #define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200)
4857 #define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400)
4858 #define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800)
4859 #define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000)
4860 #define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000)
4861 #define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000)
4862 #define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000)
4864 #define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000)
4865 #define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000)
4866 #define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000)
4867 #define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000)
4868 #define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000)
4869 #define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000)
4870 #define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000)
4871 #define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000)
4872 #define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000)
4874 #define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000)
4875 #define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000)
4876 #define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000)
4877 #define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000)
4878 #define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000)
4879 #define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000)
4880 #define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000)
4881 #define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000)
4882 #define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000)
4884 /****************** Bit definition for FSMC_PIO4 register *******************/
4885 #define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF)
4886 #define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001)
4887 #define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002)
4888 #define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004)
4889 #define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008)
4890 #define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010)
4891 #define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020)
4892 #define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040)
4893 #define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080)
4895 #define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00)
4896 #define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100)
4897 #define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200)
4898 #define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400)
4899 #define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800)
4900 #define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000)
4901 #define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000)
4902 #define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000)
4903 #define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000)
4905 #define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000)
4906 #define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000)
4907 #define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000)
4908 #define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000)
4909 #define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000)
4910 #define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000)
4911 #define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000)
4912 #define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000)
4913 #define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000)
4915 #define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000)
4916 #define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000)
4917 #define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000)
4918 #define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000)
4919 #define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000)
4920 #define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000)
4921 #define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000)
4922 #define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000)
4923 #define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000)
4925 /****************** Bit definition for FSMC_ECCR2 register ******************/
4926 #define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF)
4928 /****************** Bit definition for FSMC_ECCR3 register ******************/
4929 #define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF)
4930 #endif /* STM32F40_41xxx */
4931 
4932 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
4933 /******************************************************************************/
4934 /* */
4935 /* Flexible Memory Controller */
4936 /* */
4937 /******************************************************************************/
4938 /****************** Bit definition for FMC_BCR1 register *******************/
4939 #define FMC_BCR1_MBKEN ((uint32_t)0x00000001)
4940 #define FMC_BCR1_MUXEN ((uint32_t)0x00000002)
4942 #define FMC_BCR1_MTYP ((uint32_t)0x0000000C)
4943 #define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004)
4944 #define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008)
4946 #define FMC_BCR1_MWID ((uint32_t)0x00000030)
4947 #define FMC_BCR1_MWID_0 ((uint32_t)0x00000010)
4948 #define FMC_BCR1_MWID_1 ((uint32_t)0x00000020)
4950 #define FMC_BCR1_FACCEN ((uint32_t)0x00000040)
4951 #define FMC_BCR1_BURSTEN ((uint32_t)0x00000100)
4952 #define FMC_BCR1_WAITPOL ((uint32_t)0x00000200)
4953 #define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400)
4954 #define FMC_BCR1_WAITCFG ((uint32_t)0x00000800)
4955 #define FMC_BCR1_WREN ((uint32_t)0x00001000)
4956 #define FMC_BCR1_WAITEN ((uint32_t)0x00002000)
4957 #define FMC_BCR1_EXTMOD ((uint32_t)0x00004000)
4958 #define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000)
4959 #define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000)
4960 #define FMC_BCR1_CCLKEN ((uint32_t)0x00100000)
4962 /****************** Bit definition for FMC_BCR2 register *******************/
4963 #define FMC_BCR2_MBKEN ((uint32_t)0x00000001)
4964 #define FMC_BCR2_MUXEN ((uint32_t)0x00000002)
4966 #define FMC_BCR2_MTYP ((uint32_t)0x0000000C)
4967 #define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004)
4968 #define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008)
4970 #define FMC_BCR2_MWID ((uint32_t)0x00000030)
4971 #define FMC_BCR2_MWID_0 ((uint32_t)0x00000010)
4972 #define FMC_BCR2_MWID_1 ((uint32_t)0x00000020)
4974 #define FMC_BCR2_FACCEN ((uint32_t)0x00000040)
4975 #define FMC_BCR2_BURSTEN ((uint32_t)0x00000100)
4976 #define FMC_BCR2_WAITPOL ((uint32_t)0x00000200)
4977 #define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400)
4978 #define FMC_BCR2_WAITCFG ((uint32_t)0x00000800)
4979 #define FMC_BCR2_WREN ((uint32_t)0x00001000)
4980 #define FMC_BCR2_WAITEN ((uint32_t)0x00002000)
4981 #define FMC_BCR2_EXTMOD ((uint32_t)0x00004000)
4982 #define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000)
4983 #define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000)
4985 /****************** Bit definition for FMC_BCR3 register *******************/
4986 #define FMC_BCR3_MBKEN ((uint32_t)0x00000001)
4987 #define FMC_BCR3_MUXEN ((uint32_t)0x00000002)
4989 #define FMC_BCR3_MTYP ((uint32_t)0x0000000C)
4990 #define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004)
4991 #define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008)
4993 #define FMC_BCR3_MWID ((uint32_t)0x00000030)
4994 #define FMC_BCR3_MWID_0 ((uint32_t)0x00000010)
4995 #define FMC_BCR3_MWID_1 ((uint32_t)0x00000020)
4997 #define FMC_BCR3_FACCEN ((uint32_t)0x00000040)
4998 #define FMC_BCR3_BURSTEN ((uint32_t)0x00000100)
4999 #define FMC_BCR3_WAITPOL ((uint32_t)0x00000200)
5000 #define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400)
5001 #define FMC_BCR3_WAITCFG ((uint32_t)0x00000800)
5002 #define FMC_BCR3_WREN ((uint32_t)0x00001000)
5003 #define FMC_BCR3_WAITEN ((uint32_t)0x00002000)
5004 #define FMC_BCR3_EXTMOD ((uint32_t)0x00004000)
5005 #define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000)
5006 #define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000)
5008 /****************** Bit definition for FMC_BCR4 register *******************/
5009 #define FMC_BCR4_MBKEN ((uint32_t)0x00000001)
5010 #define FMC_BCR4_MUXEN ((uint32_t)0x00000002)
5012 #define FMC_BCR4_MTYP ((uint32_t)0x0000000C)
5013 #define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004)
5014 #define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008)
5016 #define FMC_BCR4_MWID ((uint32_t)0x00000030)
5017 #define FMC_BCR4_MWID_0 ((uint32_t)0x00000010)
5018 #define FMC_BCR4_MWID_1 ((uint32_t)0x00000020)
5020 #define FMC_BCR4_FACCEN ((uint32_t)0x00000040)
5021 #define FMC_BCR4_BURSTEN ((uint32_t)0x00000100)
5022 #define FMC_BCR4_WAITPOL ((uint32_t)0x00000200)
5023 #define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400)
5024 #define FMC_BCR4_WAITCFG ((uint32_t)0x00000800)
5025 #define FMC_BCR4_WREN ((uint32_t)0x00001000)
5026 #define FMC_BCR4_WAITEN ((uint32_t)0x00002000)
5027 #define FMC_BCR4_EXTMOD ((uint32_t)0x00004000)
5028 #define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000)
5029 #define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000)
5031 /****************** Bit definition for FMC_BTR1 register ******************/
5032 #define FMC_BTR1_ADDSET ((uint32_t)0x0000000F)
5033 #define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001)
5034 #define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002)
5035 #define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004)
5036 #define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008)
5038 #define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0)
5039 #define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010)
5040 #define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020)
5041 #define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040)
5042 #define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080)
5044 #define FMC_BTR1_DATAST ((uint32_t)0x0000FF00)
5045 #define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100)
5046 #define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200)
5047 #define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400)
5048 #define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800)
5049 #define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000)
5050 #define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000)
5051 #define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000)
5052 #define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000)
5054 #define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000)
5055 #define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000)
5056 #define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000)
5057 #define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000)
5058 #define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000)
5060 #define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000)
5061 #define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000)
5062 #define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000)
5063 #define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000)
5064 #define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000)
5066 #define FMC_BTR1_DATLAT ((uint32_t)0x0F000000)
5067 #define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000)
5068 #define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000)
5069 #define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000)
5070 #define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000)
5072 #define FMC_BTR1_ACCMOD ((uint32_t)0x30000000)
5073 #define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000)
5074 #define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000)
5076 /****************** Bit definition for FMC_BTR2 register *******************/
5077 #define FMC_BTR2_ADDSET ((uint32_t)0x0000000F)
5078 #define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001)
5079 #define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002)
5080 #define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004)
5081 #define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008)
5083 #define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0)
5084 #define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010)
5085 #define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020)
5086 #define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040)
5087 #define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080)
5089 #define FMC_BTR2_DATAST ((uint32_t)0x0000FF00)
5090 #define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100)
5091 #define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200)
5092 #define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400)
5093 #define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800)
5094 #define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000)
5095 #define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000)
5096 #define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000)
5097 #define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000)
5099 #define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000)
5100 #define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000)
5101 #define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000)
5102 #define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000)
5103 #define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000)
5105 #define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000)
5106 #define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000)
5107 #define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000)
5108 #define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000)
5109 #define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000)
5111 #define FMC_BTR2_DATLAT ((uint32_t)0x0F000000)
5112 #define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000)
5113 #define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000)
5114 #define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000)
5115 #define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000)
5117 #define FMC_BTR2_ACCMOD ((uint32_t)0x30000000)
5118 #define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000)
5119 #define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000)
5121 /******************* Bit definition for FMC_BTR3 register *******************/
5122 #define FMC_BTR3_ADDSET ((uint32_t)0x0000000F)
5123 #define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001)
5124 #define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002)
5125 #define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004)
5126 #define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008)
5128 #define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0)
5129 #define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010)
5130 #define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020)
5131 #define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040)
5132 #define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080)
5134 #define FMC_BTR3_DATAST ((uint32_t)0x0000FF00)
5135 #define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100)
5136 #define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200)
5137 #define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400)
5138 #define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800)
5139 #define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000)
5140 #define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000)
5141 #define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000)
5142 #define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000)
5144 #define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000)
5145 #define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000)
5146 #define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000)
5147 #define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000)
5148 #define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000)
5150 #define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000)
5151 #define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000)
5152 #define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000)
5153 #define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000)
5154 #define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000)
5156 #define FMC_BTR3_DATLAT ((uint32_t)0x0F000000)
5157 #define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000)
5158 #define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000)
5159 #define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000)
5160 #define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000)
5162 #define FMC_BTR3_ACCMOD ((uint32_t)0x30000000)
5163 #define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000)
5164 #define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000)
5166 /****************** Bit definition for FMC_BTR4 register *******************/
5167 #define FMC_BTR4_ADDSET ((uint32_t)0x0000000F)
5168 #define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001)
5169 #define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002)
5170 #define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004)
5171 #define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008)
5173 #define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0)
5174 #define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010)
5175 #define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020)
5176 #define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040)
5177 #define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080)
5179 #define FMC_BTR4_DATAST ((uint32_t)0x0000FF00)
5180 #define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100)
5181 #define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200)
5182 #define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400)
5183 #define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800)
5184 #define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000)
5185 #define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000)
5186 #define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000)
5187 #define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000)
5189 #define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000)
5190 #define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000)
5191 #define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000)
5192 #define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000)
5193 #define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000)
5195 #define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000)
5196 #define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000)
5197 #define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000)
5198 #define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000)
5199 #define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000)
5201 #define FMC_BTR4_DATLAT ((uint32_t)0x0F000000)
5202 #define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000)
5203 #define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000)
5204 #define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000)
5205 #define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000)
5207 #define FMC_BTR4_ACCMOD ((uint32_t)0x30000000)
5208 #define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000)
5209 #define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000)
5211 /****************** Bit definition for FMC_BWTR1 register ******************/
5212 #define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F)
5213 #define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001)
5214 #define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002)
5215 #define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004)
5216 #define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008)
5218 #define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0)
5219 #define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010)
5220 #define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020)
5221 #define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040)
5222 #define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080)
5224 #define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00)
5225 #define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100)
5226 #define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200)
5227 #define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400)
5228 #define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800)
5229 #define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000)
5230 #define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000)
5231 #define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000)
5232 #define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000)
5234 #define FMC_BWTR1_CLKDIV ((uint32_t)0x00F00000)
5235 #define FMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000)
5236 #define FMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000)
5237 #define FMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000)
5238 #define FMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000)
5240 #define FMC_BWTR1_DATLAT ((uint32_t)0x0F000000)
5241 #define FMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000)
5242 #define FMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000)
5243 #define FMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000)
5244 #define FMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000)
5246 #define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000)
5247 #define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000)
5248 #define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000)
5250 /****************** Bit definition for FMC_BWTR2 register ******************/
5251 #define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F)
5252 #define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001)
5253 #define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002)
5254 #define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004)
5255 #define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008)
5257 #define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0)
5258 #define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010)
5259 #define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020)
5260 #define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040)
5261 #define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080)
5263 #define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00)
5264 #define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100)
5265 #define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200)
5266 #define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400)
5267 #define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800)
5268 #define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000)
5269 #define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000)
5270 #define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000)
5271 #define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000)
5273 #define FMC_BWTR2_CLKDIV ((uint32_t)0x00F00000)
5274 #define FMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000)
5275 #define FMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000)
5276 #define FMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000)
5277 #define FMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000)
5279 #define FMC_BWTR2_DATLAT ((uint32_t)0x0F000000)
5280 #define FMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000)
5281 #define FMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000)
5282 #define FMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000)
5283 #define FMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000)
5285 #define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000)
5286 #define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000)
5287 #define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000)
5289 /****************** Bit definition for FMC_BWTR3 register ******************/
5290 #define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F)
5291 #define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001)
5292 #define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002)
5293 #define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004)
5294 #define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008)
5296 #define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0)
5297 #define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010)
5298 #define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020)
5299 #define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040)
5300 #define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080)
5302 #define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00)
5303 #define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100)
5304 #define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200)
5305 #define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400)
5306 #define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800)
5307 #define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000)
5308 #define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000)
5309 #define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000)
5310 #define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000)
5312 #define FMC_BWTR3_CLKDIV ((uint32_t)0x00F00000)
5313 #define FMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000)
5314 #define FMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000)
5315 #define FMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000)
5316 #define FMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000)
5318 #define FMC_BWTR3_DATLAT ((uint32_t)0x0F000000)
5319 #define FMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000)
5320 #define FMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000)
5321 #define FMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000)
5322 #define FMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000)
5324 #define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000)
5325 #define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000)
5326 #define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000)
5328 /****************** Bit definition for FMC_BWTR4 register ******************/
5329 #define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F)
5330 #define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001)
5331 #define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002)
5332 #define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004)
5333 #define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008)
5335 #define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0)
5336 #define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010)
5337 #define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020)
5338 #define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040)
5339 #define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080)
5341 #define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00)
5342 #define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100)
5343 #define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200)
5344 #define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400)
5345 #define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800)
5346 #define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000)
5347 #define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000)
5348 #define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000)
5349 #define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000)
5351 #define FMC_BWTR4_CLKDIV ((uint32_t)0x00F00000)
5352 #define FMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000)
5353 #define FMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000)
5354 #define FMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000)
5355 #define FMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000)
5357 #define FMC_BWTR4_DATLAT ((uint32_t)0x0F000000)
5358 #define FMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000)
5359 #define FMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000)
5360 #define FMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000)
5361 #define FMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000)
5363 #define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000)
5364 #define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000)
5365 #define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000)
5367 /****************** Bit definition for FMC_PCR2 register *******************/
5368 #define FMC_PCR2_PWAITEN ((uint32_t)0x00000002)
5369 #define FMC_PCR2_PBKEN ((uint32_t)0x00000004)
5370 #define FMC_PCR2_PTYP ((uint32_t)0x00000008)
5372 #define FMC_PCR2_PWID ((uint32_t)0x00000030)
5373 #define FMC_PCR2_PWID_0 ((uint32_t)0x00000010)
5374 #define FMC_PCR2_PWID_1 ((uint32_t)0x00000020)
5376 #define FMC_PCR2_ECCEN ((uint32_t)0x00000040)
5378 #define FMC_PCR2_TCLR ((uint32_t)0x00001E00)
5379 #define FMC_PCR2_TCLR_0 ((uint32_t)0x00000200)
5380 #define FMC_PCR2_TCLR_1 ((uint32_t)0x00000400)
5381 #define FMC_PCR2_TCLR_2 ((uint32_t)0x00000800)
5382 #define FMC_PCR2_TCLR_3 ((uint32_t)0x00001000)
5384 #define FMC_PCR2_TAR ((uint32_t)0x0001E000)
5385 #define FMC_PCR2_TAR_0 ((uint32_t)0x00002000)
5386 #define FMC_PCR2_TAR_1 ((uint32_t)0x00004000)
5387 #define FMC_PCR2_TAR_2 ((uint32_t)0x00008000)
5388 #define FMC_PCR2_TAR_3 ((uint32_t)0x00010000)
5390 #define FMC_PCR2_ECCPS ((uint32_t)0x000E0000)
5391 #define FMC_PCR2_ECCPS_0 ((uint32_t)0x00020000)
5392 #define FMC_PCR2_ECCPS_1 ((uint32_t)0x00040000)
5393 #define FMC_PCR2_ECCPS_2 ((uint32_t)0x00080000)
5395 /****************** Bit definition for FMC_PCR3 register *******************/
5396 #define FMC_PCR3_PWAITEN ((uint32_t)0x00000002)
5397 #define FMC_PCR3_PBKEN ((uint32_t)0x00000004)
5398 #define FMC_PCR3_PTYP ((uint32_t)0x00000008)
5400 #define FMC_PCR3_PWID ((uint32_t)0x00000030)
5401 #define FMC_PCR3_PWID_0 ((uint32_t)0x00000010)
5402 #define FMC_PCR3_PWID_1 ((uint32_t)0x00000020)
5404 #define FMC_PCR3_ECCEN ((uint32_t)0x00000040)
5406 #define FMC_PCR3_TCLR ((uint32_t)0x00001E00)
5407 #define FMC_PCR3_TCLR_0 ((uint32_t)0x00000200)
5408 #define FMC_PCR3_TCLR_1 ((uint32_t)0x00000400)
5409 #define FMC_PCR3_TCLR_2 ((uint32_t)0x00000800)
5410 #define FMC_PCR3_TCLR_3 ((uint32_t)0x00001000)
5412 #define FMC_PCR3_TAR ((uint32_t)0x0001E000)
5413 #define FMC_PCR3_TAR_0 ((uint32_t)0x00002000)
5414 #define FMC_PCR3_TAR_1 ((uint32_t)0x00004000)
5415 #define FMC_PCR3_TAR_2 ((uint32_t)0x00008000)
5416 #define FMC_PCR3_TAR_3 ((uint32_t)0x00010000)
5418 #define FMC_PCR3_ECCPS ((uint32_t)0x000E0000)
5419 #define FMC_PCR3_ECCPS_0 ((uint32_t)0x00020000)
5420 #define FMC_PCR3_ECCPS_1 ((uint32_t)0x00040000)
5421 #define FMC_PCR3_ECCPS_2 ((uint32_t)0x00080000)
5423 /****************** Bit definition for FMC_PCR4 register *******************/
5424 #define FMC_PCR4_PWAITEN ((uint32_t)0x00000002)
5425 #define FMC_PCR4_PBKEN ((uint32_t)0x00000004)
5426 #define FMC_PCR4_PTYP ((uint32_t)0x00000008)
5428 #define FMC_PCR4_PWID ((uint32_t)0x00000030)
5429 #define FMC_PCR4_PWID_0 ((uint32_t)0x00000010)
5430 #define FMC_PCR4_PWID_1 ((uint32_t)0x00000020)
5432 #define FMC_PCR4_ECCEN ((uint32_t)0x00000040)
5434 #define FMC_PCR4_TCLR ((uint32_t)0x00001E00)
5435 #define FMC_PCR4_TCLR_0 ((uint32_t)0x00000200)
5436 #define FMC_PCR4_TCLR_1 ((uint32_t)0x00000400)
5437 #define FMC_PCR4_TCLR_2 ((uint32_t)0x00000800)
5438 #define FMC_PCR4_TCLR_3 ((uint32_t)0x00001000)
5440 #define FMC_PCR4_TAR ((uint32_t)0x0001E000)
5441 #define FMC_PCR4_TAR_0 ((uint32_t)0x00002000)
5442 #define FMC_PCR4_TAR_1 ((uint32_t)0x00004000)
5443 #define FMC_PCR4_TAR_2 ((uint32_t)0x00008000)
5444 #define FMC_PCR4_TAR_3 ((uint32_t)0x00010000)
5446 #define FMC_PCR4_ECCPS ((uint32_t)0x000E0000)
5447 #define FMC_PCR4_ECCPS_0 ((uint32_t)0x00020000)
5448 #define FMC_PCR4_ECCPS_1 ((uint32_t)0x00040000)
5449 #define FMC_PCR4_ECCPS_2 ((uint32_t)0x00080000)
5451 /******************* Bit definition for FMC_SR2 register *******************/
5452 #define FMC_SR2_IRS ((uint8_t)0x01)
5453 #define FMC_SR2_ILS ((uint8_t)0x02)
5454 #define FMC_SR2_IFS ((uint8_t)0x04)
5455 #define FMC_SR2_IREN ((uint8_t)0x08)
5456 #define FMC_SR2_ILEN ((uint8_t)0x10)
5457 #define FMC_SR2_IFEN ((uint8_t)0x20)
5458 #define FMC_SR2_FEMPT ((uint8_t)0x40)
5460 /******************* Bit definition for FMC_SR3 register *******************/
5461 #define FMC_SR3_IRS ((uint8_t)0x01)
5462 #define FMC_SR3_ILS ((uint8_t)0x02)
5463 #define FMC_SR3_IFS ((uint8_t)0x04)
5464 #define FMC_SR3_IREN ((uint8_t)0x08)
5465 #define FMC_SR3_ILEN ((uint8_t)0x10)
5466 #define FMC_SR3_IFEN ((uint8_t)0x20)
5467 #define FMC_SR3_FEMPT ((uint8_t)0x40)
5469 /******************* Bit definition for FMC_SR4 register *******************/
5470 #define FMC_SR4_IRS ((uint8_t)0x01)
5471 #define FMC_SR4_ILS ((uint8_t)0x02)
5472 #define FMC_SR4_IFS ((uint8_t)0x04)
5473 #define FMC_SR4_IREN ((uint8_t)0x08)
5474 #define FMC_SR4_ILEN ((uint8_t)0x10)
5475 #define FMC_SR4_IFEN ((uint8_t)0x20)
5476 #define FMC_SR4_FEMPT ((uint8_t)0x40)
5478 /****************** Bit definition for FMC_PMEM2 register ******************/
5479 #define FMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF)
5480 #define FMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001)
5481 #define FMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002)
5482 #define FMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004)
5483 #define FMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008)
5484 #define FMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010)
5485 #define FMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020)
5486 #define FMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040)
5487 #define FMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080)
5489 #define FMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00)
5490 #define FMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100)
5491 #define FMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200)
5492 #define FMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400)
5493 #define FMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800)
5494 #define FMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000)
5495 #define FMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000)
5496 #define FMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000)
5497 #define FMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000)
5499 #define FMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000)
5500 #define FMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000)
5501 #define FMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000)
5502 #define FMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000)
5503 #define FMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000)
5504 #define FMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000)
5505 #define FMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000)
5506 #define FMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000)
5507 #define FMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000)
5509 #define FMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000)
5510 #define FMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000)
5511 #define FMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000)
5512 #define FMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000)
5513 #define FMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000)
5514 #define FMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000)
5515 #define FMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000)
5516 #define FMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000)
5517 #define FMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000)
5519 /****************** Bit definition for FMC_PMEM3 register ******************/
5520 #define FMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF)
5521 #define FMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001)
5522 #define FMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002)
5523 #define FMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004)
5524 #define FMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008)
5525 #define FMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010)
5526 #define FMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020)
5527 #define FMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040)
5528 #define FMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080)
5530 #define FMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00)
5531 #define FMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100)
5532 #define FMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200)
5533 #define FMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400)
5534 #define FMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800)
5535 #define FMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000)
5536 #define FMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000)
5537 #define FMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000)
5538 #define FMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000)
5540 #define FMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000)
5541 #define FMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000)
5542 #define FMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000)
5543 #define FMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000)
5544 #define FMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000)
5545 #define FMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000)
5546 #define FMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000)
5547 #define FMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000)
5548 #define FMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000)
5550 #define FMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000)
5551 #define FMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000)
5552 #define FMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000)
5553 #define FMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000)
5554 #define FMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000)
5555 #define FMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000)
5556 #define FMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000)
5557 #define FMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000)
5558 #define FMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000)
5560 /****************** Bit definition for FMC_PMEM4 register ******************/
5561 #define FMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF)
5562 #define FMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001)
5563 #define FMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002)
5564 #define FMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004)
5565 #define FMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008)
5566 #define FMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010)
5567 #define FMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020)
5568 #define FMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040)
5569 #define FMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080)
5571 #define FMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00)
5572 #define FMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100)
5573 #define FMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200)
5574 #define FMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400)
5575 #define FMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800)
5576 #define FMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000)
5577 #define FMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000)
5578 #define FMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000)
5579 #define FMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000)
5581 #define FMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000)
5582 #define FMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000)
5583 #define FMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000)
5584 #define FMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000)
5585 #define FMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000)
5586 #define FMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000)
5587 #define FMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000)
5588 #define FMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000)
5589 #define FMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000)
5591 #define FMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000)
5592 #define FMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000)
5593 #define FMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000)
5594 #define FMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000)
5595 #define FMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000)
5596 #define FMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000)
5597 #define FMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000)
5598 #define FMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000)
5599 #define FMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000)
5601 /****************** Bit definition for FMC_PATT2 register ******************/
5602 #define FMC_PATT2_ATTSET2 ((uint32_t)0x000000FF)
5603 #define FMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001)
5604 #define FMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002)
5605 #define FMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004)
5606 #define FMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008)
5607 #define FMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010)
5608 #define FMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020)
5609 #define FMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040)
5610 #define FMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080)
5612 #define FMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00)
5613 #define FMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100)
5614 #define FMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200)
5615 #define FMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400)
5616 #define FMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800)
5617 #define FMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000)
5618 #define FMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000)
5619 #define FMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000)
5620 #define FMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000)
5622 #define FMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000)
5623 #define FMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000)
5624 #define FMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000)
5625 #define FMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000)
5626 #define FMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000)
5627 #define FMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000)
5628 #define FMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000)
5629 #define FMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000)
5630 #define FMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000)
5632 #define FMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000)
5633 #define FMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000)
5634 #define FMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000)
5635 #define FMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000)
5636 #define FMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000)
5637 #define FMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000)
5638 #define FMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000)
5639 #define FMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000)
5640 #define FMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000)
5642 /****************** Bit definition for FMC_PATT3 register ******************/
5643 #define FMC_PATT3_ATTSET3 ((uint32_t)0x000000FF)
5644 #define FMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001)
5645 #define FMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002)
5646 #define FMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004)
5647 #define FMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008)
5648 #define FMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010)
5649 #define FMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020)
5650 #define FMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040)
5651 #define FMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080)
5653 #define FMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00)
5654 #define FMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100)
5655 #define FMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200)
5656 #define FMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400)
5657 #define FMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800)
5658 #define FMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000)
5659 #define FMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000)
5660 #define FMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000)
5661 #define FMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000)
5663 #define FMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000)
5664 #define FMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000)
5665 #define FMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000)
5666 #define FMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000)
5667 #define FMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000)
5668 #define FMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000)
5669 #define FMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000)
5670 #define FMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000)
5671 #define FMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000)
5673 #define FMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000)
5674 #define FMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000)
5675 #define FMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000)
5676 #define FMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000)
5677 #define FMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000)
5678 #define FMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000)
5679 #define FMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000)
5680 #define FMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000)
5681 #define FMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000)
5683 /****************** Bit definition for FMC_PATT4 register ******************/
5684 #define FMC_PATT4_ATTSET4 ((uint32_t)0x000000FF)
5685 #define FMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001)
5686 #define FMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002)
5687 #define FMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004)
5688 #define FMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008)
5689 #define FMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010)
5690 #define FMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020)
5691 #define FMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040)
5692 #define FMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080)
5694 #define FMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00)
5695 #define FMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100)
5696 #define FMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200)
5697 #define FMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400)
5698 #define FMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800)
5699 #define FMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000)
5700 #define FMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000)
5701 #define FMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000)
5702 #define FMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000)
5704 #define FMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000)
5705 #define FMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000)
5706 #define FMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000)
5707 #define FMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000)
5708 #define FMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000)
5709 #define FMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000)
5710 #define FMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000)
5711 #define FMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000)
5712 #define FMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000)
5714 #define FMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000)
5715 #define FMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000)
5716 #define FMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000)
5717 #define FMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000)
5718 #define FMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000)
5719 #define FMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000)
5720 #define FMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000)
5721 #define FMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000)
5722 #define FMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000)
5724 /****************** Bit definition for FMC_PIO4 register *******************/
5725 #define FMC_PIO4_IOSET4 ((uint32_t)0x000000FF)
5726 #define FMC_PIO4_IOSET4_0 ((uint32_t)0x00000001)
5727 #define FMC_PIO4_IOSET4_1 ((uint32_t)0x00000002)
5728 #define FMC_PIO4_IOSET4_2 ((uint32_t)0x00000004)
5729 #define FMC_PIO4_IOSET4_3 ((uint32_t)0x00000008)
5730 #define FMC_PIO4_IOSET4_4 ((uint32_t)0x00000010)
5731 #define FMC_PIO4_IOSET4_5 ((uint32_t)0x00000020)
5732 #define FMC_PIO4_IOSET4_6 ((uint32_t)0x00000040)
5733 #define FMC_PIO4_IOSET4_7 ((uint32_t)0x00000080)
5735 #define FMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00)
5736 #define FMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100)
5737 #define FMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200)
5738 #define FMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400)
5739 #define FMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800)
5740 #define FMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000)
5741 #define FMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000)
5742 #define FMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000)
5743 #define FMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000)
5745 #define FMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000)
5746 #define FMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000)
5747 #define FMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000)
5748 #define FMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000)
5749 #define FMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000)
5750 #define FMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000)
5751 #define FMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000)
5752 #define FMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000)
5753 #define FMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000)
5755 #define FMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000)
5756 #define FMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000)
5757 #define FMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000)
5758 #define FMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000)
5759 #define FMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000)
5760 #define FMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000)
5761 #define FMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000)
5762 #define FMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000)
5763 #define FMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000)
5765 /****************** Bit definition for FMC_ECCR2 register ******************/
5766 #define FMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF)
5768 /****************** Bit definition for FMC_ECCR3 register ******************/
5769 #define FMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF)
5771 /****************** Bit definition for FMC_SDCR1 register ******************/
5772 #define FMC_SDCR1_NC ((uint32_t)0x00000003)
5773 #define FMC_SDCR1_NC_0 ((uint32_t)0x00000001)
5774 #define FMC_SDCR1_NC_1 ((uint32_t)0x00000002)
5776 #define FMC_SDCR1_NR ((uint32_t)0x0000000C)
5777 #define FMC_SDCR1_NR_0 ((uint32_t)0x00000004)
5778 #define FMC_SDCR1_NR_1 ((uint32_t)0x00000008)
5780 #define FMC_SDCR1_MWID ((uint32_t)0x00000030)
5781 #define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010)
5782 #define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020)
5784 #define FMC_SDCR1_NB ((uint32_t)0x00000040)
5786 #define FMC_SDCR1_CAS ((uint32_t)0x00000180)
5787 #define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080)
5788 #define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100)
5790 #define FMC_SDCR1_WP ((uint32_t)0x00000200)
5792 #define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00)
5793 #define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400)
5794 #define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800)
5796 #define FMC_SDCR1_RBURST ((uint32_t)0x00001000)
5798 #define FMC_SDCR1_RPIPE ((uint32_t)0x00006000)
5799 #define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000)
5800 #define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000)
5802 /****************** Bit definition for FMC_SDCR2 register ******************/
5803 #define FMC_SDCR2_NC ((uint32_t)0x00000003)
5804 #define FMC_SDCR2_NC_0 ((uint32_t)0x00000001)
5805 #define FMC_SDCR2_NC_1 ((uint32_t)0x00000002)
5807 #define FMC_SDCR2_NR ((uint32_t)0x0000000C)
5808 #define FMC_SDCR2_NR_0 ((uint32_t)0x00000004)
5809 #define FMC_SDCR2_NR_1 ((uint32_t)0x00000008)
5811 #define FMC_SDCR2_MWID ((uint32_t)0x00000030)
5812 #define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010)
5813 #define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020)
5815 #define FMC_SDCR2_NB ((uint32_t)0x00000040)
5817 #define FMC_SDCR2_CAS ((uint32_t)0x00000180)
5818 #define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080)
5819 #define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100)
5821 #define FMC_SDCR2_WP ((uint32_t)0x00000200)
5823 #define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00)
5824 #define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400)
5825 #define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800)
5827 #define FMC_SDCR2_RBURST ((uint32_t)0x00001000)
5829 #define FMC_SDCR2_RPIPE ((uint32_t)0x00006000)
5830 #define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000)
5831 #define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000)
5833 /****************** Bit definition for FMC_SDTR1 register ******************/
5834 #define FMC_SDTR1_TMRD ((uint32_t)0x0000000F)
5835 #define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001)
5836 #define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002)
5837 #define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004)
5838 #define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008)
5840 #define FMC_SDTR1_TXSR ((uint32_t)0x000000F0)
5841 #define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010)
5842 #define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020)
5843 #define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040)
5844 #define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080)
5846 #define FMC_SDTR1_TRAS ((uint32_t)0x00000F00)
5847 #define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100)
5848 #define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200)
5849 #define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400)
5850 #define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800)
5852 #define FMC_SDTR1_TRC ((uint32_t)0x0000F000)
5853 #define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000)
5854 #define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000)
5855 #define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000)
5857 #define FMC_SDTR1_TWR ((uint32_t)0x000F0000)
5858 #define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000)
5859 #define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000)
5860 #define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000)
5862 #define FMC_SDTR1_TRP ((uint32_t)0x00F00000)
5863 #define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000)
5864 #define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000)
5865 #define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000)
5867 #define FMC_SDTR1_TRCD ((uint32_t)0x0F000000)
5868 #define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000)
5869 #define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000)
5870 #define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000)
5872 /****************** Bit definition for FMC_SDTR2 register ******************/
5873 #define FMC_SDTR2_TMRD ((uint32_t)0x0000000F)
5874 #define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001)
5875 #define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002)
5876 #define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004)
5877 #define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008)
5879 #define FMC_SDTR2_TXSR ((uint32_t)0x000000F0)
5880 #define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010)
5881 #define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020)
5882 #define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040)
5883 #define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080)
5885 #define FMC_SDTR2_TRAS ((uint32_t)0x00000F00)
5886 #define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100)
5887 #define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200)
5888 #define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400)
5889 #define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800)
5891 #define FMC_SDTR2_TRC ((uint32_t)0x0000F000)
5892 #define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000)
5893 #define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000)
5894 #define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000)
5896 #define FMC_SDTR2_TWR ((uint32_t)0x000F0000)
5897 #define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000)
5898 #define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000)
5899 #define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000)
5901 #define FMC_SDTR2_TRP ((uint32_t)0x00F00000)
5902 #define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000)
5903 #define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000)
5904 #define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000)
5906 #define FMC_SDTR2_TRCD ((uint32_t)0x0F000000)
5907 #define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000)
5908 #define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000)
5909 #define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000)
5911 /****************** Bit definition for FMC_SDCMR register ******************/
5912 #define FMC_SDCMR_MODE ((uint32_t)0x00000007)
5913 #define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001)
5914 #define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002)
5915 #define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003)
5917 #define FMC_SDCMR_CTB2 ((uint32_t)0x00000008)
5919 #define FMC_SDCMR_CTB1 ((uint32_t)0x00000010)
5921 #define FMC_SDCMR_NRFS ((uint32_t)0x000001E0)
5922 #define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020)
5923 #define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040)
5924 #define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080)
5925 #define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100)
5927 #define FMC_SDCMR_MRD ((uint32_t)0x003FFE00)
5929 /****************** Bit definition for FMC_SDRTR register ******************/
5930 #define FMC_SDRTR_CRE ((uint32_t)0x00000001)
5932 #define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE)
5934 #define FMC_SDRTR_REIE ((uint32_t)0x00004000)
5936 /****************** Bit definition for FMC_SDSR register ******************/
5937 #define FMC_SDSR_RE ((uint32_t)0x00000001)
5939 #define FMC_SDSR_MODES1 ((uint32_t)0x00000006)
5940 #define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002)
5941 #define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004)
5943 #define FMC_SDSR_MODES2 ((uint32_t)0x00000018)
5944 #define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008)
5945 #define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010)
5947 #define FMC_SDSR_BUSY ((uint32_t)0x00000020)
5949 #endif /* STM32F427_437xx || STM32F429_439xx */
5950 
5951 /******************************************************************************/
5952 /* */
5953 /* General Purpose I/O */
5954 /* */
5955 /******************************************************************************/
5956 /****************** Bits definition for GPIO_MODER register *****************/
5957 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
5958 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
5959 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
5960 
5961 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
5962 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
5963 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
5964 
5965 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
5966 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
5967 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
5968 
5969 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
5970 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
5971 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
5972 
5973 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
5974 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
5975 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
5976 
5977 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
5978 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
5979 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
5980 
5981 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
5982 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
5983 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
5984 
5985 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
5986 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
5987 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
5988 
5989 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
5990 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
5991 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
5992 
5993 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
5994 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
5995 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
5996 
5997 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
5998 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
5999 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
6000 
6001 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
6002 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
6003 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
6004 
6005 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
6006 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
6007 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
6008 
6009 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
6010 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
6011 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
6012 
6013 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
6014 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
6015 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
6016 
6017 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
6018 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
6019 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
6020 
6021 /****************** Bits definition for GPIO_OTYPER register ****************/
6022 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
6023 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
6024 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
6025 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
6026 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
6027 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
6028 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
6029 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
6030 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
6031 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
6032 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
6033 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
6034 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
6035 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
6036 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
6037 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
6038 
6039 /****************** Bits definition for GPIO_OSPEEDR register ***************/
6040 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
6041 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
6042 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
6043 
6044 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
6045 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
6046 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
6047 
6048 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
6049 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
6050 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
6051 
6052 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
6053 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
6054 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
6055 
6056 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
6057 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
6058 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
6059 
6060 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
6061 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
6062 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
6063 
6064 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
6065 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
6066 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
6067 
6068 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
6069 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
6070 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
6071 
6072 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
6073 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
6074 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
6075 
6076 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
6077 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
6078 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
6079 
6080 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
6081 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
6082 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
6083 
6084 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
6085 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
6086 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
6087 
6088 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
6089 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
6090 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
6091 
6092 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
6093 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
6094 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
6095 
6096 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
6097 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
6098 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
6099 
6100 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
6101 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
6102 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
6103 
6104 /****************** Bits definition for GPIO_PUPDR register *****************/
6105 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
6106 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
6107 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
6108 
6109 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
6110 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
6111 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
6112 
6113 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
6114 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
6115 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
6116 
6117 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
6118 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
6119 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
6120 
6121 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
6122 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
6123 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
6124 
6125 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
6126 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
6127 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
6128 
6129 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
6130 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
6131 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
6132 
6133 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
6134 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
6135 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
6136 
6137 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
6138 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
6139 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
6140 
6141 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
6142 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
6143 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
6144 
6145 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
6146 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
6147 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
6148 
6149 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
6150 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
6151 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
6152 
6153 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
6154 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
6155 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
6156 
6157 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
6158 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
6159 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
6160 
6161 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
6162 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
6163 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
6164 
6165 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
6166 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
6167 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
6168 
6169 /****************** Bits definition for GPIO_IDR register *******************/
6170 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
6171 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
6172 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
6173 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
6174 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
6175 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
6176 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
6177 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
6178 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
6179 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
6180 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
6181 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
6182 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
6183 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
6184 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
6185 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
6186 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
6187 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
6188 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
6189 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
6190 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
6191 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
6192 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
6193 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
6194 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
6195 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
6196 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
6197 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
6198 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
6199 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
6200 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
6201 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
6202 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
6203 
6204 /****************** Bits definition for GPIO_ODR register *******************/
6205 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
6206 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
6207 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
6208 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
6209 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
6210 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
6211 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
6212 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
6213 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
6214 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
6215 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
6216 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
6217 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
6218 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
6219 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
6220 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
6221 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
6222 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
6223 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
6224 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
6225 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
6226 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
6227 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
6228 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
6229 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
6230 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
6231 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
6232 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
6233 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
6234 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
6235 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
6236 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
6237 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
6238 
6239 /****************** Bits definition for GPIO_BSRR register ******************/
6240 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
6241 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
6242 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
6243 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
6244 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
6245 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
6246 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
6247 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
6248 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
6249 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
6250 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
6251 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
6252 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
6253 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
6254 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
6255 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
6256 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
6257 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
6258 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
6259 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
6260 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
6261 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
6262 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
6263 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
6264 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
6265 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
6266 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
6267 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
6268 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
6269 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
6270 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
6271 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
6272 
6273 /******************************************************************************/
6274 /* */
6275 /* HASH */
6276 /* */
6277 /******************************************************************************/
6278 /****************** Bits definition for HASH_CR register ********************/
6279 #define HASH_CR_INIT ((uint32_t)0x00000004)
6280 #define HASH_CR_DMAE ((uint32_t)0x00000008)
6281 #define HASH_CR_DATATYPE ((uint32_t)0x00000030)
6282 #define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010)
6283 #define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020)
6284 #define HASH_CR_MODE ((uint32_t)0x00000040)
6285 #define HASH_CR_ALGO ((uint32_t)0x00040080)
6286 #define HASH_CR_ALGO_0 ((uint32_t)0x00000080)
6287 #define HASH_CR_ALGO_1 ((uint32_t)0x00040000)
6288 #define HASH_CR_NBW ((uint32_t)0x00000F00)
6289 #define HASH_CR_NBW_0 ((uint32_t)0x00000100)
6290 #define HASH_CR_NBW_1 ((uint32_t)0x00000200)
6291 #define HASH_CR_NBW_2 ((uint32_t)0x00000400)
6292 #define HASH_CR_NBW_3 ((uint32_t)0x00000800)
6293 #define HASH_CR_DINNE ((uint32_t)0x00001000)
6294 #define HASH_CR_MDMAT ((uint32_t)0x00002000)
6295 #define HASH_CR_LKEY ((uint32_t)0x00010000)
6296 
6297 /****************** Bits definition for HASH_STR register *******************/
6298 #define HASH_STR_NBW ((uint32_t)0x0000001F)
6299 #define HASH_STR_NBW_0 ((uint32_t)0x00000001)
6300 #define HASH_STR_NBW_1 ((uint32_t)0x00000002)
6301 #define HASH_STR_NBW_2 ((uint32_t)0x00000004)
6302 #define HASH_STR_NBW_3 ((uint32_t)0x00000008)
6303 #define HASH_STR_NBW_4 ((uint32_t)0x00000010)
6304 #define HASH_STR_DCAL ((uint32_t)0x00000100)
6305 
6306 /****************** Bits definition for HASH_IMR register *******************/
6307 #define HASH_IMR_DINIM ((uint32_t)0x00000001)
6308 #define HASH_IMR_DCIM ((uint32_t)0x00000002)
6309 
6310 /****************** Bits definition for HASH_SR register ********************/
6311 #define HASH_SR_DINIS ((uint32_t)0x00000001)
6312 #define HASH_SR_DCIS ((uint32_t)0x00000002)
6313 #define HASH_SR_DMAS ((uint32_t)0x00000004)
6314 #define HASH_SR_BUSY ((uint32_t)0x00000008)
6315 
6316 /******************************************************************************/
6317 /* */
6318 /* Inter-integrated Circuit Interface */
6319 /* */
6320 /******************************************************************************/
6321 /******************* Bit definition for I2C_CR1 register ********************/
6322 #define I2C_CR1_PE ((uint16_t)0x0001)
6323 #define I2C_CR1_SMBUS ((uint16_t)0x0002)
6324 #define I2C_CR1_SMBTYPE ((uint16_t)0x0008)
6325 #define I2C_CR1_ENARP ((uint16_t)0x0010)
6326 #define I2C_CR1_ENPEC ((uint16_t)0x0020)
6327 #define I2C_CR1_ENGC ((uint16_t)0x0040)
6328 #define I2C_CR1_NOSTRETCH ((uint16_t)0x0080)
6329 #define I2C_CR1_START ((uint16_t)0x0100)
6330 #define I2C_CR1_STOP ((uint16_t)0x0200)
6331 #define I2C_CR1_ACK ((uint16_t)0x0400)
6332 #define I2C_CR1_POS ((uint16_t)0x0800)
6333 #define I2C_CR1_PEC ((uint16_t)0x1000)
6334 #define I2C_CR1_ALERT ((uint16_t)0x2000)
6335 #define I2C_CR1_SWRST ((uint16_t)0x8000)
6337 /******************* Bit definition for I2C_CR2 register ********************/
6338 #define I2C_CR2_FREQ ((uint16_t)0x003F)
6339 #define I2C_CR2_FREQ_0 ((uint16_t)0x0001)
6340 #define I2C_CR2_FREQ_1 ((uint16_t)0x0002)
6341 #define I2C_CR2_FREQ_2 ((uint16_t)0x0004)
6342 #define I2C_CR2_FREQ_3 ((uint16_t)0x0008)
6343 #define I2C_CR2_FREQ_4 ((uint16_t)0x0010)
6344 #define I2C_CR2_FREQ_5 ((uint16_t)0x0020)
6346 #define I2C_CR2_ITERREN ((uint16_t)0x0100)
6347 #define I2C_CR2_ITEVTEN ((uint16_t)0x0200)
6348 #define I2C_CR2_ITBUFEN ((uint16_t)0x0400)
6349 #define I2C_CR2_DMAEN ((uint16_t)0x0800)
6350 #define I2C_CR2_LAST ((uint16_t)0x1000)
6352 /******************* Bit definition for I2C_OAR1 register *******************/
6353 #define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE)
6354 #define I2C_OAR1_ADD8_9 ((uint16_t)0x0300)
6356 #define I2C_OAR1_ADD0 ((uint16_t)0x0001)
6357 #define I2C_OAR1_ADD1 ((uint16_t)0x0002)
6358 #define I2C_OAR1_ADD2 ((uint16_t)0x0004)
6359 #define I2C_OAR1_ADD3 ((uint16_t)0x0008)
6360 #define I2C_OAR1_ADD4 ((uint16_t)0x0010)
6361 #define I2C_OAR1_ADD5 ((uint16_t)0x0020)
6362 #define I2C_OAR1_ADD6 ((uint16_t)0x0040)
6363 #define I2C_OAR1_ADD7 ((uint16_t)0x0080)
6364 #define I2C_OAR1_ADD8 ((uint16_t)0x0100)
6365 #define I2C_OAR1_ADD9 ((uint16_t)0x0200)
6367 #define I2C_OAR1_ADDMODE ((uint16_t)0x8000)
6369 /******************* Bit definition for I2C_OAR2 register *******************/
6370 #define I2C_OAR2_ENDUAL ((uint8_t)0x01)
6371 #define I2C_OAR2_ADD2 ((uint8_t)0xFE)
6373 /******************** Bit definition for I2C_DR register ********************/
6374 #define I2C_DR_DR ((uint8_t)0xFF)
6376 /******************* Bit definition for I2C_SR1 register ********************/
6377 #define I2C_SR1_SB ((uint16_t)0x0001)
6378 #define I2C_SR1_ADDR ((uint16_t)0x0002)
6379 #define I2C_SR1_BTF ((uint16_t)0x0004)
6380 #define I2C_SR1_ADD10 ((uint16_t)0x0008)
6381 #define I2C_SR1_STOPF ((uint16_t)0x0010)
6382 #define I2C_SR1_RXNE ((uint16_t)0x0040)
6383 #define I2C_SR1_TXE ((uint16_t)0x0080)
6384 #define I2C_SR1_BERR ((uint16_t)0x0100)
6385 #define I2C_SR1_ARLO ((uint16_t)0x0200)
6386 #define I2C_SR1_AF ((uint16_t)0x0400)
6387 #define I2C_SR1_OVR ((uint16_t)0x0800)
6388 #define I2C_SR1_PECERR ((uint16_t)0x1000)
6389 #define I2C_SR1_TIMEOUT ((uint16_t)0x4000)
6390 #define I2C_SR1_SMBALERT ((uint16_t)0x8000)
6392 /******************* Bit definition for I2C_SR2 register ********************/
6393 #define I2C_SR2_MSL ((uint16_t)0x0001)
6394 #define I2C_SR2_BUSY ((uint16_t)0x0002)
6395 #define I2C_SR2_TRA ((uint16_t)0x0004)
6396 #define I2C_SR2_GENCALL ((uint16_t)0x0010)
6397 #define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020)
6398 #define I2C_SR2_SMBHOST ((uint16_t)0x0040)
6399 #define I2C_SR2_DUALF ((uint16_t)0x0080)
6400 #define I2C_SR2_PEC ((uint16_t)0xFF00)
6402 /******************* Bit definition for I2C_CCR register ********************/
6403 #define I2C_CCR_CCR ((uint16_t)0x0FFF)
6404 #define I2C_CCR_DUTY ((uint16_t)0x4000)
6405 #define I2C_CCR_FS ((uint16_t)0x8000)
6407 /****************** Bit definition for I2C_TRISE register *******************/
6408 #define I2C_TRISE_TRISE ((uint8_t)0x3F)
6410 /****************** Bit definition for I2C_FLTR register *******************/
6411 #define I2C_FLTR_DNF ((uint8_t)0x0F)
6412 #define I2C_FLTR_ANOFF ((uint8_t)0x10)
6414 /******************************************************************************/
6415 /* */
6416 /* Independent WATCHDOG */
6417 /* */
6418 /******************************************************************************/
6419 /******************* Bit definition for IWDG_KR register ********************/
6420 #define IWDG_KR_KEY ((uint16_t)0xFFFF)
6422 /******************* Bit definition for IWDG_PR register ********************/
6423 #define IWDG_PR_PR ((uint8_t)0x07)
6424 #define IWDG_PR_PR_0 ((uint8_t)0x01)
6425 #define IWDG_PR_PR_1 ((uint8_t)0x02)
6426 #define IWDG_PR_PR_2 ((uint8_t)0x04)
6428 /******************* Bit definition for IWDG_RLR register *******************/
6429 #define IWDG_RLR_RL ((uint16_t)0x0FFF)
6431 /******************* Bit definition for IWDG_SR register ********************/
6432 #define IWDG_SR_PVU ((uint8_t)0x01)
6433 #define IWDG_SR_RVU ((uint8_t)0x02)
6435 /******************************************************************************/
6436 /* */
6437 /* LCD-TFT Display Controller (LTDC) */
6438 /* */
6439 /******************************************************************************/
6440 
6441 /******************** Bit definition for LTDC_SSCR register *****************/
6442 
6443 #define LTDC_SSCR_VSH ((uint32_t)0x000007FF)
6444 #define LTDC_SSCR_HSW ((uint32_t)0x0FFF0000)
6446 /******************** Bit definition for LTDC_BPCR register *****************/
6447 
6448 #define LTDC_BPCR_AVBP ((uint32_t)0x000007FF)
6449 #define LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000)
6451 /******************** Bit definition for LTDC_AWCR register *****************/
6452 
6453 #define LTDC_AWCR_AAH ((uint32_t)0x000007FF)
6454 #define LTDC_AWCR_AAW ((uint32_t)0x0FFF0000)
6456 /******************** Bit definition for LTDC_TWCR register *****************/
6457 
6458 #define LTDC_TWCR_TOTALH ((uint32_t)0x000007FF)
6459 #define LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000)
6461 /******************** Bit definition for LTDC_GCR register ******************/
6462 
6463 #define LTDC_GCR_LTDCEN ((uint32_t)0x00000001)
6464 #define LTDC_GCR_DBW ((uint32_t)0x00000070)
6465 #define LTDC_GCR_DGW ((uint32_t)0x00000700)
6466 #define LTDC_GCR_DRW ((uint32_t)0x00007000)
6467 #define LTDC_GCR_DTEN ((uint32_t)0x00010000)
6468 #define LTDC_GCR_PCPOL ((uint32_t)0x10000000)
6469 #define LTDC_GCR_DEPOL ((uint32_t)0x20000000)
6470 #define LTDC_GCR_VSPOL ((uint32_t)0x40000000)
6471 #define LTDC_GCR_HSPOL ((uint32_t)0x80000000)
6473 /******************** Bit definition for LTDC_SRCR register *****************/
6474 
6475 #define LTDC_SRCR_IMR ((uint32_t)0x00000001)
6476 #define LTDC_SRCR_VBR ((uint32_t)0x00000002)
6478 /******************** Bit definition for LTDC_BCCR register *****************/
6479 
6480 #define LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF)
6481 #define LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00)
6482 #define LTDC_BCCR_BCRED ((uint32_t)0x00FF0000)
6484 /******************** Bit definition for LTDC_IER register ******************/
6485 
6486 #define LTDC_IER_LIE ((uint32_t)0x00000001)
6487 #define LTDC_IER_FUIE ((uint32_t)0x00000002)
6488 #define LTDC_IER_TERRIE ((uint32_t)0x00000004)
6489 #define LTDC_IER_RRIE ((uint32_t)0x00000008)
6491 /******************** Bit definition for LTDC_ISR register ******************/
6492 
6493 #define LTDC_ISR_LIF ((uint32_t)0x00000001)
6494 #define LTDC_ISR_FUIF ((uint32_t)0x00000002)
6495 #define LTDC_ISR_TERRIF ((uint32_t)0x00000004)
6496 #define LTDC_ISR_RRIF ((uint32_t)0x00000008)
6498 /******************** Bit definition for LTDC_ICR register ******************/
6499 
6500 #define LTDC_ICR_CLIF ((uint32_t)0x00000001)
6501 #define LTDC_ICR_CFUIF ((uint32_t)0x00000002)
6502 #define LTDC_ICR_CTERRIF ((uint32_t)0x00000004)
6503 #define LTDC_ICR_CRRIF ((uint32_t)0x00000008)
6505 /******************** Bit definition for LTDC_LIPCR register ****************/
6506 
6507 #define LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF)
6509 /******************** Bit definition for LTDC_CPSR register *****************/
6510 
6511 #define LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF)
6512 #define LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000)
6514 /******************** Bit definition for LTDC_CDSR register *****************/
6515 
6516 #define LTDC_CDSR_VDES ((uint32_t)0x00000001)
6517 #define LTDC_CDSR_HDES ((uint32_t)0x00000002)
6518 #define LTDC_CDSR_VSYNCS ((uint32_t)0x00000004)
6519 #define LTDC_CDSR_HSYNCS ((uint32_t)0x00000008)
6521 /******************** Bit definition for LTDC_LxCR register *****************/
6522 
6523 #define LTDC_LxCR_LEN ((uint32_t)0x00000001)
6524 #define LTDC_LxCR_COLKEN ((uint32_t)0x00000002)
6525 #define LTDC_LxCR_CLUTEN ((uint32_t)0x00000010)
6527 /******************** Bit definition for LTDC_LxWHPCR register **************/
6528 
6529 #define LTDC_LxWHPCR_WHSTPOS ((uint32_t)0x00000FFF)
6530 #define LTDC_LxWHPCR_WHSPPOS ((uint32_t)0xFFFF0000)
6532 /******************** Bit definition for LTDC_LxWVPCR register **************/
6533 
6534 #define LTDC_LxWVPCR_WVSTPOS ((uint32_t)0x00000FFF)
6535 #define LTDC_LxWVPCR_WVSPPOS ((uint32_t)0xFFFF0000)
6537 /******************** Bit definition for LTDC_LxCKCR register ***************/
6538 
6539 #define LTDC_LxCKCR_CKBLUE ((uint32_t)0x000000FF)
6540 #define LTDC_LxCKCR_CKGREEN ((uint32_t)0x0000FF00)
6541 #define LTDC_LxCKCR_CKRED ((uint32_t)0x00FF0000)
6543 /******************** Bit definition for LTDC_LxPFCR register ***************/
6544 
6545 #define LTDC_LxPFCR_PF ((uint32_t)0x00000007)
6547 /******************** Bit definition for LTDC_LxCACR register ***************/
6548 
6549 #define LTDC_LxCACR_CONSTA ((uint32_t)0x000000FF)
6551 /******************** Bit definition for LTDC_LxDCCR register ***************/
6552 
6553 #define LTDC_LxDCCR_DCBLUE ((uint32_t)0x000000FF)
6554 #define LTDC_LxDCCR_DCGREEN ((uint32_t)0x0000FF00)
6555 #define LTDC_LxDCCR_DCRED ((uint32_t)0x00FF0000)
6556 #define LTDC_LxDCCR_DCALPHA ((uint32_t)0xFF000000)
6558 /******************** Bit definition for LTDC_LxBFCR register ***************/
6559 
6560 #define LTDC_LxBFCR_BF2 ((uint32_t)0x00000007)
6561 #define LTDC_LxBFCR_BF1 ((uint32_t)0x00000700)
6563 /******************** Bit definition for LTDC_LxCFBAR register **************/
6564 
6565 #define LTDC_LxCFBAR_CFBADD ((uint32_t)0xFFFFFFFF)
6567 /******************** Bit definition for LTDC_LxCFBLR register **************/
6568 
6569 #define LTDC_LxCFBLR_CFBLL ((uint32_t)0x00001FFF)
6570 #define LTDC_LxCFBLR_CFBP ((uint32_t)0x1FFF0000)
6572 /******************** Bit definition for LTDC_LxCFBLNR register *************/
6573 
6574 #define LTDC_LxCFBLNR_CFBLNBR ((uint32_t)0x000007FF)
6576 /******************** Bit definition for LTDC_LxCLUTWR register *************/
6577 
6578 #define LTDC_LxCLUTWR_BLUE ((uint32_t)0x000000FF)
6579 #define LTDC_LxCLUTWR_GREEN ((uint32_t)0x0000FF00)
6580 #define LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000)
6581 #define LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000)
6583 /******************************************************************************/
6584 /* */
6585 /* Power Control */
6586 /* */
6587 /******************************************************************************/
6588 /******************** Bit definition for PWR_CR register ********************/
6589 #define PWR_CR_LPDS ((uint32_t)0x00000001)
6590 #define PWR_CR_PDDS ((uint32_t)0x00000002)
6591 #define PWR_CR_CWUF ((uint32_t)0x00000004)
6592 #define PWR_CR_CSBF ((uint32_t)0x00000008)
6593 #define PWR_CR_PVDE ((uint32_t)0x00000010)
6595 #define PWR_CR_PLS ((uint32_t)0x000000E0)
6596 #define PWR_CR_PLS_0 ((uint32_t)0x00000020)
6597 #define PWR_CR_PLS_1 ((uint32_t)0x00000040)
6598 #define PWR_CR_PLS_2 ((uint32_t)0x00000080)
6601 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000)
6602 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020)
6603 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040)
6604 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060)
6605 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080)
6606 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0)
6607 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0)
6608 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0)
6610 #define PWR_CR_DBP ((uint32_t)0x00000100)
6611 #define PWR_CR_FPDS ((uint32_t)0x00000200)
6612 #define PWR_CR_LPUDS ((uint32_t)0x00000400)
6613 #define PWR_CR_MRUDS ((uint32_t)0x00000800)
6614 #define PWR_CR_LPLVDS ((uint32_t)0x00000400)
6615 #define PWR_CR_MRLVDS ((uint32_t)0x00000800)
6617 #define PWR_CR_ADCDC1 ((uint32_t)0x00002000)
6619 #define PWR_CR_VOS ((uint32_t)0x0000C000)
6620 #define PWR_CR_VOS_0 ((uint32_t)0x00004000)
6621 #define PWR_CR_VOS_1 ((uint32_t)0x00008000)
6623 #define PWR_CR_ODEN ((uint32_t)0x00010000)
6624 #define PWR_CR_ODSWEN ((uint32_t)0x00020000)
6625 #define PWR_CR_UDEN ((uint32_t)0x000C0000)
6626 #define PWR_CR_UDEN_0 ((uint32_t)0x00040000)
6627 #define PWR_CR_UDEN_1 ((uint32_t)0x00080000)
6629 #define PWR_CR_FMSSR ((uint32_t)0x00100000)
6630 #define PWR_CR_FISSR ((uint32_t)0x00200000)
6632 /* Legacy define */
6633 #define PWR_CR_PMODE PWR_CR_VOS
6634 
6635 /******************* Bit definition for PWR_CSR register ********************/
6636 #define PWR_CSR_WUF ((uint32_t)0x00000001)
6637 #define PWR_CSR_SBF ((uint32_t)0x00000002)
6638 #define PWR_CSR_PVDO ((uint32_t)0x00000004)
6639 #define PWR_CSR_BRR ((uint32_t)0x00000008)
6640 #define PWR_CSR_EWUP ((uint32_t)0x00000100)
6641 #define PWR_CSR_BRE ((uint32_t)0x00000200)
6642 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000)
6643 #define PWR_CSR_ODRDY ((uint32_t)0x00010000)
6644 #define PWR_CSR_ODSWRDY ((uint32_t)0x00020000)
6645 #define PWR_CSR_UDSWRDY ((uint32_t)0x000C0000)
6647 /* Legacy define */
6648 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
6649 
6650 /******************************************************************************/
6651 /* */
6652 /* Reset and Clock Control */
6653 /* */
6654 /******************************************************************************/
6655 /******************** Bit definition for RCC_CR register ********************/
6656 #define RCC_CR_HSION ((uint32_t)0x00000001)
6657 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
6658 
6659 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
6660 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)
6661 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)
6662 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)
6663 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)
6664 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)
6666 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
6667 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)
6668 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)
6669 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)
6670 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)
6671 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)
6672 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)
6673 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)
6674 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)
6676 #define RCC_CR_HSEON ((uint32_t)0x00010000)
6677 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
6678 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
6679 #define RCC_CR_CSSON ((uint32_t)0x00080000)
6680 #define RCC_CR_PLLON ((uint32_t)0x01000000)
6681 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
6682 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
6683 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
6684 #define RCC_CR_PLLSAION ((uint32_t)0x10000000)
6685 #define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)
6686 
6687 /******************** Bit definition for RCC_PLLCFGR register ***************/
6688 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
6689 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
6690 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
6691 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
6692 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
6693 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
6694 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
6695 
6696 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
6697 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
6698 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
6699 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
6700 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
6701 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
6702 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
6703 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
6704 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
6705 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
6706 
6707 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
6708 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
6709 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
6710 
6711 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
6712 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
6713 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
6714 
6715 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
6716 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
6717 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
6718 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
6719 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
6720 
6721 /******************** Bit definition for RCC_CFGR register ******************/
6723 #define RCC_CFGR_SW ((uint32_t)0x00000003)
6724 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001)
6725 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002)
6727 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000)
6728 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001)
6729 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002)
6732 #define RCC_CFGR_SWS ((uint32_t)0x0000000C)
6733 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004)
6734 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008)
6736 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000)
6737 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004)
6738 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008)
6741 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0)
6742 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010)
6743 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020)
6744 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040)
6745 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080)
6747 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000)
6748 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080)
6749 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090)
6750 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0)
6751 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0)
6752 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0)
6753 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0)
6754 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0)
6755 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0)
6758 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00)
6759 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400)
6760 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800)
6761 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000)
6763 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000)
6764 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000)
6765 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400)
6766 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800)
6767 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00)
6770 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000)
6771 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000)
6772 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000)
6773 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000)
6775 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000)
6776 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000)
6777 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000)
6778 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000)
6779 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000)
6782 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
6783 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
6784 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
6785 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
6786 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
6787 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
6788 
6790 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
6791 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
6792 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
6793 
6794 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
6795 
6796 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
6797 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
6798 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
6799 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
6800 
6801 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
6802 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
6803 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
6804 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
6805 
6806 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
6807 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
6808 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
6809 
6810 /******************** Bit definition for RCC_CIR register *******************/
6811 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
6812 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
6813 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
6814 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
6815 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
6816 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
6817 #define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)
6818 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
6819 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
6820 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
6821 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
6822 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
6823 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
6824 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
6825 #define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)
6826 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
6827 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
6828 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
6829 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
6830 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
6831 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
6832 #define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)
6833 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
6834 
6835 /******************** Bit definition for RCC_AHB1RSTR register **************/
6836 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
6837 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
6838 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
6839 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
6840 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
6841 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
6842 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
6843 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
6844 #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
6845 #define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)
6846 #define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)
6847 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
6848 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
6849 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
6850 #define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
6851 #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
6852 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
6853 
6854 /******************** Bit definition for RCC_AHB2RSTR register **************/
6855 #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
6856 #define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)
6857 #define RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020)
6858  /* maintained for legacy purpose */
6859  #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
6860 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
6861 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
6862 
6863 /******************** Bit definition for RCC_AHB3RSTR register **************/
6864 #if defined(STM32F40_41xxx)
6865 #define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)
6866 #endif /* STM32F40_41xxx */
6867 
6868 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
6869 #define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
6870 #endif /* STM32F427_437xx || STM32F429_439xx */
6871 /******************** Bit definition for RCC_APB1RSTR register **************/
6872 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
6873 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
6874 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
6875 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
6876 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
6877 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
6878 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
6879 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
6880 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
6881 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
6882 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
6883 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
6884 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
6885 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
6886 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
6887 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
6888 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
6889 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
6890 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
6891 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
6892 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
6893 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
6894 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
6895 #define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)
6896 #define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)
6897 
6898 /******************** Bit definition for RCC_APB2RSTR register **************/
6899 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
6900 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
6901 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
6902 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
6903 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
6904 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
6905 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
6906 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
6907 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
6908 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
6909 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
6910 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
6911 #define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
6912 #define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
6913 #define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)
6914 #define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000)
6915 
6916 /* Old SPI1RST bit definition, maintained for legacy purpose */
6917 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
6918 
6919 /******************** Bit definition for RCC_AHB1ENR register ***************/
6920 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
6921 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
6922 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
6923 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
6924 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
6925 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
6926 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
6927 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
6928 #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
6929 #define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)
6930 #define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)
6931 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
6932 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
6933 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
6934 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
6935 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
6936 #define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)
6937 #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
6938 #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
6939 #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
6940 #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
6941 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
6942 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
6943 
6944 /******************** Bit definition for RCC_AHB2ENR register ***************/
6945 #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
6946 #define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)
6947 #define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)
6948 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
6949 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
6950 
6951 /******************** Bit definition for RCC_AHB3ENR register ***************/
6952 
6953 #if defined(STM32F40_41xxx)
6954 #define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)
6955 #endif /* STM32F40_41xxx */
6956 
6957 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
6958 #define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
6959 #endif /* STM32F427_437xx || STM32F429_439xx */
6960 
6961 /******************** Bit definition for RCC_APB1ENR register ***************/
6962 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
6963 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
6964 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
6965 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
6966 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
6967 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
6968 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
6969 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
6970 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
6971 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
6972 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
6973 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
6974 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
6975 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
6976 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
6977 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
6978 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
6979 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
6980 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
6981 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
6982 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
6983 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
6984 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
6985 #define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)
6986 #define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)
6987 
6988 /******************** Bit definition for RCC_APB2ENR register ***************/
6989 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
6990 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
6991 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
6992 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
6993 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
6994 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
6995 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
6996 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
6997 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
6998 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
6999 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
7000 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
7001 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
7002 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
7003 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
7004 #define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
7005 #define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)
7006 #define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)
7007 
7008 /******************** Bit definition for RCC_AHB1LPENR register *************/
7009 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
7010 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
7011 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
7012 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
7013 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
7014 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
7015 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
7016 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
7017 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
7018 #define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)
7019 #define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)
7020 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
7021 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
7022 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
7023 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
7024 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
7025 #define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
7026 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
7027 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
7028 #define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)
7029 #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
7030 #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
7031 #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
7032 #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
7033 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
7034 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
7035 
7036 /******************** Bit definition for RCC_AHB2LPENR register *************/
7037 #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
7038 #define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)
7039 #define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)
7040 #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
7041 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
7042 
7043 /******************** Bit definition for RCC_AHB3LPENR register *************/
7044 #if defined(STM32F40_41xxx)
7045 #define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)
7046 #endif /* STM32F40_41xxx */
7047 
7048 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
7049 #define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)
7050 #endif /* STM32F427_437xx || STM32F429_439xx */
7051 
7052 /******************** Bit definition for RCC_APB1LPENR register *************/
7053 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
7054 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
7055 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
7056 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
7057 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
7058 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
7059 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
7060 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
7061 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
7062 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
7063 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
7064 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
7065 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
7066 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
7067 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
7068 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
7069 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
7070 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
7071 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
7072 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
7073 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
7074 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
7075 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
7076 #define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)
7077 #define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)
7078 
7079 /******************** Bit definition for RCC_APB2LPENR register *************/
7080 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
7081 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
7082 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
7083 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
7084 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
7085 #define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200)
7086 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
7087 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
7088 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
7089 #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
7090 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
7091 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
7092 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
7093 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
7094 #define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
7095 #define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)
7096 #define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)
7097 #define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)
7098 
7099 /******************** Bit definition for RCC_BDCR register ******************/
7100 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
7101 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
7102 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
7103 #define RCC_BDCR_LSEMOD ((uint32_t)0x00000008)
7104 
7105 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
7106 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
7107 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
7108 
7109 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
7110 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
7111 
7112 /******************** Bit definition for RCC_CSR register *******************/
7113 #define RCC_CSR_LSION ((uint32_t)0x00000001)
7114 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
7115 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
7116 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
7117 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
7118 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
7119 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
7120 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
7121 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
7122 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
7123 
7124 /******************** Bit definition for RCC_SSCGR register *****************/
7125 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
7126 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
7127 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
7128 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
7129 
7130 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
7131 #define RCC_PLLI2SCFGR_PLLI2SM ((uint32_t)0x0000003F)
7132 #define RCC_PLLI2SCFGR_PLLI2SM_0 ((uint32_t)0x00000001)
7133 #define RCC_PLLI2SCFGR_PLLI2SM_1 ((uint32_t)0x00000002)
7134 #define RCC_PLLI2SCFGR_PLLI2SM_2 ((uint32_t)0x00000004)
7135 #define RCC_PLLI2SCFGR_PLLI2SM_3 ((uint32_t)0x00000008)
7136 #define RCC_PLLI2SCFGR_PLLI2SM_4 ((uint32_t)0x00000010)
7137 #define RCC_PLLI2SCFGR_PLLI2SM_5 ((uint32_t)0x00000020)
7138 
7139 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
7140 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
7141 #define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)
7142 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
7143 
7144 /******************** Bit definition for RCC_PLLSAICFGR register ************/
7145 #define RCC_PLLSAICFGR_PLLI2SN ((uint32_t)0x00007FC0)
7146 #define RCC_PLLSAICFGR_PLLI2SQ ((uint32_t)0x0F000000)
7147 #define RCC_PLLSAICFGR_PLLI2SR ((uint32_t)0x70000000)
7148 
7149 /******************** Bit definition for RCC_DCKCFGR register ***************/
7150 #define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F)
7151 #define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)
7152 #define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)
7153 #define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)
7154 #define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)
7155 #define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
7156 
7157 
7158 /******************************************************************************/
7159 /* */
7160 /* RNG */
7161 /* */
7162 /******************************************************************************/
7163 /******************** Bits definition for RNG_CR register *******************/
7164 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
7165 #define RNG_CR_IE ((uint32_t)0x00000008)
7166 
7167 /******************** Bits definition for RNG_SR register *******************/
7168 #define RNG_SR_DRDY ((uint32_t)0x00000001)
7169 #define RNG_SR_CECS ((uint32_t)0x00000002)
7170 #define RNG_SR_SECS ((uint32_t)0x00000004)
7171 #define RNG_SR_CEIS ((uint32_t)0x00000020)
7172 #define RNG_SR_SEIS ((uint32_t)0x00000040)
7173 
7174 /******************************************************************************/
7175 /* */
7176 /* Real-Time Clock (RTC) */
7177 /* */
7178 /******************************************************************************/
7179 /******************** Bits definition for RTC_TR register *******************/
7180 #define RTC_TR_PM ((uint32_t)0x00400000)
7181 #define RTC_TR_HT ((uint32_t)0x00300000)
7182 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
7183 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
7184 #define RTC_TR_HU ((uint32_t)0x000F0000)
7185 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
7186 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
7187 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
7188 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
7189 #define RTC_TR_MNT ((uint32_t)0x00007000)
7190 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
7191 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
7192 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
7193 #define RTC_TR_MNU ((uint32_t)0x00000F00)
7194 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
7195 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
7196 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
7197 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
7198 #define RTC_TR_ST ((uint32_t)0x00000070)
7199 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
7200 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
7201 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
7202 #define RTC_TR_SU ((uint32_t)0x0000000F)
7203 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
7204 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
7205 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
7206 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
7207 
7208 /******************** Bits definition for RTC_DR register *******************/
7209 #define RTC_DR_YT ((uint32_t)0x00F00000)
7210 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
7211 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
7212 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
7213 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
7214 #define RTC_DR_YU ((uint32_t)0x000F0000)
7215 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
7216 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
7217 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
7218 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
7219 #define RTC_DR_WDU ((uint32_t)0x0000E000)
7220 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
7221 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
7222 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
7223 #define RTC_DR_MT ((uint32_t)0x00001000)
7224 #define RTC_DR_MU ((uint32_t)0x00000F00)
7225 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
7226 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
7227 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
7228 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
7229 #define RTC_DR_DT ((uint32_t)0x00000030)
7230 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
7231 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
7232 #define RTC_DR_DU ((uint32_t)0x0000000F)
7233 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
7234 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
7235 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
7236 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
7237 
7238 /******************** Bits definition for RTC_CR register *******************/
7239 #define RTC_CR_COE ((uint32_t)0x00800000)
7240 #define RTC_CR_OSEL ((uint32_t)0x00600000)
7241 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
7242 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
7243 #define RTC_CR_POL ((uint32_t)0x00100000)
7244 #define RTC_CR_COSEL ((uint32_t)0x00080000)
7245 #define RTC_CR_BCK ((uint32_t)0x00040000)
7246 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
7247 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
7248 #define RTC_CR_TSIE ((uint32_t)0x00008000)
7249 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
7250 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
7251 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
7252 #define RTC_CR_TSE ((uint32_t)0x00000800)
7253 #define RTC_CR_WUTE ((uint32_t)0x00000400)
7254 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
7255 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
7256 #define RTC_CR_DCE ((uint32_t)0x00000080)
7257 #define RTC_CR_FMT ((uint32_t)0x00000040)
7258 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
7259 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
7260 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
7261 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
7262 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
7263 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
7264 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
7265 
7266 /******************** Bits definition for RTC_ISR register ******************/
7267 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
7268 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
7269 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
7270 #define RTC_ISR_TSF ((uint32_t)0x00000800)
7271 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
7272 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
7273 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
7274 #define RTC_ISR_INIT ((uint32_t)0x00000080)
7275 #define RTC_ISR_INITF ((uint32_t)0x00000040)
7276 #define RTC_ISR_RSF ((uint32_t)0x00000020)
7277 #define RTC_ISR_INITS ((uint32_t)0x00000010)
7278 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
7279 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
7280 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
7281 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
7282 
7283 /******************** Bits definition for RTC_PRER register *****************/
7284 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
7285 #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
7286 
7287 /******************** Bits definition for RTC_WUTR register *****************/
7288 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
7289 
7290 /******************** Bits definition for RTC_CALIBR register ***************/
7291 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
7292 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
7293 
7294 /******************** Bits definition for RTC_ALRMAR register ***************/
7295 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
7296 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
7297 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
7298 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
7299 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
7300 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
7301 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
7302 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
7303 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
7304 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
7305 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
7306 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
7307 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
7308 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
7309 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
7310 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
7311 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
7312 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
7313 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
7314 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
7315 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
7316 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
7317 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
7318 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
7319 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
7320 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
7321 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
7322 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
7323 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
7324 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
7325 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
7326 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
7327 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
7328 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
7329 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
7330 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
7331 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
7332 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
7333 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
7334 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
7335 
7336 /******************** Bits definition for RTC_ALRMBR register ***************/
7337 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
7338 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
7339 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
7340 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
7341 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
7342 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
7343 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
7344 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
7345 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
7346 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
7347 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
7348 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
7349 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
7350 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
7351 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
7352 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
7353 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
7354 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
7355 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
7356 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
7357 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
7358 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
7359 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
7360 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
7361 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
7362 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
7363 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
7364 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
7365 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
7366 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
7367 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
7368 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
7369 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
7370 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
7371 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
7372 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
7373 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
7374 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
7375 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
7376 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
7377 
7378 /******************** Bits definition for RTC_WPR register ******************/
7379 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
7380 
7381 /******************** Bits definition for RTC_SSR register ******************/
7382 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
7383 
7384 /******************** Bits definition for RTC_SHIFTR register ***************/
7385 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
7386 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
7387 
7388 /******************** Bits definition for RTC_TSTR register *****************/
7389 #define RTC_TSTR_PM ((uint32_t)0x00400000)
7390 #define RTC_TSTR_HT ((uint32_t)0x00300000)
7391 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
7392 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
7393 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
7394 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
7395 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
7396 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
7397 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
7398 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
7399 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
7400 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
7401 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
7402 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
7403 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
7404 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
7405 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
7406 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
7407 #define RTC_TSTR_ST ((uint32_t)0x00000070)
7408 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
7409 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
7410 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
7411 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
7412 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
7413 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
7414 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
7415 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
7416 
7417 /******************** Bits definition for RTC_TSDR register *****************/
7418 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
7419 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
7420 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
7421 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
7422 #define RTC_TSDR_MT ((uint32_t)0x00001000)
7423 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
7424 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
7425 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
7426 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
7427 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
7428 #define RTC_TSDR_DT ((uint32_t)0x00000030)
7429 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
7430 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
7431 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
7432 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
7433 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
7434 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
7435 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
7436 
7437 /******************** Bits definition for RTC_TSSSR register ****************/
7438 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
7439 
7440 /******************** Bits definition for RTC_CAL register *****************/
7441 #define RTC_CALR_CALP ((uint32_t)0x00008000)
7442 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
7443 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
7444 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
7445 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
7446 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
7447 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
7448 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
7449 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
7450 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
7451 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
7452 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
7453 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
7454 
7455 /******************** Bits definition for RTC_TAFCR register ****************/
7456 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
7457 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
7458 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
7459 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
7460 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
7461 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
7462 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
7463 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
7464 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
7465 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
7466 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
7467 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
7468 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
7469 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
7470 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
7471 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
7472 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
7473 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
7474 
7475 /******************** Bits definition for RTC_ALRMASSR register *************/
7476 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
7477 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
7478 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
7479 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
7480 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
7481 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
7482 
7483 /******************** Bits definition for RTC_ALRMBSSR register *************/
7484 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
7485 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
7486 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
7487 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
7488 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
7489 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
7490 
7491 /******************** Bits definition for RTC_BKP0R register ****************/
7492 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
7493 
7494 /******************** Bits definition for RTC_BKP1R register ****************/
7495 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
7496 
7497 /******************** Bits definition for RTC_BKP2R register ****************/
7498 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
7499 
7500 /******************** Bits definition for RTC_BKP3R register ****************/
7501 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
7502 
7503 /******************** Bits definition for RTC_BKP4R register ****************/
7504 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
7505 
7506 /******************** Bits definition for RTC_BKP5R register ****************/
7507 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
7508 
7509 /******************** Bits definition for RTC_BKP6R register ****************/
7510 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
7511 
7512 /******************** Bits definition for RTC_BKP7R register ****************/
7513 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
7514 
7515 /******************** Bits definition for RTC_BKP8R register ****************/
7516 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
7517 
7518 /******************** Bits definition for RTC_BKP9R register ****************/
7519 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
7520 
7521 /******************** Bits definition for RTC_BKP10R register ***************/
7522 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
7523 
7524 /******************** Bits definition for RTC_BKP11R register ***************/
7525 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
7526 
7527 /******************** Bits definition for RTC_BKP12R register ***************/
7528 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
7529 
7530 /******************** Bits definition for RTC_BKP13R register ***************/
7531 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
7532 
7533 /******************** Bits definition for RTC_BKP14R register ***************/
7534 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
7535 
7536 /******************** Bits definition for RTC_BKP15R register ***************/
7537 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
7538 
7539 /******************** Bits definition for RTC_BKP16R register ***************/
7540 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
7541 
7542 /******************** Bits definition for RTC_BKP17R register ***************/
7543 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
7544 
7545 /******************** Bits definition for RTC_BKP18R register ***************/
7546 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
7547 
7548 /******************** Bits definition for RTC_BKP19R register ***************/
7549 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
7550 
7551 /******************************************************************************/
7552 /* */
7553 /* Serial Audio Interface */
7554 /* */
7555 /******************************************************************************/
7556 /******************** Bit definition for SAI_GCR register *******************/
7557 #define SAI_GCR_SYNCIN ((uint32_t)0x00000003)
7558 #define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001)
7559 #define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002)
7561 #define SAI_GCR_SYNCOUT ((uint32_t)0x00000030)
7562 #define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010)
7563 #define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020)
7565 /******************* Bit definition for SAI_xCR1 register *******************/
7566 #define SAI_xCR1_MODE ((uint32_t)0x00000003)
7567 #define SAI_xCR1_MODE_0 ((uint32_t)0x00000001)
7568 #define SAI_xCR1_MODE_1 ((uint32_t)0x00000002)
7570 #define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C)
7571 #define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004)
7572 #define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008)
7574 #define SAI_xCR1_DS ((uint32_t)0x000000E0)
7575 #define SAI_xCR1_DS_0 ((uint32_t)0x00000020)
7576 #define SAI_xCR1_DS_1 ((uint32_t)0x00000040)
7577 #define SAI_xCR1_DS_2 ((uint32_t)0x00000080)
7579 #define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100)
7580 #define SAI_xCR1_CKSTR ((uint32_t)0x00000200)
7582 #define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00)
7583 #define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400)
7584 #define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800)
7586 #define SAI_xCR1_MONO ((uint32_t)0x00001000)
7587 #define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000)
7588 #define SAI_xCR1_SAIEN ((uint32_t)0x00010000)
7589 #define SAI_xCR1_DMAEN ((uint32_t)0x00020000)
7590 #define SAI_xCR1_NODIV ((uint32_t)0x00080000)
7592 #define SAI_xCR1_MCKDIV ((uint32_t)0x00780000)
7593 #define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00080000)
7594 #define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00100000)
7595 #define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00200000)
7596 #define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00400000)
7598 /******************* Bit definition for SAI_xCR2 register *******************/
7599 #define SAI_xCR2_FTH ((uint32_t)0x00000003)
7600 #define SAI_xCR2_FTH_0 ((uint32_t)0x00000001)
7601 #define SAI_xCR2_FTH_1 ((uint32_t)0x00000002)
7603 #define SAI_xCR2_FFLUSH ((uint32_t)0x00000008)
7604 #define SAI_xCR2_TRIS ((uint32_t)0x00000010)
7605 #define SAI_xCR2_MUTE ((uint32_t)0x00000020)
7606 #define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040)
7608 #define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80)
7609 #define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080)
7610 #define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100)
7611 #define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200)
7612 #define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400)
7613 #define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800)
7614 #define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000)
7616 #define SAI_xCR2_CPL ((uint32_t)0x00080000)
7618 #define SAI_xCR2_COMP ((uint32_t)0x0000C000)
7619 #define SAI_xCR2_COMP_0 ((uint32_t)0x00004000)
7620 #define SAI_xCR2_COMP_1 ((uint32_t)0x00008000)
7622 /****************** Bit definition for SAI_xFRCR register *******************/
7623 #define SAI_xFRCR_FRL ((uint32_t)0x000000FF)
7624 #define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001)
7625 #define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002)
7626 #define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004)
7627 #define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008)
7628 #define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010)
7629 #define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020)
7630 #define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040)
7631 #define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080)
7633 #define SAI_xFRCR_FSALL ((uint32_t)0x00007F00)
7634 #define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100)
7635 #define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200)
7636 #define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400)
7637 #define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800)
7638 #define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000)
7639 #define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000)
7640 #define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000)
7642 #define SAI_xFRCR_FSDEF ((uint32_t)0x00010000)
7643 #define SAI_xFRCR_FSPO ((uint32_t)0x00020000)
7644 #define SAI_xFRCR_FSOFF ((uint32_t)0x00040000)
7646 /****************** Bit definition for SAI_xSLOTR register *******************/
7647 #define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F)
7648 #define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001)
7649 #define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002)
7650 #define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004)
7651 #define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008)
7652 #define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010)
7654 #define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0)
7655 #define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040)
7656 #define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080)
7658 #define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00)
7659 #define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100)
7660 #define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200)
7661 #define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400)
7662 #define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800)
7664 #define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000)
7666 /******************* Bit definition for SAI_xIMR register *******************/
7667 #define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001)
7668 #define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002)
7669 #define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004)
7670 #define SAI_xIMR_FREQIE ((uint32_t)0x00000008)
7671 #define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010)
7672 #define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020)
7673 #define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040)
7675 /******************** Bit definition for SAI_xSR register *******************/
7676 #define SAI_xSR_OVRUDR ((uint32_t)0x00000001)
7677 #define SAI_xSR_MUTEDET ((uint32_t)0x00000002)
7678 #define SAI_xSR_WCKCFG ((uint32_t)0x00000004)
7679 #define SAI_xSR_FREQ ((uint32_t)0x00000008)
7680 #define SAI_xSR_CNRDY ((uint32_t)0x00000010)
7681 #define SAI_xSR_AFSDET ((uint32_t)0x00000020)
7682 #define SAI_xSR_LFSDET ((uint32_t)0x00000040)
7684 #define SAI_xSR_FLVL ((uint32_t)0x00070000)
7685 #define SAI_xSR_FLVL_0 ((uint32_t)0x00010000)
7686 #define SAI_xSR_FLVL_1 ((uint32_t)0x00020000)
7687 #define SAI_xSR_FLVL_2 ((uint32_t)0x00030000)
7689 /****************** Bit definition for SAI_xCLRFR register ******************/
7690 #define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001)
7691 #define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002)
7692 #define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004)
7693 #define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008)
7694 #define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010)
7695 #define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020)
7696 #define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040)
7698 /****************** Bit definition for SAI_xDR register ******************/
7699 #define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF)
7700 
7701 /******************************************************************************/
7702 /* */
7703 /* SD host Interface */
7704 /* */
7705 /******************************************************************************/
7706 /****************** Bit definition for SDIO_POWER register ******************/
7707 #define SDIO_POWER_PWRCTRL ((uint8_t)0x03)
7708 #define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01)
7709 #define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02)
7711 /****************** Bit definition for SDIO_CLKCR register ******************/
7712 #define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF)
7713 #define SDIO_CLKCR_CLKEN ((uint16_t)0x0100)
7714 #define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200)
7715 #define SDIO_CLKCR_BYPASS ((uint16_t)0x0400)
7717 #define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800)
7718 #define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800)
7719 #define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000)
7721 #define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000)
7722 #define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000)
7724 /******************* Bit definition for SDIO_ARG register *******************/
7725 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF)
7727 /******************* Bit definition for SDIO_CMD register *******************/
7728 #define SDIO_CMD_CMDINDEX ((uint16_t)0x003F)
7730 #define SDIO_CMD_WAITRESP ((uint16_t)0x00C0)
7731 #define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040)
7732 #define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080)
7734 #define SDIO_CMD_WAITINT ((uint16_t)0x0100)
7735 #define SDIO_CMD_WAITPEND ((uint16_t)0x0200)
7736 #define SDIO_CMD_CPSMEN ((uint16_t)0x0400)
7737 #define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800)
7738 #define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000)
7739 #define SDIO_CMD_NIEN ((uint16_t)0x2000)
7740 #define SDIO_CMD_CEATACMD ((uint16_t)0x4000)
7742 /***************** Bit definition for SDIO_RESPCMD register *****************/
7743 #define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F)
7745 /****************** Bit definition for SDIO_RESP0 register ******************/
7746 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF)
7748 /****************** Bit definition for SDIO_RESP1 register ******************/
7749 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF)
7751 /****************** Bit definition for SDIO_RESP2 register ******************/
7752 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF)
7754 /****************** Bit definition for SDIO_RESP3 register ******************/
7755 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF)
7757 /****************** Bit definition for SDIO_RESP4 register ******************/
7758 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF)
7760 /****************** Bit definition for SDIO_DTIMER register *****************/
7761 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF)
7763 /****************** Bit definition for SDIO_DLEN register *******************/
7764 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF)
7766 /****************** Bit definition for SDIO_DCTRL register ******************/
7767 #define SDIO_DCTRL_DTEN ((uint16_t)0x0001)
7768 #define SDIO_DCTRL_DTDIR ((uint16_t)0x0002)
7769 #define SDIO_DCTRL_DTMODE ((uint16_t)0x0004)
7770 #define SDIO_DCTRL_DMAEN ((uint16_t)0x0008)
7772 #define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0)
7773 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010)
7774 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020)
7775 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040)
7776 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080)
7778 #define SDIO_DCTRL_RWSTART ((uint16_t)0x0100)
7779 #define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200)
7780 #define SDIO_DCTRL_RWMOD ((uint16_t)0x0400)
7781 #define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800)
7783 /****************** Bit definition for SDIO_DCOUNT register *****************/
7784 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF)
7786 /****************** Bit definition for SDIO_STA register ********************/
7787 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001)
7788 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002)
7789 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004)
7790 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008)
7791 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010)
7792 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020)
7793 #define SDIO_STA_CMDREND ((uint32_t)0x00000040)
7794 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080)
7795 #define SDIO_STA_DATAEND ((uint32_t)0x00000100)
7796 #define SDIO_STA_STBITERR ((uint32_t)0x00000200)
7797 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400)
7798 #define SDIO_STA_CMDACT ((uint32_t)0x00000800)
7799 #define SDIO_STA_TXACT ((uint32_t)0x00001000)
7800 #define SDIO_STA_RXACT ((uint32_t)0x00002000)
7801 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000)
7802 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000)
7803 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000)
7804 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000)
7805 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000)
7806 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000)
7807 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000)
7808 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000)
7809 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000)
7810 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000)
7812 /******************* Bit definition for SDIO_ICR register *******************/
7813 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001)
7814 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002)
7815 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004)
7816 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008)
7817 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010)
7818 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020)
7819 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040)
7820 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080)
7821 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100)
7822 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200)
7823 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400)
7824 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000)
7825 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000)
7827 /****************** Bit definition for SDIO_MASK register *******************/
7828 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001)
7829 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002)
7830 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004)
7831 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008)
7832 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010)
7833 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020)
7834 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040)
7835 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080)
7836 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100)
7837 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200)
7838 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400)
7839 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800)
7840 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000)
7841 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000)
7842 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000)
7843 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000)
7844 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000)
7845 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000)
7846 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000)
7847 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000)
7848 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000)
7849 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000)
7850 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000)
7851 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000)
7853 /***************** Bit definition for SDIO_FIFOCNT register *****************/
7854 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF)
7856 /****************** Bit definition for SDIO_FIFO register *******************/
7857 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF)
7859 /******************************************************************************/
7860 /* */
7861 /* Serial Peripheral Interface */
7862 /* */
7863 /******************************************************************************/
7864 /******************* Bit definition for SPI_CR1 register ********************/
7865 #define SPI_CR1_CPHA ((uint16_t)0x0001)
7866 #define SPI_CR1_CPOL ((uint16_t)0x0002)
7867 #define SPI_CR1_MSTR ((uint16_t)0x0004)
7869 #define SPI_CR1_BR ((uint16_t)0x0038)
7870 #define SPI_CR1_BR_0 ((uint16_t)0x0008)
7871 #define SPI_CR1_BR_1 ((uint16_t)0x0010)
7872 #define SPI_CR1_BR_2 ((uint16_t)0x0020)
7874 #define SPI_CR1_SPE ((uint16_t)0x0040)
7875 #define SPI_CR1_LSBFIRST ((uint16_t)0x0080)
7876 #define SPI_CR1_SSI ((uint16_t)0x0100)
7877 #define SPI_CR1_SSM ((uint16_t)0x0200)
7878 #define SPI_CR1_RXONLY ((uint16_t)0x0400)
7879 #define SPI_CR1_DFF ((uint16_t)0x0800)
7880 #define SPI_CR1_CRCNEXT ((uint16_t)0x1000)
7881 #define SPI_CR1_CRCEN ((uint16_t)0x2000)
7882 #define SPI_CR1_BIDIOE ((uint16_t)0x4000)
7883 #define SPI_CR1_BIDIMODE ((uint16_t)0x8000)
7885 /******************* Bit definition for SPI_CR2 register ********************/
7886 #define SPI_CR2_RXDMAEN ((uint8_t)0x01)
7887 #define SPI_CR2_TXDMAEN ((uint8_t)0x02)
7888 #define SPI_CR2_SSOE ((uint8_t)0x04)
7889 #define SPI_CR2_ERRIE ((uint8_t)0x20)
7890 #define SPI_CR2_RXNEIE ((uint8_t)0x40)
7891 #define SPI_CR2_TXEIE ((uint8_t)0x80)
7893 /******************** Bit definition for SPI_SR register ********************/
7894 #define SPI_SR_RXNE ((uint8_t)0x01)
7895 #define SPI_SR_TXE ((uint8_t)0x02)
7896 #define SPI_SR_CHSIDE ((uint8_t)0x04)
7897 #define SPI_SR_UDR ((uint8_t)0x08)
7898 #define SPI_SR_CRCERR ((uint8_t)0x10)
7899 #define SPI_SR_MODF ((uint8_t)0x20)
7900 #define SPI_SR_OVR ((uint8_t)0x40)
7901 #define SPI_SR_BSY ((uint8_t)0x80)
7903 /******************** Bit definition for SPI_DR register ********************/
7904 #define SPI_DR_DR ((uint16_t)0xFFFF)
7906 /******************* Bit definition for SPI_CRCPR register ******************/
7907 #define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF)
7909 /****************** Bit definition for SPI_RXCRCR register ******************/
7910 #define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF)
7912 /****************** Bit definition for SPI_TXCRCR register ******************/
7913 #define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF)
7915 /****************** Bit definition for SPI_I2SCFGR register *****************/
7916 #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001)
7918 #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006)
7919 #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002)
7920 #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004)
7922 #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008)
7924 #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030)
7925 #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010)
7926 #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020)
7928 #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080)
7930 #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300)
7931 #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100)
7932 #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200)
7934 #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400)
7935 #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800)
7937 /****************** Bit definition for SPI_I2SPR register *******************/
7938 #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF)
7939 #define SPI_I2SPR_ODD ((uint16_t)0x0100)
7940 #define SPI_I2SPR_MCKOE ((uint16_t)0x0200)
7942 /******************************************************************************/
7943 /* */
7944 /* SYSCFG */
7945 /* */
7946 /******************************************************************************/
7947 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
7948 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007)
7949 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
7950 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
7951 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
7953 #define SYSCFG_MEMRMP_FB_MODE ((uint32_t)0x00000100)
7955 #define SYSCFG_MEMRMP_SWP_FMC ((uint32_t)0x00000C00)
7956 #define SYSCFG_MEMRMP_SWP_FMC_0 ((uint32_t)0x00000400)
7957 #define SYSCFG_MEMRMP_SWP_FMC_1 ((uint32_t)0x00000800)
7960 /****************** Bit definition for SYSCFG_PMC register ******************/
7961 #define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000)
7962 #define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000)
7963 #define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000)
7964 #define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000)
7966 #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000)
7967 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
7968 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
7969 
7970 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
7971 #define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F)
7972 #define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0)
7973 #define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00)
7974 #define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000)
7978 #define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000)
7979 #define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001)
7980 #define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002)
7981 #define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003)
7982 #define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004)
7983 #define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005)
7984 #define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006)
7985 #define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007)
7986 #define SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008)
7987 #define SYSCFG_EXTICR1_EXTI0_PJ ((uint16_t)0x0009)
7988 #define SYSCFG_EXTICR1_EXTI0_PK ((uint16_t)0x000A)
7993 #define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000)
7994 #define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010)
7995 #define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020)
7996 #define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030)
7997 #define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040)
7998 #define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050)
7999 #define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060)
8000 #define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070)
8001 #define SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080)
8002 #define SYSCFG_EXTICR1_EXTI1_PJ ((uint16_t)0x0090)
8003 #define SYSCFG_EXTICR1_EXTI1_PK ((uint16_t)0x00A0)
8008 #define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000)
8009 #define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100)
8010 #define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200)
8011 #define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300)
8012 #define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400)
8013 #define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500)
8014 #define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600)
8015 #define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700)
8016 #define SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800)
8017 #define SYSCFG_EXTICR1_EXTI2_PJ ((uint16_t)0x0900)
8018 #define SYSCFG_EXTICR1_EXTI2_PK ((uint16_t)0x0A00)
8023 #define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000)
8024 #define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000)
8025 #define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000)
8026 #define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000)
8027 #define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000)
8028 #define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000)
8029 #define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000)
8030 #define SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000)
8031 #define SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000)
8032 #define SYSCFG_EXTICR1_EXTI3_PJ ((uint16_t)0x9000)
8033 #define SYSCFG_EXTICR1_EXTI3_PK ((uint16_t)0xA000)
8035 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
8036 #define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F)
8037 #define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0)
8038 #define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00)
8039 #define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000)
8043 #define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000)
8044 #define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001)
8045 #define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002)
8046 #define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003)
8047 #define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004)
8048 #define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005)
8049 #define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006)
8050 #define SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007)
8051 #define SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008)
8052 #define SYSCFG_EXTICR2_EXTI4_PJ ((uint16_t)0x0009)
8053 #define SYSCFG_EXTICR2_EXTI4_PK ((uint16_t)0x000A)
8058 #define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000)
8059 #define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010)
8060 #define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020)
8061 #define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030)
8062 #define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040)
8063 #define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050)
8064 #define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060)
8065 #define SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070)
8066 #define SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080)
8067 #define SYSCFG_EXTICR2_EXTI5_PJ ((uint16_t)0x0090)
8068 #define SYSCFG_EXTICR2_EXTI5_PK ((uint16_t)0x00A0)
8073 #define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000)
8074 #define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100)
8075 #define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200)
8076 #define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300)
8077 #define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400)
8078 #define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500)
8079 #define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600)
8080 #define SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700)
8081 #define SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800)
8082 #define SYSCFG_EXTICR2_EXTI6_PJ ((uint16_t)0x0900)
8083 #define SYSCFG_EXTICR2_EXTI6_PK ((uint16_t)0x0A00)
8088 #define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000)
8089 #define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000)
8090 #define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000)
8091 #define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000)
8092 #define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000)
8093 #define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000)
8094 #define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000)
8095 #define SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000)
8096 #define SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000)
8097 #define SYSCFG_EXTICR2_EXTI7_PJ ((uint16_t)0x9000)
8098 #define SYSCFG_EXTICR2_EXTI7_PK ((uint16_t)0xA000)
8100 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
8101 #define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F)
8102 #define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0)
8103 #define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00)
8104 #define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000)
8109 #define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000)
8110 #define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001)
8111 #define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002)
8112 #define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003)
8113 #define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004)
8114 #define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005)
8115 #define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006)
8116 #define SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007)
8117 #define SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008)
8118 #define SYSCFG_EXTICR3_EXTI8_PJ ((uint16_t)0x0009)
8123 #define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000)
8124 #define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010)
8125 #define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020)
8126 #define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030)
8127 #define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040)
8128 #define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050)
8129 #define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060)
8130 #define SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070)
8131 #define SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080)
8132 #define SYSCFG_EXTICR3_EXTI9_PJ ((uint16_t)0x0090)
8137 #define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000)
8138 #define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100)
8139 #define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200)
8140 #define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300)
8141 #define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400)
8142 #define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500)
8143 #define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600)
8144 #define SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700)
8145 #define SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800)
8146 #define SYSCFG_EXTICR3_EXTI10_PJ ((uint16_t)0x0900)
8151 #define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000)
8152 #define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000)
8153 #define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000)
8154 #define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000)
8155 #define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000)
8156 #define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000)
8157 #define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000)
8158 #define SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000)
8159 #define SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000)
8160 #define SYSCFG_EXTICR3_EXTI11_PJ ((uint16_t)0x9000)
8162 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
8163 #define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F)
8164 #define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0)
8165 #define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00)
8166 #define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000)
8170 #define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000)
8171 #define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001)
8172 #define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002)
8173 #define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003)
8174 #define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004)
8175 #define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005)
8176 #define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006)
8177 #define SYSCFG_EXTICR4_EXTI12_PH ((uint16_t)0x0007)
8178 #define SYSCFG_EXTICR4_EXTI12_PI ((uint16_t)0x0008)
8179 #define SYSCFG_EXTICR4_EXTI12_PJ ((uint16_t)0x0009)
8184 #define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000)
8185 #define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010)
8186 #define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020)
8187 #define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030)
8188 #define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040)
8189 #define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050)
8190 #define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060)
8191 #define SYSCFG_EXTICR4_EXTI13_PH ((uint16_t)0x0070)
8192 #define SYSCFG_EXTICR4_EXTI13_PI ((uint16_t)0x0008)
8193 #define SYSCFG_EXTICR4_EXTI13_PJ ((uint16_t)0x0009)
8198 #define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000)
8199 #define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100)
8200 #define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200)
8201 #define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300)
8202 #define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400)
8203 #define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500)
8204 #define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600)
8205 #define SYSCFG_EXTICR4_EXTI14_PH ((uint16_t)0x0700)
8206 #define SYSCFG_EXTICR4_EXTI14_PI ((uint16_t)0x0800)
8207 #define SYSCFG_EXTICR4_EXTI14_PJ ((uint16_t)0x0900)
8212 #define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000)
8213 #define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000)
8214 #define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000)
8215 #define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000)
8216 #define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000)
8217 #define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000)
8218 #define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000)
8219 #define SYSCFG_EXTICR4_EXTI15_PH ((uint16_t)0x7000)
8220 #define SYSCFG_EXTICR4_EXTI15_PI ((uint16_t)0x8000)
8221 #define SYSCFG_EXTICR4_EXTI15_PJ ((uint16_t)0x9000)
8223 /****************** Bit definition for SYSCFG_CMPCR register ****************/
8224 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001)
8225 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100)
8227 /******************************************************************************/
8228 /* */
8229 /* TIM */
8230 /* */
8231 /******************************************************************************/
8232 /******************* Bit definition for TIM_CR1 register ********************/
8233 #define TIM_CR1_CEN ((uint16_t)0x0001)
8234 #define TIM_CR1_UDIS ((uint16_t)0x0002)
8235 #define TIM_CR1_URS ((uint16_t)0x0004)
8236 #define TIM_CR1_OPM ((uint16_t)0x0008)
8237 #define TIM_CR1_DIR ((uint16_t)0x0010)
8239 #define TIM_CR1_CMS ((uint16_t)0x0060)
8240 #define TIM_CR1_CMS_0 ((uint16_t)0x0020)
8241 #define TIM_CR1_CMS_1 ((uint16_t)0x0040)
8243 #define TIM_CR1_ARPE ((uint16_t)0x0080)
8245 #define TIM_CR1_CKD ((uint16_t)0x0300)
8246 #define TIM_CR1_CKD_0 ((uint16_t)0x0100)
8247 #define TIM_CR1_CKD_1 ((uint16_t)0x0200)
8249 /******************* Bit definition for TIM_CR2 register ********************/
8250 #define TIM_CR2_CCPC ((uint16_t)0x0001)
8251 #define TIM_CR2_CCUS ((uint16_t)0x0004)
8252 #define TIM_CR2_CCDS ((uint16_t)0x0008)
8254 #define TIM_CR2_MMS ((uint16_t)0x0070)
8255 #define TIM_CR2_MMS_0 ((uint16_t)0x0010)
8256 #define TIM_CR2_MMS_1 ((uint16_t)0x0020)
8257 #define TIM_CR2_MMS_2 ((uint16_t)0x0040)
8259 #define TIM_CR2_TI1S ((uint16_t)0x0080)
8260 #define TIM_CR2_OIS1 ((uint16_t)0x0100)
8261 #define TIM_CR2_OIS1N ((uint16_t)0x0200)
8262 #define TIM_CR2_OIS2 ((uint16_t)0x0400)
8263 #define TIM_CR2_OIS2N ((uint16_t)0x0800)
8264 #define TIM_CR2_OIS3 ((uint16_t)0x1000)
8265 #define TIM_CR2_OIS3N ((uint16_t)0x2000)
8266 #define TIM_CR2_OIS4 ((uint16_t)0x4000)
8268 /******************* Bit definition for TIM_SMCR register *******************/
8269 #define TIM_SMCR_SMS ((uint16_t)0x0007)
8270 #define TIM_SMCR_SMS_0 ((uint16_t)0x0001)
8271 #define TIM_SMCR_SMS_1 ((uint16_t)0x0002)
8272 #define TIM_SMCR_SMS_2 ((uint16_t)0x0004)
8274 #define TIM_SMCR_TS ((uint16_t)0x0070)
8275 #define TIM_SMCR_TS_0 ((uint16_t)0x0010)
8276 #define TIM_SMCR_TS_1 ((uint16_t)0x0020)
8277 #define TIM_SMCR_TS_2 ((uint16_t)0x0040)
8279 #define TIM_SMCR_MSM ((uint16_t)0x0080)
8281 #define TIM_SMCR_ETF ((uint16_t)0x0F00)
8282 #define TIM_SMCR_ETF_0 ((uint16_t)0x0100)
8283 #define TIM_SMCR_ETF_1 ((uint16_t)0x0200)
8284 #define TIM_SMCR_ETF_2 ((uint16_t)0x0400)
8285 #define TIM_SMCR_ETF_3 ((uint16_t)0x0800)
8287 #define TIM_SMCR_ETPS ((uint16_t)0x3000)
8288 #define TIM_SMCR_ETPS_0 ((uint16_t)0x1000)
8289 #define TIM_SMCR_ETPS_1 ((uint16_t)0x2000)
8291 #define TIM_SMCR_ECE ((uint16_t)0x4000)
8292 #define TIM_SMCR_ETP ((uint16_t)0x8000)
8294 /******************* Bit definition for TIM_DIER register *******************/
8295 #define TIM_DIER_UIE ((uint16_t)0x0001)
8296 #define TIM_DIER_CC1IE ((uint16_t)0x0002)
8297 #define TIM_DIER_CC2IE ((uint16_t)0x0004)
8298 #define TIM_DIER_CC3IE ((uint16_t)0x0008)
8299 #define TIM_DIER_CC4IE ((uint16_t)0x0010)
8300 #define TIM_DIER_COMIE ((uint16_t)0x0020)
8301 #define TIM_DIER_TIE ((uint16_t)0x0040)
8302 #define TIM_DIER_BIE ((uint16_t)0x0080)
8303 #define TIM_DIER_UDE ((uint16_t)0x0100)
8304 #define TIM_DIER_CC1DE ((uint16_t)0x0200)
8305 #define TIM_DIER_CC2DE ((uint16_t)0x0400)
8306 #define TIM_DIER_CC3DE ((uint16_t)0x0800)
8307 #define TIM_DIER_CC4DE ((uint16_t)0x1000)
8308 #define TIM_DIER_COMDE ((uint16_t)0x2000)
8309 #define TIM_DIER_TDE ((uint16_t)0x4000)
8311 /******************** Bit definition for TIM_SR register ********************/
8312 #define TIM_SR_UIF ((uint16_t)0x0001)
8313 #define TIM_SR_CC1IF ((uint16_t)0x0002)
8314 #define TIM_SR_CC2IF ((uint16_t)0x0004)
8315 #define TIM_SR_CC3IF ((uint16_t)0x0008)
8316 #define TIM_SR_CC4IF ((uint16_t)0x0010)
8317 #define TIM_SR_COMIF ((uint16_t)0x0020)
8318 #define TIM_SR_TIF ((uint16_t)0x0040)
8319 #define TIM_SR_BIF ((uint16_t)0x0080)
8320 #define TIM_SR_CC1OF ((uint16_t)0x0200)
8321 #define TIM_SR_CC2OF ((uint16_t)0x0400)
8322 #define TIM_SR_CC3OF ((uint16_t)0x0800)
8323 #define TIM_SR_CC4OF ((uint16_t)0x1000)
8325 /******************* Bit definition for TIM_EGR register ********************/
8326 #define TIM_EGR_UG ((uint8_t)0x01)
8327 #define TIM_EGR_CC1G ((uint8_t)0x02)
8328 #define TIM_EGR_CC2G ((uint8_t)0x04)
8329 #define TIM_EGR_CC3G ((uint8_t)0x08)
8330 #define TIM_EGR_CC4G ((uint8_t)0x10)
8331 #define TIM_EGR_COMG ((uint8_t)0x20)
8332 #define TIM_EGR_TG ((uint8_t)0x40)
8333 #define TIM_EGR_BG ((uint8_t)0x80)
8335 /****************** Bit definition for TIM_CCMR1 register *******************/
8336 #define TIM_CCMR1_CC1S ((uint16_t)0x0003)
8337 #define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001)
8338 #define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002)
8340 #define TIM_CCMR1_OC1FE ((uint16_t)0x0004)
8341 #define TIM_CCMR1_OC1PE ((uint16_t)0x0008)
8343 #define TIM_CCMR1_OC1M ((uint16_t)0x0070)
8344 #define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010)
8345 #define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020)
8346 #define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040)
8348 #define TIM_CCMR1_OC1CE ((uint16_t)0x0080)
8350 #define TIM_CCMR1_CC2S ((uint16_t)0x0300)
8351 #define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100)
8352 #define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200)
8354 #define TIM_CCMR1_OC2FE ((uint16_t)0x0400)
8355 #define TIM_CCMR1_OC2PE ((uint16_t)0x0800)
8357 #define TIM_CCMR1_OC2M ((uint16_t)0x7000)
8358 #define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000)
8359 #define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000)
8360 #define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000)
8362 #define TIM_CCMR1_OC2CE ((uint16_t)0x8000)
8364 /*----------------------------------------------------------------------------*/
8365 
8366 #define TIM_CCMR1_IC1PSC ((uint16_t)0x000C)
8367 #define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004)
8368 #define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008)
8370 #define TIM_CCMR1_IC1F ((uint16_t)0x00F0)
8371 #define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010)
8372 #define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020)
8373 #define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040)
8374 #define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080)
8376 #define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00)
8377 #define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400)
8378 #define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800)
8380 #define TIM_CCMR1_IC2F ((uint16_t)0xF000)
8381 #define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000)
8382 #define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000)
8383 #define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000)
8384 #define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000)
8386 /****************** Bit definition for TIM_CCMR2 register *******************/
8387 #define TIM_CCMR2_CC3S ((uint16_t)0x0003)
8388 #define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001)
8389 #define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002)
8391 #define TIM_CCMR2_OC3FE ((uint16_t)0x0004)
8392 #define TIM_CCMR2_OC3PE ((uint16_t)0x0008)
8394 #define TIM_CCMR2_OC3M ((uint16_t)0x0070)
8395 #define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010)
8396 #define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020)
8397 #define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040)
8399 #define TIM_CCMR2_OC3CE ((uint16_t)0x0080)
8401 #define TIM_CCMR2_CC4S ((uint16_t)0x0300)
8402 #define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100)
8403 #define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200)
8405 #define TIM_CCMR2_OC4FE ((uint16_t)0x0400)
8406 #define TIM_CCMR2_OC4PE ((uint16_t)0x0800)
8408 #define TIM_CCMR2_OC4M ((uint16_t)0x7000)
8409 #define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000)
8410 #define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000)
8411 #define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000)
8413 #define TIM_CCMR2_OC4CE ((uint16_t)0x8000)
8415 /*----------------------------------------------------------------------------*/
8416 
8417 #define TIM_CCMR2_IC3PSC ((uint16_t)0x000C)
8418 #define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004)
8419 #define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008)
8421 #define TIM_CCMR2_IC3F ((uint16_t)0x00F0)
8422 #define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010)
8423 #define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020)
8424 #define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040)
8425 #define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080)
8427 #define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00)
8428 #define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400)
8429 #define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800)
8431 #define TIM_CCMR2_IC4F ((uint16_t)0xF000)
8432 #define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000)
8433 #define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000)
8434 #define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000)
8435 #define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000)
8437 /******************* Bit definition for TIM_CCER register *******************/
8438 #define TIM_CCER_CC1E ((uint16_t)0x0001)
8439 #define TIM_CCER_CC1P ((uint16_t)0x0002)
8440 #define TIM_CCER_CC1NE ((uint16_t)0x0004)
8441 #define TIM_CCER_CC1NP ((uint16_t)0x0008)
8442 #define TIM_CCER_CC2E ((uint16_t)0x0010)
8443 #define TIM_CCER_CC2P ((uint16_t)0x0020)
8444 #define TIM_CCER_CC2NE ((uint16_t)0x0040)
8445 #define TIM_CCER_CC2NP ((uint16_t)0x0080)
8446 #define TIM_CCER_CC3E ((uint16_t)0x0100)
8447 #define TIM_CCER_CC3P ((uint16_t)0x0200)
8448 #define TIM_CCER_CC3NE ((uint16_t)0x0400)
8449 #define TIM_CCER_CC3NP ((uint16_t)0x0800)
8450 #define TIM_CCER_CC4E ((uint16_t)0x1000)
8451 #define TIM_CCER_CC4P ((uint16_t)0x2000)
8452 #define TIM_CCER_CC4NP ((uint16_t)0x8000)
8454 /******************* Bit definition for TIM_CNT register ********************/
8455 #define TIM_CNT_CNT ((uint16_t)0xFFFF)
8457 /******************* Bit definition for TIM_PSC register ********************/
8458 #define TIM_PSC_PSC ((uint16_t)0xFFFF)
8460 /******************* Bit definition for TIM_ARR register ********************/
8461 #define TIM_ARR_ARR ((uint16_t)0xFFFF)
8463 /******************* Bit definition for TIM_RCR register ********************/
8464 #define TIM_RCR_REP ((uint8_t)0xFF)
8466 /******************* Bit definition for TIM_CCR1 register *******************/
8467 #define TIM_CCR1_CCR1 ((uint16_t)0xFFFF)
8469 /******************* Bit definition for TIM_CCR2 register *******************/
8470 #define TIM_CCR2_CCR2 ((uint16_t)0xFFFF)
8472 /******************* Bit definition for TIM_CCR3 register *******************/
8473 #define TIM_CCR3_CCR3 ((uint16_t)0xFFFF)
8475 /******************* Bit definition for TIM_CCR4 register *******************/
8476 #define TIM_CCR4_CCR4 ((uint16_t)0xFFFF)
8478 /******************* Bit definition for TIM_BDTR register *******************/
8479 #define TIM_BDTR_DTG ((uint16_t)0x00FF)
8480 #define TIM_BDTR_DTG_0 ((uint16_t)0x0001)
8481 #define TIM_BDTR_DTG_1 ((uint16_t)0x0002)
8482 #define TIM_BDTR_DTG_2 ((uint16_t)0x0004)
8483 #define TIM_BDTR_DTG_3 ((uint16_t)0x0008)
8484 #define TIM_BDTR_DTG_4 ((uint16_t)0x0010)
8485 #define TIM_BDTR_DTG_5 ((uint16_t)0x0020)
8486 #define TIM_BDTR_DTG_6 ((uint16_t)0x0040)
8487 #define TIM_BDTR_DTG_7 ((uint16_t)0x0080)
8489 #define TIM_BDTR_LOCK ((uint16_t)0x0300)
8490 #define TIM_BDTR_LOCK_0 ((uint16_t)0x0100)
8491 #define TIM_BDTR_LOCK_1 ((uint16_t)0x0200)
8493 #define TIM_BDTR_OSSI ((uint16_t)0x0400)
8494 #define TIM_BDTR_OSSR ((uint16_t)0x0800)
8495 #define TIM_BDTR_BKE ((uint16_t)0x1000)
8496 #define TIM_BDTR_BKP ((uint16_t)0x2000)
8497 #define TIM_BDTR_AOE ((uint16_t)0x4000)
8498 #define TIM_BDTR_MOE ((uint16_t)0x8000)
8500 /******************* Bit definition for TIM_DCR register ********************/
8501 #define TIM_DCR_DBA ((uint16_t)0x001F)
8502 #define TIM_DCR_DBA_0 ((uint16_t)0x0001)
8503 #define TIM_DCR_DBA_1 ((uint16_t)0x0002)
8504 #define TIM_DCR_DBA_2 ((uint16_t)0x0004)
8505 #define TIM_DCR_DBA_3 ((uint16_t)0x0008)
8506 #define TIM_DCR_DBA_4 ((uint16_t)0x0010)
8508 #define TIM_DCR_DBL ((uint16_t)0x1F00)
8509 #define TIM_DCR_DBL_0 ((uint16_t)0x0100)
8510 #define TIM_DCR_DBL_1 ((uint16_t)0x0200)
8511 #define TIM_DCR_DBL_2 ((uint16_t)0x0400)
8512 #define TIM_DCR_DBL_3 ((uint16_t)0x0800)
8513 #define TIM_DCR_DBL_4 ((uint16_t)0x1000)
8515 /******************* Bit definition for TIM_DMAR register *******************/
8516 #define TIM_DMAR_DMAB ((uint16_t)0xFFFF)
8518 /******************* Bit definition for TIM_OR register *********************/
8519 #define TIM_OR_TI4_RMP ((uint16_t)0x00C0)
8520 #define TIM_OR_TI4_RMP_0 ((uint16_t)0x0040)
8521 #define TIM_OR_TI4_RMP_1 ((uint16_t)0x0080)
8522 #define TIM_OR_ITR1_RMP ((uint16_t)0x0C00)
8523 #define TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400)
8524 #define TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800)
8527 /******************************************************************************/
8528 /* */
8529 /* Universal Synchronous Asynchronous Receiver Transmitter */
8530 /* */
8531 /******************************************************************************/
8532 /******************* Bit definition for USART_SR register *******************/
8533 #define USART_SR_PE ((uint16_t)0x0001)
8534 #define USART_SR_FE ((uint16_t)0x0002)
8535 #define USART_SR_NE ((uint16_t)0x0004)
8536 #define USART_SR_ORE ((uint16_t)0x0008)
8537 #define USART_SR_IDLE ((uint16_t)0x0010)
8538 #define USART_SR_RXNE ((uint16_t)0x0020)
8539 #define USART_SR_TC ((uint16_t)0x0040)
8540 #define USART_SR_TXE ((uint16_t)0x0080)
8541 #define USART_SR_LBD ((uint16_t)0x0100)
8542 #define USART_SR_CTS ((uint16_t)0x0200)
8544 /******************* Bit definition for USART_DR register *******************/
8545 #define USART_DR_DR ((uint16_t)0x01FF)
8547 /****************** Bit definition for USART_BRR register *******************/
8548 #define USART_BRR_DIV_Fraction ((uint16_t)0x000F)
8549 #define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0)
8551 /****************** Bit definition for USART_CR1 register *******************/
8552 #define USART_CR1_SBK ((uint16_t)0x0001)
8553 #define USART_CR1_RWU ((uint16_t)0x0002)
8554 #define USART_CR1_RE ((uint16_t)0x0004)
8555 #define USART_CR1_TE ((uint16_t)0x0008)
8556 #define USART_CR1_IDLEIE ((uint16_t)0x0010)
8557 #define USART_CR1_RXNEIE ((uint16_t)0x0020)
8558 #define USART_CR1_TCIE ((uint16_t)0x0040)
8559 #define USART_CR1_TXEIE ((uint16_t)0x0080)
8560 #define USART_CR1_PEIE ((uint16_t)0x0100)
8561 #define USART_CR1_PS ((uint16_t)0x0200)
8562 #define USART_CR1_PCE ((uint16_t)0x0400)
8563 #define USART_CR1_WAKE ((uint16_t)0x0800)
8564 #define USART_CR1_M ((uint16_t)0x1000)
8565 #define USART_CR1_UE ((uint16_t)0x2000)
8566 #define USART_CR1_OVER8 ((uint16_t)0x8000)
8568 /****************** Bit definition for USART_CR2 register *******************/
8569 #define USART_CR2_ADD ((uint16_t)0x000F)
8570 #define USART_CR2_LBDL ((uint16_t)0x0020)
8571 #define USART_CR2_LBDIE ((uint16_t)0x0040)
8572 #define USART_CR2_LBCL ((uint16_t)0x0100)
8573 #define USART_CR2_CPHA ((uint16_t)0x0200)
8574 #define USART_CR2_CPOL ((uint16_t)0x0400)
8575 #define USART_CR2_CLKEN ((uint16_t)0x0800)
8577 #define USART_CR2_STOP ((uint16_t)0x3000)
8578 #define USART_CR2_STOP_0 ((uint16_t)0x1000)
8579 #define USART_CR2_STOP_1 ((uint16_t)0x2000)
8581 #define USART_CR2_LINEN ((uint16_t)0x4000)
8583 /****************** Bit definition for USART_CR3 register *******************/
8584 #define USART_CR3_EIE ((uint16_t)0x0001)
8585 #define USART_CR3_IREN ((uint16_t)0x0002)
8586 #define USART_CR3_IRLP ((uint16_t)0x0004)
8587 #define USART_CR3_HDSEL ((uint16_t)0x0008)
8588 #define USART_CR3_NACK ((uint16_t)0x0010)
8589 #define USART_CR3_SCEN ((uint16_t)0x0020)
8590 #define USART_CR3_DMAR ((uint16_t)0x0040)
8591 #define USART_CR3_DMAT ((uint16_t)0x0080)
8592 #define USART_CR3_RTSE ((uint16_t)0x0100)
8593 #define USART_CR3_CTSE ((uint16_t)0x0200)
8594 #define USART_CR3_CTSIE ((uint16_t)0x0400)
8595 #define USART_CR3_ONEBIT ((uint16_t)0x0800)
8597 /****************** Bit definition for USART_GTPR register ******************/
8598 #define USART_GTPR_PSC ((uint16_t)0x00FF)
8599 #define USART_GTPR_PSC_0 ((uint16_t)0x0001)
8600 #define USART_GTPR_PSC_1 ((uint16_t)0x0002)
8601 #define USART_GTPR_PSC_2 ((uint16_t)0x0004)
8602 #define USART_GTPR_PSC_3 ((uint16_t)0x0008)
8603 #define USART_GTPR_PSC_4 ((uint16_t)0x0010)
8604 #define USART_GTPR_PSC_5 ((uint16_t)0x0020)
8605 #define USART_GTPR_PSC_6 ((uint16_t)0x0040)
8606 #define USART_GTPR_PSC_7 ((uint16_t)0x0080)
8608 #define USART_GTPR_GT ((uint16_t)0xFF00)
8610 /******************************************************************************/
8611 /* */
8612 /* Window WATCHDOG */
8613 /* */
8614 /******************************************************************************/
8615 /******************* Bit definition for WWDG_CR register ********************/
8616 #define WWDG_CR_T ((uint8_t)0x7F)
8617 #define WWDG_CR_T0 ((uint8_t)0x01)
8618 #define WWDG_CR_T1 ((uint8_t)0x02)
8619 #define WWDG_CR_T2 ((uint8_t)0x04)
8620 #define WWDG_CR_T3 ((uint8_t)0x08)
8621 #define WWDG_CR_T4 ((uint8_t)0x10)
8622 #define WWDG_CR_T5 ((uint8_t)0x20)
8623 #define WWDG_CR_T6 ((uint8_t)0x40)
8625 #define WWDG_CR_WDGA ((uint8_t)0x80)
8627 /******************* Bit definition for WWDG_CFR register *******************/
8628 #define WWDG_CFR_W ((uint16_t)0x007F)
8629 #define WWDG_CFR_W0 ((uint16_t)0x0001)
8630 #define WWDG_CFR_W1 ((uint16_t)0x0002)
8631 #define WWDG_CFR_W2 ((uint16_t)0x0004)
8632 #define WWDG_CFR_W3 ((uint16_t)0x0008)
8633 #define WWDG_CFR_W4 ((uint16_t)0x0010)
8634 #define WWDG_CFR_W5 ((uint16_t)0x0020)
8635 #define WWDG_CFR_W6 ((uint16_t)0x0040)
8637 #define WWDG_CFR_WDGTB ((uint16_t)0x0180)
8638 #define WWDG_CFR_WDGTB0 ((uint16_t)0x0080)
8639 #define WWDG_CFR_WDGTB1 ((uint16_t)0x0100)
8641 #define WWDG_CFR_EWI ((uint16_t)0x0200)
8643 /******************* Bit definition for WWDG_SR register ********************/
8644 #define WWDG_SR_EWIF ((uint8_t)0x01)
8647 /******************************************************************************/
8648 /* */
8649 /* DBG */
8650 /* */
8651 /******************************************************************************/
8652 /******************** Bit definition for DBGMCU_IDCODE register *************/
8653 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
8654 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
8655 
8656 /******************** Bit definition for DBGMCU_CR register *****************/
8657 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
8658 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
8659 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
8660 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
8661 
8662 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
8663 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)
8664 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)
8666 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
8667 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
8668 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
8669 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
8670 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
8671 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
8672 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
8673 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
8674 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
8675 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
8676 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
8677 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
8678 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
8679 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
8680 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
8681 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
8682 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
8683 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
8684 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
8685 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
8686 
8687 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
8688 #define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
8689 #define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
8690 #define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
8691 #define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
8692 #define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
8693 
8694 /******************************************************************************/
8695 /* */
8696 /* Ethernet MAC Registers bits definitions */
8697 /* */
8698 /******************************************************************************/
8699 /* Bit definition for Ethernet MAC Control Register register */
8700 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
8701 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
8702 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
8703 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
8704  #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
8705  #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
8706  #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
8707  #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
8708  #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
8709  #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
8710  #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
8711 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
8712 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
8713 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
8714 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
8715 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
8716 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
8717 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
8718 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
8719 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
8720  a transmission attempt during retries after a collision: 0 =< r <2^k */
8721  #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
8722  #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
8723  #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
8724  #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
8725 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
8726 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
8727 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
8728 
8729 /* Bit definition for Ethernet MAC Frame Filter Register */
8730 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
8731 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
8732 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
8733 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
8734 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
8735  #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
8736  #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
8737  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
8738 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
8739 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
8740 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
8741 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
8742 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
8743 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
8744 
8745 /* Bit definition for Ethernet MAC Hash Table High Register */
8746 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
8747 
8748 /* Bit definition for Ethernet MAC Hash Table Low Register */
8749 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
8750 
8751 /* Bit definition for Ethernet MAC MII Address Register */
8752 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
8753 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
8754 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
8755  #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
8756  #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
8757  #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
8758  #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
8759  #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
8760 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
8761 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
8762 
8763 /* Bit definition for Ethernet MAC MII Data Register */
8764 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
8765 
8766 /* Bit definition for Ethernet MAC Flow Control Register */
8767 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
8768 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
8769 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
8770  #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
8771  #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
8772  #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
8773  #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
8774 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
8775 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
8776 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
8777 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
8778 
8779 /* Bit definition for Ethernet MAC VLAN Tag Register */
8780 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
8781 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
8782 
8783 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
8784 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
8785 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
8786  Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
8787 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
8788  Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
8789  Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
8790  Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
8791  Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
8792  RSVD - Filter1 Command - RSVD - Filter0 Command
8793  Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
8794  Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
8795  Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
8796 
8797 /* Bit definition for Ethernet MAC PMT Control and Status Register */
8798 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
8799 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
8800 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
8801 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
8802 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
8803 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
8804 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
8805 
8806 /* Bit definition for Ethernet MAC Status Register */
8807 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
8808 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
8809 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
8810 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
8811 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
8812 
8813 /* Bit definition for Ethernet MAC Interrupt Mask Register */
8814 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
8815 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
8816 
8817 /* Bit definition for Ethernet MAC Address0 High Register */
8818 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
8819 
8820 /* Bit definition for Ethernet MAC Address0 Low Register */
8821 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
8822 
8823 /* Bit definition for Ethernet MAC Address1 High Register */
8824 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
8825 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
8826 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
8827  #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
8828  #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
8829  #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
8830  #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
8831  #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
8832  #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
8833 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
8834 
8835 /* Bit definition for Ethernet MAC Address1 Low Register */
8836 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
8837 
8838 /* Bit definition for Ethernet MAC Address2 High Register */
8839 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
8840 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
8841 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
8842  #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
8843  #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
8844  #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
8845  #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
8846  #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
8847  #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
8848 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
8849 
8850 /* Bit definition for Ethernet MAC Address2 Low Register */
8851 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
8852 
8853 /* Bit definition for Ethernet MAC Address3 High Register */
8854 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
8855 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
8856 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
8857  #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
8858  #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
8859  #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
8860  #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
8861  #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
8862  #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
8863 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
8864 
8865 /* Bit definition for Ethernet MAC Address3 Low Register */
8866 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
8867 
8868 /******************************************************************************/
8869 /* Ethernet MMC Registers bits definition */
8870 /******************************************************************************/
8871 
8872 /* Bit definition for Ethernet MMC Contol Register */
8873 #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
8874 #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
8875 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
8876 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
8877 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
8878 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
8879 
8880 /* Bit definition for Ethernet MMC Receive Interrupt Register */
8881 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
8882 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
8883 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
8884 
8885 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
8886 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
8887 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
8888 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
8889 
8890 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
8891 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
8892 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
8893 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
8894 
8895 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
8896 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
8897 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
8898 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
8899 
8900 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
8901 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
8902 
8903 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
8904 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
8905 
8906 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
8907 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
8908 
8909 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
8910 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
8911 
8912 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
8913 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
8914 
8915 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
8916 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
8917 
8918 /******************************************************************************/
8919 /* Ethernet PTP Registers bits definition */
8920 /******************************************************************************/
8921 
8922 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
8923 #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
8924 #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
8925 #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
8926 #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
8927 #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
8928 #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
8929 #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
8930 #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
8931 #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
8932 
8933 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
8934 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
8935 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
8936 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
8937 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
8938 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
8939 
8940 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
8941 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
8942 
8943 /* Bit definition for Ethernet PTP Time Stamp High Register */
8944 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
8945 
8946 /* Bit definition for Ethernet PTP Time Stamp Low Register */
8947 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
8948 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
8949 
8950 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
8951 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
8952 
8953 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
8954 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
8955 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
8956 
8957 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
8958 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
8959 
8960 /* Bit definition for Ethernet PTP Target Time High Register */
8961 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
8962 
8963 /* Bit definition for Ethernet PTP Target Time Low Register */
8964 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
8965 
8966 /* Bit definition for Ethernet PTP Time Stamp Status Register */
8967 #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
8968 #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
8969 
8970 /******************************************************************************/
8971 /* Ethernet DMA Registers bits definition */
8972 /******************************************************************************/
8973 
8974 /* Bit definition for Ethernet DMA Bus Mode Register */
8975 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
8976 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
8977 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
8978 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
8979  #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
8980  #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
8981  #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
8982  #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
8983  #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
8984  #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
8985  #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
8986  #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
8987  #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
8988  #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
8989  #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
8990  #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
8991 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
8992 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
8993  #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
8994  #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
8995  #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
8996  #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
8997 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
8998  #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
8999  #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
9000  #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
9001  #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
9002  #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
9003  #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
9004  #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
9005  #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
9006  #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
9007  #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
9008  #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
9009  #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
9010 #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
9011 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
9012 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
9013 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
9014 
9015 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
9016 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
9017 
9018 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
9019 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
9020 
9021 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
9022 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
9023 
9024 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
9025 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
9026 
9027 /* Bit definition for Ethernet DMA Status Register */
9028 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
9029 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
9030 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
9031 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
9032  /* combination with EBS[2:0] for GetFlagStatus function */
9033  #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
9034  #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
9035  #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
9036 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
9037  #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
9038  #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
9039  #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
9040  #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
9041  #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
9042  #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
9043 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
9044  #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
9045  #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
9046  #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
9047  #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
9048  #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
9049  #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
9050 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
9051 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
9052 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
9053 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
9054 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
9055 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
9056 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
9057 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
9058 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
9059 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
9060 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
9061 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
9062 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
9063 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
9064 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
9065 
9066 /* Bit definition for Ethernet DMA Operation Mode Register */
9067 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
9068 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
9069 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
9070 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
9071 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
9072 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
9073  #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
9074  #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
9075  #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
9076  #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
9077  #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
9078  #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
9079  #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
9080  #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
9081 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
9082 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
9083 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
9084 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
9085  #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
9086  #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
9087  #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
9088  #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
9089 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
9090 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
9091 
9092 /* Bit definition for Ethernet DMA Interrupt Enable Register */
9093 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
9094 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
9095 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
9096 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
9097 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
9098 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
9099 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
9100 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
9101 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
9102 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
9103 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
9104 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
9105 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
9106 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
9107 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
9108 
9109 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
9110 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
9111 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
9112 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
9113 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
9114 
9115 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
9116 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
9117 
9118 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
9119 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
9120 
9121 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
9122 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
9123 
9124 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
9125 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
9126 
9135 #ifdef USE_STDPERIPH_DRIVER
9136  #include "stm32f4xx_conf.h"
9137 #endif /* USE_STDPERIPH_DRIVER */
9138 
9143 #define SET_BIT(REG, BIT) ((REG) |= (BIT))
9144 
9145 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
9146 
9147 #define READ_BIT(REG, BIT) ((REG) & (BIT))
9148 
9149 #define CLEAR_REG(REG) ((REG) = (0x0))
9150 
9151 #define WRITE_REG(REG, VAL) ((REG) = (VAL))
9152 
9153 #define READ_REG(REG) ((REG))
9154 
9155 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
9156 
9161 #ifdef __cplusplus
9162 }
9163 #endif /* __cplusplus */
9164 
9165 #endif /* __STM32F4xx_H */
9166 
9175 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
vuc32
__I uint32_t vuc32
Definition: stm32f4xx.h:508
I2C2_ER_IRQn
Definition: stm32f4xx.h:222
TIM7_IRQn
Definition: stm32f4xx.h:243
TIM8_CC_IRQn
Definition: stm32f4xx.h:234
LTDC_TypeDef
LCD-TFT Display Controller.
Definition: stm32f4xx.h:1060
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f4xx.h:580
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f4xx.h:1007
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f4xx.h:1257
SDIO_IRQn
Definition: stm32f4xx.h:237
vsc8
__I int8_t vsc8
Definition: stm32f4xx.h:494
DMA2_Stream5_IRQn
Definition: stm32f4xx.h:256
CAN1_RX0_IRQn
Definition: stm32f4xx.h:208
TIM4_IRQn
Definition: stm32f4xx.h:218
FSMC_Bank1_TypeDef
Flexible Static Memory Controller.
Definition: stm32f4xx.h:855
DCMI_IRQn
Definition: stm32f4xx.h:266
TIM1_UP_TIM10_IRQn
Definition: stm32f4xx.h:213
RTC_Alarm_IRQn
Definition: stm32f4xx.h:229
MemoryManagement_IRQn
Definition: stm32f4xx.h:178
s32
int32_t s32
Definition: stm32f4xx.h:480
DMA1_Stream7_IRQn
Definition: stm32f4xx.h:235
TIM8_UP_TIM13_IRQn
Definition: stm32f4xx.h:232
UART5_IRQn
Definition: stm32f4xx.h:241
__I
#define __I
Definition: core_cm4.h:219
DMA1_Stream1_IRQn
Definition: stm32f4xx.h:198
ETH_IRQn
Definition: stm32f4xx.h:249
USART6_IRQn
Definition: stm32f4xx.h:259
PVD_IRQn
Definition: stm32f4xx.h:187
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f4xx.h:825
USART1_IRQn
Definition: stm32f4xx.h:225
FSMC_Bank3_TypeDef
Flexible Static Memory Controller Bank3.
Definition: stm32f4xx.h:887
ETH_WKUP_IRQn
Definition: stm32f4xx.h:250
EXTI0_IRQn
Definition: stm32f4xx.h:192
I2C1_EV_IRQn
Definition: stm32f4xx.h:219
FPU_IRQn
Definition: stm32f4xx.h:269
CRC_TypeDef
CRC calculation unit.
Definition: stm32f4xx.h:632
DMA2_Stream2_IRQn
Definition: stm32f4xx.h:246
TIM1_BRK_TIM9_IRQn
Definition: stm32f4xx.h:212
SPI2_IRQn
Definition: stm32f4xx.h:224
DMA2_Stream4_IRQn
Definition: stm32f4xx.h:248
DMA1_Stream6_IRQn
Definition: stm32f4xx.h:203
HASH_RNG_IRQn
Definition: stm32f4xx.h:268
DMA2_Stream7_IRQn
Definition: stm32f4xx.h:258
__IO
#define __IO
Definition: core_cm4.h:222
FSMC_IRQn
Definition: stm32f4xx.h:236
OTG_HS_EP1_OUT_IRQn
Definition: stm32f4xx.h:262
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
CAN2_TX_IRQn
Definition: stm32f4xx.h:251
DMA_TypeDef
Definition: stm32f4xx.h:708
OTG_FS_WKUP_IRQn
Definition: stm32f4xx.h:230
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f4xx.h:1349
OTG_HS_WKUP_IRQn
Definition: stm32f4xx.h:264
USART2_IRQn
Definition: stm32f4xx.h:226
CAN1_RX1_IRQn
Definition: stm32f4xx.h:209
CAN1_SCE_IRQn
Definition: stm32f4xx.h:210
DebugMonitor_IRQn
Definition: stm32f4xx.h:182
LTDC_Layer_TypeDef
LCD-TFT Display layer x Controller.
Definition: stm32f4xx.h:1085
SPI3_IRQn
Definition: stm32f4xx.h:239
CAN2_RX0_IRQn
Definition: stm32f4xx.h:252
HASH_DIGEST_TypeDef
HASH_DIGEST.
Definition: stm32f4xx.h:1420
DMA1_Stream2_IRQn
Definition: stm32f4xx.h:199
DMA1_Stream4_IRQn
Definition: stm32f4xx.h:201
sc16
const int16_t sc16
Definition: stm32f4xx.h:485
OTG_FS_IRQn
Definition: stm32f4xx.h:255
UsageFault_IRQn
Definition: stm32f4xx.h:180
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f4xx.h:989
USART3_IRQn
Definition: stm32f4xx.h:227
TIM8_BRK_TIM12_IRQn
Definition: stm32f4xx.h:231
vsc32
__I int32_t vsc32
Definition: stm32f4xx.h:492
SVCall_IRQn
Definition: stm32f4xx.h:181
BusFault_IRQn
Definition: stm32f4xx.h:179
PendSV_IRQn
Definition: stm32f4xx.h:183
CAN_TypeDef
Controller Area Network.
Definition: stm32f4xx.h:602
TIM8_TRG_COM_TIM14_IRQn
Definition: stm32f4xx.h:233
I2C3_EV_IRQn
Definition: stm32f4xx.h:260
DMA2D_TypeDef
DMA2D Controller.
Definition: stm32f4xx.h:720
FLASH_IRQn
Definition: stm32f4xx.h:190
DMA1_Stream3_IRQn
Definition: stm32f4xx.h:200
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f4xx.h:531
CAN2_RX1_IRQn
Definition: stm32f4xx.h:253
SAI_TypeDef
Serial Audio Interface.
Definition: stm32f4xx.h:1208
DMA2_Stream6_IRQn
Definition: stm32f4xx.h:257
uc8
const uint8_t uc8
Definition: stm32f4xx.h:502
FSMC_Bank2_TypeDef
Flexible Static Memory Controller Bank2.
Definition: stm32f4xx.h:873
DMA2_Stream1_IRQn
Definition: stm32f4xx.h:245
IRQn_Type
enum IRQn IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f4xx.h:568
ETH_TypeDef
Ethernet MAC.
Definition: stm32f4xx.h:751
CAN2_SCE_IRQn
Definition: stm32f4xx.h:254
uc32
const uint32_t uc32
Definition: stm32f4xx.h:500
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f4xx.h:1327
TIM_TypeDef
TIM.
Definition: stm32f4xx.h:1283
OTG_HS_EP1_IN_IRQn
Definition: stm32f4xx.h:263
CAN1_TX_IRQn
Definition: stm32f4xx.h:207
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f4xx.h:698
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f4xx.h:645
FLASH_TypeDef
FLASH Registers.
Definition: stm32f4xx.h:839
PWR_TypeDef
Power Control.
Definition: stm32f4xx.h:1108
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f4xx.h:1048
EXTI2_IRQn
Definition: stm32f4xx.h:194
EXTI4_IRQn
Definition: stm32f4xx.h:196
RTC_WKUP_IRQn
Definition: stm32f4xx.h:189
uc16
const uint16_t uc16
Definition: stm32f4xx.h:501
ADC_Common_TypeDef
Definition: stm32f4xx.h:555
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f4xx.h:1118
SPI1_IRQn
Definition: stm32f4xx.h:223
DMA2_Stream3_IRQn
Definition: stm32f4xx.h:247
vuc16
__I uint16_t vuc16
Definition: stm32f4xx.h:509
I2C1_ER_IRQn
Definition: stm32f4xx.h:220
TIM2_IRQn
Definition: stm32f4xx.h:216
RCC_IRQn
Definition: stm32f4xx.h:191
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f4xx.h:592
vsc16
__I int16_t vsc16
Definition: stm32f4xx.h:493
EXTI1_IRQn
Definition: stm32f4xx.h:193
CRYP_IRQn
Definition: stm32f4xx.h:267
EXTI3_IRQn
Definition: stm32f4xx.h:195
DMA1_Stream5_IRQn
Definition: stm32f4xx.h:202
RTC_TypeDef
Real-Time Clock.
Definition: stm32f4xx.h:1159
DCMI_TypeDef
DCMI.
Definition: stm32f4xx.h:679
UART4_IRQn
Definition: stm32f4xx.h:240
WWDG_IRQn
Definition: stm32f4xx.h:186
FSMC_Bank1E_TypeDef
Flexible Static Memory Controller Bank1E.
Definition: stm32f4xx.h:864
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f4xx.h:1020
ADC_IRQn
Definition: stm32f4xx.h:204
DMA1_Stream0_IRQn
Definition: stm32f4xx.h:197
RNG_TypeDef
RNG.
Definition: stm32f4xx.h:1429
HASH_TypeDef
HASH.
Definition: stm32f4xx.h:1404
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f4xx.h:667
TIM5_IRQn
Definition: stm32f4xx.h:238
TIM1_CC_IRQn
Definition: stm32f4xx.h:215
sc8
const int8_t sc8
Definition: stm32f4xx.h:486
SAI_Block_TypeDef
Definition: stm32f4xx.h:1213
EXTI9_5_IRQn
Definition: stm32f4xx.h:211
TAMP_STAMP_IRQn
Definition: stm32f4xx.h:188
EXTI15_10_IRQn
Definition: stm32f4xx.h:228
CRYP_TypeDef
Crypto Processor.
Definition: stm32f4xx.h:1360
TIM3_IRQn
Definition: stm32f4xx.h:217
I2C2_EV_IRQn
Definition: stm32f4xx.h:221
vuc8
__I uint8_t vuc8
Definition: stm32f4xx.h:510
SDIO_TypeDef
SD host Interface.
Definition: stm32f4xx.h:1229
I2C3_ER_IRQn
Definition: stm32f4xx.h:261
OTG_HS_IRQn
Definition: stm32f4xx.h:265
NonMaskableInt_IRQn
Definition: stm32f4xx.h:177
TIM6_DAC_IRQn
Definition: stm32f4xx.h:242
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f4xx.h:214
DMA2_Stream0_IRQn
Definition: stm32f4xx.h:244
FSMC_Bank4_TypeDef
Flexible Static Memory Controller Bank4.
Definition: stm32f4xx.h:901
SysTick_IRQn
Definition: stm32f4xx.h:184
sc32
const int32_t sc32
Definition: stm32f4xx.h:484
Generated on Sun May 10 2015 15:15:17 for discoverpixy by   doxygen 1.8.9.1