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Updated pheriph driver to 1.4

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This commit is contained in:
t-moe
2015-03-02 20:01:54 +01:00
parent cc41f75734
commit 6967573645
73 changed files with 16674 additions and 5575 deletions
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6
README.md
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@@ -1,6 +1,10 @@
BFH carme-m4 linuxsupport BFH stm32f4 discovery linuxsupport
============================ ============================
#TODO
Adjust this readme
## Synopsis ## Synopsis
The following project consists of a minimal setup for the carme-m4 STM32F407 board. The makefile should be easily adaptable to your needs. The following project consists of a minimal setup for the carme-m4 STM32F407 board. The makefile should be easily adaptable to your needs.

814
example/libs/StmCoreNPheriph/inc/core_cm4.h
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File diff suppressed because it is too large Load Diff

344
example/libs/StmCoreNPheriph/inc/core_cm4_simd.h
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@@ -1,29 +1,43 @@
/**************************************************************************//** /**************************************************************************//**
* @file core_cm4_simd.h * @file core_cm4_simd.h
* @brief CMSIS Cortex-M4 SIMD Header File * @brief CMSIS Cortex-M4 SIMD Header File
* @version V2.10 * @version V3.20
* @date 19. July 2011 * @date 25. February 2013
* *
* @note * @note
* Copyright (C) 2010-2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
* *
******************************************************************************/ ******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#ifndef __CORE_CM4_SIMD_H #ifndef __CORE_CM4_SIMD_H
#define __CORE_CM4_SIMD_H #define __CORE_CM4_SIMD_H
@@ -43,7 +57,7 @@
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */ /* ARM armcc specific functions */
/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/ /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
#define __SADD8 __sadd8 #define __SADD8 __sadd8
#define __QADD8 __qadd8 #define __QADD8 __qadd8
#define __SHADD8 __shadd8 #define __SHADD8 __shadd8
@@ -110,6 +124,8 @@
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32) ) >> 32))
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
@@ -118,70 +134,18 @@
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */ /* IAR iccarm specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
#include <cmsis_iar.h> #include <cmsis_iar.h>
/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/ /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
/* intrinsic __SADD8 see intrinsics.h */
/* intrinsic __QADD8 see intrinsics.h */
/* intrinsic __SHADD8 see intrinsics.h */
/* intrinsic __UADD8 see intrinsics.h */ #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* intrinsic __UQADD8 see intrinsics.h */ /* TI CCS specific functions */
/* intrinsic __UHADD8 see intrinsics.h */
/* intrinsic __SSUB8 see intrinsics.h */ /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
/* intrinsic __QSUB8 see intrinsics.h */ #include <cmsis_ccs.h>
/* intrinsic __SHSUB8 see intrinsics.h */
/* intrinsic __USUB8 see intrinsics.h */
/* intrinsic __UQSUB8 see intrinsics.h */
/* intrinsic __UHSUB8 see intrinsics.h */
/* intrinsic __SADD16 see intrinsics.h */
/* intrinsic __QADD16 see intrinsics.h */
/* intrinsic __SHADD16 see intrinsics.h */
/* intrinsic __UADD16 see intrinsics.h */
/* intrinsic __UQADD16 see intrinsics.h */
/* intrinsic __UHADD16 see intrinsics.h */
/* intrinsic __SSUB16 see intrinsics.h */
/* intrinsic __QSUB16 see intrinsics.h */
/* intrinsic __SHSUB16 see intrinsics.h */
/* intrinsic __USUB16 see intrinsics.h */
/* intrinsic __UQSUB16 see intrinsics.h */
/* intrinsic __UHSUB16 see intrinsics.h */
/* intrinsic __SASX see intrinsics.h */
/* intrinsic __QASX see intrinsics.h */
/* intrinsic __SHASX see intrinsics.h */
/* intrinsic __UASX see intrinsics.h */
/* intrinsic __UQASX see intrinsics.h */
/* intrinsic __UHASX see intrinsics.h */
/* intrinsic __SSAX see intrinsics.h */
/* intrinsic __QSAX see intrinsics.h */
/* intrinsic __SHSAX see intrinsics.h */
/* intrinsic __USAX see intrinsics.h */
/* intrinsic __UQSAX see intrinsics.h */
/* intrinsic __UHSAX see intrinsics.h */
/* intrinsic __USAD8 see intrinsics.h */
/* intrinsic __USADA8 see intrinsics.h */
/* intrinsic __SSAT16 see intrinsics.h */
/* intrinsic __USAT16 see intrinsics.h */
/* intrinsic __UXTB16 see intrinsics.h */
/* intrinsic __SXTB16 see intrinsics.h */
/* intrinsic __UXTAB16 see intrinsics.h */
/* intrinsic __SXTAB16 see intrinsics.h */
/* intrinsic __SMUAD see intrinsics.h */
/* intrinsic __SMUADX see intrinsics.h */
/* intrinsic __SMLAD see intrinsics.h */
/* intrinsic __SMLADX see intrinsics.h */
/* intrinsic __SMLALD see intrinsics.h */
/* intrinsic __SMLALDX see intrinsics.h */
/* intrinsic __SMUSD see intrinsics.h */
/* intrinsic __SMUSDX see intrinsics.h */
/* intrinsic __SMLSD see intrinsics.h */
/* intrinsic __SMLSDX see intrinsics.h */
/* intrinsic __SMLSLD see intrinsics.h */
/* intrinsic __SMLSLDX see intrinsics.h */
/* intrinsic __SEL see intrinsics.h */
/* intrinsic __QADD see intrinsics.h */
/* intrinsic __QSUB see intrinsics.h */
/* intrinsic __PKHBT see intrinsics.h */
/* intrinsic __PKHTB see intrinsics.h */
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
@@ -191,308 +155,308 @@
/* GNU gcc specific functions */ /* GNU gcc specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result); return(result);
} }
@@ -503,7 +467,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \ __RES; \
}) })
#define __USAT16(ARG1,ARG2) \ #define __USAT16(ARG1,ARG2) \
({ \ ({ \
uint32_t __RES, __ARG1 = (ARG1); \ uint32_t __RES, __ARG1 = (ARG1); \
@@ -511,66 +475,66 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op
__RES; \ __RES; \
}) })
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result); return(result);
} }
@@ -589,34 +553,34 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t o
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
}) })
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result); return(result);
} }
@@ -635,15 +599,15 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t o
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
}) })
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
@@ -651,10 +615,10 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1,
return(result); return(result);
} }
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result); return(result);
} }
@@ -671,11 +635,19 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1,
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
if (ARG3 == 0) \ if (ARG3 == 0) \
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
else \ else \
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \ __RES; \
}) })
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/

183
example/libs/StmCoreNPheriph/inc/core_cmFunc.h
View File

@@ -1,32 +1,46 @@
/**************************************************************************//** /**************************************************************************//**
* @file core_cmFunc.h * @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File * @brief CMSIS Cortex-M Core Function Access Header File
* @version V2.10 * @version V3.20
* @date 26. July 2011 * @date 25. February 2013
* *
* @note * @note
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
* *
******************************************************************************/ ******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMFUNC_H #ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H #define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */ /* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface /** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{ @{
*/ */
@@ -47,7 +61,7 @@
\return Control Register value \return Control Register value
*/ */
static __INLINE uint32_t __get_CONTROL(void) __STATIC_INLINE uint32_t __get_CONTROL(void)
{ {
register uint32_t __regControl __ASM("control"); register uint32_t __regControl __ASM("control");
return(__regControl); return(__regControl);
@@ -60,20 +74,20 @@ static __INLINE uint32_t __get_CONTROL(void)
\param [in] control Control Register value to set \param [in] control Control Register value to set
*/ */
static __INLINE void __set_CONTROL(uint32_t control) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{ {
register uint32_t __regControl __ASM("control"); register uint32_t __regControl __ASM("control");
__regControl = control; __regControl = control;
} }
/** \brief Get ISPR Register /** \brief Get IPSR Register
This function returns the content of the ISPR Register. This function returns the content of the IPSR Register.
\return ISPR Register value \return IPSR Register value
*/ */
static __INLINE uint32_t __get_IPSR(void) __STATIC_INLINE uint32_t __get_IPSR(void)
{ {
register uint32_t __regIPSR __ASM("ipsr"); register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR); return(__regIPSR);
@@ -86,7 +100,7 @@ static __INLINE uint32_t __get_IPSR(void)
\return APSR Register value \return APSR Register value
*/ */
static __INLINE uint32_t __get_APSR(void) __STATIC_INLINE uint32_t __get_APSR(void)
{ {
register uint32_t __regAPSR __ASM("apsr"); register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR); return(__regAPSR);
@@ -99,7 +113,7 @@ static __INLINE uint32_t __get_APSR(void)
\return xPSR Register value \return xPSR Register value
*/ */
static __INLINE uint32_t __get_xPSR(void) __STATIC_INLINE uint32_t __get_xPSR(void)
{ {
register uint32_t __regXPSR __ASM("xpsr"); register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR); return(__regXPSR);
@@ -112,7 +126,7 @@ static __INLINE uint32_t __get_xPSR(void)
\return PSP Register value \return PSP Register value
*/ */
static __INLINE uint32_t __get_PSP(void) __STATIC_INLINE uint32_t __get_PSP(void)
{ {
register uint32_t __regProcessStackPointer __ASM("psp"); register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer); return(__regProcessStackPointer);
@@ -125,7 +139,7 @@ static __INLINE uint32_t __get_PSP(void)
\param [in] topOfProcStack Process Stack Pointer value to set \param [in] topOfProcStack Process Stack Pointer value to set
*/ */
static __INLINE void __set_PSP(uint32_t topOfProcStack) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{ {
register uint32_t __regProcessStackPointer __ASM("psp"); register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack; __regProcessStackPointer = topOfProcStack;
@@ -138,7 +152,7 @@ static __INLINE void __set_PSP(uint32_t topOfProcStack)
\return MSP Register value \return MSP Register value
*/ */
static __INLINE uint32_t __get_MSP(void) __STATIC_INLINE uint32_t __get_MSP(void)
{ {
register uint32_t __regMainStackPointer __ASM("msp"); register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer); return(__regMainStackPointer);
@@ -151,7 +165,7 @@ static __INLINE uint32_t __get_MSP(void)
\param [in] topOfMainStack Main Stack Pointer value to set \param [in] topOfMainStack Main Stack Pointer value to set
*/ */
static __INLINE void __set_MSP(uint32_t topOfMainStack) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{ {
register uint32_t __regMainStackPointer __ASM("msp"); register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack; __regMainStackPointer = topOfMainStack;
@@ -164,7 +178,7 @@ static __INLINE void __set_MSP(uint32_t topOfMainStack)
\return Priority Mask value \return Priority Mask value
*/ */
static __INLINE uint32_t __get_PRIMASK(void) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{ {
register uint32_t __regPriMask __ASM("primask"); register uint32_t __regPriMask __ASM("primask");
return(__regPriMask); return(__regPriMask);
@@ -177,12 +191,12 @@ static __INLINE uint32_t __get_PRIMASK(void)
\param [in] priMask Priority Mask \param [in] priMask Priority Mask
*/ */
static __INLINE void __set_PRIMASK(uint32_t priMask) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{ {
register uint32_t __regPriMask __ASM("primask"); register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask); __regPriMask = (priMask);
} }
#if (__CORTEX_M >= 0x03) #if (__CORTEX_M >= 0x03)
@@ -208,7 +222,7 @@ static __INLINE void __set_PRIMASK(uint32_t priMask)
\return Base Priority register value \return Base Priority register value
*/ */
static __INLINE uint32_t __get_BASEPRI(void) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{ {
register uint32_t __regBasePri __ASM("basepri"); register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri); return(__regBasePri);
@@ -221,12 +235,12 @@ static __INLINE uint32_t __get_BASEPRI(void)
\param [in] basePri Base Priority value to set \param [in] basePri Base Priority value to set
*/ */
static __INLINE void __set_BASEPRI(uint32_t basePri) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{ {
register uint32_t __regBasePri __ASM("basepri"); register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff); __regBasePri = (basePri & 0xff);
} }
/** \brief Get Fault Mask /** \brief Get Fault Mask
@@ -234,7 +248,7 @@ static __INLINE void __set_BASEPRI(uint32_t basePri)
\return Fault Mask register value \return Fault Mask register value
*/ */
static __INLINE uint32_t __get_FAULTMASK(void) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{ {
register uint32_t __regFaultMask __ASM("faultmask"); register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask); return(__regFaultMask);
@@ -247,7 +261,7 @@ static __INLINE uint32_t __get_FAULTMASK(void)
\param [in] faultMask Fault Mask value to set \param [in] faultMask Fault Mask value to set
*/ */
static __INLINE void __set_FAULTMASK(uint32_t faultMask) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{ {
register uint32_t __regFaultMask __ASM("faultmask"); register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1); __regFaultMask = (faultMask & (uint32_t)1);
@@ -264,7 +278,7 @@ static __INLINE void __set_FAULTMASK(uint32_t faultMask)
\return Floating Point Status/Control register value \return Floating Point Status/Control register value
*/ */
static __INLINE uint32_t __get_FPSCR(void) __STATIC_INLINE uint32_t __get_FPSCR(void)
{ {
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr"); register uint32_t __regfpscr __ASM("fpscr");
@@ -281,7 +295,7 @@ static __INLINE uint32_t __get_FPSCR(void)
\param [in] fpscr Floating Point Status/Control value to set \param [in] fpscr Floating Point Status/Control value to set
*/ */
static __INLINE void __set_FPSCR(uint32_t fpscr) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{ {
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr"); register uint32_t __regfpscr __ASM("fpscr");
@@ -297,6 +311,13 @@ static __INLINE void __set_FPSCR(uint32_t fpscr)
#include <cmsis_iar.h> #include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */ /* GNU gcc specific functions */
@@ -305,9 +326,9 @@ static __INLINE void __set_FPSCR(uint32_t fpscr)
This function enables IRQ interrupts by clearing the I-bit in the CPSR. This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes. Can only be executed in Privileged modes.
*/ */
__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{ {
__ASM volatile ("cpsie i"); __ASM volatile ("cpsie i" : : : "memory");
} }
@@ -316,9 +337,9 @@ __attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
This function disables IRQ interrupts by setting the I-bit in the CPSR. This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes. Can only be executed in Privileged modes.
*/ */
__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{ {
__ASM volatile ("cpsid i"); __ASM volatile ("cpsid i" : : : "memory");
} }
@@ -328,7 +349,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
\return Control Register value \return Control Register value
*/ */
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{ {
uint32_t result; uint32_t result;
@@ -343,19 +364,19 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
\param [in] control Control Register value to set \param [in] control Control Register value to set
*/ */
__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control) __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{ {
__ASM volatile ("MSR control, %0" : : "r" (control) ); __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
} }
/** \brief Get ISPR Register /** \brief Get IPSR Register
This function returns the content of the ISPR Register. This function returns the content of the IPSR Register.
\return ISPR Register value \return IPSR Register value
*/ */
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{ {
uint32_t result; uint32_t result;
@@ -370,7 +391,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
\return APSR Register value \return APSR Register value
*/ */
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{ {
uint32_t result; uint32_t result;
@@ -385,7 +406,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
\return xPSR Register value \return xPSR Register value
*/ */
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{ {
uint32_t result; uint32_t result;
@@ -400,14 +421,14 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
\return PSP Register value \return PSP Register value
*/ */
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{ {
register uint32_t result; register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) ); __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result); return(result);
} }
/** \brief Set Process Stack Pointer /** \brief Set Process Stack Pointer
@@ -415,9 +436,9 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
\param [in] topOfProcStack Process Stack Pointer value to set \param [in] topOfProcStack Process Stack Pointer value to set
*/ */
__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack) __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{ {
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
} }
@@ -427,14 +448,14 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOf
\return MSP Register value \return MSP Register value
*/ */
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{ {
register uint32_t result; register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) ); __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result); return(result);
} }
/** \brief Set Main Stack Pointer /** \brief Set Main Stack Pointer
@@ -442,9 +463,9 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
\param [in] topOfMainStack Main Stack Pointer value to set \param [in] topOfMainStack Main Stack Pointer value to set
*/ */
__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack) __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{ {
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
} }
@@ -454,7 +475,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOf
\return Priority Mask value \return Priority Mask value
*/ */
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{ {
uint32_t result; uint32_t result;
@@ -469,11 +490,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
\param [in] priMask Priority Mask \param [in] priMask Priority Mask
*/ */
__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask) __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{ {
__ASM volatile ("MSR primask, %0" : : "r" (priMask) ); __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
} }
#if (__CORTEX_M >= 0x03) #if (__CORTEX_M >= 0x03)
@@ -482,9 +503,9 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t p
This function enables FIQ interrupts by clearing the F-bit in the CPSR. This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes. Can only be executed in Privileged modes.
*/ */
__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{ {
__ASM volatile ("cpsie f"); __ASM volatile ("cpsie f" : : : "memory");
} }
@@ -493,9 +514,9 @@ __attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
This function disables FIQ interrupts by setting the F-bit in the CPSR. This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes. Can only be executed in Privileged modes.
*/ */
__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void) __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{ {
__ASM volatile ("cpsid f"); __ASM volatile ("cpsid f" : : : "memory");
} }
@@ -505,10 +526,10 @@ __attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void
\return Base Priority register value \return Base Priority register value
*/ */
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result); return(result);
} }
@@ -520,9 +541,9 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
\param [in] basePri Base Priority value to set \param [in] basePri Base Priority value to set
*/ */
__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value) __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{ {
__ASM volatile ("MSR basepri, %0" : : "r" (value) ); __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
} }
@@ -532,10 +553,10 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t v
\return Fault Mask register value \return Fault Mask register value
*/ */
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) ); __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result); return(result);
} }
@@ -547,9 +568,9 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void
\param [in] faultMask Fault Mask value to set \param [in] faultMask Fault Mask value to set
*/ */
__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask) __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{ {
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
} }
#endif /* (__CORTEX_M >= 0x03) */ #endif /* (__CORTEX_M >= 0x03) */
@@ -563,12 +584,15 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t
\return Floating Point Status/Control register value \return Floating Point Status/Control register value
*/ */
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{ {
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result; uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result); return(result);
#else #else
return(0); return(0);
@@ -582,10 +606,13 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
\param [in] fpscr Floating Point Status/Control value to set \param [in] fpscr Floating Point Status/Control value to set
*/ */
__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr) __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{ {
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); /* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
#endif #endif
} }

243
example/libs/StmCoreNPheriph/inc/core_cmInstr.h
View File

@@ -1,25 +1,39 @@
/**************************************************************************//** /**************************************************************************//**
* @file core_cmInstr.h * @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File * @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V2.10 * @version V3.20
* @date 19. July 2011 * @date 05. March 2013
* *
* @note * @note
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
* *
******************************************************************************/ ******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMINSTR_H #ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H #define __CORE_CMINSTR_H
@@ -71,8 +85,8 @@
/** \brief Instruction Synchronization Barrier /** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor, Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed. memory, after the instruction has been completed.
*/ */
#define __ISB() __isb(0xF) #define __ISB() __isb(0xF)
@@ -80,7 +94,7 @@
/** \brief Data Synchronization Barrier /** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier. This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete. It completes when all explicit memory accesses before this instruction complete.
*/ */
#define __DSB() __dsb(0xF) #define __DSB() __dsb(0xF)
@@ -88,7 +102,7 @@
/** \brief Data Memory Barrier /** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion. and after the instruction, without ensuring their completion.
*/ */
#define __DMB() __dmb(0xF) #define __DMB() __dmb(0xF)
@@ -111,12 +125,13 @@
\param [in] value Value to reverse \param [in] value Value to reverse
\return Reversed value \return Reversed value
*/ */
static __INLINE __ASM uint32_t __REV16(uint32_t value) #ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{ {
rev16 r0, r0 rev16 r0, r0
bx lr bx lr
} }
#endif
/** \brief Reverse byte order in signed short value /** \brief Reverse byte order in signed short value
@@ -125,11 +140,35 @@ static __INLINE __ASM uint32_t __REV16(uint32_t value)
\param [in] value Value to reverse \param [in] value Value to reverse
\return Reversed value \return Reversed value
*/ */
static __INLINE __ASM int32_t __REVSH(int32_t value) #ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{ {
revsh r0, r0 revsh r0, r0
bx lr bx lr
} }
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03) #if (__CORTEX_M >= 0x03)
@@ -247,7 +286,7 @@ static __INLINE __ASM int32_t __REVSH(int32_t value)
\param [in] value Value to count the leading zeros \param [in] value Value to count the leading zeros
\return number of leading zeros in value \return number of leading zeros in value
*/ */
#define __CLZ __clz #define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */ #endif /* (__CORTEX_M >= 0x03) */
@@ -259,14 +298,31 @@ static __INLINE __ASM int32_t __REVSH(int32_t value)
#include <cmsis_iar.h> #include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */ /* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constrant "l"
* Otherwise, use general registers, specified by constrant "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/** \brief No Operation /** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes. No Operation does nothing. This instruction can be used for code alignment purposes.
*/ */
__attribute__( ( always_inline ) ) static __INLINE void __NOP(void) __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{ {
__ASM volatile ("nop"); __ASM volatile ("nop");
} }
@@ -277,7 +333,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
Wait For Interrupt is a hint instruction that suspends execution Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs. until one of a number of events occurs.
*/ */
__attribute__( ( always_inline ) ) static __INLINE void __WFI(void) __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{ {
__ASM volatile ("wfi"); __ASM volatile ("wfi");
} }
@@ -288,7 +344,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
Wait For Event is a hint instruction that permits the processor to enter Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs. a low-power state until one of a number of events occurs.
*/ */
__attribute__( ( always_inline ) ) static __INLINE void __WFE(void) __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{ {
__ASM volatile ("wfe"); __ASM volatile ("wfe");
} }
@@ -298,7 +354,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
Send Event is a hint instruction. It causes an event to be signaled to the CPU. Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/ */
__attribute__( ( always_inline ) ) static __INLINE void __SEV(void) __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{ {
__ASM volatile ("sev"); __ASM volatile ("sev");
} }
@@ -306,11 +362,11 @@ __attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
/** \brief Instruction Synchronization Barrier /** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor, Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed. memory, after the instruction has been completed.
*/ */
__attribute__( ( always_inline ) ) static __INLINE void __ISB(void) __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{ {
__ASM volatile ("isb"); __ASM volatile ("isb");
} }
@@ -318,10 +374,10 @@ __attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
/** \brief Data Synchronization Barrier /** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier. This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete. It completes when all explicit memory accesses before this instruction complete.
*/ */
__attribute__( ( always_inline ) ) static __INLINE void __DSB(void) __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{ {
__ASM volatile ("dsb"); __ASM volatile ("dsb");
} }
@@ -329,10 +385,10 @@ __attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
/** \brief Data Memory Barrier /** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion. and after the instruction, without ensuring their completion.
*/ */
__attribute__( ( always_inline ) ) static __INLINE void __DMB(void) __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{ {
__ASM volatile ("dmb"); __ASM volatile ("dmb");
} }
@@ -345,12 +401,16 @@ __attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
\param [in] value Value to reverse \param [in] value Value to reverse
\return Reversed value \return Reversed value
*/ */
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{ {
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result; uint32_t result;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result); return(result);
#endif
} }
@@ -361,11 +421,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value
\param [in] value Value to reverse \param [in] value Value to reverse
\return Reversed value \return Reversed value
*/ */
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result); return(result);
} }
@@ -377,15 +437,44 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t val
\param [in] value Value to reverse \param [in] value Value to reverse
\return Reversed value \return Reversed value
*/ */
__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value) __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{ {
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
#else
uint32_t result; uint32_t result;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result); return(result);
#endif
} }
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32 - op2));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#if (__CORTEX_M >= 0x03) #if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value /** \brief Reverse bit order of value
@@ -395,10 +484,10 @@ __attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value
\param [in] value Value to reverse \param [in] value Value to reverse
\return Reversed value \return Reversed value
*/ */
__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result); return(result);
} }
@@ -411,11 +500,18 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t valu
\param [in] ptr Pointer to data \param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr) \return value of type uint8_t at (*ptr)
*/ */
__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr) __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{ {
uint8_t result; uint32_t result;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result); return(result);
} }
@@ -427,11 +523,18 @@ __attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uin
\param [in] ptr Pointer to data \param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr) \return value of type uint16_t at (*ptr)
*/ */
__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr) __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{ {
uint16_t result; uint32_t result;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result); return(result);
} }
@@ -443,11 +546,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile ui
\param [in] ptr Pointer to data \param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr) \return value of type uint32_t at (*ptr)
*/ */
__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result); return(result);
} }
@@ -461,11 +564,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile ui
\return 0 Function succeeded \return 0 Function succeeded
\return 1 Function failed \return 1 Function failed
*/ */
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result); return(result);
} }
@@ -479,11 +582,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t val
\return 0 Function succeeded \return 0 Function succeeded
\return 1 Function failed \return 1 Function failed
*/ */
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result); return(result);
} }
@@ -497,11 +600,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t va
\return 0 Function succeeded \return 0 Function succeeded
\return 1 Function failed \return 1 Function failed
*/ */
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{ {
uint32_t result; uint32_t result;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result); return(result);
} }
@@ -511,9 +614,9 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t va
This function removes the exclusive lock which is created by LDREX. This function removes the exclusive lock which is created by LDREX.
*/ */
__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void) __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{ {
__ASM volatile ("clrex"); __ASM volatile ("clrex" ::: "memory");
} }
@@ -556,10 +659,10 @@ __attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
\param [in] value Value to count the leading zeros \param [in] value Value to count the leading zeros
\return number of leading zeros in value \return number of leading zeros in value
*/ */
__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value) __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{ {
uint8_t result; uint32_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result); return(result);
} }

26
example/libs/StmCoreNPheriph/inc/misc.h
View File

@@ -2,21 +2,27 @@
****************************************************************************** ******************************************************************************
* @file misc.h * @file misc.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the miscellaneous * @brief This file contains all the functions prototypes for the miscellaneous
* firmware library functions (add-on to CMSIS functions). * firmware library functions (add-on to CMSIS functions).
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -169,4 +175,4 @@ void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

3145
example/libs/StmCoreNPheriph/inc/stm32f4xx.h
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File diff suppressed because it is too large Load Diff

33
example/libs/StmCoreNPheriph/inc/stm32f4xx_adc.h
View File

@@ -2,21 +2,27 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_adc.h * @file stm32f4xx_adc.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the ADC firmware * @brief This file contains all the functions prototypes for the ADC firmware
* library. * library.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -319,7 +325,14 @@ typedef struct
#define ADC_Channel_17 ((uint8_t)0x11) #define ADC_Channel_17 ((uint8_t)0x11)
#define ADC_Channel_18 ((uint8_t)0x12) #define ADC_Channel_18 ((uint8_t)0x12)
#if defined (STM32F40_41xxx)
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) #define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
#endif /* STM32F40_41xxx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F411xE)
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_18)
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) #define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18) #define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18)
@@ -640,4 +653,4 @@ void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
example/libs/StmCoreNPheriph/inc/stm32f4xx_can.h
View File

@@ -2,21 +2,27 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_can.h * @file stm32f4xx_can.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the CAN firmware * @brief This file contains all the functions prototypes for the CAN firmware
* library. * library.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -635,4 +641,4 @@ void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

81
example/libs/StmCoreNPheriph/inc/stm32f4xx_conf.h
View File

@@ -1,54 +1,47 @@
/** /**
****************************************************************************** ******************************************************************************
* @file IO_Toggle/stm32f4xx_conf.h * @file Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_conf.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 19-September-2011 * @date 04-August-2014
* @brief Library configuration file. * @brief Library configuration file.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_CONF_H #ifndef __STM32F4xx_CONF_H
#define __STM32F4xx_CONF_H #define __STM32F4xx_CONF_H
#if defined (HSE_VALUE)
/* Redefine the HSE value; it's equal to 8 MHz on the STM32F4-DISCOVERY Kit */
#undef HSE_VALUE
#define HSE_VALUE ((uint32_t)8000000)
#endif /* HSE_VALUE */
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
/* Uncomment the line below to enable peripheral header file inclusion */ /* Uncomment the line below to enable peripheral header file inclusion */
#include "stm32f4xx_adc.h" #include "stm32f4xx_adc.h"
#include "stm32f4xx_can.h"
#include "stm32f4xx_crc.h" #include "stm32f4xx_crc.h"
#include "stm32f4xx_cryp.h"
#include "stm32f4xx_dac.h"
#include "stm32f4xx_dbgmcu.h" #include "stm32f4xx_dbgmcu.h"
#include "stm32f4xx_dcmi.h"
#include "stm32f4xx_dma.h" #include "stm32f4xx_dma.h"
#include "stm32f4xx_exti.h" #include "stm32f4xx_exti.h"
#include "stm32f4xx_flash.h" #include "stm32f4xx_flash.h"
#include "stm32f4xx_fsmc.h"
#include "stm32f4xx_hash.h"
#include "stm32f4xx_gpio.h" #include "stm32f4xx_gpio.h"
#include "stm32f4xx_i2c.h" #include "stm32f4xx_i2c.h"
#include "stm32f4xx_iwdg.h" #include "stm32f4xx_iwdg.h"
#include "stm32f4xx_pwr.h" #include "stm32f4xx_pwr.h"
#include "stm32f4xx_rcc.h" #include "stm32f4xx_rcc.h"
#include "stm32f4xx_rng.h"
#include "stm32f4xx_rtc.h" #include "stm32f4xx_rtc.h"
#include "stm32f4xx_sdio.h" #include "stm32f4xx_sdio.h"
#include "stm32f4xx_spi.h" #include "stm32f4xx_spi.h"
@@ -58,6 +51,44 @@
#include "stm32f4xx_wwdg.h" #include "stm32f4xx_wwdg.h"
#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
#if defined (STM32F429_439xx)
#include "stm32f4xx_cryp.h"
#include "stm32f4xx_hash.h"
#include "stm32f4xx_rng.h"
#include "stm32f4xx_can.h"
#include "stm32f4xx_dac.h"
#include "stm32f4xx_dcmi.h"
#include "stm32f4xx_dma2d.h"
#include "stm32f4xx_fmc.h"
#include "stm32f4xx_ltdc.h"
#include "stm32f4xx_sai.h"
#endif /* STM32F429_439xx */
#if defined (STM32F427_437xx)
#include "stm32f4xx_cryp.h"
#include "stm32f4xx_hash.h"
#include "stm32f4xx_rng.h"
#include "stm32f4xx_can.h"
#include "stm32f4xx_dac.h"
#include "stm32f4xx_dcmi.h"
#include "stm32f4xx_dma2d.h"
#include "stm32f4xx_fmc.h"
#include "stm32f4xx_sai.h"
#endif /* STM32F427_437xx */
#if defined (STM32F40_41xxx)
#include "stm32f4xx_cryp.h"
#include "stm32f4xx_hash.h"
#include "stm32f4xx_rng.h"
#include "stm32f4xx_can.h"
#include "stm32f4xx_dac.h"
#include "stm32f4xx_dcmi.h"
#include "stm32f4xx_fsmc.h"
#endif /* STM32F40_41xxx */
#if defined (STM32F411xE)
#include "stm32f4xx_flash_ramfunc.h"
#endif /* STM32F411xE */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
@@ -91,4 +122,4 @@
#endif /* __STM32F4xx_CONF_H */ #endif /* __STM32F4xx_CONF_H */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
example/libs/StmCoreNPheriph/inc/stm32f4xx_crc.h
View File

@@ -2,21 +2,27 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_crc.h * @file stm32f4xx_crc.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the CRC firmware * @brief This file contains all the functions prototypes for the CRC firmware
* library. * library.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -74,4 +80,4 @@ uint8_t CRC_GetIDRegister(void);
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

114
example/libs/StmCoreNPheriph/inc/stm32f4xx_cryp.h
View File

@@ -2,21 +2,27 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_cryp.h * @file stm32f4xx_cryp.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the Cryptographic * @brief This file contains all the functions prototypes for the Cryptographic
* processor(CRYP) firmware library. * processor(CRYP) firmware library.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -46,14 +52,14 @@
*/ */
typedef struct typedef struct
{ {
uint16_t CRYP_AlgoDir; /*!< Encrypt or Decrypt. This parameter can be a uint32_t CRYP_AlgoDir; /*!< Encrypt or Decrypt. This parameter can be a
value of @ref CRYP_Algorithm_Direction */ value of @ref CRYP_Algorithm_Direction */
uint16_t CRYP_AlgoMode; /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB, uint32_t CRYP_AlgoMode; /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB,
AES-CBC, AES-CTR, AES-Key. This parameter can be AES-CBC, AES-CTR, AES-Key, AES-GCM and AES-CCM.
a value of @ref CRYP_Algorithm_Mode */ This parameter can be a value of @ref CRYP_Algorithm_Mode */
uint16_t CRYP_DataType; /*!< 32-bit data, 16-bit data, bit data or bit-string. uint32_t CRYP_DataType; /*!< 32-bit data, 16-bit data, bit data or bit string.
This parameter can be a value of @ref CRYP_Data_Type */ This parameter can be a value of @ref CRYP_Data_Type */
uint16_t CRYP_KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit uint32_t CRYP_KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit
key length. This parameter can be a value of key length. This parameter can be a value of
@ref CRYP_Key_Size_for_AES_only */ @ref CRYP_Key_Size_for_AES_only */
}CRYP_InitTypeDef; }CRYP_InitTypeDef;
@@ -88,14 +94,14 @@ typedef struct
*/ */
typedef struct typedef struct
{ {
/*!< Configuration */ /*!< Current Configuration */
uint32_t CR_bits9to2; uint32_t CR_CurrentConfig;
/*!< KEY */ /*!< IV */
uint32_t CRYP_IV0LR; uint32_t CRYP_IV0LR;
uint32_t CRYP_IV0RR; uint32_t CRYP_IV0RR;
uint32_t CRYP_IV1LR; uint32_t CRYP_IV1LR;
uint32_t CRYP_IV1RR; uint32_t CRYP_IV1RR;
/*!< IV */ /*!< KEY */
uint32_t CRYP_K0LR; uint32_t CRYP_K0LR;
uint32_t CRYP_K0RR; uint32_t CRYP_K0RR;
uint32_t CRYP_K1LR; uint32_t CRYP_K1LR;
@@ -104,6 +110,8 @@ typedef struct
uint32_t CRYP_K2RR; uint32_t CRYP_K2RR;
uint32_t CRYP_K3LR; uint32_t CRYP_K3LR;
uint32_t CRYP_K3RR; uint32_t CRYP_K3RR;
uint32_t CRYP_CSGCMCCMR[8];
uint32_t CRYP_CSGCMR[8];
}CRYP_Context; }CRYP_Context;
@@ -130,31 +138,54 @@ typedef struct
*/ */
/*!< TDES Modes */ /*!< TDES Modes */
#define CRYP_AlgoMode_TDES_ECB ((uint16_t)0x0000) #define CRYP_AlgoMode_TDES_ECB ((uint32_t)0x00000000)
#define CRYP_AlgoMode_TDES_CBC ((uint16_t)0x0008) #define CRYP_AlgoMode_TDES_CBC ((uint32_t)0x00000008)
/*!< DES Modes */ /*!< DES Modes */
#define CRYP_AlgoMode_DES_ECB ((uint16_t)0x0010) #define CRYP_AlgoMode_DES_ECB ((uint32_t)0x00000010)
#define CRYP_AlgoMode_DES_CBC ((uint16_t)0x0018) #define CRYP_AlgoMode_DES_CBC ((uint32_t)0x00000018)
/*!< AES Modes */ /*!< AES Modes */
#define CRYP_AlgoMode_AES_ECB ((uint16_t)0x0020) #define CRYP_AlgoMode_AES_ECB ((uint32_t)0x00000020)
#define CRYP_AlgoMode_AES_CBC ((uint16_t)0x0028) #define CRYP_AlgoMode_AES_CBC ((uint32_t)0x00000028)
#define CRYP_AlgoMode_AES_CTR ((uint16_t)0x0030) #define CRYP_AlgoMode_AES_CTR ((uint32_t)0x00000030)
#define CRYP_AlgoMode_AES_Key ((uint16_t)0x0038) #define CRYP_AlgoMode_AES_Key ((uint32_t)0x00000038)
#define CRYP_AlgoMode_AES_GCM ((uint32_t)0x00080000)
#define CRYP_AlgoMode_AES_CCM ((uint32_t)0x00080008)
#define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \ #define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \
((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \ ((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \
((ALGOMODE) == CRYP_AlgoMode_DES_ECB)|| \ ((ALGOMODE) == CRYP_AlgoMode_DES_ECB) || \
((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \ ((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \
((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \ ((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \
((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \ ((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \
((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \ ((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \
((ALGOMODE) == CRYP_AlgoMode_AES_Key)) ((ALGOMODE) == CRYP_AlgoMode_AES_Key) || \
((ALGOMODE) == CRYP_AlgoMode_AES_GCM) || \
((ALGOMODE) == CRYP_AlgoMode_AES_CCM))
/** /**
* @} * @}
*/ */
/** @defgroup CRYP_Phase
* @{
*/
/*!< The phases are valid only for AES-GCM and AES-CCM modes */
#define CRYP_Phase_Init ((uint32_t)0x00000000)
#define CRYP_Phase_Header CRYP_CR_GCM_CCMPH_0
#define CRYP_Phase_Payload CRYP_CR_GCM_CCMPH_1
#define CRYP_Phase_Final CRYP_CR_GCM_CCMPH
#define IS_CRYP_PHASE(PHASE) (((PHASE) == CRYP_Phase_Init) || \
((PHASE) == CRYP_Phase_Header) || \
((PHASE) == CRYP_Phase_Payload) || \
((PHASE) == CRYP_Phase_Final))
/**
* @}
*/
/** @defgroup CRYP_Data_Type /** @defgroup CRYP_Data_Type
* @{ * @{
*/ */
@@ -260,23 +291,24 @@ void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct); void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);
void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct); void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);
void CRYP_Cmd(FunctionalState NewState); void CRYP_Cmd(FunctionalState NewState);
void CRYP_PhaseConfig(uint32_t CRYP_Phase);
void CRYP_FIFOFlush(void);
/* CRYP Data processing functions *********************************************/ /* CRYP Data processing functions *********************************************/
void CRYP_DataIn(uint32_t Data); void CRYP_DataIn(uint32_t Data);
uint32_t CRYP_DataOut(void); uint32_t CRYP_DataOut(void);
void CRYP_FIFOFlush(void);
/* CRYP Context swapping functions ********************************************/ /* CRYP Context swapping functions ********************************************/
ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave, ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave,
CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore); void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore);
/* CRYP's DMA interface function **********************************************/ /* CRYP DMA interface function ************************************************/
void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState); void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState);
/* Interrupts and flags management functions **********************************/ /* Interrupts and flags management functions **********************************/
void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState); void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState);
ITStatus CRYP_GetITStatus(uint8_t CRYP_IT); ITStatus CRYP_GetITStatus(uint8_t CRYP_IT);
FunctionalState CRYP_GetCmdStatus(void);
FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG); FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG);
/* High Level AES functions **************************************************/ /* High Level AES functions **************************************************/
@@ -297,6 +329,20 @@ ErrorStatus CRYP_AES_CTR(uint8_t Mode,
uint8_t *Input, uint32_t Ilength, uint8_t *Input, uint32_t Ilength,
uint8_t *Output); uint8_t *Output);
ErrorStatus CRYP_AES_GCM(uint8_t Mode, uint8_t InitVectors[16],
uint8_t *Key, uint16_t Keysize,
uint8_t *Input, uint32_t ILength,
uint8_t *Header, uint32_t HLength,
uint8_t *Output, uint8_t *AuthTAG);
ErrorStatus CRYP_AES_CCM(uint8_t Mode,
uint8_t* Nonce, uint32_t NonceSize,
uint8_t* Key, uint16_t Keysize,
uint8_t* Input, uint32_t ILength,
uint8_t* Header, uint32_t HLength, uint8_t *HBuffer,
uint8_t* Output,
uint8_t* AuthTAG, uint32_t TAGSize);
/* High Level TDES functions **************************************************/ /* High Level TDES functions **************************************************/
ErrorStatus CRYP_TDES_ECB(uint8_t Mode, ErrorStatus CRYP_TDES_ECB(uint8_t Mode,
uint8_t Key[24], uint8_t Key[24],
@@ -335,4 +381,4 @@ ErrorStatus CRYP_DES_CBC(uint8_t Mode,
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
example/libs/StmCoreNPheriph/inc/stm32f4xx_dac.h
View File

@@ -2,21 +2,27 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_dac.h * @file stm32f4xx_dac.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the DAC firmware * @brief This file contains all the functions prototypes for the DAC firmware
* library. * library.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -295,4 +301,4 @@ void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
example/libs/StmCoreNPheriph/inc/stm32f4xx_dbgmcu.h
View File

@@ -2,20 +2,26 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_dbgmcu.h * @file stm32f4xx_dbgmcu.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the DBGMCU firmware library. * @brief This file contains all the functions prototypes for the DBGMCU firmware library.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -100,4 +106,4 @@ void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
example/libs/StmCoreNPheriph/inc/stm32f4xx_dcmi.h
View File

@@ -2,20 +2,26 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_dcmi.h * @file stm32f4xx_dcmi.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the DCMI firmware library. * @brief This file contains all the functions prototypes for the DCMI firmware library.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -303,4 +309,4 @@ void DCMI_ClearITPendingBit(uint16_t DCMI_IT);
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

28
example/libs/StmCoreNPheriph/inc/stm32f4xx_dma.h
View File

@@ -2,21 +2,27 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_dma.h * @file stm32f4xx_dma.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the DMA firmware * @brief This file contains all the functions prototypes for the DMA firmware
* library. * library.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -393,7 +399,7 @@ typedef struct
#define DMA_FLAG_TCIF7 ((uint32_t)0x28000000) #define DMA_FLAG_TCIF7 ((uint32_t)0x28000000)
#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \ #define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \
(((FLAG) & 0xC082F082) == 0x00) && ((FLAG) != 0x00)) (((FLAG) & 0xC002F082) == 0x00) && ((FLAG) != 0x00))
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \ #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \
((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \ ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \
@@ -600,4 +606,4 @@ void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

475
example/libs/StmCoreNPheriph/inc/stm32f4xx_dma2d.h Normal file
View File

@@ -0,0 +1,475 @@
/**
******************************************************************************
* @file stm32f4xx_dma2d.h
* @author MCD Application Team
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the DMA2D firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_DMA2D_H
#define __STM32F4xx_DMA2D_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup DMA2D
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief DMA2D Init structure definition
*/
typedef struct
{
uint32_t DMA2D_Mode; /*!< configures the DMA2D transfer mode.
This parameter can be one value of @ref DMA2D_MODE */
uint32_t DMA2D_CMode; /*!< configures the color format of the output image.
This parameter can be one value of @ref DMA2D_CMODE */
uint32_t DMA2D_OutputBlue; /*!< configures the blue value of the output image.
This parameter must range:
- from 0x00 to 0xFF if ARGB8888 color mode is slected
- from 0x00 to 0xFF if RGB888 color mode is slected
- from 0x00 to 0x1F if RGB565 color mode is slected
- from 0x00 to 0x1F if ARGB1555 color mode is slected
- from 0x00 to 0x0F if ARGB4444 color mode is slected */
uint32_t DMA2D_OutputGreen; /*!< configures the green value of the output image.
This parameter must range:
- from 0x00 to 0xFF if ARGB8888 color mode is slected
- from 0x00 to 0xFF if RGB888 color mode is slected
- from 0x00 to 0x2F if RGB565 color mode is slected
- from 0x00 to 0x1F if ARGB1555 color mode is slected
- from 0x00 to 0x0F if ARGB4444 color mode is slected */
uint32_t DMA2D_OutputRed; /*!< configures the red value of the output image.
This parameter must range:
- from 0x00 to 0xFF if ARGB8888 color mode is slected
- from 0x00 to 0xFF if RGB888 color mode is slected
- from 0x00 to 0x1F if RGB565 color mode is slected
- from 0x00 to 0x1F if ARGB1555 color mode is slected
- from 0x00 to 0x0F if ARGB4444 color mode is slected */
uint32_t DMA2D_OutputAlpha; /*!< configures the alpha channel of the output color.
This parameter must range:
- from 0x00 to 0xFF if ARGB8888 color mode is slected
- from 0x00 to 0x01 if ARGB1555 color mode is slected
- from 0x00 to 0x0F if ARGB4444 color mode is slected */
uint32_t DMA2D_OutputMemoryAdd; /*!< Specifies the memory address. This parameter
must be range from 0x00000000 to 0xFFFFFFFF. */
uint32_t DMA2D_OutputOffset; /*!< Specifies the Offset value. This parameter must be range from
0x0000 to 0x3FFF. */
uint32_t DMA2D_NumberOfLine; /*!< Configures the number of line of the area to be transfered.
This parameter must range from 0x0000 to 0xFFFF */
uint32_t DMA2D_PixelPerLine; /*!< Configures the number pixel per line of the area to be transfered.
This parameter must range from 0x0000 to 0x3FFF */
} DMA2D_InitTypeDef;
typedef struct
{
uint32_t DMA2D_FGMA; /*!< configures the DMA2D foreground memory address.
This parameter must be range from 0x00000000 to 0xFFFFFFFF. */
uint32_t DMA2D_FGO; /*!< configures the DMA2D foreground offset.
This parameter must be range from 0x0000 to 0x3FFF. */
uint32_t DMA2D_FGCM; /*!< configures the DMA2D foreground color mode .
This parameter can be one value of @ref DMA2D_FGCM */
uint32_t DMA2D_FG_CLUT_CM; /*!< configures the DMA2D foreground CLUT color mode.
This parameter can be one value of @ref DMA2D_FG_CLUT_CM */
uint32_t DMA2D_FG_CLUT_SIZE; /*!< configures the DMA2D foreground CLUT size.
This parameter must range from 0x00 to 0xFF. */
uint32_t DMA2D_FGPFC_ALPHA_MODE; /*!< configures the DMA2D foreground alpha mode.
This parameter can be one value of @ref DMA2D_FGPFC_ALPHA_MODE */
uint32_t DMA2D_FGPFC_ALPHA_VALUE; /*!< Specifies the DMA2D foreground alpha value
must be range from 0x00 to 0xFF. */
uint32_t DMA2D_FGC_BLUE; /*!< Specifies the DMA2D foreground blue value
must be range from 0x00 to 0xFF. */
uint32_t DMA2D_FGC_GREEN; /*!< Specifies the DMA2D foreground green value
must be range from 0x00 to 0xFF. */
uint32_t DMA2D_FGC_RED; /*!< Specifies the DMA2D foreground red value
must be range from 0x00 to 0xFF. */
uint32_t DMA2D_FGCMAR; /*!< Configures the DMA2D foreground CLUT memory address.
This parameter must range from 0x00000000 to 0xFFFFFFFF. */
} DMA2D_FG_InitTypeDef;
typedef struct
{
uint32_t DMA2D_BGMA; /*!< configures the DMA2D background memory address.
This parameter must be range from 0x00000000 to 0xFFFFFFFF. */
uint32_t DMA2D_BGO; /*!< configures the DMA2D background offset.
This parameter must be range from 0x0000 to 0x3FFF. */
uint32_t DMA2D_BGCM; /*!< configures the DMA2D background color mode .
This parameter can be one value of @ref DMA2D_FGCM */
uint32_t DMA2D_BG_CLUT_CM; /*!< configures the DMA2D background CLUT color mode.
This parameter can be one value of @ref DMA2D_FG_CLUT_CM */
uint32_t DMA2D_BG_CLUT_SIZE; /*!< configures the DMA2D background CLUT size.
This parameter must range from 0x00 to 0xFF. */
uint32_t DMA2D_BGPFC_ALPHA_MODE; /*!< configures the DMA2D background alpha mode.
This parameter can be one value of @ref DMA2D_FGPFC_ALPHA_MODE */
uint32_t DMA2D_BGPFC_ALPHA_VALUE; /*!< Specifies the DMA2D background alpha value
must be range from 0x00 to 0xFF. */
uint32_t DMA2D_BGC_BLUE; /*!< Specifies the DMA2D background blue value
must be range from 0x00 to 0xFF. */
uint32_t DMA2D_BGC_GREEN; /*!< Specifies the DMA2D background green value
must be range from 0x00 to 0xFF. */
uint32_t DMA2D_BGC_RED; /*!< Specifies the DMA2D background red value
must be range from 0x00 to 0xFF. */
uint32_t DMA2D_BGCMAR; /*!< Configures the DMA2D background CLUT memory address.
This parameter must range from 0x00000000 to 0xFFFFFFFF. */
} DMA2D_BG_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMA2D_Exported_Constants
* @{
*/
/** @defgroup DMA2D_MODE
* @{
*/
#define DMA2D_M2M ((uint32_t)0x00000000)
#define DMA2D_M2M_PFC ((uint32_t)0x00010000)
#define DMA2D_M2M_BLEND ((uint32_t)0x00020000)
#define DMA2D_R2M ((uint32_t)0x00030000)
#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
/**
* @}
*/
/** @defgroup DMA2D_CMODE
* @{
*/
#define DMA2D_ARGB8888 ((uint32_t)0x00000000)
#define DMA2D_RGB888 ((uint32_t)0x00000001)
#define DMA2D_RGB565 ((uint32_t)0x00000002)
#define DMA2D_ARGB1555 ((uint32_t)0x00000003)
#define DMA2D_ARGB4444 ((uint32_t)0x00000004)
#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \
((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \
((MODE_ARGB) == DMA2D_ARGB4444))
/**
* @}
*/
/** @defgroup DMA2D_OUTPUT_COLOR
* @{
*/
#define DMA2D_Output_Color ((uint32_t)0x000000FF)
#define IS_DMA2D_OGREEN(OGREEN) ((OGREEN) <= DMA2D_Output_Color)
#define IS_DMA2D_ORED(ORED) ((ORED) <= DMA2D_Output_Color)
#define IS_DMA2D_OBLUE(OBLUE) ((OBLUE) <= DMA2D_Output_Color)
#define IS_DMA2D_OALPHA(OALPHA) ((OALPHA) <= DMA2D_Output_Color)
/**
* @}
*/
/** @defgroup DMA2D_OUTPUT_OFFSET
* @{
*/
#define DMA2D_OUTPUT_OFFSET ((uint32_t)0x00003FFF)
#define IS_DMA2D_OUTPUT_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OUTPUT_OFFSET)
/**
* @}
*/
/** @defgroup DMA2D_SIZE
* @{
*/
#define DMA2D_pixel ((uint32_t)0x00003FFF)
#define DMA2D_Line ((uint32_t)0x0000FFFF)
#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_Line)
#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_pixel)
/**
* @}
*/
/** @defgroup DMA2D_OFFSET
* @{
*/
#define OFFSET ((uint32_t)0x00003FFF)
#define IS_DMA2D_FGO(FGO) ((FGO) <= OFFSET)
#define IS_DMA2D_BGO(BGO) ((BGO) <= OFFSET)
/**
* @}
*/
/** @defgroup DMA2D_FGCM
* @{
*/
#define CM_ARGB8888 ((uint32_t)0x00000000)
#define CM_RGB888 ((uint32_t)0x00000001)
#define CM_RGB565 ((uint32_t)0x00000002)
#define CM_ARGB1555 ((uint32_t)0x00000003)
#define CM_ARGB4444 ((uint32_t)0x00000004)
#define CM_L8 ((uint32_t)0x00000005)
#define CM_AL44 ((uint32_t)0x00000006)
#define CM_AL88 ((uint32_t)0x00000007)
#define CM_L4 ((uint32_t)0x00000008)
#define CM_A8 ((uint32_t)0x00000009)
#define CM_A4 ((uint32_t)0x0000000A)
#define IS_DMA2D_FGCM(FGCM) (((FGCM) == CM_ARGB8888) || ((FGCM) == CM_RGB888) || \
((FGCM) == CM_RGB565) || ((FGCM) == CM_ARGB1555) || \
((FGCM) == CM_ARGB4444) || ((FGCM) == CM_L8) || \
((FGCM) == CM_AL44) || ((FGCM) == CM_AL88) || \
((FGCM) == CM_L4) || ((FGCM) == CM_A8) || \
((FGCM) == CM_A4))
#define IS_DMA2D_BGCM(BGCM) (((BGCM) == CM_ARGB8888) || ((BGCM) == CM_RGB888) || \
((BGCM) == CM_RGB565) || ((BGCM) == CM_ARGB1555) || \
((BGCM) == CM_ARGB4444) || ((BGCM) == CM_L8) || \
((BGCM) == CM_AL44) || ((BGCM) == CM_AL88) || \
((BGCM) == CM_L4) || ((BGCM) == CM_A8) || \
((BGCM) == CM_A4))
/**
* @}
*/
/** @defgroup DMA2D_FG_CLUT_CM
* @{
*/
#define CLUT_CM_ARGB8888 ((uint32_t)0x00000000)
#define CLUT_CM_RGB888 ((uint32_t)0x00000001)
#define IS_DMA2D_FG_CLUT_CM(FG_CLUT_CM) (((FG_CLUT_CM) == CLUT_CM_ARGB8888) || ((FG_CLUT_CM) == CLUT_CM_RGB888))
#define IS_DMA2D_BG_CLUT_CM(BG_CLUT_CM) (((BG_CLUT_CM) == CLUT_CM_ARGB8888) || ((BG_CLUT_CM) == CLUT_CM_RGB888))
/**
* @}
*/
/** @defgroup DMA2D_FG_COLOR_VALUE
* @{
*/
#define COLOR_VALUE ((uint32_t)0x000000FF)
#define IS_DMA2D_FG_CLUT_SIZE(FG_CLUT_SIZE) ((FG_CLUT_SIZE) <= COLOR_VALUE)
#define IS_DMA2D_FG_ALPHA_VALUE(FG_ALPHA_VALUE) ((FG_ALPHA_VALUE) <= COLOR_VALUE)
#define IS_DMA2D_FGC_BLUE(FGC_BLUE) ((FGC_BLUE) <= COLOR_VALUE)
#define IS_DMA2D_FGC_GREEN(FGC_GREEN) ((FGC_GREEN) <= COLOR_VALUE)
#define IS_DMA2D_FGC_RED(FGC_RED) ((FGC_RED) <= COLOR_VALUE)
#define IS_DMA2D_BG_CLUT_SIZE(BG_CLUT_SIZE) ((BG_CLUT_SIZE) <= COLOR_VALUE)
#define IS_DMA2D_BG_ALPHA_VALUE(BG_ALPHA_VALUE) ((BG_ALPHA_VALUE) <= COLOR_VALUE)
#define IS_DMA2D_BGC_BLUE(BGC_BLUE) ((BGC_BLUE) <= COLOR_VALUE)
#define IS_DMA2D_BGC_GREEN(BGC_GREEN) ((BGC_GREEN) <= COLOR_VALUE)
#define IS_DMA2D_BGC_RED(BGC_RED) ((BGC_RED) <= COLOR_VALUE)
/**
* @}
*/
/** DMA2D_FGPFC_ALPHA_MODE
* @{
*/
#define NO_MODIF_ALPHA_VALUE ((uint32_t)0x00000000)
#define REPLACE_ALPHA_VALUE ((uint32_t)0x00000001)
#define COMBINE_ALPHA_VALUE ((uint32_t)0x00000002)
#define IS_DMA2D_FG_ALPHA_MODE(FG_ALPHA_MODE) (((FG_ALPHA_MODE) == NO_MODIF_ALPHA_VALUE) || \
((FG_ALPHA_MODE) == REPLACE_ALPHA_VALUE) || \
((FG_ALPHA_MODE) == COMBINE_ALPHA_VALUE))
#define IS_DMA2D_BG_ALPHA_MODE(BG_ALPHA_MODE) (((BG_ALPHA_MODE) == NO_MODIF_ALPHA_VALUE) || \
((BG_ALPHA_MODE) == REPLACE_ALPHA_VALUE) || \
((BG_ALPHA_MODE) == COMBINE_ALPHA_VALUE))
/**
* @}
*/
/** @defgroup DMA2D_Interrupts
* @{
*/
#define DMA2D_IT_CE DMA2D_CR_CEIE
#define DMA2D_IT_CTC DMA2D_CR_CTCIE
#define DMA2D_IT_CAE DMA2D_CR_CAEIE
#define DMA2D_IT_TW DMA2D_CR_TWIE
#define DMA2D_IT_TC DMA2D_CR_TCIE
#define DMA2D_IT_TE DMA2D_CR_TEIE
#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
/**
* @}
*/
/** @defgroup DMA2D_Flag
* @{
*/
#define DMA2D_FLAG_CE DMA2D_ISR_CEIF
#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF
#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF
#define DMA2D_FLAG_TW DMA2D_ISR_TWIF
#define DMA2D_FLAG_TC DMA2D_ISR_TCIF
#define DMA2D_FLAG_TE DMA2D_ISR_TEIF
#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
/**
* @}
*/
/** @defgroup DMA2D_DeadTime
* @{
*/
#define DEADTIME ((uint32_t)0x000000FF)
#define IS_DMA2D_DEAD_TIME(DEAD_TIME) ((DEAD_TIME) <= DEADTIME)
#define LINE_WATERMARK DMA2D_LWR_LW
#define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the DMA2D configuration to the default reset state *****/
void DMA2D_DeInit(void);
/* Initialization and Configuration functions *********************************/
void DMA2D_Init(DMA2D_InitTypeDef* DMA2D_InitStruct);
void DMA2D_StructInit(DMA2D_InitTypeDef* DMA2D_InitStruct);
void DMA2D_StartTransfer(void);
void DMA2D_AbortTransfer(void);
void DMA2D_Suspend(FunctionalState NewState);
void DMA2D_FGConfig(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct);
void DMA2D_FG_StructInit(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct);
void DMA2D_BGConfig(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct);
void DMA2D_BG_StructInit(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct);
void DMA2D_FGStart(FunctionalState NewState);
void DMA2D_BGStart(FunctionalState NewState);
void DMA2D_DeadTimeConfig(uint32_t DMA2D_DeadTime, FunctionalState NewState);
void DMA2D_LineWatermarkConfig(uint32_t DMA2D_LWatermarkConfig);
/* Interrupts and flags management functions **********************************/
void DMA2D_ITConfig(uint32_t DMA2D_IT, FunctionalState NewState);
FlagStatus DMA2D_GetFlagStatus(uint32_t DMA2D_FLAG);
void DMA2D_ClearFlag(uint32_t DMA2D_FLAG);
ITStatus DMA2D_GetITStatus(uint32_t DMA2D_IT);
void DMA2D_ClearITPendingBit(uint32_t DMA2D_IT);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_DMA2D_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
example/libs/StmCoreNPheriph/inc/stm32f4xx_exti.h
View File

@@ -2,21 +2,27 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_exti.h * @file stm32f4xx_exti.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the EXTI firmware * @brief This file contains all the functions prototypes for the EXTI firmware
* library. * library.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -174,4 +180,4 @@ void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

326
example/libs/StmCoreNPheriph/inc/stm32f4xx_flash.h
View File

@@ -2,21 +2,27 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_flash.h * @file stm32f4xx_flash.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the FLASH * @brief This file contains all the functions prototypes for the FLASH
* firmware library. * firmware library.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -46,6 +52,7 @@
typedef enum typedef enum
{ {
FLASH_BUSY = 1, FLASH_BUSY = 1,
FLASH_ERROR_RD,
FLASH_ERROR_PGS, FLASH_ERROR_PGS,
FLASH_ERROR_PGP, FLASH_ERROR_PGP,
FLASH_ERROR_PGA, FLASH_ERROR_PGA,
@@ -64,23 +71,40 @@ typedef enum
/** @defgroup Flash_Latency /** @defgroup Flash_Latency
* @{ * @{
*/ */
#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */ #define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */
#define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */ #define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */
#define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */ #define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */
#define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */ #define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */
#define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */ #define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */
#define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */ #define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */
#define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */ #define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */
#define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */ #define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */
#define FLASH_Latency_8 ((uint8_t)0x0008) /*!< FLASH Eight Latency cycles */
#define FLASH_Latency_9 ((uint8_t)0x0009) /*!< FLASH Nine Latency cycles */
#define FLASH_Latency_10 ((uint8_t)0x000A) /*!< FLASH Ten Latency cycles */
#define FLASH_Latency_11 ((uint8_t)0x000B) /*!< FLASH Eleven Latency cycles */
#define FLASH_Latency_12 ((uint8_t)0x000C) /*!< FLASH Twelve Latency cycles */
#define FLASH_Latency_13 ((uint8_t)0x000D) /*!< FLASH Thirteen Latency cycles */
#define FLASH_Latency_14 ((uint8_t)0x000E) /*!< FLASH Fourteen Latency cycles */
#define FLASH_Latency_15 ((uint8_t)0x000F) /*!< FLASH Fifteen Latency cycles */
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
((LATENCY) == FLASH_Latency_1) || \ #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
((LATENCY) == FLASH_Latency_2) || \ ((LATENCY) == FLASH_Latency_1) || \
((LATENCY) == FLASH_Latency_3) || \ ((LATENCY) == FLASH_Latency_2) || \
((LATENCY) == FLASH_Latency_4) || \ ((LATENCY) == FLASH_Latency_3) || \
((LATENCY) == FLASH_Latency_5) || \ ((LATENCY) == FLASH_Latency_4) || \
((LATENCY) == FLASH_Latency_6) || \ ((LATENCY) == FLASH_Latency_5) || \
((LATENCY) == FLASH_Latency_7)) ((LATENCY) == FLASH_Latency_6) || \
((LATENCY) == FLASH_Latency_7) || \
((LATENCY) == FLASH_Latency_8) || \
((LATENCY) == FLASH_Latency_9) || \
((LATENCY) == FLASH_Latency_10) || \
((LATENCY) == FLASH_Latency_11) || \
((LATENCY) == FLASH_Latency_12) || \
((LATENCY) == FLASH_Latency_13) || \
((LATENCY) == FLASH_Latency_14) || \
((LATENCY) == FLASH_Latency_15))
/** /**
* @} * @}
*/ */
@@ -96,34 +120,72 @@ typedef enum
#define IS_VOLTAGERANGE(RANGE)(((RANGE) == VoltageRange_1) || \ #define IS_VOLTAGERANGE(RANGE)(((RANGE) == VoltageRange_1) || \
((RANGE) == VoltageRange_2) || \ ((RANGE) == VoltageRange_2) || \
((RANGE) == VoltageRange_3) || \ ((RANGE) == VoltageRange_3) || \
((RANGE) == VoltageRange_4)) ((RANGE) == VoltageRange_4))
/** /**
* @} * @}
*/ */
/** @defgroup FLASH_Sectors /** @defgroup FLASH_Sectors
* @{ * @{
*/ */
#define FLASH_Sector_0 ((uint16_t)0x0000) /*!< Sector Number 0 */ #define FLASH_Sector_0 ((uint16_t)0x0000) /*!< Sector Number 0 */
#define FLASH_Sector_1 ((uint16_t)0x0008) /*!< Sector Number 1 */ #define FLASH_Sector_1 ((uint16_t)0x0008) /*!< Sector Number 1 */
#define FLASH_Sector_2 ((uint16_t)0x0010) /*!< Sector Number 2 */ #define FLASH_Sector_2 ((uint16_t)0x0010) /*!< Sector Number 2 */
#define FLASH_Sector_3 ((uint16_t)0x0018) /*!< Sector Number 3 */ #define FLASH_Sector_3 ((uint16_t)0x0018) /*!< Sector Number 3 */
#define FLASH_Sector_4 ((uint16_t)0x0020) /*!< Sector Number 4 */ #define FLASH_Sector_4 ((uint16_t)0x0020) /*!< Sector Number 4 */
#define FLASH_Sector_5 ((uint16_t)0x0028) /*!< Sector Number 5 */ #define FLASH_Sector_5 ((uint16_t)0x0028) /*!< Sector Number 5 */
#define FLASH_Sector_6 ((uint16_t)0x0030) /*!< Sector Number 6 */ #define FLASH_Sector_6 ((uint16_t)0x0030) /*!< Sector Number 6 */
#define FLASH_Sector_7 ((uint16_t)0x0038) /*!< Sector Number 7 */ #define FLASH_Sector_7 ((uint16_t)0x0038) /*!< Sector Number 7 */
#define FLASH_Sector_8 ((uint16_t)0x0040) /*!< Sector Number 8 */ #define FLASH_Sector_8 ((uint16_t)0x0040) /*!< Sector Number 8 */
#define FLASH_Sector_9 ((uint16_t)0x0048) /*!< Sector Number 9 */ #define FLASH_Sector_9 ((uint16_t)0x0048) /*!< Sector Number 9 */
#define FLASH_Sector_10 ((uint16_t)0x0050) /*!< Sector Number 10 */ #define FLASH_Sector_10 ((uint16_t)0x0050) /*!< Sector Number 10 */
#define FLASH_Sector_11 ((uint16_t)0x0058) /*!< Sector Number 11 */ #define FLASH_Sector_11 ((uint16_t)0x0058) /*!< Sector Number 11 */
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_Sector_0) || ((SECTOR) == FLASH_Sector_1) ||\ #define FLASH_Sector_12 ((uint16_t)0x0080) /*!< Sector Number 12 */
((SECTOR) == FLASH_Sector_2) || ((SECTOR) == FLASH_Sector_3) ||\ #define FLASH_Sector_13 ((uint16_t)0x0088) /*!< Sector Number 13 */
((SECTOR) == FLASH_Sector_4) || ((SECTOR) == FLASH_Sector_5) ||\ #define FLASH_Sector_14 ((uint16_t)0x0090) /*!< Sector Number 14 */
((SECTOR) == FLASH_Sector_6) || ((SECTOR) == FLASH_Sector_7) ||\ #define FLASH_Sector_15 ((uint16_t)0x0098) /*!< Sector Number 15 */
((SECTOR) == FLASH_Sector_8) || ((SECTOR) == FLASH_Sector_9) ||\ #define FLASH_Sector_16 ((uint16_t)0x00A0) /*!< Sector Number 16 */
((SECTOR) == FLASH_Sector_10) || ((SECTOR) == FLASH_Sector_11)) #define FLASH_Sector_17 ((uint16_t)0x00A8) /*!< Sector Number 17 */
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\ #define FLASH_Sector_18 ((uint16_t)0x00B0) /*!< Sector Number 18 */
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) #define FLASH_Sector_19 ((uint16_t)0x00B8) /*!< Sector Number 19 */
#define FLASH_Sector_20 ((uint16_t)0x00C0) /*!< Sector Number 20 */
#define FLASH_Sector_21 ((uint16_t)0x00C8) /*!< Sector Number 21 */
#define FLASH_Sector_22 ((uint16_t)0x00D0) /*!< Sector Number 22 */
#define FLASH_Sector_23 ((uint16_t)0x00D8) /*!< Sector Number 23 */
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_Sector_0) || ((SECTOR) == FLASH_Sector_1) ||\
((SECTOR) == FLASH_Sector_2) || ((SECTOR) == FLASH_Sector_3) ||\
((SECTOR) == FLASH_Sector_4) || ((SECTOR) == FLASH_Sector_5) ||\
((SECTOR) == FLASH_Sector_6) || ((SECTOR) == FLASH_Sector_7) ||\
((SECTOR) == FLASH_Sector_8) || ((SECTOR) == FLASH_Sector_9) ||\
((SECTOR) == FLASH_Sector_10) || ((SECTOR) == FLASH_Sector_11) ||\
((SECTOR) == FLASH_Sector_12) || ((SECTOR) == FLASH_Sector_13) ||\
((SECTOR) == FLASH_Sector_14) || ((SECTOR) == FLASH_Sector_15) ||\
((SECTOR) == FLASH_Sector_16) || ((SECTOR) == FLASH_Sector_17) ||\
((SECTOR) == FLASH_Sector_18) || ((SECTOR) == FLASH_Sector_19) ||\
((SECTOR) == FLASH_Sector_20) || ((SECTOR) == FLASH_Sector_21) ||\
((SECTOR) == FLASH_Sector_22) || ((SECTOR) == FLASH_Sector_23))
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x081FFFFF)) ||\
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
#endif /* STM32F427_437xx || STM32F429_439xx */
#if defined (STM32F40_41xxx)
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x080FFFFF)) ||\
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
#endif /* STM32F40_41xxx */
#if defined (STM32F401xx)
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF)) ||\
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
#endif /* STM32F401xx */
#if defined (STM32F411xE)
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0807FFFF)) ||\
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
#endif /* STM32F411xE */
/** /**
* @} * @}
*/ */
@@ -131,18 +193,30 @@ typedef enum
/** @defgroup Option_Bytes_Write_Protection /** @defgroup Option_Bytes_Write_Protection
* @{ * @{
*/ */
#define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ #define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
#define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ #define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
#define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ #define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
#define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */ #define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
#define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */ #define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
#define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */ #define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
#define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */ #define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */
#define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */ #define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */
#define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */ #define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */
#define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */ #define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */
#define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */ #define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */
#define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */ #define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */
#define OB_WRP_Sector_12 ((uint32_t)0x00000001) /*!< Write protection of Sector12 */
#define OB_WRP_Sector_13 ((uint32_t)0x00000002) /*!< Write protection of Sector13 */
#define OB_WRP_Sector_14 ((uint32_t)0x00000004) /*!< Write protection of Sector14 */
#define OB_WRP_Sector_15 ((uint32_t)0x00000008) /*!< Write protection of Sector15 */
#define OB_WRP_Sector_16 ((uint32_t)0x00000010) /*!< Write protection of Sector16 */
#define OB_WRP_Sector_17 ((uint32_t)0x00000020) /*!< Write protection of Sector17 */
#define OB_WRP_Sector_18 ((uint32_t)0x00000040) /*!< Write protection of Sector18 */
#define OB_WRP_Sector_19 ((uint32_t)0x00000080) /*!< Write protection of Sector19 */
#define OB_WRP_Sector_20 ((uint32_t)0x00000100) /*!< Write protection of Sector20 */
#define OB_WRP_Sector_21 ((uint32_t)0x00000200) /*!< Write protection of Sector21 */
#define OB_WRP_Sector_22 ((uint32_t)0x00000400) /*!< Write protection of Sector22 */
#define OB_WRP_Sector_23 ((uint32_t)0x00000800) /*!< Write protection of Sector23 */
#define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */ #define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
#define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) #define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
@@ -150,6 +224,50 @@ typedef enum
* @} * @}
*/ */
/** @defgroup Selection_Protection_Mode
* @{
*/
#define OB_PcROP_Disable ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */
#define OB_PcROP_Enable ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i */
#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PcROP_Disable) || ((PCROP) == OB_PcROP_Enable))
/**
* @}
*/
/** @defgroup Option_Bytes_PC_ReadWrite_Protection
* @{
*/
#define OB_PCROP_Sector_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */
#define OB_PCROP_Sector_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */
#define OB_PCROP_Sector_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */
#define OB_PCROP_Sector_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */
#define OB_PCROP_Sector_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */
#define OB_PCROP_Sector_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */
#define OB_PCROP_Sector_6 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6 */
#define OB_PCROP_Sector_7 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7 */
#define OB_PCROP_Sector_8 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector8 */
#define OB_PCROP_Sector_9 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector9 */
#define OB_PCROP_Sector_10 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector10 */
#define OB_PCROP_Sector_11 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector11 */
#define OB_PCROP_Sector_12 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector12 */
#define OB_PCROP_Sector_13 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector13 */
#define OB_PCROP_Sector_14 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector14 */
#define OB_PCROP_Sector_15 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector15 */
#define OB_PCROP_Sector_16 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector16 */
#define OB_PCROP_Sector_17 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector17 */
#define OB_PCROP_Sector_18 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector18 */
#define OB_PCROP_Sector_19 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector19 */
#define OB_PCROP_Sector_20 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector20 */
#define OB_PCROP_Sector_21 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector21 */
#define OB_PCROP_Sector_22 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector22 */
#define OB_PCROP_Sector_23 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector23 */
#define OB_PCROP_Sector_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */
#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
/**
* @}
*/
/** @defgroup FLASH_Option_Bytes_Read_Protection /** @defgroup FLASH_Option_Bytes_Read_Protection
* @{ * @{
*/ */
@@ -207,6 +325,16 @@ typedef enum
/** /**
* @} * @}
*/ */
/** @defgroup FLASH_Dual_Boot
* @{
*/
#define OB_Dual_BootEnabled ((uint8_t)0x10) /*!< Dual Bank Boot Enable */
#define OB_Dual_BootDisabled ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */
#define IS_OB_BOOT(BOOT) (((BOOT) == OB_Dual_BootEnabled) || ((BOOT) == OB_Dual_BootDisabled))
/**
* @}
*/
/** @defgroup FLASH_Interrupts /** @defgroup FLASH_Interrupts
* @{ * @{
@@ -221,18 +349,19 @@ typedef enum
/** @defgroup FLASH_Flags /** @defgroup FLASH_Flags
* @{ * @{
*/ */
#define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */ #define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */
#define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */ #define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */
#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ #define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
#define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */ #define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */
#define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */ #define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */
#define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */ #define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */
#define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */ #define FLASH_FLAG_RDERR ((uint32_t)0x00000100) /*!< Read Protection error flag (PCROP) */
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF0C) == 0x00000000) && ((FLAG) != 0x00000000)) #define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \ #define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFE0C) == 0x00000000) && ((FLAG) != 0x00000000))
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \
((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \ ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \
((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \ ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \
((FLAG) == FLASH_FLAG_BSY)) ((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_RDERR))
/** /**
* @} * @}
*/ */
@@ -262,15 +391,30 @@ typedef enum
*/ */
/** /**
* @brief ACR register byte 0 (Bits[8:0]) base address * @brief ACR register byte 0 (Bits[7:0]) base address
*/ */
#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) #define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
/** /**
* @brief OPTCR register byte 3 (Bits[24:16]) base address * @brief OPTCR register byte 0 (Bits[7:0]) base address
*/ */
#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14) #define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14)
/**
* @brief OPTCR register byte 1 (Bits[15:8]) base address
*/
#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15) #define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)
/**
* @brief OPTCR register byte 2 (Bits[23:16]) base address
*/
#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16) #define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16)
/**
* @brief OPTCR register byte 3 (Bits[31:24]) base address
*/
#define OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17)
/**
* @brief OPTCR1 register byte 0 (Bits[7:0]) base address
*/
#define OPTCR1_BYTE2_ADDRESS ((uint32_t)0x40023C1A)
/** /**
* @} * @}
@@ -288,32 +432,42 @@ void FLASH_InstructionCacheReset(void);
void FLASH_DataCacheReset(void); void FLASH_DataCacheReset(void);
/* FLASH Memory Programming functions *****************************************/ /* FLASH Memory Programming functions *****************************************/
void FLASH_Unlock(void); void FLASH_Unlock(void);
void FLASH_Lock(void); void FLASH_Lock(void);
FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange); FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange);
FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange); FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange);
FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange);
FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange);
FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data); FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data);
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data); FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data);
/* Option Bytes Programming functions *****************************************/ /* Option Bytes Programming functions *****************************************/
void FLASH_OB_Unlock(void); void FLASH_OB_Unlock(void);
void FLASH_OB_Lock(void); void FLASH_OB_Lock(void);
void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
void FLASH_OB_RDPConfig(uint8_t OB_RDP); void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState);
void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP);
void FLASH_OB_BORConfig(uint8_t OB_BOR); void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState);
void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState);
void FLASH_OB_RDPConfig(uint8_t OB_RDP);
void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
void FLASH_OB_BORConfig(uint8_t OB_BOR);
void FLASH_OB_BootConfig(uint8_t OB_BOOT);
FLASH_Status FLASH_OB_Launch(void); FLASH_Status FLASH_OB_Launch(void);
uint8_t FLASH_OB_GetUser(void); uint8_t FLASH_OB_GetUser(void);
uint16_t FLASH_OB_GetWRP(void); uint16_t FLASH_OB_GetWRP(void);
FlagStatus FLASH_OB_GetRDP(void); uint16_t FLASH_OB_GetWRP1(void);
uint8_t FLASH_OB_GetBOR(void); uint16_t FLASH_OB_GetPCROP(void);
uint16_t FLASH_OB_GetPCROP1(void);
FlagStatus FLASH_OB_GetRDP(void);
uint8_t FLASH_OB_GetBOR(void);
/* Interrupts and flags management functions **********************************/ /* Interrupts and flags management functions **********************************/
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
void FLASH_ClearFlag(uint32_t FLASH_FLAG); void FLASH_ClearFlag(uint32_t FLASH_FLAG);
FLASH_Status FLASH_GetStatus(void); FLASH_Status FLASH_GetStatus(void);
FLASH_Status FLASH_WaitForLastOperation(void); FLASH_Status FLASH_WaitForLastOperation(void);
@@ -331,4 +485,4 @@ FLASH_Status FLASH_WaitForLastOperation(void);
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

103
example/libs/StmCoreNPheriph/inc/stm32f4xx_flash_ramfunc.h Normal file
View File

@@ -0,0 +1,103 @@
/**
******************************************************************************
* @file stm32f4xx_flash_ramfunc.h
* @author MCD Application Team
* @version V1.4.0
* @date 04-August-2014
* @brief Header file of FLASH RAMFUNC driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_FLASH_RAMFUNC_H
#define __STM32F4xx_FLASH_RAMFUNC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup FLASH RAMFUNC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/**
* @brief __RAM_FUNC definition
*/
#if defined ( __CC_ARM )
/* ARM Compiler
------------
RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
dialog.
*/
#define __RAM_FUNC void
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
RAM functions are defined using a specific toolchain keyword "__ramfunc".
*/
#define __RAM_FUNC __ramfunc void
#elif defined ( __GNUC__ )
/* GNU Compiler
------------
RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
*/
#define __RAM_FUNC void __attribute__((section(".RamFunc")))
#endif
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
__RAM_FUNC FLASH_FlashInterfaceCmd(FunctionalState NewState);
__RAM_FUNC FLASH_FlashSleepModeCmd(FunctionalState NewState);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_FLASH_RAMFUNC_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

44
example/libs/StmCoreNPheriph/inc/stm32f4xx_fsmc.h
View File

@@ -2,21 +2,27 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_fsmc.h * @file stm32f4xx_fsmc.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the FSMC firmware * @brief This file contains all the functions prototypes for the FSMC firmware
* library. * library.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -91,7 +97,7 @@ typedef struct
This parameter can be a value of @ref FSMC_NORSRAM_Bank */ This parameter can be a value of @ref FSMC_NORSRAM_Bank */
uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
multiplexed on the databus or not. multiplexed on the data bus or not.
This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
@@ -125,7 +131,7 @@ typedef struct
uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
This parameter can be a value of @ref FSMC_Write_Operation */ This parameter can be a value of @ref FSMC_Write_Operation */
uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait state insertion via wait
signal, valid for Flash memory access in burst mode. signal, valid for Flash memory access in burst mode.
This parameter can be a value of @ref FSMC_Wait_Signal */ This parameter can be a value of @ref FSMC_Wait_Signal */
@@ -135,9 +141,9 @@ typedef struct
uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
This parameter can be a value of @ref FSMC_Write_Burst */ This parameter can be a value of @ref FSMC_Write_Burst */
FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the Extended Mode is not used*/
FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the Extended Mode is used*/
}FSMC_NORSRAMInitTypeDef; }FSMC_NORSRAMInitTypeDef;
/** /**
@@ -146,26 +152,26 @@ typedef struct
typedef struct typedef struct
{ {
uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
the command assertion for NAND-Flash read or write access the command assertion for NAND Flash read or write access
to common/Attribute or I/O memory space (depending on to common/Attribute or I/O memory space (depending on
the memory space timing to be configured). the memory space timing to be configured).
This parameter can be a value between 0 and 0xFF.*/ This parameter can be a value between 0 and 0xFF.*/
uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
command for NAND-Flash read or write access to command for NAND Flash read or write access to
common/Attribute or I/O memory space (depending on the common/Attribute or I/O memory space (depending on the
memory space timing to be configured). memory space timing to be configured).
This parameter can be a number between 0x00 and 0xFF */ This parameter can be a number between 0x00 and 0xFF */
uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
(and data for write access) after the command deassertion (and data for write access) after the command de-assertion
for NAND-Flash read or write access to common/Attribute for NAND Flash read or write access to common/Attribute
or I/O memory space (depending on the memory space timing or I/O memory space (depending on the memory space timing
to be configured). to be configured).
This parameter can be a number between 0x00 and 0xFF */ This parameter can be a number between 0x00 and 0xFF */
uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
databus is kept in HiZ after the start of a NAND-Flash data bus is kept in HiZ after the start of a NAND Flash
write access to common/Attribute or I/O memory space (depending write access to common/Attribute or I/O memory space (depending
on the memory space timing to be configured). on the memory space timing to be configured).
This parameter can be a number between 0x00 and 0xFF */ This parameter can be a number between 0x00 and 0xFF */
@@ -666,4 +672,4 @@ void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

198
example/libs/StmCoreNPheriph/inc/stm32f4xx_gpio.h
View File

@@ -2,21 +2,27 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_gpio.h * @file stm32f4xx_gpio.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the GPIO firmware * @brief This file contains all the functions prototypes for the GPIO firmware
* library. * library.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -49,8 +55,10 @@
((PERIPH) == GPIOF) || \ ((PERIPH) == GPIOF) || \
((PERIPH) == GPIOG) || \ ((PERIPH) == GPIOG) || \
((PERIPH) == GPIOH) || \ ((PERIPH) == GPIOH) || \
((PERIPH) == GPIOI)) ((PERIPH) == GPIOI) || \
((PERIPH) == GPIOJ) || \
((PERIPH) == GPIOK))
/** /**
* @brief GPIO Configuration Mode enumeration * @brief GPIO Configuration Mode enumeration
*/ */
@@ -80,13 +88,20 @@ typedef enum
*/ */
typedef enum typedef enum
{ {
GPIO_Speed_2MHz = 0x00, /*!< Low speed */ GPIO_Low_Speed = 0x00, /*!< Low speed */
GPIO_Speed_25MHz = 0x01, /*!< Medium speed */ GPIO_Medium_Speed = 0x01, /*!< Medium speed */
GPIO_Speed_50MHz = 0x02, /*!< Fast speed */ GPIO_Fast_Speed = 0x02, /*!< Fast speed */
GPIO_Speed_100MHz = 0x03 /*!< High speed on 30 pF (80 MHz Output max speed on 15 pF) */ GPIO_High_Speed = 0x03 /*!< High speed */
}GPIOSpeed_TypeDef; }GPIOSpeed_TypeDef;
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_2MHz) || ((SPEED) == GPIO_Speed_25MHz) || \
((SPEED) == GPIO_Speed_50MHz)|| ((SPEED) == GPIO_Speed_100MHz)) /* Add legacy definition */
#define GPIO_Speed_2MHz GPIO_Low_Speed
#define GPIO_Speed_25MHz GPIO_Medium_Speed
#define GPIO_Speed_50MHz GPIO_Fast_Speed
#define GPIO_Speed_100MHz GPIO_High_Speed
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Low_Speed) || ((SPEED) == GPIO_Medium_Speed) || \
((SPEED) == GPIO_Fast_Speed)|| ((SPEED) == GPIO_High_Speed))
/** /**
* @brief GPIO Configuration PullUp PullDown enumeration * @brief GPIO Configuration PullUp PullDown enumeration
@@ -159,7 +174,8 @@ typedef struct
#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ #define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ #define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */
#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) #define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ #define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
((PIN) == GPIO_Pin_1) || \ ((PIN) == GPIO_Pin_1) || \
((PIN) == GPIO_Pin_2) || \ ((PIN) == GPIO_Pin_2) || \
@@ -264,38 +280,56 @@ typedef struct
/** /**
* @brief AF 5 selection * @brief AF 5 selection
*/ */
#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ #define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
#define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping (Only for STM32F411xE Devices) */
#define GPIO_AF_SPI4 ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */
#define GPIO_AF_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
#define GPIO_AF_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
/** /**
* @brief AF 6 selection * @brief AF 6 selection
*/ */
#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping (Only for STM32F411xE Devices) */
#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping (Only for STM32F411xE Devices) */
#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5 Alternate Function mapping (Only for STM32F411xE Devices) */
#define GPIO_AF_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
/** /**
* @brief AF 7 selection * @brief AF 7 selection
*/ */
#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ #define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ #define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ #define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
#define GPIO_AF_I2S3ext ((uint8_t)0x07) /* I2S3ext Alternate Function mapping */ #define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3ext Alternate Function mapping */
/**
* @brief AF 7 selection Legacy
*/
#define GPIO_AF_I2S3ext GPIO_AF7_SPI3
/** /**
* @brief AF 8 selection * @brief AF 8 selection
*/ */
#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ #define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ #define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ #define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
#define GPIO_AF_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */
#define GPIO_AF_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
/** /**
* @brief AF 9 selection * @brief AF 9 selection
*/ */
#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ #define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ #define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ #define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ #define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ #define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping (Only for STM32F401xx/STM32F411xE Devices) */
#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping (Only for STM32F401xx/STM32F411xE Devices) */
/** /**
* @brief AF 10 selection * @brief AF 10 selection
*/ */
@@ -310,38 +344,100 @@ typedef struct
/** /**
* @brief AF 12 selection * @brief AF 12 selection
*/ */
#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */ #if defined (STM32F40_41xxx)
#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */ #define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */
#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */ #endif /* STM32F40_41xxx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define GPIO_AF_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
#endif /* STM32F427_437xx || STM32F429_439xx */
#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
/** /**
* @brief AF 13 selection * @brief AF 13 selection
*/ */
#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ #define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
/**
* @brief AF 14 selection
*/
#define GPIO_AF_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */
/** /**
* @brief AF 15 selection * @brief AF 15 selection
*/ */
#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ #define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ #if defined (STM32F40_41xxx)
((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ #define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \ ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \ ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \
((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \ ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \
((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \
((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_FSMC) || \ ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
((AF) == GPIO_AF_OTG_HS_FS) || ((AF) == GPIO_AF_SDIO) || \ ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \
((AF) == GPIO_AF_DCMI) || ((AF) == GPIO_AF_EVENTOUT)) ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \
((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_FSMC))
#endif /* STM32F40_41xxx */
#if defined (STM32F401xx)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_USART6) || \
((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4))
#endif /* STM32F401xx */
#if defined (STM32F411xE)
#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 13) && ((AF) != 14))
#endif /* STM32F411xE */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \
((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \
((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \
((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \
((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \
((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4) || \
((AF) == GPIO_AF_SPI5) || ((AF) == GPIO_AF_SPI6) || \
((AF) == GPIO_AF_UART7) || ((AF) == GPIO_AF_UART8) || \
((AF) == GPIO_AF_FMC) || ((AF) == GPIO_AF_SAI1) || \
((AF) == GPIO_AF_LTDC))
#endif /* STM32F427_437xx || STM32F429_439xx */
/** /**
* @} * @}
*/ */
@@ -365,7 +461,7 @@ typedef struct
*/ */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/* Function used to set the GPIO configuration to the default reset state ****/ /* Function used to set the GPIO configuration to the default reset state ****/
void GPIO_DeInit(GPIO_TypeDef* GPIOx); void GPIO_DeInit(GPIO_TypeDef* GPIOx);
@@ -403,4 +499,4 @@ void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

93
example/libs/StmCoreNPheriph/inc/stm32f4xx_hash.h
View File

@@ -2,21 +2,27 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_hash.h * @file stm32f4xx_hash.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the HASH * @brief This file contains all the functions prototypes for the HASH
* firmware library. * firmware library.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -46,12 +52,12 @@
*/ */
typedef struct typedef struct
{ {
uint32_t HASH_AlgoSelection; /*!< SHA-1 or MD5. This parameter can be a value uint32_t HASH_AlgoSelection; /*!< SHA-1, SHA-224, SHA-256 or MD5. This parameter
of @ref HASH_Algo_Selection */ can be a value of @ref HASH_Algo_Selection */
uint32_t HASH_AlgoMode; /*!< HASH or HMAC. This parameter can be a value uint32_t HASH_AlgoMode; /*!< HASH or HMAC. This parameter can be a value
of @ref HASH_processor_Algorithm_Mode */ of @ref HASH_processor_Algorithm_Mode */
uint32_t HASH_DataType; /*!< 32-bit data, 16-bit data, 8-bit data or uint32_t HASH_DataType; /*!< 32-bit data, 16-bit data, 8-bit data or
bit-string. This parameter can be a value of bit string. This parameter can be a value of
@ref HASH_Data_Type */ @ref HASH_Data_Type */
uint32_t HASH_HMACKeyType; /*!< HMAC Short key or HMAC Long Key. This parameter uint32_t HASH_HMACKeyType; /*!< HMAC Short key or HMAC Long Key. This parameter
can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */ can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */
@@ -62,7 +68,9 @@ typedef struct
*/ */
typedef struct typedef struct
{ {
uint32_t Data[5]; /*!< Message digest result : 5x 32bit words for SHA1 or uint32_t Data[8]; /*!< Message digest result : 8x 32bit wors for SHA-256,
7x 32bit wors for SHA-224,
5x 32bit words for SHA-1 or
4x 32bit words for MD5 */ 4x 32bit words for MD5 */
} HASH_MsgDigest; } HASH_MsgDigest;
@@ -74,7 +82,7 @@ typedef struct
uint32_t HASH_IMR; uint32_t HASH_IMR;
uint32_t HASH_STR; uint32_t HASH_STR;
uint32_t HASH_CR; uint32_t HASH_CR;
uint32_t HASH_CSR[51]; uint32_t HASH_CSR[54];
}HASH_Context; }HASH_Context;
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
@@ -86,10 +94,14 @@ typedef struct
/** @defgroup HASH_Algo_Selection /** @defgroup HASH_Algo_Selection
* @{ * @{
*/ */
#define HASH_AlgoSelection_SHA1 ((uint16_t)0x0000) /*!< HASH function is SHA1 */ #define HASH_AlgoSelection_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */
#define HASH_AlgoSelection_MD5 ((uint16_t)0x0080) /*!< HASH function is MD5 */ #define HASH_AlgoSelection_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */
#define HASH_AlgoSelection_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */
#define HASH_AlgoSelection_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \ #define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \
((ALGOSELECTION) == HASH_AlgoSelection_SHA224) || \
((ALGOSELECTION) == HASH_AlgoSelection_SHA256) || \
((ALGOSELECTION) == HASH_AlgoSelection_MD5)) ((ALGOSELECTION) == HASH_AlgoSelection_MD5))
/** /**
* @} * @}
@@ -98,8 +110,8 @@ typedef struct
/** @defgroup HASH_processor_Algorithm_Mode /** @defgroup HASH_processor_Algorithm_Mode
* @{ * @{
*/ */
#define HASH_AlgoMode_HASH ((uint16_t)0x0000) /*!< Algorithm is HASH */ #define HASH_AlgoMode_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */
#define HASH_AlgoMode_HMAC ((uint16_t)0x0040) /*!< Algorithm is HMAC */ #define HASH_AlgoMode_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \ #define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \
((ALGOMODE) == HASH_AlgoMode_HMAC)) ((ALGOMODE) == HASH_AlgoMode_HMAC))
@@ -110,14 +122,14 @@ typedef struct
/** @defgroup HASH_Data_Type /** @defgroup HASH_Data_Type
* @{ * @{
*/ */
#define HASH_DataType_32b ((uint16_t)0x0000) #define HASH_DataType_32b ((uint32_t)0x0000) /*!< 32-bit data. No swapping */
#define HASH_DataType_16b ((uint16_t)0x0010) #define HASH_DataType_16b HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
#define HASH_DataType_8b ((uint16_t)0x0020) #define HASH_DataType_8b HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
#define HASH_DataType_1b ((uint16_t)0x0030) #define HASH_DataType_1b HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \ #define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \
((DATATYPE) == HASH_DataType_16b)|| \ ((DATATYPE) == HASH_DataType_16b)|| \
((DATATYPE) == HASH_DataType_8b)|| \ ((DATATYPE) == HASH_DataType_8b) || \
((DATATYPE) == HASH_DataType_1b)) ((DATATYPE) == HASH_DataType_1b))
/** /**
* @} * @}
@@ -127,10 +139,10 @@ typedef struct
* @{ * @{
*/ */
#define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */ #define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */
#define HASH_HMACKeyType_LongKey ((uint32_t)0x00010000) /*!< HMAC Key is > 64 bytes */ #define HASH_HMACKeyType_LongKey HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */
#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \ #define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \
((KEYTYPE) == HASH_HMACKeyType_LongKey)) ((KEYTYPE) == HASH_HMACKeyType_LongKey))
/** /**
* @} * @}
*/ */
@@ -147,10 +159,10 @@ typedef struct
/** @defgroup HASH_interrupts_definition /** @defgroup HASH_interrupts_definition
* @{ * @{
*/ */
#define HASH_IT_DINI ((uint8_t)0x01) /*!< A new block can be entered into the input buffer (DIN)*/ #define HASH_IT_DINI HASH_IMR_DINIM /*!< A new block can be entered into the input buffer (DIN) */
#define HASH_IT_DCI ((uint8_t)0x02) /*!< Digest calculation complete */ #define HASH_IT_DCI HASH_IMR_DCIM /*!< Digest calculation complete */
#define IS_HASH_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00)) #define IS_HASH_IT(IT) ((((IT) & (uint32_t)0xFFFFFFFC) == 0x00000000) && ((IT) != 0x00000000))
#define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI)) #define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI))
/** /**
@@ -160,11 +172,11 @@ typedef struct
/** @defgroup HASH_flags_definition /** @defgroup HASH_flags_definition
* @{ * @{
*/ */
#define HASH_FLAG_DINIS ((uint16_t)0x0001) /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer.*/ #define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */
#define HASH_FLAG_DCIS ((uint16_t)0x0002) /*!< Digest calculation complete */ #define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
#define HASH_FLAG_DMAS ((uint16_t)0x0004) /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */ #define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
#define HASH_FLAG_BUSY ((uint16_t)0x0008) /*!< The hash core is Busy : processing a block of data */ #define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy : processing a block of data */
#define HASH_FLAG_DINNE ((uint16_t)0x1000) /*!< DIN not empty : The input buffer contains at least one word of data */ #define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : The input buffer contains at least one word of data */
#define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \ #define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \
((FLAG) == HASH_FLAG_DCIS) || \ ((FLAG) == HASH_FLAG_DCIS) || \
@@ -199,21 +211,22 @@ void HASH_DataIn(uint32_t Data);
uint8_t HASH_GetInFIFOWordsNbr(void); uint8_t HASH_GetInFIFOWordsNbr(void);
void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber); void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber);
void HASH_StartDigest(void); void HASH_StartDigest(void);
void HASH_AutoStartDigest(FunctionalState NewState);
void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest); void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest);
/* HASH Context swapping functions ********************************************/ /* HASH Context swapping functions ********************************************/
void HASH_SaveContext(HASH_Context* HASH_ContextSave); void HASH_SaveContext(HASH_Context* HASH_ContextSave);
void HASH_RestoreContext(HASH_Context* HASH_ContextRestore); void HASH_RestoreContext(HASH_Context* HASH_ContextRestore);
/* HASH's DMA interface function **********************************************/ /* HASH DMA interface function ************************************************/
void HASH_DMACmd(FunctionalState NewState); void HASH_DMACmd(FunctionalState NewState);
/* HASH Interrupts and flags management functions *****************************/ /* HASH Interrupts and flags management functions *****************************/
void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState); void HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState);
FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG); FlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG);
void HASH_ClearFlag(uint16_t HASH_FLAG); void HASH_ClearFlag(uint32_t HASH_FLAG);
ITStatus HASH_GetITStatus(uint8_t HASH_IT); ITStatus HASH_GetITStatus(uint32_t HASH_IT);
void HASH_ClearITPendingBit(uint8_t HASH_IT); void HASH_ClearITPendingBit(uint32_t HASH_IT);
/* High Level SHA1 functions **************************************************/ /* High Level SHA1 functions **************************************************/
ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]); ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]);
@@ -241,4 +254,4 @@ ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen,
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

39
example/libs/StmCoreNPheriph/inc/stm32f4xx_i2c.h
View File

@@ -2,21 +2,27 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_i2c.h * @file stm32f4xx_i2c.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the I2C firmware * @brief This file contains all the functions prototypes for the I2C firmware
* library. * library.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -76,6 +82,17 @@ typedef struct
#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ #define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
((PERIPH) == I2C2) || \ ((PERIPH) == I2C2) || \
((PERIPH) == I2C3)) ((PERIPH) == I2C3))
/** @defgroup I2C_Digital_Filter
* @{
*/
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
/**
* @}
*/
/** @defgroup I2C_mode /** @defgroup I2C_mode
* @{ * @{
*/ */
@@ -534,6 +551,8 @@ void I2C_DeInit(I2C_TypeDef* I2Cx);
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter);
void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
@@ -689,4 +708,4 @@ void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
example/libs/StmCoreNPheriph/inc/stm32f4xx_iwdg.h
View File

@@ -2,21 +2,27 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_iwdg.h * @file stm32f4xx_iwdg.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the IWDG * @brief This file contains all the functions prototypes for the IWDG
* firmware library. * firmware library.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -122,4 +128,4 @@ FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

531
example/libs/StmCoreNPheriph/inc/stm32f4xx_ltdc.h Normal file
View File

@@ -0,0 +1,531 @@
/**
******************************************************************************
* @file stm32f4xx_ltdc.h
* @author MCD Application Team
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the LTDC firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_LTDC_H
#define __STM32F4xx_LTDC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup LTDC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief LTDC Init structure definition
*/
typedef struct
{
uint32_t LTDC_HSPolarity; /*!< configures the horizontal synchronization polarity.
This parameter can be one value of @ref LTDC_HSPolarity */
uint32_t LTDC_VSPolarity; /*!< configures the vertical synchronization polarity.
This parameter can be one value of @ref LTDC_VSPolarity */
uint32_t LTDC_DEPolarity; /*!< configures the data enable polarity. This parameter can
be one of value of @ref LTDC_DEPolarity */
uint32_t LTDC_PCPolarity; /*!< configures the pixel clock polarity. This parameter can
be one of value of @ref LTDC_PCPolarity */
uint32_t LTDC_HorizontalSync; /*!< configures the number of Horizontal synchronization
width. This parameter must range from 0x000 to 0xFFF. */
uint32_t LTDC_VerticalSync; /*!< configures the number of Vertical synchronization
heigh. This parameter must range from 0x000 to 0x7FF. */
uint32_t LTDC_AccumulatedHBP; /*!< configures the accumulated horizontal back porch width.
This parameter must range from LTDC_HorizontalSync to 0xFFF. */
uint32_t LTDC_AccumulatedVBP; /*!< configures the accumulated vertical back porch heigh.
This parameter must range from LTDC_VerticalSync to 0x7FF. */
uint32_t LTDC_AccumulatedActiveW; /*!< configures the accumulated active width. This parameter
must range from LTDC_AccumulatedHBP to 0xFFF. */
uint32_t LTDC_AccumulatedActiveH; /*!< configures the accumulated active heigh. This parameter
must range from LTDC_AccumulatedVBP to 0x7FF. */
uint32_t LTDC_TotalWidth; /*!< configures the total width. This parameter
must range from LTDC_AccumulatedActiveW to 0xFFF. */
uint32_t LTDC_TotalHeigh; /*!< configures the total heigh. This parameter
must range from LTDC_AccumulatedActiveH to 0x7FF. */
uint32_t LTDC_BackgroundRedValue; /*!< configures the background red value.
This parameter must range from 0x00 to 0xFF. */
uint32_t LTDC_BackgroundGreenValue; /*!< configures the background green value.
This parameter must range from 0x00 to 0xFF. */
uint32_t LTDC_BackgroundBlueValue; /*!< configures the background blue value.
This parameter must range from 0x00 to 0xFF. */
} LTDC_InitTypeDef;
/**
* @brief LTDC Layer structure definition
*/
typedef struct
{
uint32_t LTDC_HorizontalStart; /*!< Configures the Window Horizontal Start Position.
This parameter must range from 0x000 to 0xFFF. */
uint32_t LTDC_HorizontalStop; /*!< Configures the Window Horizontal Stop Position.
This parameter must range from 0x0000 to 0xFFFF. */
uint32_t LTDC_VerticalStart; /*!< Configures the Window vertical Start Position.
This parameter must range from 0x000 to 0xFFF. */
uint32_t LTDC_VerticalStop; /*!< Configures the Window vaertical Stop Position.
This parameter must range from 0x0000 to 0xFFFF. */
uint32_t LTDC_PixelFormat; /*!< Specifies the pixel format. This parameter can be
one of value of @ref LTDC_Pixelformat */
uint32_t LTDC_ConstantAlpha; /*!< Specifies the constant alpha used for blending.
This parameter must range from 0x00 to 0xFF. */
uint32_t LTDC_DefaultColorBlue; /*!< Configures the default blue value.
This parameter must range from 0x00 to 0xFF. */
uint32_t LTDC_DefaultColorGreen; /*!< Configures the default green value.
This parameter must range from 0x00 to 0xFF. */
uint32_t LTDC_DefaultColorRed; /*!< Configures the default red value.
This parameter must range from 0x00 to 0xFF. */
uint32_t LTDC_DefaultColorAlpha; /*!< Configures the default alpha value.
This parameter must range from 0x00 to 0xFF. */
uint32_t LTDC_BlendingFactor_1; /*!< Select the blending factor 1. This parameter
can be one of value of @ref LTDC_BlendingFactor1 */
uint32_t LTDC_BlendingFactor_2; /*!< Select the blending factor 2. This parameter
can be one of value of @ref LTDC_BlendingFactor2 */
uint32_t LTDC_CFBStartAdress; /*!< Configures the color frame buffer address */
uint32_t LTDC_CFBLineLength; /*!< Configures the color frame buffer line length.
This parameter must range from 0x0000 to 0x1FFF. */
uint32_t LTDC_CFBPitch; /*!< Configures the color frame buffer pitch in bytes.
This parameter must range from 0x0000 to 0x1FFF. */
uint32_t LTDC_CFBLineNumber; /*!< Specifies the number of line in frame buffer.
This parameter must range from 0x000 to 0x7FF. */
} LTDC_Layer_InitTypeDef;
/**
* @brief LTDC Position structure definition
*/
typedef struct
{
uint32_t LTDC_POSX; /*!< Current X Position */
uint32_t LTDC_POSY; /*!< Current Y Position */
} LTDC_PosTypeDef;
typedef struct
{
uint32_t LTDC_BlueWidth; /*!< Blue width */
uint32_t LTDC_GreenWidth; /*!< Green width */
uint32_t LTDC_RedWidth; /*!< Red width */
} LTDC_RGBTypeDef;
typedef struct
{
uint32_t LTDC_ColorKeyBlue; /*!< Configures the color key blue value.
This parameter must range from 0x00 to 0xFF. */
uint32_t LTDC_ColorKeyGreen; /*!< Configures the color key green value.
This parameter must range from 0x00 to 0xFF. */
uint32_t LTDC_ColorKeyRed; /*!< Configures the color key red value.
This parameter must range from 0x00 to 0xFF. */
} LTDC_ColorKeying_InitTypeDef;
typedef struct
{
uint32_t LTDC_CLUTAdress; /*!< Configures the CLUT address.
This parameter must range from 0x00 to 0xFF. */
uint32_t LTDC_BlueValue; /*!< Configures the blue value.
This parameter must range from 0x00 to 0xFF. */
uint32_t LTDC_GreenValue; /*!< Configures the green value.
This parameter must range from 0x00 to 0xFF. */
uint32_t LTDC_RedValue; /*!< Configures the red value.
This parameter must range from 0x00 to 0xFF. */
} LTDC_CLUT_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup LTDC_Exported_Constants
* @}
*/
/** @defgroup LTDC_SYNC
* @{
*/
#define LTDC_HorizontalSYNC ((uint32_t)0x00000FFF)
#define LTDC_VerticalSYNC ((uint32_t)0x000007FF)
#define IS_LTDC_HSYNC(HSYNC) ((HSYNC) <= LTDC_HorizontalSYNC)
#define IS_LTDC_VSYNC(VSYNC) ((VSYNC) <= LTDC_VerticalSYNC)
#define IS_LTDC_AHBP(AHBP) ((AHBP) <= LTDC_HorizontalSYNC)
#define IS_LTDC_AVBP(AVBP) ((AVBP) <= LTDC_VerticalSYNC)
#define IS_LTDC_AAW(AAW) ((AAW) <= LTDC_HorizontalSYNC)
#define IS_LTDC_AAH(AAH) ((AAH) <= LTDC_VerticalSYNC)
#define IS_LTDC_TOTALW(TOTALW) ((TOTALW) <= LTDC_HorizontalSYNC)
#define IS_LTDC_TOTALH(TOTALH) ((TOTALH) <= LTDC_VerticalSYNC)
/**
* @}
*/
/** @defgroup LTDC_HSPolarity
* @{
*/
#define LTDC_HSPolarity_AL ((uint32_t)0x00000000) /*!< Horizontal Synchronization is active low. */
#define LTDC_HSPolarity_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */
#define IS_LTDC_HSPOL(HSPOL) (((HSPOL) == LTDC_HSPolarity_AL) || \
((HSPOL) == LTDC_HSPolarity_AH))
/**
* @}
*/
/** @defgroup LTDC_VSPolarity
* @{
*/
#define LTDC_VSPolarity_AL ((uint32_t)0x00000000) /*!< Vertical Synchronization is active low. */
#define LTDC_VSPolarity_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */
#define IS_LTDC_VSPOL(VSPOL) (((VSPOL) == LTDC_VSPolarity_AL) || \
((VSPOL) == LTDC_VSPolarity_AH))
/**
* @}
*/
/** @defgroup LTDC_DEPolarity
* @{
*/
#define LTDC_DEPolarity_AL ((uint32_t)0x00000000) /*!< Data Enable, is active low. */
#define LTDC_DEPolarity_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */
#define IS_LTDC_DEPOL(DEPOL) (((DEPOL) == LTDC_VSPolarity_AL) || \
((DEPOL) == LTDC_DEPolarity_AH))
/**
* @}
*/
/** @defgroup LTDC_PCPolarity
* @{
*/
#define LTDC_PCPolarity_IPC ((uint32_t)0x00000000) /*!< input pixel clock. */
#define LTDC_PCPolarity_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */
#define IS_LTDC_PCPOL(PCPOL) (((PCPOL) == LTDC_PCPolarity_IPC) || \
((PCPOL) == LTDC_PCPolarity_IIPC))
/**
* @}
*/
/** @defgroup LTDC_Reload
* @{
*/
#define LTDC_IMReload LTDC_SRCR_IMR /*!< Immediately Reload. */
#define LTDC_VBReload LTDC_SRCR_VBR /*!< Vertical Blanking Reload. */
#define IS_LTDC_RELOAD(RELOAD) (((RELOAD) == LTDC_IMReload) || \
((RELOAD) == LTDC_VBReload))
/**
* @}
*/
/** @defgroup LTDC_Back_Color
* @{
*/
#define LTDC_Back_Color ((uint32_t)0x000000FF)
#define IS_LTDC_BackBlueValue(BBLUE) ((BBLUE) <= LTDC_Back_Color)
#define IS_LTDC_BackGreenValue(BGREEN) ((BGREEN) <= LTDC_Back_Color)
#define IS_LTDC_BackRedValue(BRED) ((BRED) <= LTDC_Back_Color)
/**
* @}
*/
/** @defgroup LTDC_Position
* @{
*/
#define LTDC_POS_CY LTDC_CPSR_CYPOS
#define LTDC_POS_CX LTDC_CPSR_CXPOS
#define IS_LTDC_GET_POS(POS) (((POS) <= LTDC_POS_CY))
/**
* @}
*/
/** @defgroup LTDC_LIPosition
* @{
*/
#define IS_LTDC_LIPOS(LIPOS) ((LIPOS) <= 0x7FF)
/**
* @}
*/
/** @defgroup LTDC_CurrentStatus
* @{
*/
#define LTDC_CD_VDES LTDC_CDSR_VDES
#define LTDC_CD_HDES LTDC_CDSR_HDES
#define LTDC_CD_VSYNC LTDC_CDSR_VSYNCS
#define LTDC_CD_HSYNC LTDC_CDSR_HSYNCS
#define IS_LTDC_GET_CD(CD) (((CD) == LTDC_CD_VDES) || ((CD) == LTDC_CD_HDES) || \
((CD) == LTDC_CD_VSYNC) || ((CD) == LTDC_CD_HSYNC))
/**
* @}
*/
/** @defgroup LTDC_Interrupts
* @{
*/
#define LTDC_IT_LI LTDC_IER_LIE
#define LTDC_IT_FU LTDC_IER_FUIE
#define LTDC_IT_TERR LTDC_IER_TERRIE
#define LTDC_IT_RR LTDC_IER_RRIE
#define IS_LTDC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF0) == 0x00) && ((IT) != 0x00))
/**
* @}
*/
/** @defgroup LTDC_Flag
* @{
*/
#define LTDC_FLAG_LI LTDC_ISR_LIF
#define LTDC_FLAG_FU LTDC_ISR_FUIF
#define LTDC_FLAG_TERR LTDC_ISR_TERRIF
#define LTDC_FLAG_RR LTDC_ISR_RRIF
#define IS_LTDC_FLAG(FLAG) (((FLAG) == LTDC_FLAG_LI) || ((FLAG) == LTDC_FLAG_FU) || \
((FLAG) == LTDC_FLAG_TERR) || ((FLAG) == LTDC_FLAG_RR))
/**
* @}
*/
/** @defgroup LTDC_Pixelformat
* @{
*/
#define LTDC_Pixelformat_ARGB8888 ((uint32_t)0x00000000)
#define LTDC_Pixelformat_RGB888 ((uint32_t)0x00000001)
#define LTDC_Pixelformat_RGB565 ((uint32_t)0x00000002)
#define LTDC_Pixelformat_ARGB1555 ((uint32_t)0x00000003)
#define LTDC_Pixelformat_ARGB4444 ((uint32_t)0x00000004)
#define LTDC_Pixelformat_L8 ((uint32_t)0x00000005)
#define LTDC_Pixelformat_AL44 ((uint32_t)0x00000006)
#define LTDC_Pixelformat_AL88 ((uint32_t)0x00000007)
#define IS_LTDC_Pixelformat(Pixelformat) (((Pixelformat) == LTDC_Pixelformat_ARGB8888) || ((Pixelformat) == LTDC_Pixelformat_RGB888) || \
((Pixelformat) == LTDC_Pixelformat_RGB565) || ((Pixelformat) == LTDC_Pixelformat_ARGB1555) || \
((Pixelformat) == LTDC_Pixelformat_ARGB4444) || ((Pixelformat) == LTDC_Pixelformat_L8) || \
((Pixelformat) == LTDC_Pixelformat_AL44) || ((Pixelformat) == LTDC_Pixelformat_AL88))
/**
* @}
*/
/** @defgroup LTDC_BlendingFactor1
* @{
*/
#define LTDC_BlendingFactor1_CA ((uint32_t)0x00000400)
#define LTDC_BlendingFactor1_PAxCA ((uint32_t)0x00000600)
#define IS_LTDC_BlendingFactor1(BlendingFactor1) (((BlendingFactor1) == LTDC_BlendingFactor1_CA) || ((BlendingFactor1) == LTDC_BlendingFactor1_PAxCA))
/**
* @}
*/
/** @defgroup LTDC_BlendingFactor2
* @{
*/
#define LTDC_BlendingFactor2_CA ((uint32_t)0x00000005)
#define LTDC_BlendingFactor2_PAxCA ((uint32_t)0x00000007)
#define IS_LTDC_BlendingFactor2(BlendingFactor2) (((BlendingFactor2) == LTDC_BlendingFactor2_CA) || ((BlendingFactor2) == LTDC_BlendingFactor2_PAxCA))
/**
* @}
*/
/** @defgroup LTDC_LAYER_Config
* @{
*/
#define LTDC_STOPPosition ((uint32_t)0x0000FFFF)
#define LTDC_STARTPosition ((uint32_t)0x00000FFF)
#define LTDC_DefaultColorConfig ((uint32_t)0x000000FF)
#define LTDC_ColorFrameBuffer ((uint32_t)0x00001FFF)
#define LTDC_LineNumber ((uint32_t)0x000007FF)
#define IS_LTDC_HCONFIGST(HCONFIGST) ((HCONFIGST) <= LTDC_STARTPosition)
#define IS_LTDC_HCONFIGSP(HCONFIGSP) ((HCONFIGSP) <= LTDC_STOPPosition)
#define IS_LTDC_VCONFIGST(VCONFIGST) ((VCONFIGST) <= LTDC_STARTPosition)
#define IS_LTDC_VCONFIGSP(VCONFIGSP) ((VCONFIGSP) <= LTDC_STOPPosition)
#define IS_LTDC_DEFAULTCOLOR(DEFAULTCOLOR) ((DEFAULTCOLOR) <= LTDC_DefaultColorConfig)
#define IS_LTDC_CFBP(CFBP) ((CFBP) <= LTDC_ColorFrameBuffer)
#define IS_LTDC_CFBLL(CFBLL) ((CFBLL) <= LTDC_ColorFrameBuffer)
#define IS_LTDC_CFBLNBR(CFBLNBR) ((CFBLNBR) <= LTDC_LineNumber)
/**
* @}
*/
/** @defgroup LTDC_colorkeying_Config
* @{
*/
#define LTDC_colorkeyingConfig ((uint32_t)0x000000FF)
#define IS_LTDC_CKEYING(CKEYING) ((CKEYING) <= LTDC_colorkeyingConfig)
/**
* @}
*/
/** @defgroup LTDC_CLUT_Config
* @{
*/
#define LTDC_CLUTWR ((uint32_t)0x000000FF)
#define IS_LTDC_CLUTWR(CLUTWR) ((CLUTWR) <= LTDC_CLUTWR)
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the LTDC configuration to the default reset state *****/
void LTDC_DeInit(void);
/* Initialization and Configuration functions *********************************/
void LTDC_Init(LTDC_InitTypeDef* LTDC_InitStruct);
void LTDC_StructInit(LTDC_InitTypeDef* LTDC_InitStruct);
void LTDC_Cmd(FunctionalState NewState);
void LTDC_DitherCmd(FunctionalState NewState);
LTDC_RGBTypeDef LTDC_GetRGBWidth(void);
void LTDC_RGBStructInit(LTDC_RGBTypeDef* LTDC_RGB_InitStruct);
void LTDC_LIPConfig(uint32_t LTDC_LIPositionConfig);
void LTDC_ReloadConfig(uint32_t LTDC_Reload);
void LTDC_LayerInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_Layer_InitTypeDef* LTDC_Layer_InitStruct);
void LTDC_LayerStructInit(LTDC_Layer_InitTypeDef * LTDC_Layer_InitStruct);
void LTDC_LayerCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState);
LTDC_PosTypeDef LTDC_GetPosStatus(void);
void LTDC_PosStructInit(LTDC_PosTypeDef* LTDC_Pos_InitStruct);
FlagStatus LTDC_GetCDStatus(uint32_t LTDC_CD);
void LTDC_ColorKeyingConfig(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct, FunctionalState NewState);
void LTDC_ColorKeyingStructInit(LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct);
void LTDC_CLUTCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState);
void LTDC_CLUTInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct);
void LTDC_CLUTStructInit(LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct);
void LTDC_LayerPosition(LTDC_Layer_TypeDef* LTDC_Layerx, uint16_t OffsetX, uint16_t OffsetY);
void LTDC_LayerAlpha(LTDC_Layer_TypeDef* LTDC_Layerx, uint8_t ConstantAlpha);
void LTDC_LayerAddress(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Address);
void LTDC_LayerSize(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Width, uint32_t Height);
void LTDC_LayerPixelFormat(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t PixelFormat);
/* Interrupts and flags management functions **********************************/
void LTDC_ITConfig(uint32_t LTDC_IT, FunctionalState NewState);
FlagStatus LTDC_GetFlagStatus(uint32_t LTDC_FLAG);
void LTDC_ClearFlag(uint32_t LTDC_FLAG);
ITStatus LTDC_GetITStatus(uint32_t LTDC_IT);
void LTDC_ClearITPendingBit(uint32_t LTDC_IT);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_LTDC_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

93
example/libs/StmCoreNPheriph/inc/stm32f4xx_pwr.h
View File

@@ -2,21 +2,27 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_pwr.h * @file stm32f4xx_pwr.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the PWR firmware * @brief This file contains all the functions prototypes for the PWR firmware
* library. * library.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -49,7 +55,6 @@
/** @defgroup PWR_PVD_detection_level /** @defgroup PWR_PVD_detection_level
* @{ * @{
*/ */
#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0 #define PWR_PVDLevel_0 PWR_CR_PLS_LEV0
#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1 #define PWR_PVDLevel_1 PWR_CR_PLS_LEV1
#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2 #define PWR_PVDLevel_2 PWR_CR_PLS_LEV2
@@ -71,11 +76,29 @@
/** @defgroup PWR_Regulator_state_in_STOP_mode /** @defgroup PWR_Regulator_state_in_STOP_mode
* @{ * @{
*/ */
#define PWR_MainRegulator_ON ((uint32_t)0x00000000)
#define PWR_LowPowerRegulator_ON PWR_CR_LPDS
/* --- PWR_Legacy ---*/
#define PWR_Regulator_ON PWR_MainRegulator_ON
#define PWR_Regulator_LowPower PWR_LowPowerRegulator_ON
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MainRegulator_ON) || \
((REGULATOR) == PWR_LowPowerRegulator_ON))
/**
* @}
*/
/** @defgroup PWR_Regulator_state_in_UnderDrive_mode
* @{
*/
#define PWR_MainRegulator_UnderDrive_ON PWR_CR_MRUDS
#define PWR_LowPowerRegulator_UnderDrive_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MainRegulator_UnderDrive_ON) || \
((REGULATOR) == PWR_LowPowerRegulator_UnderDrive_ON))
#define PWR_Regulator_ON ((uint32_t)0x00000000)
#define PWR_Regulator_LowPower PWR_CR_LPDS
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
((REGULATOR) == PWR_Regulator_LowPower))
/** /**
* @} * @}
*/ */
@@ -83,19 +106,22 @@
/** @defgroup PWR_STOP_mode_entry /** @defgroup PWR_STOP_mode_entry
* @{ * @{
*/ */
#define PWR_STOPEntry_WFI ((uint8_t)0x01) #define PWR_STOPEntry_WFI ((uint8_t)0x01)
#define PWR_STOPEntry_WFE ((uint8_t)0x02) #define PWR_STOPEntry_WFE ((uint8_t)0x02)
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
/**
* @}
*/
/** @defgroup PWR_Regulator_Voltage_Scale /** @defgroup PWR_Regulator_Voltage_Scale
* @{ * @{
*/ */
#define PWR_Regulator_Voltage_Scale1 ((uint32_t)0x0000C000)
#define PWR_Regulator_Voltage_Scale1 ((uint32_t)0x00004000) #define PWR_Regulator_Voltage_Scale2 ((uint32_t)0x00008000)
#define PWR_Regulator_Voltage_Scale2 ((uint32_t)0x00000000) #define PWR_Regulator_Voltage_Scale3 ((uint32_t)0x00004000)
#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || ((VOLTAGE) == PWR_Regulator_Voltage_Scale2)) #define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || \
((VOLTAGE) == PWR_Regulator_Voltage_Scale2) || \
((VOLTAGE) == PWR_Regulator_Voltage_Scale3))
/** /**
* @} * @}
*/ */
@@ -103,26 +129,27 @@
/** @defgroup PWR_Flag /** @defgroup PWR_Flag
* @{ * @{
*/ */
#define PWR_FLAG_WU PWR_CSR_WUF #define PWR_FLAG_WU PWR_CSR_WUF
#define PWR_FLAG_SB PWR_CSR_SBF #define PWR_FLAG_SB PWR_CSR_SBF
#define PWR_FLAG_PVDO PWR_CSR_PVDO #define PWR_FLAG_PVDO PWR_CSR_PVDO
#define PWR_FLAG_BRR PWR_CSR_BRR #define PWR_FLAG_BRR PWR_CSR_BRR
#define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY #define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
#define PWR_FLAG_ODRDY PWR_CSR_ODRDY
#define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY
#define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY
/** @defgroup PWR_Flag_Legacy /* --- FLAG Legacy ---*/
* @{
*/
#define PWR_FLAG_REGRDY PWR_FLAG_VOSRDY #define PWR_FLAG_REGRDY PWR_FLAG_VOSRDY
/**
* @}
*/
#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \ ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \
((FLAG) == PWR_FLAG_VOSRDY)) ((FLAG) == PWR_FLAG_VOSRDY) || ((FLAG) == PWR_FLAG_ODRDY) || \
((FLAG) == PWR_FLAG_ODSWRDY) || ((FLAG) == PWR_FLAG_UDRDY))
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
((FLAG) == PWR_FLAG_UDRDY))
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
/** /**
* @} * @}
*/ */
@@ -150,12 +177,18 @@ void PWR_WakeUpPinCmd(FunctionalState NewState);
/* Main and Backup Regulators configuration functions *************************/ /* Main and Backup Regulators configuration functions *************************/
void PWR_BackupRegulatorCmd(FunctionalState NewState); void PWR_BackupRegulatorCmd(FunctionalState NewState);
void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage); void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage);
void PWR_OverDriveCmd(FunctionalState NewState);
void PWR_OverDriveSWCmd(FunctionalState NewState);
void PWR_UnderDriveCmd(FunctionalState NewState);
void PWR_MainRegulatorLowVoltageCmd(FunctionalState NewState);
void PWR_LowRegulatorLowVoltageCmd(FunctionalState NewState);
/* FLASH Power Down configuration functions ***********************************/ /* FLASH Power Down configuration functions ***********************************/
void PWR_FlashPowerDownCmd(FunctionalState NewState); void PWR_FlashPowerDownCmd(FunctionalState NewState);
/* Low Power modes configuration functions ************************************/ /* Low Power modes configuration functions ************************************/
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
void PWR_EnterSTANDBYMode(void); void PWR_EnterSTANDBYMode(void);
/* Flags management functions *************************************************/ /* Flags management functions *************************************************/
@@ -176,4 +209,4 @@ void PWR_ClearFlag(uint32_t PWR_FLAG);
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

274
example/libs/StmCoreNPheriph/inc/stm32f4xx_rcc.h
View File

@@ -2,20 +2,26 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_rcc.h * @file stm32f4xx_rcc.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the RCC firmware library. * @brief This file contains all the functions prototypes for the RCC firmware library.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -42,9 +48,9 @@
typedef struct typedef struct
{ {
uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */ uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */
uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */ uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */
uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */ uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */
uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */ uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */
}RCC_ClocksTypeDef; }RCC_ClocksTypeDef;
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
@@ -64,7 +70,18 @@ typedef struct
/** /**
* @} * @}
*/ */
/** @defgroup RCC_LSE_Dual_Mode_Selection
* @{
*/
#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \
((MODE) == RCC_LSE_HIGHDRIVE_MODE))
/**
* @}
*/
/** @defgroup RCC_PLL_Clock_Source /** @defgroup RCC_PLL_Clock_Source
* @{ * @{
*/ */
@@ -78,7 +95,26 @@ typedef struct
#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
#define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
#define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000)
#define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000)
#define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000)
#define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000)
#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\
((VALUE) == RCC_PLLSAIDivR_Div4) ||\
((VALUE) == RCC_PLLSAIDivR_Div8) ||\
((VALUE) == RCC_PLLSAIDivR_Div16))
/** /**
* @} * @}
*/ */
@@ -140,14 +176,17 @@ typedef struct
#define RCC_IT_HSIRDY ((uint8_t)0x04) #define RCC_IT_HSIRDY ((uint8_t)0x04)
#define RCC_IT_HSERDY ((uint8_t)0x08) #define RCC_IT_HSERDY ((uint8_t)0x08)
#define RCC_IT_PLLRDY ((uint8_t)0x10) #define RCC_IT_PLLRDY ((uint8_t)0x10)
#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
#define RCC_IT_PLLSAIRDY ((uint8_t)0x40)
#define RCC_IT_CSS ((uint8_t)0x80) #define RCC_IT_CSS ((uint8_t)0x80)
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
((IT) == RCC_IT_PLLI2SRDY)) ((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY))
#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00)) #define IS_RCC_CLEAR_IT(IT)((IT) != 0x00)
/** /**
* @} * @}
*/ */
@@ -245,6 +284,45 @@ typedef struct
/** /**
* @} * @}
*/ */
/** @defgroup RCC_SAI_BlockA_Clock_Source
* @{
*/
#define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000)
#define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000)
#define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000)
#define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\
((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\
((SOURCE) == RCC_SAIACLKSource_Ext))
/**
* @}
*/
/** @defgroup RCC_SAI_BlockB_Clock_Source
* @{
*/
#define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000)
#define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000)
#define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000)
#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\
((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\
((SOURCE) == RCC_SAIBCLKSource_Ext))
/**
* @}
*/
/** @defgroup RCC_TIM_PRescaler_Selection
* @{
*/
#define RCC_TIMPrescDesactivated ((uint8_t)0x00)
#define RCC_TIMPrescActivated ((uint8_t)0x01)
#define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated))
/**
* @}
*/
/** @defgroup RCC_AHB1_Peripherals /** @defgroup RCC_AHB1_Peripherals
* @{ * @{
@@ -257,24 +335,30 @@ typedef struct
#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020) #define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)
#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) #define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)
#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080) #define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)
#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) #define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
#define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200)
#define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400)
#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000) #define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)
#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) #define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000)
#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000) #define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)
#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000) #define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000)
#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000) #define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)
#define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000)
#define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000) #define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)
#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) #define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)
#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000) #define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)
#define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000)
#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000) #define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)
#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000) #define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)
#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) #define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000)
#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) #define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)
#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000) #define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)
#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000) #define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)
#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x818BEE00) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00)) #define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x810BE800) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81986E00) == 0x00) && ((PERIPH) != 0x00)) #define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD1FE800) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81106800) == 0x00) && ((PERIPH) != 0x00))
/** /**
* @} * @}
*/ */
@@ -295,7 +379,14 @@ typedef struct
/** @defgroup RCC_AHB3_Peripherals /** @defgroup RCC_AHB3_Peripherals
* @{ * @{
*/ */
#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) #if defined (STM32F40_41xxx)
#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
#endif /* STM32F40_41xxx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define RCC_AHB3Periph_FMC ((uint32_t)0x00000001)
#endif /* STM32F427_437xx || STM32F429_439xx */
#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
/** /**
* @} * @}
@@ -327,7 +418,9 @@ typedef struct
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) #define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) #define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC9013600) == 0x00) && ((PERIPH) != 0x00)) #define RCC_APB1Periph_UART7 ((uint32_t)0x40000000)
#define RCC_APB1Periph_UART8 ((uint32_t)0x80000000)
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x09013600) == 0x00) && ((PERIPH) != 0x00))
/** /**
* @} * @}
*/ */
@@ -345,12 +438,19 @@ typedef struct
#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400) #define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400)
#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800) #define RCC_APB2Periph_SDIO ((uint32_t)0x00000800)
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
#define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000)
#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) #define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000) #define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000)
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000) #define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)
#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) #define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A0CC) == 0x00) && ((PERIPH) != 0x00)) #define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000)
#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A6CC) == 0x00) && ((PERIPH) != 0x00)) #define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000)
#define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000)
#define RCC_APB2Periph_LTDC ((uint32_t)0x04000000)
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFB8880CC) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFB8886CC) == 0x00) && ((PERIPH) != 0x00))
/** /**
* @} * @}
*/ */
@@ -406,6 +506,7 @@ typedef struct
#define RCC_FLAG_HSERDY ((uint8_t)0x31) #define RCC_FLAG_HSERDY ((uint8_t)0x31)
#define RCC_FLAG_PLLRDY ((uint8_t)0x39) #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D)
#define RCC_FLAG_LSERDY ((uint8_t)0x41) #define RCC_FLAG_LSERDY ((uint8_t)0x41)
#define RCC_FLAG_LSIRDY ((uint8_t)0x61) #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
#define RCC_FLAG_BORRST ((uint8_t)0x79) #define RCC_FLAG_BORRST ((uint8_t)0x79)
@@ -415,13 +516,15 @@ typedef struct
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \ ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
((FLAG) == RCC_FLAG_PLLI2SRDY)) ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \
((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY))
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
/** /**
* @} * @}
@@ -438,60 +541,77 @@ typedef struct
void RCC_DeInit(void); void RCC_DeInit(void);
/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
void RCC_HSEConfig(uint8_t RCC_HSE); void RCC_HSEConfig(uint8_t RCC_HSE);
ErrorStatus RCC_WaitForHSEStartUp(void); ErrorStatus RCC_WaitForHSEStartUp(void);
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
void RCC_HSICmd(FunctionalState NewState); void RCC_HSICmd(FunctionalState NewState);
void RCC_LSEConfig(uint8_t RCC_LSE); void RCC_LSEConfig(uint8_t RCC_LSE);
void RCC_LSICmd(FunctionalState NewState); void RCC_LSICmd(FunctionalState NewState);
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
void RCC_PLLCmd(FunctionalState NewState);
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ); #if defined (STM32F40_41xxx) || defined (STM32F401xx)
void RCC_PLLCmd(FunctionalState NewState); void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR); #elif defined (STM32F411xE)
void RCC_PLLI2SCmd(FunctionalState NewState); void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM);
#elif defined (STM32F427_437xx) || defined (STM32F429_439xx)
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR);
#else
#endif /* STM32F40_41xxx || STM32F401xx */
void RCC_ClockSecuritySystemCmd(FunctionalState NewState); void RCC_PLLI2SCmd(FunctionalState NewState);
void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div); void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR);
void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div); void RCC_PLLSAICmd(FunctionalState NewState);
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
/* System, AHB and APB busses clocks configuration functions ******************/ /* System, AHB and APB busses clocks configuration functions ******************/
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
uint8_t RCC_GetSYSCLKSource(void); uint8_t RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(uint32_t RCC_SYSCLK); void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
void RCC_PCLK1Config(uint32_t RCC_HCLK); void RCC_PCLK1Config(uint32_t RCC_HCLK);
void RCC_PCLK2Config(uint32_t RCC_HCLK); void RCC_PCLK2Config(uint32_t RCC_HCLK);
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
/* Peripheral clocks configuration functions **********************************/ /* Peripheral clocks configuration functions **********************************/
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState); void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_BackupResetCmd(FunctionalState NewState); void RCC_BackupResetCmd(FunctionalState NewState);
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ);
void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ);
void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource);
void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource);
void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR);
void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);
void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_LSEModeConfig(uint8_t Mode);
/* Interrupts and flags management functions **********************************/ /* Interrupts and flags management functions **********************************/
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
void RCC_ClearFlag(void); void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(uint8_t RCC_IT); ITStatus RCC_GetITStatus(uint8_t RCC_IT);
void RCC_ClearITPendingBit(uint8_t RCC_IT); void RCC_ClearITPendingBit(uint8_t RCC_IT);
#ifdef __cplusplus #ifdef __cplusplus
} }
@@ -507,4 +627,4 @@ void RCC_ClearITPendingBit(uint8_t RCC_IT);
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
example/libs/StmCoreNPheriph/inc/stm32f4xx_rng.h
View File

@@ -2,21 +2,27 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_rng.h * @file stm32f4xx_rng.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the Random * @brief This file contains all the functions prototypes for the Random
* Number Generator(RNG) firmware library. * Number Generator(RNG) firmware library.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -111,4 +117,4 @@ void RNG_ClearITPendingBit(uint8_t RNG_IT);
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
example/libs/StmCoreNPheriph/inc/stm32f4xx_rtc.h
View File

@@ -2,21 +2,27 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_rtc.h * @file stm32f4xx_rtc.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the RTC firmware * @brief This file contains all the functions prototypes for the RTC firmware
* library. * library.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -872,4 +878,4 @@ void RTC_ClearITPendingBit(uint32_t RTC_IT);
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

611
example/libs/StmCoreNPheriph/inc/stm32f4xx_sai.h Normal file
View File

@@ -0,0 +1,611 @@
/**
******************************************************************************
* @file stm32f4xx_sai.h
* @author MCD Application Team
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the SAI
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_SAI_H
#define __STM32F4xx_SAI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup SAI
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief SAI Block Init structure definition
*/
typedef struct
{
uint32_t SAI_AudioMode; /*!< Specifies the SAI Block Audio Mode.
This parameter can be a value of @ref SAI_Block_Mode */
uint32_t SAI_Protocol; /*!< Specifies the SAI Block Protocol.
This parameter can be a value of @ref SAI_Block_Protocol */
uint32_t SAI_DataSize; /*!< Specifies the SAI Block data size.
This parameter can be a value of @ref SAI_Block_Data_Size
@note this value is ignored when AC'97 or SPDIF protocols are selected.*/
uint32_t SAI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission
@note this value has no meaning when AC'97 or SPDIF protocols are selected.*/
uint32_t SAI_ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity.
This parameter can be a value of @ref SAI_Block_Clock_Strobing */
uint32_t SAI_Synchro; /*!< Specifies SAI Block synchronization
This parameter can be a value of @ref SAI_Block_Synchronization */
uint32_t SAI_OUTDRIV; /*!< Specifies when SAI Block outputs are driven.
This parameter can be a value of @ref SAI_Block_Output_Drive
@note this value has to be set before enabling the audio block
but after the audio block configuration. */
uint32_t SAI_NoDivider; /*!< Specifies whether Master Clock will be divided or not.
This parameter can be a value of @ref SAI_Block_NoDivider */
uint32_t SAI_MasterDivider; /*!< Specifies SAI Block Master Clock Divider.
@note the Master Clock Frequency is calculated accordingly to the
following formula : MCLK_x = SAI_CK_x/(MCKDIV[3:0]*2)*/
uint32_t SAI_FIFOThreshold; /*!< Specifies SAI Block FIFO Threshold.
This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
}SAI_InitTypeDef;
/**
* @brief SAI Block Frame Init structure definition
*/
typedef struct
{
uint32_t SAI_FrameLength; /*!< Specifies the Frame Length, the number of SCK clocks
for each audio frame.
This parameter must be a number between 8 and 256.
@note If master Clock MCLK_x pin is declared as an output, the frame length
should be Aligned to a number equal to power of 2 in order to keep
in an audio frame, an integer number of MCLK pulses by bit Clock.
@note this value is ignored when AC'97 or SPDIF protocols are selected.*/
uint32_t SAI_ActiveFrameLength; /*!< Specifies the Frame synchronization active level length.
This Parameter specifies the length in number of bit clock (SCK + 1)
of the active level of FS signal in audio frame.
This parameter must be a number between 1 and 128.
@note this value is ignored when AC'97 or SPDIF protocols are selected.*/
uint32_t SAI_FSDefinition; /*!< Specifies the Frame Synchronization definition.
This parameter can be a value of @ref SAI_Block_FS_Definition
@note this value is ignored when AC'97 or SPDIF protocols are selected.*/
uint32_t SAI_FSPolarity; /*!< Specifies the Frame Synchronization Polarity.
This parameter can be a value of @ref SAI_Block_FS_Polarity
@note this value is ignored when AC'97 or SPDIF protocols are selected.*/
uint32_t SAI_FSOffset; /*!< Specifies the Frame Synchronization Offset.
This parameter can be a value of @ref SAI_Block_FS_Offset
@note this value is ignored when AC'97 or SPDIF protocols are selected.*/
}SAI_FrameInitTypeDef;
/**
* @brief SAI Block Slot Init Structure definition
*/
typedef struct
{
uint32_t SAI_FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot.
This parameter must be a number between 0 and 24.
@note this value is ignored when AC'97 or SPDIF protocols are selected.*/
uint32_t SAI_SlotSize; /*!< Specifies the Slot Size.
This parameter can be a value of @ref SAI_Block_Slot_Size
@note this value is ignored when AC'97 or SPDIF protocols are selected.*/
uint32_t SAI_SlotNumber; /*!< Specifies the number of slot in the audio frame.
This parameter must be a number between 1 and 16.
@note this value is ignored when AC'97 or SPDIF protocols are selected.*/
uint32_t SAI_SlotActive; /*!< Specifies the slots in audio frame that will be activated.
This parameter can be a value of @ ref SAI_Block_Slot_Active
@note this value is ignored when AC'97 or SPDIF protocols are selected.*/
}SAI_SlotInitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup SAI_Exported_Constants
* @{
*/
#define IS_SAI_PERIPH(PERIPH) ((PERIPH) == SAI1)
#define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \
((PERIPH) == SAI1_Block_B))
/** @defgroup SAI_Block_Mode
* @{
*/
#define SAI_Mode_MasterTx ((uint32_t)0x00000000)
#define SAI_Mode_MasterRx ((uint32_t)0x00000001)
#define SAI_Mode_SlaveTx ((uint32_t)0x00000002)
#define SAI_Mode_SlaveRx ((uint32_t)0x00000003)
#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_Mode_MasterTx) || \
((MODE) == SAI_Mode_MasterRx) || \
((MODE) == SAI_Mode_SlaveTx) || \
((MODE) == SAI_Mode_SlaveRx))
/**
* @}
*/
/** @defgroup SAI_Block_Protocol
* @{
*/
#define SAI_Free_Protocol ((uint32_t)0x00000000)
#define SAI_SPDIF_Protocol ((uint32_t)SAI_xCR1_PRTCFG_0)
#define SAI_AC97_Protocol ((uint32_t)SAI_xCR1_PRTCFG_1)
#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_Free_Protocol) || \
((PROTOCOL) == SAI_SPDIF_Protocol) || \
((PROTOCOL) == SAI_AC97_Protocol))
/**
* @}
*/
/** @defgroup SAI_Block_Data_Size
* @{
*/
#define SAI_DataSize_8b ((uint32_t)0x00000040)
#define SAI_DataSize_10b ((uint32_t)0x00000060)
#define SAI_DataSize_16b ((uint32_t)0x00000080)
#define SAI_DataSize_20b ((uint32_t)0x000000A0)
#define SAI_DataSize_24b ((uint32_t)0x000000C0)
#define SAI_DataSize_32b ((uint32_t)0x000000E0)
#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DataSize_8b) || \
((DATASIZE) == SAI_DataSize_10b) || \
((DATASIZE) == SAI_DataSize_16b) || \
((DATASIZE) == SAI_DataSize_20b) || \
((DATASIZE) == SAI_DataSize_24b) || \
((DATASIZE) == SAI_DataSize_32b))
/**
* @}
*/
/** @defgroup SAI_Block_MSB_LSB_transmission
* @{
*/
#define SAI_FirstBit_MSB ((uint32_t)0x00000000)
#define SAI_FirstBit_LSB ((uint32_t)SAI_xCR1_LSBFIRST)
#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FirstBit_MSB) || \
((BIT) == SAI_FirstBit_LSB))
/**
* @}
*/
/** @defgroup SAI_Block_Clock_Strobing
* @{
*/
#define SAI_ClockStrobing_FallingEdge ((uint32_t)0x00000000)
#define SAI_ClockStrobing_RisingEdge ((uint32_t)SAI_xCR1_CKSTR)
#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_ClockStrobing_FallingEdge) || \
((CLOCK) == SAI_ClockStrobing_RisingEdge))
/**
* @}
*/
/** @defgroup SAI_Block_Synchronization
* @{
*/
#define SAI_Asynchronous ((uint32_t)0x00000000)
#define SAI_Synchronous ((uint32_t)SAI_xCR1_SYNCEN_0)
#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_Synchronous) || \
((SYNCHRO) == SAI_Asynchronous))
/**
* @}
*/
/** @defgroup SAI_Block_Output_Drive
* @{
*/
#define SAI_OutputDrive_Disabled ((uint32_t)0x00000000)
#define SAI_OutputDrive_Enabled ((uint32_t)SAI_xCR1_OUTDRIV)
#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OutputDrive_Disabled) || \
((DRIVE) == SAI_OutputDrive_Enabled))
/**
* @}
*/
/** @defgroup SAI_Block_NoDivider
* @{
*/
#define SAI_MasterDivider_Enabled ((uint32_t)0x00000000)
#define SAI_MasterDivider_Disabled ((uint32_t)SAI_xCR1_NODIV)
#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MasterDivider_Enabled) || \
((NODIVIDER) == SAI_MasterDivider_Disabled))
/**
* @}
*/
/** @defgroup SAI_Block_Master_Divider
* @{
*/
#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)
/**
* @}
*/
/** @defgroup SAI_Block_Frame_Length
* @{
*/
#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
/**
* @}
*/
/** @defgroup SAI_Block_Active_FrameLength
* @{
*/
#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))
/**
* @}
*/
/** @defgroup SAI_Block_FS_Definition
* @{
*/
#define SAI_FS_StartFrame ((uint32_t)0x00000000)
#define I2S_FS_ChannelIdentification ((uint32_t)SAI_xFRCR_FSDEF)
#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_StartFrame) || \
((DEFINITION) == I2S_FS_ChannelIdentification))
/**
* @}
*/
/** @defgroup SAI_Block_FS_Polarity
* @{
*/
#define SAI_FS_ActiveLow ((uint32_t)0x00000000)
#define SAI_FS_ActiveHigh ((uint32_t)SAI_xFRCR_FSPO)
#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ActiveLow) || \
((POLARITY) == SAI_FS_ActiveHigh))
/**
* @}
*/
/** @defgroup SAI_Block_FS_Offset
* @{
*/
#define SAI_FS_FirstBit ((uint32_t)0x00000000)
#define SAI_FS_BeforeFirstBit ((uint32_t)SAI_xFRCR_FSOFF)
#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FirstBit) || \
((OFFSET) == SAI_FS_BeforeFirstBit))
/**
* @}
*/
/** @defgroup SAI_Block_Slot_FirstBit_Offset
* @{
*/
#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)
/**
* @}
*/
/** @defgroup SAI_Block_Slot_Size
* @{
*/
#define SAI_SlotSize_DataSize ((uint32_t)0x00000000)
#define SAI_SlotSize_16b ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
#define SAI_SlotSize_32b ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SlotSize_DataSize) || \
((SIZE) == SAI_SlotSize_16b) || \
((SIZE) == SAI_SlotSize_32b))
/**
* @}
*/
/** @defgroup SAI_Block_Slot_Number
* @{
*/
#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
/**
* @}
*/
/** @defgroup SAI_Block_Slot_Active
* @{
*/
#define SAI_Slot_NotActive ((uint32_t)0x00000000)
#define SAI_SlotActive_0 ((uint32_t)0x00010000)
#define SAI_SlotActive_1 ((uint32_t)0x00020000)
#define SAI_SlotActive_2 ((uint32_t)0x00040000)
#define SAI_SlotActive_3 ((uint32_t)0x00080000)
#define SAI_SlotActive_4 ((uint32_t)0x00100000)
#define SAI_SlotActive_5 ((uint32_t)0x00200000)
#define SAI_SlotActive_6 ((uint32_t)0x00400000)
#define SAI_SlotActive_7 ((uint32_t)0x00800000)
#define SAI_SlotActive_8 ((uint32_t)0x01000000)
#define SAI_SlotActive_9 ((uint32_t)0x02000000)
#define SAI_SlotActive_10 ((uint32_t)0x04000000)
#define SAI_SlotActive_11 ((uint32_t)0x08000000)
#define SAI_SlotActive_12 ((uint32_t)0x10000000)
#define SAI_SlotActive_13 ((uint32_t)0x20000000)
#define SAI_SlotActive_14 ((uint32_t)0x40000000)
#define SAI_SlotActive_15 ((uint32_t)0x80000000)
#define SAI_SlotActive_ALL ((uint32_t)0xFFFF0000)
#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) != 0)
/**
* @}
*/
/** @defgroup SAI_Mono_Streo_Mode
* @{
*/
#define SAI_MonoMode ((uint32_t)SAI_xCR1_MONO)
#define SAI_StreoMode ((uint32_t)0x00000000)
#define IS_SAI_BLOCK_MONO_STREO_MODE(MODE) (((MODE) == SAI_MonoMode) ||\
((MODE) == SAI_StreoMode))
/**
* @}
*/
/** @defgroup SAI_TRIState_Management
* @{
*/
#define SAI_Output_NotReleased ((uint32_t)0x00000000)
#define SAI_Output_Released ((uint32_t)SAI_xCR2_TRIS)
#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_Output_NotReleased) ||\
((STATE) == SAI_Output_Released))
/**
* @}
*/
/** @defgroup SAI_Block_Fifo_Threshold
* @{
*/
#define SAI_Threshold_FIFOEmpty ((uint32_t)0x00000000)
#define SAI_FIFOThreshold_1QuarterFull ((uint32_t)0x00000001)
#define SAI_FIFOThreshold_HalfFull ((uint32_t)0x00000002)
#define SAI_FIFOThreshold_3QuartersFull ((uint32_t)0x00000003)
#define SAI_FIFOThreshold_Full ((uint32_t)0x00000004)
#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_Threshold_FIFOEmpty) || \
((THRESHOLD) == SAI_FIFOThreshold_1QuarterFull) || \
((THRESHOLD) == SAI_FIFOThreshold_HalfFull) || \
((THRESHOLD) == SAI_FIFOThreshold_3QuartersFull) || \
((THRESHOLD) == SAI_FIFOThreshold_Full))
/**
* @}
*/
/** @defgroup SAI_Block_Companding_Mode
* @{
*/
#define SAI_NoCompanding ((uint32_t)0x00000000)
#define SAI_ULaw_1CPL_Companding ((uint32_t)0x00008000)
#define SAI_ALaw_1CPL_Companding ((uint32_t)0x0000C000)
#define SAI_ULaw_2CPL_Companding ((uint32_t)0x0000A000)
#define SAI_ALaw_2CPL_Companding ((uint32_t)0x0000E000)
#define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NoCompanding) || \
((MODE) == SAI_ULaw_1CPL_Companding) || \
((MODE) == SAI_ALaw_1CPL_Companding) || \
((MODE) == SAI_ULaw_2CPL_Companding) || \
((MODE) == SAI_ALaw_2CPL_Companding))
/**
* @}
*/
/** @defgroup SAI_Block_Mute_Value
* @{
*/
#define SAI_ZeroValue ((uint32_t)0x00000000)
#define SAI_LastSentValue ((uint32_t)SAI_xCR2_MUTEVAL)
#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZeroValue) || \
((VALUE) == SAI_LastSentValue))
/**
* @}
*/
/** @defgroup SAI_Block_Mute_Frame_Counter
* @{
*/
#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
/**
* @}
*/
/** @defgroup SAI_Block_Interrupts_Definition
* @{
*/
#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE)
#define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE)
#define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE)
#define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE)
#define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE)
#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE)
#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE)
#define IS_SAI_BLOCK_CONFIG_IT(IT) (((IT) == SAI_IT_OVRUDR) || \
((IT) == SAI_IT_MUTEDET) || \
((IT) == SAI_IT_WCKCFG) || \
((IT) == SAI_IT_FREQ) || \
((IT) == SAI_IT_CNRDY) || \
((IT) == SAI_IT_AFSDET) || \
((IT) == SAI_IT_LFSDET))
/**
* @}
*/
/** @defgroup SAI_Block_Flags_Definition
* @{
*/
#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR)
#define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET)
#define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG)
#define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ)
#define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY)
#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET)
#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET)
#define IS_SAI_BLOCK_GET_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR) || \
((FLAG) == SAI_FLAG_MUTEDET) || \
((FLAG) == SAI_FLAG_WCKCFG) || \
((FLAG) == SAI_FLAG_FREQ) || \
((FLAG) == SAI_FLAG_CNRDY) || \
((FLAG) == SAI_FLAG_AFSDET) || \
((FLAG) == SAI_FLAG_LFSDET))
#define IS_SAI_BLOCK_CLEAR_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR) || \
((FLAG) == SAI_FLAG_MUTEDET) || \
((FLAG) == SAI_FLAG_WCKCFG) || \
((FLAG) == SAI_FLAG_FREQ) || \
((FLAG) == SAI_FLAG_CNRDY) || \
((FLAG) == SAI_FLAG_AFSDET) || \
((FLAG) == SAI_FLAG_LFSDET))
/**
* @}
*/
/** @defgroup SAI_Block_Fifo_Status_Level
* @{
*/
#define SAI_FIFOStatus_Empty ((uint32_t)0x00000000)
#define SAI_FIFOStatus_Less1QuarterFull ((uint32_t)0x00010000)
#define SAI_FIFOStatus_1QuarterFull ((uint32_t)0x00020000)
#define SAI_FIFOStatus_HalfFull ((uint32_t)0x00030000)
#define SAI_FIFOStatus_3QuartersFull ((uint32_t)0x00040000)
#define SAI_FIFOStatus_Full ((uint32_t)0x00050000)
#define IS_SAI_BLOCK_FIFO_STATUS(STATUS) (((STATUS) == SAI_FIFOStatus_Less1QuarterFull ) || \
((STATUS) == SAI_FIFOStatus_HalfFull) || \
((STATUS) == SAI_FIFOStatus_1QuarterFull) || \
((STATUS) == SAI_FIFOStatus_3QuartersFull) || \
((STATUS) == SAI_FIFOStatus_Full) || \
((STATUS) == SAI_FIFOStatus_Empty))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Function used to set the SAI configuration to the default reset state *****/
void SAI_DeInit(SAI_TypeDef* SAIx);
/* Initialization and Configuration functions *********************************/
void SAI_Init(SAI_Block_TypeDef* SAI_Block_x, SAI_InitTypeDef* SAI_InitStruct);
void SAI_FrameInit(SAI_Block_TypeDef* SAI_Block_x, SAI_FrameInitTypeDef* SAI_FrameInitStruct);
void SAI_SlotInit(SAI_Block_TypeDef* SAI_Block_x, SAI_SlotInitTypeDef* SAI_SlotInitStruct);
void SAI_StructInit(SAI_InitTypeDef* SAI_InitStruct);
void SAI_FrameStructInit(SAI_FrameInitTypeDef* SAI_FrameInitStruct);
void SAI_SlotStructInit(SAI_SlotInitTypeDef* SAI_SlotInitStruct);
void SAI_Cmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState);
void SAI_MonoModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_Mono_StreoMode);
void SAI_TRIStateConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_TRIState);
void SAI_CompandingModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_CompandingMode);
void SAI_MuteModeCmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState);
void SAI_MuteValueConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteValue);
void SAI_MuteFrameCounterConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteCounter);
void SAI_FlushFIFO(SAI_Block_TypeDef* SAI_Block_x);
/* Data transfers functions ***************************************************/
void SAI_SendData(SAI_Block_TypeDef* SAI_Block_x, uint32_t Data);
uint32_t SAI_ReceiveData(SAI_Block_TypeDef* SAI_Block_x);
/* DMA transfers management functions *****************************************/
void SAI_DMACmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void SAI_ITConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState);
FlagStatus SAI_GetFlagStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG);
void SAI_ClearFlag(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG);
ITStatus SAI_GetITStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT);
void SAI_ClearITPendingBit(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT);
FunctionalState SAI_GetCmdStatus(SAI_Block_TypeDef* SAI_Block_x);
uint32_t SAI_GetFIFOStatus(SAI_Block_TypeDef* SAI_Block_x);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F4xx_SAI_H */
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

32
example/libs/StmCoreNPheriph/inc/stm32f4xx_sdio.h
View File

@@ -2,21 +2,27 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_sdio.h * @file stm32f4xx_sdio.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the SDIO firmware * @brief This file contains all the functions prototypes for the SDIO firmware
* library. * library.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -77,7 +83,7 @@ typedef struct
uint32_t SDIO_Response; /*!< Specifies the SDIO response type. uint32_t SDIO_Response; /*!< Specifies the SDIO response type.
This parameter can be a value of @ref SDIO_Response_Type */ This parameter can be a value of @ref SDIO_Response_Type */
uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled. uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait for interrupt request is enabled or disabled.
This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
@@ -453,8 +459,8 @@ typedef struct
* @{ * @{
*/ */
#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000) #define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)
#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001) #define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)
#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
((MODE) == SDIO_ReadWaitMode_DATA2)) ((MODE) == SDIO_ReadWaitMode_DATA2))
/** /**
@@ -527,4 +533,4 @@ void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

46
example/libs/StmCoreNPheriph/inc/stm32f4xx_spi.h
View File

@@ -2,21 +2,27 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_spi.h * @file stm32f4xx_spi.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the SPI * @brief This file contains all the functions prototypes for the SPI
* firmware library. * firmware library.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -112,19 +118,25 @@ typedef struct
#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ #define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
((PERIPH) == SPI2) || \ ((PERIPH) == SPI2) || \
((PERIPH) == SPI3)) ((PERIPH) == SPI3) || \
((PERIPH) == SPI4) || \
((PERIPH) == SPI5) || \
((PERIPH) == SPI6))
#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \ #define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \
((PERIPH) == SPI2) || \ ((PERIPH) == SPI2) || \
((PERIPH) == SPI3) || \ ((PERIPH) == SPI3) || \
((PERIPH) == SPI4) || \
((PERIPH) == SPI5) || \
((PERIPH) == SPI6) || \
((PERIPH) == I2S2ext) || \ ((PERIPH) == I2S2ext) || \
((PERIPH) == I2S3ext)) ((PERIPH) == I2S3ext))
#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ #define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
((PERIPH) == SPI3)) ((PERIPH) == SPI3))
#define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \ #define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \
((PERIPH) == SPI3) || \ ((PERIPH) == SPI3) || \
((PERIPH) == I2S2ext) || \ ((PERIPH) == I2S2ext) || \
((PERIPH) == I2S3ext)) ((PERIPH) == I2S3ext))
@@ -534,4 +546,4 @@ void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

123
example/libs/StmCoreNPheriph/inc/stm32f4xx_syscfg.h
View File

@@ -2,21 +2,27 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_syscfg.h * @file stm32f4xx_syscfg.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the SYSCFG firmware * @brief This file contains all the functions prototypes for the SYSCFG firmware
* library. * library.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -58,16 +64,21 @@
#define EXTI_PortSourceGPIOG ((uint8_t)0x06) #define EXTI_PortSourceGPIOG ((uint8_t)0x06)
#define EXTI_PortSourceGPIOH ((uint8_t)0x07) #define EXTI_PortSourceGPIOH ((uint8_t)0x07)
#define EXTI_PortSourceGPIOI ((uint8_t)0x08) #define EXTI_PortSourceGPIOI ((uint8_t)0x08)
#define EXTI_PortSourceGPIOJ ((uint8_t)0x09)
#define EXTI_PortSourceGPIOK ((uint8_t)0x0A)
#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \ #define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
((PORTSOURCE) == EXTI_PortSourceGPIOE) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
((PORTSOURCE) == EXTI_PortSourceGPIOF) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \
((PORTSOURCE) == EXTI_PortSourceGPIOG) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \
((PORTSOURCE) == EXTI_PortSourceGPIOH) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOH) || \
((PORTSOURCE) == EXTI_PortSourceGPIOI)) ((PORTSOURCE) == EXTI_PortSourceGPIOI) || \
((PORTSOURCE) == EXTI_PortSourceGPIOJ) || \
((PORTSOURCE) == EXTI_PortSourceGPIOK))
/** /**
* @} * @}
*/ */
@@ -92,16 +103,16 @@
#define EXTI_PinSource13 ((uint8_t)0x0D) #define EXTI_PinSource13 ((uint8_t)0x0D)
#define EXTI_PinSource14 ((uint8_t)0x0E) #define EXTI_PinSource14 ((uint8_t)0x0E)
#define EXTI_PinSource15 ((uint8_t)0x0F) #define EXTI_PinSource15 ((uint8_t)0x0F)
#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ #define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
((PINSOURCE) == EXTI_PinSource1) || \ ((PINSOURCE) == EXTI_PinSource1) || \
((PINSOURCE) == EXTI_PinSource2) || \ ((PINSOURCE) == EXTI_PinSource2) || \
((PINSOURCE) == EXTI_PinSource3) || \ ((PINSOURCE) == EXTI_PinSource3) || \
((PINSOURCE) == EXTI_PinSource4) || \ ((PINSOURCE) == EXTI_PinSource4) || \
((PINSOURCE) == EXTI_PinSource5) || \ ((PINSOURCE) == EXTI_PinSource5) || \
((PINSOURCE) == EXTI_PinSource6) || \ ((PINSOURCE) == EXTI_PinSource6) || \
((PINSOURCE) == EXTI_PinSource7) || \ ((PINSOURCE) == EXTI_PinSource7) || \
((PINSOURCE) == EXTI_PinSource8) || \ ((PINSOURCE) == EXTI_PinSource8) || \
((PINSOURCE) == EXTI_PinSource9) || \ ((PINSOURCE) == EXTI_PinSource9) || \
((PINSOURCE) == EXTI_PinSource10) || \ ((PINSOURCE) == EXTI_PinSource10) || \
((PINSOURCE) == EXTI_PinSource11) || \ ((PINSOURCE) == EXTI_PinSource11) || \
((PINSOURCE) == EXTI_PinSource12) || \ ((PINSOURCE) == EXTI_PinSource12) || \
@@ -118,13 +129,38 @@
*/ */
#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00) #define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01) #define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)
#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02)
#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03) #define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
#define SYSCFG_MemoryRemap_SDRAM ((uint8_t)0x04)
#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ #if defined (STM32F40_41xxx)
((REMAP) == SYSCFG_MemoryRemap_SRAM) || \ #define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02)
((REMAP) == SYSCFG_MemoryRemap_FSMC)) #endif /* STM32F40_41xxx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define SYSCFG_MemoryRemap_FMC ((uint8_t)0x02)
#endif /* STM32F427_437xx || STM32F429_439xx */
#if defined (STM32F40_41xxx)
#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
((REMAP) == SYSCFG_MemoryRemap_SRAM) || \
((REMAP) == SYSCFG_MemoryRemap_FSMC))
#endif /* STM32F40_41xxx */
#if defined (STM32F401xx) || defined (STM32F411xE)
#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
((REMAP) == SYSCFG_MemoryRemap_SRAM))
#endif /* STM32F401xx || STM32F411xE */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
((REMAP) == SYSCFG_MemoryRemap_SRAM) || \
((REMAP) == SYSCFG_MemoryRemap_SDRAM) || \
((REMAP) == SYSCFG_MemoryRemap_FMC))
#endif /* STM32F427_437xx || STM32F429_439xx */
/** /**
* @} * @}
*/ */
@@ -133,11 +169,11 @@
/** @defgroup SYSCFG_ETHERNET_Media_Interface /** @defgroup SYSCFG_ETHERNET_Media_Interface
* @{ * @{
*/ */
#define SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000) #define SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000)
#define SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001) #define SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001)
#define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \ #define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \
((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII)) ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII))
/** /**
* @} * @}
*/ */
@@ -150,10 +186,11 @@
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
void SYSCFG_DeInit(void); void SYSCFG_DeInit(void);
void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap); void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); void SYSCFG_MemorySwappingBank(FunctionalState NewState);
void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface); void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
void SYSCFG_CompensationCellCmd(FunctionalState NewState); void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface);
void SYSCFG_CompensationCellCmd(FunctionalState NewState);
FlagStatus SYSCFG_GetCompensationCellStatus(void); FlagStatus SYSCFG_GetCompensationCellStatus(void);
#ifdef __cplusplus #ifdef __cplusplus
@@ -170,4 +207,4 @@ FlagStatus SYSCFG_GetCompensationCellStatus(void);
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
example/libs/StmCoreNPheriph/inc/stm32f4xx_tim.h
View File

@@ -2,21 +2,27 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_tim.h * @file stm32f4xx_tim.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the TIM firmware * @brief This file contains all the functions prototypes for the TIM firmware
* library. * library.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -1141,4 +1147,4 @@ void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

32
example/libs/StmCoreNPheriph/inc/stm32f4xx_usart.h
View File

@@ -2,21 +2,27 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_usart.h * @file stm32f4xx_usart.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the USART * @brief This file contains all the functions prototypes for the USART
* firmware library. * firmware library.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -106,7 +112,9 @@ typedef struct
((PERIPH) == USART3) || \ ((PERIPH) == USART3) || \
((PERIPH) == UART4) || \ ((PERIPH) == UART4) || \
((PERIPH) == UART5) || \ ((PERIPH) == UART5) || \
((PERIPH) == USART6)) ((PERIPH) == USART6) || \
((PERIPH) == UART7) || \
((PERIPH) == UART8))
#define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \ #define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \
((PERIPH) == USART2) || \ ((PERIPH) == USART2) || \
@@ -420,4 +428,4 @@ void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
example/libs/StmCoreNPheriph/inc/stm32f4xx_wwdg.h
View File

@@ -2,21 +2,27 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_wwdg.h * @file stm32f4xx_wwdg.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file contains all the functions prototypes for the WWDG firmware * @brief This file contains all the functions prototypes for the WWDG firmware
* library. * library.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -102,4 +108,4 @@ void WWDG_ClearFlag(void);
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

28
example/libs/StmCoreNPheriph/inc/system_stm32f4xx.h
View File

@@ -2,20 +2,26 @@
****************************************************************************** ******************************************************************************
* @file system_stm32f4xx.h * @file system_stm32f4xx.h
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -96,4 +102,4 @@ extern void SystemCoreClockUpdate(void);
/** /**
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
example/libs/StmCoreNPheriph/src/misc.c
View File

@@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file misc.c * @file misc.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides all the miscellaneous firmware functions (add-on * @brief This file provides all the miscellaneous firmware functions (add-on
* to CMSIS functions). * to CMSIS functions).
* *
@@ -55,14 +55,20 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -240,4 +246,4 @@ void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

511
example/libs/StmCoreNPheriph/src/stm32f4xx_adc.c
View File

@@ -2,96 +2,104 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_adc.c * @file stm32f4xx_adc.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides firmware functions to manage the following * @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) peripheral: * functionalities of the Analog to Digital Convertor (ADC) peripheral:
* - Initialization and Configuration (in addition to ADC multi mode * + Initialization and Configuration (in addition to ADC multi mode
* selection) * selection)
* - Analog Watchdog configuration * + Analog Watchdog configuration
* - Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT * + Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT
* management * management
* - Regular Channels Configuration * + Regular Channels Configuration
* - Regular Channels DMA Configuration * + Regular Channels DMA Configuration
* - Injected channels Configuration * + Injected channels Configuration
* - Interrupts and flags management * + Interrupts and flags management
* *
* @verbatim @verbatim
* ===============================================================================
* =================================================================== ##### How to use this driver #####
* How to use this driver ===============================================================================
* =================================================================== [..]
(#) Enable the ADC interface clock using
* 1. Enable the ADC interface clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE);
* RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE);
* (#) ADC pins configuration
* 2. ADC pins configuration (++) Enable the clock for the ADC GPIOs using the following function:
* - Enable the clock for the ADC GPIOs using the following function: RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
* RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); (++) Configure these ADC pins in analog mode using GPIO_Init();
* - Configure these ADC pins in analog mode using GPIO_Init();
* (#) Configure the ADC Prescaler, conversion resolution and data
* 3. Configure the ADC Prescaler, conversion resolution and data alignment using the ADC_Init() function.
* alignment using the ADC_Init() function. (#) Activate the ADC peripheral using ADC_Cmd() function.
* 4. Activate the ADC peripheral using ADC_Cmd() function.
* *** Regular channels group configuration ***
* Regular channels group configuration ============================================
* ==================================== [..]
* - To configure the ADC regular channels group features, use (+) To configure the ADC regular channels group features, use
* ADC_Init() and ADC_RegularChannelConfig() functions. ADC_Init() and ADC_RegularChannelConfig() functions.
* - To activate the continuous mode, use the ADC_continuousModeCmd() (+) To activate the continuous mode, use the ADC_continuousModeCmd()
* function. function.
* - To configurate and activate the Discontinuous mode, use the (+) To configurate and activate the Discontinuous mode, use the
* ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions. ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions.
* - To read the ADC converted values, use the ADC_GetConversionValue() (+) To read the ADC converted values, use the ADC_GetConversionValue()
* function. function.
*
* Multi mode ADCs Regular channels configuration *** Multi mode ADCs Regular channels configuration ***
* =============================================== ======================================================
* - Refer to "Regular channels group configuration" description to [..]
* configure the ADC1, ADC2 and ADC3 regular channels. (+) Refer to "Regular channels group configuration" description to
* - Select the Multi mode ADC regular channels features (dual or configure the ADC1, ADC2 and ADC3 regular channels.
* triple mode) using ADC_CommonInit() function and configure (+) Select the Multi mode ADC regular channels features (dual or
* the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd() triple mode) using ADC_CommonInit() function and configure
* functions. the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd()
* - Read the ADCs converted values using the functions.
* ADC_GetMultiModeConversionValue() function. (+) Read the ADCs converted values using the
* ADC_GetMultiModeConversionValue() function.
* DMA for Regular channels group features configuration
* ====================================================== *** DMA for Regular channels group features configuration ***
* - To enable the DMA mode for regular channels group, use the =============================================================
* ADC_DMACmd() function. [..]
* - To enable the generation of DMA requests continuously at the end (+) To enable the DMA mode for regular channels group, use the
* of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() ADC_DMACmd() function.
* function. (+) To enable the generation of DMA requests continuously at the end
* of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd()
* Injected channels group configuration function.
* =====================================
* - To configure the ADC Injected channels group features, use *** Injected channels group configuration ***
* ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig() =============================================
* functions. [..]
* - To activate the continuous mode, use the ADC_continuousModeCmd() (+) To configure the ADC Injected channels group features, use
* function. ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig()
* - To activate the Injected Discontinuous mode, use the functions.
* ADC_InjectedDiscModeCmd() function. (+) To activate the continuous mode, use the ADC_continuousModeCmd()
* - To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() function.
* function. (+) To activate the Injected Discontinuous mode, use the
* - To read the ADC converted values, use the ADC_GetInjectedConversionValue() ADC_InjectedDiscModeCmd() function.
* function. (+) To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd()
* function.
* @endverbatim (+) To read the ADC converted values, use the ADC_GetInjectedConversionValue()
* function.
@endverbatim
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2> * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
****************************************************************************** * You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/ */
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@@ -176,23 +184,22 @@
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Initialization and Configuration functions ##### Initialization and Configuration functions #####
=============================================================================== ===============================================================================
This section provides functions allowing to: [..] This section provides functions allowing to:
- Initialize and configure the ADC Prescaler (+) Initialize and configure the ADC Prescaler
- ADC Conversion Resolution (12bit..6bit) (+) ADC Conversion Resolution (12bit..6bit)
- Scan Conversion Mode (multichannels or one channel) for regular group (+) Scan Conversion Mode (multichannel or one channel) for regular group
- ADC Continuous Conversion Mode (Continuous or Single conversion) for (+) ADC Continuous Conversion Mode (Continuous or Single conversion) for
regular group regular group
- External trigger Edge and source of regular group, (+) External trigger Edge and source of regular group,
- Converted data alignment (left or right) (+) Converted data alignment (left or right)
- The number of ADC conversions that will be done using the sequencer for (+) The number of ADC conversions that will be done using the sequencer for
regular channel group regular channel group
- Multi ADC mode selection (+) Multi ADC mode selection
- Direct memory access mode selection for multi ADC mode (+) Direct memory access mode selection for multi ADC mode
- Delay between 2 sampling phases (used in dual or triple interleaved modes) (+) Delay between 2 sampling phases (used in dual or triple interleaved modes)
- Enable or disable the ADC peripheral (+) Enable or disable the ADC peripheral
@endverbatim @endverbatim
* @{ * @{
*/ */
@@ -414,20 +421,18 @@ void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Analog Watchdog configuration functions ##### Analog Watchdog configuration functions #####
=============================================================================== ===============================================================================
[..] This section provides functions allowing to configure the Analog Watchdog
This section provides functions allowing to configure the Analog Watchdog (AWD) feature in the ADC.
(AWD) feature in the ADC.
A typical configuration Analog Watchdog is done following these steps : [..] A typical configuration Analog Watchdog is done following these steps :
1. the ADC guarded channel(s) is (are) selected using the (#) the ADC guarded channel(s) is (are) selected using the
ADC_AnalogWatchdogSingleChannelConfig() function. ADC_AnalogWatchdogSingleChannelConfig() function.
2. The Analog watchdog lower and higher threshold are configured using the (#) The Analog watchdog lower and higher threshold are configured using the
ADC_AnalogWatchdogThresholdsConfig() function. ADC_AnalogWatchdogThresholdsConfig() function.
3. The Analog watchdog is enabled and configured to enable the check, on one (#) The Analog watchdog is enabled and configured to enable the check, on one
or more channels, using the ADC_AnalogWatchdogCmd() function. or more channels, using the ADC_AnalogWatchdogCmd() function.
@endverbatim @endverbatim
* @{ * @{
*/ */
@@ -546,30 +551,29 @@ void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channe
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Temperature Sensor, Vrefint and VBAT management functions ##### Temperature Sensor, Vrefint and VBAT management functions #####
=============================================================================== ===============================================================================
[..] This section provides functions allowing to enable/ disable the internal
This section provides functions allowing to enable/ disable the internal connections between the ADC and the Temperature Sensor, the Vrefint and
connections between the ADC and the Temperature Sensor, the Vrefint and the the Vbat sources.
Vbat sources.
A typical configuration to get the Temperature sensor and Vrefint channels [..] A typical configuration to get the Temperature sensor and Vrefint channels
voltages is done following these steps : voltages is done following these steps :
1. Enable the internal connection of Temperature sensor and Vrefint sources (#) Enable the internal connection of Temperature sensor and Vrefint sources
with the ADC channels using ADC_TempSensorVrefintCmd() function. with the ADC channels using ADC_TempSensorVrefintCmd() function.
2. Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using (#) Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using
ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions
3. Get the voltage values, using ADC_GetConversionValue() or (#) Get the voltage values, using ADC_GetConversionValue() or
ADC_GetInjectedConversionValue(). ADC_GetInjectedConversionValue().
A typical configuration to get the VBAT channel voltage is done following [..] A typical configuration to get the VBAT channel voltage is done following
these steps : these steps :
1. Enable the internal connection of VBAT source with the ADC channel using (#) Enable the internal connection of VBAT source with the ADC channel using
ADC_VBATCmd() function. ADC_VBATCmd() function.
2. Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or (#) Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or
ADC_InjectedChannelConfig() functions ADC_InjectedChannelConfig() functions
3. Get the voltage value, using ADC_GetConversionValue() or (#) Get the voltage value, using ADC_GetConversionValue() or
ADC_GetInjectedConversionValue(). ADC_GetInjectedConversionValue().
@endverbatim @endverbatim
* @{ * @{
@@ -600,6 +604,10 @@ void ADC_TempSensorVrefintCmd(FunctionalState NewState)
/** /**
* @brief Enables or disables the VBAT (Voltage Battery) channel. * @brief Enables or disables the VBAT (Voltage Battery) channel.
*
* @note the Battery voltage measured is equal to VBAT/2 on STM32F40xx and
* STM32F41xx devices and equal to VBAT/4 on STM32F42xx and STM32F43xx devices
*
* @param NewState: new state of the VBAT channel. * @param NewState: new state of the VBAT channel.
* This parameter can be: ENABLE or DISABLE. * This parameter can be: ENABLE or DISABLE.
* @retval None * @retval None
@@ -629,40 +637,39 @@ void ADC_VBATCmd(FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Regular Channels Configuration functions ##### Regular Channels Configuration functions #####
=============================================================================== ===============================================================================
This section provides functions allowing to manage the ADC's regular channels, [..] This section provides functions allowing to manage the ADC's regular channels,
it is composed of 2 sub sections : it is composed of 2 sub sections :
1. Configuration and management functions for regular channels: This subsection (#) Configuration and management functions for regular channels: This subsection
provides functions allowing to configure the ADC regular channels : provides functions allowing to configure the ADC regular channels :
- Configure the rank in the regular group sequencer for each channel (++) Configure the rank in the regular group sequencer for each channel
- Configure the sampling time for each channel (++) Configure the sampling time for each channel
- select the conversion Trigger for regular channels (++) select the conversion Trigger for regular channels
- select the desired EOC event behavior configuration (++) select the desired EOC event behavior configuration
- Activate the continuous Mode (*) (++) Activate the continuous Mode (*)
- Activate the Discontinuous Mode (++) Activate the Discontinuous Mode
Please Note that the following features for regular channels are configurated -@@- Please Note that the following features for regular channels
using the ADC_Init() function : are configurated using the ADC_Init() function :
- scan mode activation (+@@) scan mode activation
- continuous mode activation (**) (+@@) continuous mode activation (**)
- External trigger source (+@@) External trigger source
- External trigger edge (+@@) External trigger edge
- number of conversion in the regular channels group sequencer. (+@@) number of conversion in the regular channels group sequencer.
@note (*) and (**) are performing the same configuration -@@- (*) and (**) are performing the same configuration
2. Get the conversion data: This subsection provides an important function in (#) Get the conversion data: This subsection provides an important function in
the ADC peripheral since it returns the converted data of the current the ADC peripheral since it returns the converted data of the current
regular channel. When the Conversion value is read, the EOC Flag is regular channel. When the Conversion value is read, the EOC Flag is
automatically cleared. automatically cleared.
@note For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions -@- For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions
results data (in the selected multi mode) can be returned in the same results data (in the selected multi mode) can be returned in the same
time using ADC_GetMultiModeConversionValue() function. time using ADC_GetMultiModeConversionValue() function.
@endverbatim @endverbatim
* @{ * @{
*/ */
@@ -846,7 +853,7 @@ FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_ALL_PERIPH(ADCx));
/* Check the status of SWSTART bit */ /* Check the status of SWSTART bit */
if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET) if ((ADCx->CR2 & ADC_CR2_SWSTART) != (uint32_t)RESET)
{ {
/* SWSTART bit is set */ /* SWSTART bit is set */
bitstatus = SET; bitstatus = SET;
@@ -1010,29 +1017,26 @@ uint32_t ADC_GetMultiModeConversionValue(void)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Regular Channels DMA Configuration functions ##### Regular Channels DMA Configuration functions #####
=============================================================================== ===============================================================================
[..] This section provides functions allowing to configure the DMA for ADC
This section provides functions allowing to configure the DMA for ADC regular regular channels.
channels. Since converted regular channel values are stored into a unique data
Since converted regular channel values are stored into a unique data register, register, it is useful to use DMA for conversion of more than one regular
it is useful to use DMA for conversion of more than one regular channel. This channel. This avoids the loss of the data already stored in the ADC
avoids the loss of the data already stored in the ADC Data register. Data register.
When the DMA mode is enabled (using the ADC_DMACmd() function), after each
When the DMA mode is enabled (using the ADC_DMACmd() function), after each conversion of a regular channel, a DMA request is generated.
conversion of a regular channel, a DMA request is generated. [..] Depending on the "DMA disable selection for Independent ADC mode"
configuration (using the ADC_DMARequestAfterLastTransferCmd() function),
Depending on the "DMA disable selection for Independent ADC mode" at the end of the last DMA transfer, two possibilities are allowed:
configuration (using the ADC_DMARequestAfterLastTransferCmd() function), (+) No new DMA request is issued to the DMA controller (feature DISABLED)
at the end of the last DMA transfer, two possibilities are allowed: (+) Requests can continue to be generated (feature ENABLED).
- No new DMA request is issued to the DMA controller (feature DISABLED) [..] Depending on the "DMA disable selection for multi ADC mode" configuration
- Requests can continue to be generated (feature ENABLED). (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function),
at the end of the last DMA transfer, two possibilities are allowed:
Depending on the "DMA disable selection for multi ADC mode" configuration (+) No new DMA request is issued to the DMA controller (feature DISABLED)
(using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function), (+) Requests can continue to be generated (feature ENABLED).
at the end of the last DMA transfer, two possibilities are allowed:
- No new DMA request is issued to the DMA controller (feature DISABLED)
- Requests can continue to be generated (feature ENABLED).
@endverbatim @endverbatim
* @{ * @{
@@ -1120,26 +1124,26 @@ void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Injected channels Configuration functions ##### Injected channels Configuration functions #####
=============================================================================== ===============================================================================
This section provide functions allowing to configure the ADC Injected channels, [..] This section provide functions allowing to configure the ADC Injected channels,
it is composed of 2 sub sections : it is composed of 2 sub sections :
1. Configuration functions for Injected channels: This subsection provides (#) Configuration functions for Injected channels: This subsection provides
functions allowing to configure the ADC injected channels : functions allowing to configure the ADC injected channels :
- Configure the rank in the injected group sequencer for each channel (++) Configure the rank in the injected group sequencer for each channel
- Configure the sampling time for each channel (++) Configure the sampling time for each channel
- Activate the Auto injected Mode (++) Activate the Auto injected Mode
- Activate the Discontinuous Mode (++) Activate the Discontinuous Mode
- scan mode activation (++) scan mode activation
- External/software trigger source (++) External/software trigger source
- External trigger edge (++) External trigger edge
- injected channels sequencer. (++) injected channels sequencer.
2. Get the Specified Injected channel conversion data: This subsection (#) Get the Specified Injected channel conversion data: This subsection
provides an important function in the ADC peripheral since it returns the provides an important function in the ADC peripheral since it returns the
converted data of the specific injected channel. converted data of the specific injected channel.
@endverbatim @endverbatim
* @{ * @{
@@ -1493,75 +1497,74 @@ uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedC
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Interrupts and flags management functions ##### Interrupts and flags management functions #####
=============================================================================== ===============================================================================
This section provides functions allowing to configure the ADC Interrupts and [..] This section provides functions allowing to configure the ADC Interrupts
to get the status and clear flags and Interrupts pending bits. and to get the status and clear flags and Interrupts pending bits.
Each ADC provides 4 Interrupts sources and 6 Flags which can be divided into [..] Each ADC provides 4 Interrupts sources and 6 Flags which can be divided
3 groups: into 3 groups:
I. Flags and Interrupts for ADC regular channels *** Flags and Interrupts for ADC regular channels ***
================================================= =====================================================
Flags : [..]
---------- (+) Flags :
1. ADC_FLAG_OVR : Overrun detection when regular converted data are lost (##) ADC_FLAG_OVR : Overrun detection when regular converted data are lost
2. ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate (depending (##) ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate
on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) the end of: (depending on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() )
==> a regular CHANNEL conversion the end of:
==> sequence of regular GROUP conversions . (+++) a regular CHANNEL conversion
(+++) sequence of regular GROUP conversions .
3. ADC_FLAG_STRT: Regular channel start ==> to indicate when regular CHANNEL (##) ADC_FLAG_STRT: Regular channel start ==> to indicate when regular
conversion starts. CHANNEL conversion starts.
[..]
Interrupts : (+) Interrupts :
------------ (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection
1. ADC_IT_OVR : specifies the interrupt source for Overrun detection event. event.
2. ADC_IT_EOC : specifies the interrupt source for Regular channel end of (##) ADC_IT_EOC : specifies the interrupt source for Regular channel end
conversion event. of conversion event.
II. Flags and Interrupts for ADC Injected channels *** Flags and Interrupts for ADC Injected channels ***
================================================= ======================================================
Flags : [..]
---------- (+) Flags :
1. ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate at (##) ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate
the end of injected GROUP conversion at the end of injected GROUP conversion
2. ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when (##) ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when
injected GROUP conversion starts. injected GROUP conversion starts.
[..]
(+) Interrupts :
(##) ADC_IT_JEOC : specifies the interrupt source for Injected channel
end of conversion event.
Interrupts : *** General Flags and Interrupts for the ADC ***
------------ ================================================
1. ADC_IT_JEOC : specifies the interrupt source for Injected channel end of [..]
conversion event. (+)Flags :
(##) ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage
III. General Flags and Interrupts for the ADC crosses the programmed thresholds values.
================================================= [..]
Flags : (+) Interrupts :
---------- (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog event.
1. ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage
crosses the programmed thresholds values.
Interrupts :
------------
1. ADC_IT_AWD : specifies the interrupt source for Analog watchdog event.
The user should identify which mode will be used in his application to manage [..] The user should identify which mode will be used in his application to
the ADC controller events: Polling mode or Interrupt mode. manage the ADC controller events: Polling mode or Interrupt mode.
In the Polling Mode it is advised to use the following functions: [..] In the Polling Mode it is advised to use the following functions:
- ADC_GetFlagStatus() : to check if flags events occur. (+) ADC_GetFlagStatus() : to check if flags events occur.
- ADC_ClearFlag() : to clear the flags events. (+) ADC_ClearFlag() : to clear the flags events.
In the Interrupt Mode it is advised to use the following functions: [..] In the Interrupt Mode it is advised to use the following functions:
- ADC_ITConfig() : to enable or disable the interrupt source. (+) ADC_ITConfig() : to enable or disable the interrupt source.
- ADC_GetITStatus() : to check if Interrupt occurs. (+) ADC_GetITStatus() : to check if Interrupt occurs.
- ADC_ClearITPendingBit() : to clear the Interrupt pending Bit (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit
(corresponding Flag). (corresponding Flag).
@endverbatim @endverbatim
* @{ * @{
*/ */
@@ -1739,4 +1742,4 @@ void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

454
example/libs/StmCoreNPheriph/src/stm32f4xx_can.c
View File

@@ -2,77 +2,81 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_can.c * @file stm32f4xx_can.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides firmware functions to manage the following * @brief This file provides firmware functions to manage the following
* functionalities of the Controller area network (CAN) peripheral: * functionalities of the Controller area network (CAN) peripheral:
* - Initialization and Configuration * + Initialization and Configuration
* - CAN Frames Transmission * + CAN Frames Transmission
* - CAN Frames Reception * + CAN Frames Reception
* - Operation modes switch * + Operation modes switch
* - Error management * + Error management
* - Interrupts and flags * + Interrupts and flags
* *
* @verbatim @verbatim
* ===============================================================================
* =================================================================== ##### How to use this driver #####
* How to use this driver ===============================================================================
* =================================================================== [..]
(#) Enable the CAN controller interface clock using
* 1. Enable the CAN controller interface clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); for CAN1
* RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); for CAN1 and RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE); for CAN2
* and RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE); for CAN2 -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
* @note In case you are using CAN2 only, you have to enable the CAN1 clock.
* (#) CAN pins configuration
* 2. CAN pins configuration (++) Enable the clock for the CAN GPIOs using the following function:
* - Enable the clock for the CAN GPIOs using the following function: RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
* RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); (++) Connect the involved CAN pins to AF9 using the following function
* - Connect the involved CAN pins to AF9 using the following function GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx);
* GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx); (++) Configure these CAN pins in alternate function mode by calling
* - Configure these CAN pins in alternate function mode by calling the function GPIO_Init();
* the function GPIO_Init();
* (#) Initialise and configure the CAN using CAN_Init() and
* 3. Initialise and configure the CAN using CAN_Init() and CAN_FilterInit() functions.
* CAN_FilterInit() functions.
* (#) Transmit the desired CAN frame using CAN_Transmit() function.
* 4. Transmit the desired CAN frame using CAN_Transmit() function.
* (#) Check the transmission of a CAN frame using CAN_TransmitStatus()
* 5. Check the transmission of a CAN frame using CAN_TransmitStatus() function.
* function.
* (#) Cancel the transmission of a CAN frame using CAN_CancelTransmit()
* 6. Cancel the transmission of a CAN frame using CAN_CancelTransmit() function.
* function.
* (#) Receive a CAN frame using CAN_Recieve() function.
* 7. Receive a CAN frame using CAN_Recieve() function.
* (#) Release the receive FIFOs using CAN_FIFORelease() function.
* 8. Release the receive FIFOs using CAN_FIFORelease() function.
* (#) Return the number of pending received frames using
* 9. Return the number of pending received frames using CAN_MessagePending() function.
* CAN_MessagePending() function.
* (#) To control CAN events you can use one of the following two methods:
* 10. To control CAN events you can use one of the following two methods: (++) Check on CAN flags using the CAN_GetFlagStatus() function.
* - Check on CAN flags using the CAN_GetFlagStatus() function. (++) Use CAN interrupts through the function CAN_ITConfig() at
* - Use CAN interrupts through the function CAN_ITConfig() at initialization phase and CAN_GetITStatus() function into
* initialization phase and CAN_GetITStatus() function into interrupt routines to check if the event has occurred or not.
* interrupt routines to check if the event has occurred or not. After checking on a flag you should clear it using CAN_ClearFlag()
* After checking on a flag you should clear it using CAN_ClearFlag() function. And after checking on an interrupt event you should
* function. And after checking on an interrupt event you should clear it using CAN_ClearITPendingBit() function.
* clear it using CAN_ClearITPendingBit() function.
* @endverbatim
*
* @endverbatim
*
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -138,17 +142,17 @@ static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Initialization and Configuration functions ##### Initialization and Configuration functions #####
=============================================================================== ===============================================================================
This section provides functions allowing to [..] This section provides functions allowing to
- Initialize the CAN peripherals : Prescaler, operating mode, the maximum number (+) Initialize the CAN peripherals : Prescaler, operating mode, the maximum
of time quanta to perform resynchronization, the number of time quanta in number of time quanta to perform resynchronization, the number of time
Bit Segment 1 and 2 and many other modes. quanta in Bit Segment 1 and 2 and many other modes.
Refer to @ref CAN_InitTypeDef for more details. Refer to @ref CAN_InitTypeDef for more details.
- Configures the CAN reception filter. (+) Configures the CAN reception filter.
- Select the start bank filter for slave CAN. (+) Select the start bank filter for slave CAN.
- Enables or disables the Debug Freeze mode for CAN (+) Enables or disables the Debug Freeze mode for CAN
- Enables or disables the CAN Time Trigger Operation communication mode (+)Enables or disables the CAN Time Trigger Operation communication mode
@endverbatim @endverbatim
* @{ * @{
@@ -551,12 +555,12 @@ void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
CAN Frames Transmission functions ##### CAN Frames Transmission functions #####
=============================================================================== ===============================================================================
This section provides functions allowing to [..] This section provides functions allowing to
- Initiate and transmit a CAN frame message (if there is an empty mailbox). (+) Initiate and transmit a CAN frame message (if there is an empty mailbox).
- Check the transmission status of a CAN Frame (+) Check the transmission status of a CAN Frame
- Cancel a transmit request (+) Cancel a transmit request
@endverbatim @endverbatim
* @{ * @{
@@ -723,12 +727,12 @@ void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
CAN Frames Reception functions ##### CAN Frames Reception functions #####
=============================================================================== ===============================================================================
This section provides functions allowing to [..] This section provides functions allowing to
- Receive a correct CAN frame (+) Receive a correct CAN frame
- Release a specified receive FIFO (2 FIFOs are available) (+) Release a specified receive FIFO (2 FIFOs are available)
- Return the number of the pending received CAN frames (+) Return the number of the pending received CAN frames
@endverbatim @endverbatim
* @{ * @{
@@ -844,12 +848,12 @@ uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
CAN Operation modes functions ##### CAN Operation modes functions #####
=============================================================================== ===============================================================================
This section provides functions allowing to select the CAN Operation modes [..] This section provides functions allowing to select the CAN Operation modes
- sleep mode (+) sleep mode
- normal mode (+) normal mode
- initialization mode (+) initialization mode
@endverbatim @endverbatim
* @{ * @{
@@ -1004,16 +1008,16 @@ uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
CAN Bus Error management functions ##### CAN Bus Error management functions #####
=============================================================================== ===============================================================================
This section provides functions allowing to [..] This section provides functions allowing to
- Return the CANx's last error code (LEC) (+) Return the CANx's last error code (LEC)
- Return the CANx Receive Error Counter (REC) (+) Return the CANx Receive Error Counter (REC)
- Return the LSB of the 9-bit CANx Transmit Error Counter(TEC). (+) Return the LSB of the 9-bit CANx Transmit Error Counter(TEC).
@note If TEC is greater than 255, The CAN is in bus-off state. -@- If TEC is greater than 255, The CAN is in bus-off state.
@note if REC or TEC are greater than 96, an Error warning flag occurs. -@- if REC or TEC are greater than 96, an Error warning flag occurs.
@note if REC or TEC are greater than 127, an Error Passive Flag occurs. -@- if REC or TEC are greater than 127, an Error Passive Flag occurs.
@endverbatim @endverbatim
* @{ * @{
@@ -1099,163 +1103,161 @@ uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Interrupts and flags management functions ##### Interrupts and flags management functions #####
=============================================================================== ===============================================================================
This section provides functions allowing to configure the CAN Interrupts and [..] This section provides functions allowing to configure the CAN Interrupts
to get the status and clear flags and Interrupts pending bits. and to get the status and clear flags and Interrupts pending bits.
The CAN provides 14 Interrupts sources and 15 Flags: The CAN provides 14 Interrupts sources and 15 Flags:
===============
Flags : *** Flags ***
=============== =============
The 15 flags can be divided on 4 groups: [..] The 15 flags can be divided on 4 groups:
A. Transmit Flags (+) Transmit Flags
----------------------- (++) CAN_FLAG_RQCP0,
CAN_FLAG_RQCP0, (++) CAN_FLAG_RQCP1,
CAN_FLAG_RQCP1, (++) CAN_FLAG_RQCP2 : Request completed MailBoxes 0, 1 and 2 Flags
CAN_FLAG_RQCP2 : Request completed MailBoxes 0, 1 and 2 Flags Set when when the last request (transmit or abort)
Set when when the last request (transmit or abort) has has been performed.
been performed.
B. Receive Flags (+) Receive Flags
-----------------------
CAN_FLAG_FMP0,
CAN_FLAG_FMP1 : FIFO 0 and 1 Message Pending Flags
set to signal that messages are pending in the receive
FIFO.
These Flags are cleared only by hardware.
CAN_FLAG_FF0, (++) CAN_FLAG_FMP0,
CAN_FLAG_FF1 : FIFO 0 and 1 Full Flags (++) CAN_FLAG_FMP1 : FIFO 0 and 1 Message Pending Flags
set when three messages are stored in the selected set to signal that messages are pending in the receive
FIFO. FIFO.
These Flags are cleared only by hardware.
CAN_FLAG_FOV0 (++) CAN_FLAG_FF0,
CAN_FLAG_FOV1 : FIFO 0 and 1 Overrun Flags (++) CAN_FLAG_FF1 : FIFO 0 and 1 Full Flags
set when a new message has been received and passed set when three messages are stored in the selected
the filter while the FIFO was full. FIFO.
C. Operating Mode Flags (++) CAN_FLAG_FOV0
----------------------- (++) CAN_FLAG_FOV1 : FIFO 0 and 1 Overrun Flags
CAN_FLAG_WKU : Wake up Flag set when a new message has been received and passed
set to signal that a SOF bit has been detected while the filter while the FIFO was full.
the CAN hardware was in Sleep mode.
(+) Operating Mode Flags
(++) CAN_FLAG_WKU : Wake up Flag
set to signal that a SOF bit has been detected while
the CAN hardware was in Sleep mode.
CAN_FLAG_SLAK : Sleep acknowledge Flag (++) CAN_FLAG_SLAK : Sleep acknowledge Flag
Set to signal that the CAN has entered Sleep Mode. Set to signal that the CAN has entered Sleep Mode.
D. Error Flags (+) Error Flags
-----------------------
CAN_FLAG_EWG : Error Warning Flag (++) CAN_FLAG_EWG : Error Warning Flag
Set when the warning limit has been reached (Receive Set when the warning limit has been reached (Receive
Error Counter or Transmit Error Counter greater than 96). Error Counter or Transmit Error Counter greater than 96).
This Flag is cleared only by hardware. This Flag is cleared only by hardware.
CAN_FLAG_EPV : Error Passive Flag (++) CAN_FLAG_EPV : Error Passive Flag
Set when the Error Passive limit has been reached Set when the Error Passive limit has been reached
(Receive Error Counter or Transmit Error Counter (Receive Error Counter or Transmit Error Counter
greater than 127). greater than 127).
This Flag is cleared only by hardware. This Flag is cleared only by hardware.
CAN_FLAG_BOF : Bus-Off Flag (++) CAN_FLAG_BOF : Bus-Off Flag
set when CAN enters the bus-off state. The bus-off set when CAN enters the bus-off state. The bus-off
state is entered on TEC overflow, greater than 255. state is entered on TEC overflow, greater than 255.
This Flag is cleared only by hardware. This Flag is cleared only by hardware.
CAN_FLAG_LEC : Last error code Flag (++) CAN_FLAG_LEC : Last error code Flag
set If a message has been transferred (reception or set If a message has been transferred (reception or
transmission) with error, and the error code is hold. transmission) with error, and the error code is hold.
=============== *** Interrupts ***
Interrupts : ==================
=============== [..] The 14 interrupts can be divided on 4 groups:
The 14 interrupts can be divided on 4 groups:
A. Transmit interrupt (+) Transmit interrupt
-----------------------
CAN_IT_TME : Transmit mailbox empty Interrupt (++) CAN_IT_TME : Transmit mailbox empty Interrupt
if enabled, this interrupt source is pending when if enabled, this interrupt source is pending when
no transmit request are pending for Tx mailboxes. no transmit request are pending for Tx mailboxes.
B. Receive Interrupts (+) Receive Interrupts
-----------------------
CAN_IT_FMP0, (++) CAN_IT_FMP0,
CAN_IT_FMP1 : FIFO 0 and FIFO1 message pending Interrupts (++) CAN_IT_FMP1 : FIFO 0 and FIFO1 message pending Interrupts
if enabled, these interrupt sources are pending when if enabled, these interrupt sources are pending
messages are pending in the receive FIFO. when messages are pending in the receive FIFO.
The corresponding interrupt pending bits are cleared The corresponding interrupt pending bits are cleared
only by hardware. only by hardware.
CAN_IT_FF0, (++) CAN_IT_FF0,
CAN_IT_FF1 : FIFO 0 and FIFO1 full Interrupts (++) CAN_IT_FF1 : FIFO 0 and FIFO1 full Interrupts
if enabled, these interrupt sources are pending when if enabled, these interrupt sources are pending
three messages are stored in the selected FIFO. when three messages are stored in the selected FIFO.
CAN_IT_FOV0, (++) CAN_IT_FOV0,
CAN_IT_FOV1 : FIFO 0 and FIFO1 overrun Interrupts (++) CAN_IT_FOV1 : FIFO 0 and FIFO1 overrun Interrupts
if enabled, these interrupt sources are pending when if enabled, these interrupt sources are pending
a new message has been received and passed the filter when a new message has been received and passed
while the FIFO was full. the filter while the FIFO was full.
C. Operating Mode Interrupts (+) Operating Mode Interrupts
-------------------------------
CAN_IT_WKU : Wake-up Interrupt (++) CAN_IT_WKU : Wake-up Interrupt
if enabled, this interrupt source is pending when if enabled, this interrupt source is pending when
a SOF bit has been detected while the CAN hardware was a SOF bit has been detected while the CAN hardware
in Sleep mode. was in Sleep mode.
CAN_IT_SLK : Sleep acknowledge Interrupt (++) CAN_IT_SLK : Sleep acknowledge Interrupt
if enabled, this interrupt source is pending when if enabled, this interrupt source is pending when
the CAN has entered Sleep Mode. the CAN has entered Sleep Mode.
D. Error Interrupts (+) Error Interrupts
-----------------------
CAN_IT_EWG : Error warning Interrupt (++) CAN_IT_EWG : Error warning Interrupt
if enabled, this interrupt source is pending when if enabled, this interrupt source is pending when
the warning limit has been reached (Receive Error the warning limit has been reached (Receive Error
Counter or Transmit Error Counter=96). Counter or Transmit Error Counter=96).
CAN_IT_EPV : Error passive Interrupt (++) CAN_IT_EPV : Error passive Interrupt
if enabled, this interrupt source is pending when if enabled, this interrupt source is pending when
the Error Passive limit has been reached (Receive the Error Passive limit has been reached (Receive
Error Counter or Transmit Error Counter>127). Error Counter or Transmit Error Counter>127).
CAN_IT_BOF : Bus-off Interrupt (++) CAN_IT_BOF : Bus-off Interrupt
if enabled, this interrupt source is pending when if enabled, this interrupt source is pending when
CAN enters the bus-off state. The bus-off state is CAN enters the bus-off state. The bus-off state is
entered on TEC overflow, greater than 255. entered on TEC overflow, greater than 255.
This Flag is cleared only by hardware. This Flag is cleared only by hardware.
CAN_IT_LEC : Last error code Interrupt (++) CAN_IT_LEC : Last error code Interrupt
if enabled, this interrupt source is pending when if enabled, this interrupt source is pending when
a message has been transferred (reception or a message has been transferred (reception or
transmission) with error, and the error code is hold. transmission) with error, and the error code is hold.
CAN_IT_ERR : Error Interrupt (++) CAN_IT_ERR : Error Interrupt
if enabled, this interrupt source is pending when if enabled, this interrupt source is pending when
an error condition is pending. an error condition is pending.
[..] Managing the CAN controller events :
Managing the CAN controller events :
------------------------------------ The user should identify which mode will be used in his application to
The user should identify which mode will be used in his application to manage manage the CAN controller events: Polling mode or Interrupt mode.
the CAN controller events: Polling mode or Interrupt mode.
1. In the Polling Mode it is advised to use the following functions: (#) In the Polling Mode it is advised to use the following functions:
- CAN_GetFlagStatus() : to check if flags events occur. (++) CAN_GetFlagStatus() : to check if flags events occur.
- CAN_ClearFlag() : to clear the flags events. (++) CAN_ClearFlag() : to clear the flags events.
2. In the Interrupt Mode it is advised to use the following functions: (#) In the Interrupt Mode it is advised to use the following functions:
- CAN_ITConfig() : to enable or disable the interrupt source. (++) CAN_ITConfig() : to enable or disable the interrupt source.
- CAN_GetITStatus() : to check if Interrupt occurs. (++) CAN_GetITStatus() : to check if Interrupt occurs.
- CAN_ClearITPendingBit() : to clear the Interrupt pending Bit (corresponding Flag). (++) CAN_ClearITPendingBit() : to clear the Interrupt pending Bit
@note This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts (corresponding Flag).
-@@- This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts
pending bits since there are cleared only by hardware. pending bits since there are cleared only by hardware.
@endverbatim @endverbatim
@@ -1695,4 +1697,4 @@ static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
example/libs/StmCoreNPheriph/src/stm32f4xx_crc.c
View File

@@ -2,20 +2,26 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_crc.c * @file stm32f4xx_crc.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides all the CRC firmware functions. * @brief This file provides all the CRC firmware functions.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -124,4 +130,4 @@ uint8_t CRC_GetIDRegister(void)
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

604
example/libs/StmCoreNPheriph/src/stm32f4xx_cryp.c
View File

@@ -2,156 +2,161 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_cryp.c * @file stm32f4xx_cryp.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides firmware functions to manage the following * @brief This file provides firmware functions to manage the following
* functionalities of the Cryptographic processor (CRYP) peripheral: * functionalities of the Cryptographic processor (CRYP) peripheral:
* - Initialization and Configuration functions * + Initialization and Configuration functions
* - Data treatment functions * + Data treatment functions
* - Context swapping functions * + Context swapping functions
* - DMA interface function * + DMA interface function
* - Interrupts and flags management * + Interrupts and flags management
* *
* @verbatim @verbatim
* ===================================================================
* =================================================================== ##### How to use this driver #####
* How to use this driver ===================================================================
* =================================================================== [..]
* 1. Enable the CRYP controller clock using (#) Enable the CRYP controller clock using
* RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
*
* 2. Initialise the CRYP using CRYP_Init(), CRYP_KeyInit() and if
* needed CRYP_IVInit().
*
* 3. Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function.
*
* 4. Enable the CRYP controller using the CRYP_Cmd() function.
*
* 5. If using DMA for Data input and output transfer,
* Activate the needed DMA Requests using CRYP_DMACmd() function
* 6. If DMA is not used for data transfer, use CRYP_DataIn() and (#) Initialise the CRYP using CRYP_Init(), CRYP_KeyInit() and if needed
* CRYP_DataOut() functions to enter data to IN FIFO and get result CRYP_IVInit().
* from OUT FIFO.
* (#) Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function.
* 7. To control CRYP events you can use one of the following
* two methods: (#) Enable the CRYP controller using the CRYP_Cmd() function.
* - Check on CRYP flags using the CRYP_GetFlagStatus() function.
* - Use CRYP interrupts through the function CRYP_ITConfig() at (#) If using DMA for Data input and output transfer, activate the needed DMA
* initialization phase and CRYP_GetITStatus() function into Requests using CRYP_DMACmd() function
* interrupt routines in processing phase.
* (#) If DMA is not used for data transfer, use CRYP_DataIn() and CRYP_DataOut()
* 8. Save and restore Cryptographic processor context using functions to enter data to IN FIFO and get result from OUT FIFO.
* CRYP_SaveContext() and CRYP_RestoreContext() functions.
* (#) To control CRYP events you can use one of the following two methods:
* (++) Check on CRYP flags using the CRYP_GetFlagStatus() function.
* =================================================================== (++) Use CRYP interrupts through the function CRYP_ITConfig() at
* Procedure to perform an encryption or a decryption initialization phase and CRYP_GetITStatus() function into interrupt
* =================================================================== routines in processing phase.
*
* Initialization (#) Save and restore Cryptographic processor context using CRYP_SaveContext()
* =============== and CRYP_RestoreContext() functions.
* 1. Initialize the peripheral using CRYP_Init(), CRYP_KeyInit() and
* CRYP_IVInit functions:
* - Configure the key size (128-, 192- or 256-bit, in the AES only) *** Procedure to perform an encryption or a decryption ***
* - Enter the symmetric key ==========================================================
* - Configure the data type
* - In case of decryption in AES-ECB or AES-CBC, you must prepare *** Initialization ***
* the key: configure the key preparation mode. Then Enable the CRYP ======================
* peripheral using CRYP_Cmd() function: the BUSY flag is set. [..]
* Wait until BUSY flag is reset : the key is prepared for decryption (#) Initialize the peripheral using CRYP_Init(), CRYP_KeyInit() and CRYP_IVInit
* - Configure the algorithm and chaining (the DES/TDES in ECB/CBC, the functions:
* AES in ECB/CBC/CTR) (++) Configure the key size (128-, 192- or 256-bit, in the AES only)
* - Configure the direction (encryption/decryption). (++) Enter the symmetric key
* - Write the initialization vectors (in CBC or CTR modes only) (++) Configure the data type
* (++) In case of decryption in AES-ECB or AES-CBC, you must prepare
* 2. Flush the IN and OUT FIFOs using the CRYP_FIFOFlush() function the key: configure the key preparation mode. Then Enable the CRYP
* peripheral using CRYP_Cmd() function: the BUSY flag is set.
* Wait until BUSY flag is reset : the key is prepared for decryption
* Basic Processing mode (polling mode) (++) Configure the algorithm and chaining (the DES/TDES in ECB/CBC, the
* ==================================== AES in ECB/CBC/CTR)
* 1. Enable the cryptographic processor using CRYP_Cmd() function. (++) Configure the direction (encryption/decryption).
* (++) Write the initialization vectors (in CBC or CTR modes only)
* 2. Write the first blocks in the input FIFO (2 to 8 words) using
* CRYP_DataIn() function. (#) Flush the IN and OUT FIFOs using the CRYP_FIFOFlush() function
*
* 3. Repeat the following sequence until the complete message has been
* processed: *** Basic Processing mode (polling mode) ***
* ============================================
* a) Wait for flag CRYP_FLAG_OFNE occurs (using CRYP_GetFlagStatus() [..]
* function), then read the OUT-FIFO using CRYP_DataOut() function (#) Enable the cryptographic processor using CRYP_Cmd() function.
* (1 block or until the FIFO is empty)
* (#) Write the first blocks in the input FIFO (2 to 8 words) using
* b) Wait for flag CRYP_FLAG_IFNF occurs, (using CRYP_GetFlagStatus() CRYP_DataIn() function.
* function then write the IN FIFO using CRYP_DataIn() function
* (1 block or until the FIFO is full) (#) Repeat the following sequence until the complete message has been
* processed:
* 4. At the end of the processing, CRYP_FLAG_BUSY flag will be reset and
* both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is (++) Wait for flag CRYP_FLAG_OFNE occurs (using CRYP_GetFlagStatus()
* reset). You can disable the peripheral using CRYP_Cmd() function. function), then read the OUT-FIFO using CRYP_DataOut() function
* (1 block or until the FIFO is empty)
* Interrupts Processing mode
* =========================== (++) Wait for flag CRYP_FLAG_IFNF occurs, (using CRYP_GetFlagStatus()
* In this mode, Processing is done when the data are transferred by the function then write the IN FIFO using CRYP_DataIn() function
* CPU during interrupts. (1 block or until the FIFO is full)
*
* 1. Enable the interrupts CRYP_IT_INI and CRYP_IT_OUTI using (#) At the end of the processing, CRYP_FLAG_BUSY flag will be reset and
* CRYP_ITConfig() function. both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is
* reset). You can disable the peripheral using CRYP_Cmd() function.
* 2. Enable the cryptographic processor using CRYP_Cmd() function.
* *** Interrupts Processing mode ***
* 3. In the CRYP_IT_INI interrupt handler : load the input message into the ==================================
* IN FIFO using CRYP_DataIn() function . You can load 2 or 4 words at a [..] In this mode, Processing is done when the data are transferred by the
* time, or load data until the IN FIFO is full. When the last word of CPU during interrupts.
* the message has been entered into the IN FIFO, disable the CRYP_IT_INI
* interrupt (using CRYP_ITConfig() function). (#) Enable the interrupts CRYP_IT_INI and CRYP_IT_OUTI using CRYP_ITConfig()
* function.
* 4. In the CRYP_IT_OUTI interrupt handler : read the output message from
* the OUT FIFO using CRYP_DataOut() function. You can read 1 block (2 or (#) Enable the cryptographic processor using CRYP_Cmd() function.
* 4 words) at a time or read data until the FIFO is empty.
* When the last word has been read, INIM=0, BUSY=0 and both FIFOs are (#) In the CRYP_IT_INI interrupt handler : load the input message into the
* empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset). IN FIFO using CRYP_DataIn() function . You can load 2 or 4 words at a
* You can disable the CRYP_IT_OUTI interrupt (using CRYP_ITConfig() time, or load data until the IN FIFO is full. When the last word of
* function) and you can disable the peripheral using CRYP_Cmd() function. the message has been entered into the IN FIFO, disable the CRYP_IT_INI
* interrupt (using CRYP_ITConfig() function).
* DMA Processing mode
* ==================== (#) In the CRYP_IT_OUTI interrupt handler : read the output message from
* In this mode, Processing is done when the DMA is used to transfer the the OUT FIFO using CRYP_DataOut() function. You can read 1 block (2 or
* data from/to the memory. 4 words) at a time or read data until the FIFO is empty.
* When the last word has been read, INIM=0, BUSY=0 and both FIFOs are
* 1. Configure the DMA controller to transfer the input data from the empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset).
* memory using DMA_Init() function. You can disable the CRYP_IT_OUTI interrupt (using CRYP_ITConfig()
* The transfer length is the length of the message. function) and you can disable the peripheral using CRYP_Cmd() function.
* As message padding is not managed by the peripheral, the message
* length must be an entire number of blocks. The data are transferred *** DMA Processing mode ***
* in burst mode. The burst length is 4 words in the AES and 2 or 4 ===========================
* words in the DES/TDES. The DMA should be configured to set an [..] In this mode, Processing is done when the DMA is used to transfer the
* interrupt on transfer completion of the output data to indicate that data from/to the memory.
* the processing is finished.
* Refer to DMA peripheral driver for more details. (#) Configure the DMA controller to transfer the input data from the
* memory using DMA_Init() function.
* 2. Enable the cryptographic processor using CRYP_Cmd() function. The transfer length is the length of the message.
* Enable the DMA requests CRYP_DMAReq_DataIN and CRYP_DMAReq_DataOUT As message padding is not managed by the peripheral, the message
* using CRYP_DMACmd() function. length must be an entire number of blocks. The data are transferred
* in burst mode. The burst length is 4 words in the AES and 2 or 4
* 3. All the transfers and processing are managed by the DMA and the words in the DES/TDES. The DMA should be configured to set an
* cryptographic processor. The DMA transfer complete interrupt indicates interrupt on transfer completion of the output data to indicate that
* that the processing is complete. Both FIFOs are normally empty and the processing is finished.
* CRYP_FLAG_BUSY flag is reset. Refer to DMA peripheral driver for more details.
*
* @endverbatim (#) Enable the cryptographic processor using CRYP_Cmd() function.
Enable the DMA requests CRYP_DMAReq_DataIN and CRYP_DMAReq_DataOUT
using CRYP_DMACmd() function.
(#) All the transfers and processing are managed by the DMA and the
cryptographic processor. The DMA transfer complete interrupt indicates
that the processing is complete. Both FIFOs are normally empty and
CRYP_FLAG_BUSY flag is reset.
@endverbatim
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -187,23 +192,22 @@
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Initialization and Configuration functions ##### Initialization and Configuration functions #####
=============================================================================== ===============================================================================
This section provides functions allowing to [..] This section provides functions allowing to
- Initialize the cryptographic Processor using CRYP_Init() function (+) Initialize the cryptographic Processor using CRYP_Init() function
- Encrypt or Decrypt (++) Encrypt or Decrypt
- mode : TDES-ECB, TDES-CBC, (++) mode : TDES-ECB, TDES-CBC,
DES-ECB, DES-CBC, DES-ECB, DES-CBC,
AES-ECB, AES-CBC, AES-CTR, AES-Key AES-ECB, AES-CBC, AES-CTR, AES-Key, AES-GCM, AES-CCM
- DataType : 32-bit data, 16-bit data, bit data or bit-string (++) DataType : 32-bit data, 16-bit data, bit data or bit-string
- Key Size (only in AES modes) (++) Key Size (only in AES modes)
- Configure the Encrypt or Decrypt Key using CRYP_KeyInit() function (+) Configure the Encrypt or Decrypt Key using CRYP_KeyInit() function
- Configure the Initialization Vectors(IV) for CBC and CTR modes using (+) Configure the Initialization Vectors(IV) for CBC and CTR modes using
CRYP_IVInit() function. CRYP_IVInit() function.
- Flushes the IN and OUT FIFOs : using CRYP_FIFOFlush() function. (+) Flushes the IN and OUT FIFOs : using CRYP_FIFOFlush() function.
- Enable or disable the CRYP Processor using CRYP_Cmd() function (+) Enable or disable the CRYP Processor using CRYP_Cmd() function
@endverbatim @endverbatim
* @{ * @{
*/ */
@@ -244,10 +248,10 @@ void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct)
CRYP->CR |= CRYP_InitStruct->CRYP_DataType; CRYP->CR |= CRYP_InitStruct->CRYP_DataType;
/* select Key size (used only with AES algorithm) */ /* select Key size (used only with AES algorithm) */
if ((CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_ECB) || if ((CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_TDES_ECB) &&
(CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CBC) || (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_TDES_CBC) &&
(CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CTR) || (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_DES_ECB) &&
(CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_Key)) (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_DES_CBC))
{ {
assert_param(IS_CRYP_KEYSIZE(CRYP_InitStruct->CRYP_KeySize)); assert_param(IS_CRYP_KEYSIZE(CRYP_InitStruct->CRYP_KeySize));
CRYP->CR &= ~CRYP_CR_KEYSIZE; CRYP->CR &= ~CRYP_CR_KEYSIZE;
@@ -348,6 +352,35 @@ void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct)
CRYP_IVInitStruct->CRYP_IV1Right = 0; CRYP_IVInitStruct->CRYP_IV1Right = 0;
} }
/**
* @brief Configures the AES-CCM and AES-GCM phases
* @note This function is used only with AES-CCM or AES-GCM Algorithms
* @param CRYP_Phase: specifies the CRYP AES-CCM and AES-GCM phase to be configured.
* This parameter can be one of the following values:
* @arg CRYP_Phase_Init: Initialization phase
* @arg CRYP_Phase_Header: Header phase
* @arg CRYP_Phase_Payload: Payload phase
* @arg CRYP_Phase_Final: Final phase
* @retval None
*/
void CRYP_PhaseConfig(uint32_t CRYP_Phase)
{ uint32_t tempcr = 0;
/* Check the parameter */
assert_param(IS_CRYP_PHASE(CRYP_Phase));
/* Get the CR register */
tempcr = CRYP->CR;
/* Reset the phase configuration bits: GCMP_CCMPH */
tempcr &= (uint32_t)(~CRYP_CR_GCM_CCMPH);
/* Set the selected phase */
tempcr |= (uint32_t)CRYP_Phase;
/* Set the CR register */
CRYP->CR = tempcr;
}
/** /**
* @brief Flushes the IN and OUT FIFOs (that is read and write pointers of the * @brief Flushes the IN and OUT FIFOs (that is read and write pointers of the
* FIFOs are reset) * FIFOs are reset)
@@ -392,12 +425,12 @@ void CRYP_Cmd(FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
CRYP Data processing functions ##### CRYP Data processing functions #####
=============================================================================== ===============================================================================
This section provides functions allowing the encryption and decryption [..] This section provides functions allowing the encryption and decryption
operations: operations:
- Enter data to be treated in the IN FIFO : using CRYP_DataIn() function. (+) Enter data to be treated in the IN FIFO : using CRYP_DataIn() function.
- Get the data result from the OUT FIFO : using CRYP_DataOut() function. (+) Get the data result from the OUT FIFO : using CRYP_DataOut() function.
@endverbatim @endverbatim
* @{ * @{
@@ -433,20 +466,18 @@ uint32_t CRYP_DataOut(void)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Context swapping functions ##### Context swapping functions #####
=============================================================================== ===============================================================================
[..] This section provides functions allowing to save and store CRYP Context
This section provides functions allowing to save and store CRYP Context [..] It is possible to interrupt an encryption/ decryption/ key generation process
to perform another processing with a higher priority, and to complete the
It is possible to interrupt an encryption/ decryption/ key generation process interrupted process later on, when the higher-priority task is complete. To do
to perform another processing with a higher priority, and to complete the so, the context of the interrupted task must be saved from the CRYP registers
interrupted process later on, when the higher-priority task is complete. To do to memory, and then be restored from memory to the CRYP registers.
so, the context of the interrupted task must be saved from the CRYP registers
to memory, and then be restored from memory to the CRYP registers.
1. To save the current context, use CRYP_SaveContext() function (#) To save the current context, use CRYP_SaveContext() function
2. To restore the saved context, use CRYP_RestoreContext() function (#) To restore the saved context, use CRYP_RestoreContext() function
@endverbatim @endverbatim
* @{ * @{
@@ -506,11 +537,12 @@ ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave,
CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DOEN; CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DOEN;
CRYP->CR &= ~(uint32_t)CRYP_CR_CRYPEN; CRYP->CR &= ~(uint32_t)CRYP_CR_CRYPEN;
/* Save the current configuration (bits [9:2] in the CRYP_CR register) */ /* Save the current configuration (bit 19, bit[17:16] and bits [9:2] in the CRYP_CR register) */
CRYP_ContextSave->CR_bits9to2 = CRYP->CR & (CRYP_CR_KEYSIZE | CRYP_ContextSave->CR_CurrentConfig = CRYP->CR & (CRYP_CR_GCM_CCMPH |
CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE |
CRYP_CR_ALGOMODE | CRYP_CR_DATATYPE |
CRYP_CR_ALGODIR); CRYP_CR_ALGOMODE |
CRYP_CR_ALGODIR);
/* and, if not in ECB mode, the initialization vectors. */ /* and, if not in ECB mode, the initialization vectors. */
CRYP_ContextSave->CRYP_IV0LR = CRYP->IV0LR; CRYP_ContextSave->CRYP_IV0LR = CRYP->IV0LR;
@@ -528,6 +560,25 @@ ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave,
CRYP_ContextSave->CRYP_K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; CRYP_ContextSave->CRYP_K3LR = CRYP_KeyInitStruct->CRYP_Key3Left;
CRYP_ContextSave->CRYP_K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; CRYP_ContextSave->CRYP_K3RR = CRYP_KeyInitStruct->CRYP_Key3Right;
/* Save the content of context swap registers */
CRYP_ContextSave->CRYP_CSGCMCCMR[0] = CRYP->CSGCMCCM0R;
CRYP_ContextSave->CRYP_CSGCMCCMR[1] = CRYP->CSGCMCCM1R;
CRYP_ContextSave->CRYP_CSGCMCCMR[2] = CRYP->CSGCMCCM2R;
CRYP_ContextSave->CRYP_CSGCMCCMR[3] = CRYP->CSGCMCCM3R;
CRYP_ContextSave->CRYP_CSGCMCCMR[4] = CRYP->CSGCMCCM4R;
CRYP_ContextSave->CRYP_CSGCMCCMR[5] = CRYP->CSGCMCCM5R;
CRYP_ContextSave->CRYP_CSGCMCCMR[6] = CRYP->CSGCMCCM6R;
CRYP_ContextSave->CRYP_CSGCMCCMR[7] = CRYP->CSGCMCCM7R;
CRYP_ContextSave->CRYP_CSGCMR[0] = CRYP->CSGCM0R;
CRYP_ContextSave->CRYP_CSGCMR[1] = CRYP->CSGCM1R;
CRYP_ContextSave->CRYP_CSGCMR[2] = CRYP->CSGCM2R;
CRYP_ContextSave->CRYP_CSGCMR[3] = CRYP->CSGCM3R;
CRYP_ContextSave->CRYP_CSGCMR[4] = CRYP->CSGCM4R;
CRYP_ContextSave->CRYP_CSGCMR[5] = CRYP->CSGCM5R;
CRYP_ContextSave->CRYP_CSGCMR[6] = CRYP->CSGCM6R;
CRYP_ContextSave->CRYP_CSGCMR[7] = CRYP->CSGCM7R;
/* When needed, save the DMA status (pointers for IN and OUT messages, /* When needed, save the DMA status (pointers for IN and OUT messages,
number of remaining bytes, etc.) */ number of remaining bytes, etc.) */
@@ -552,7 +603,7 @@ void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore)
{ {
/* Configure the processor with the saved configuration */ /* Configure the processor with the saved configuration */
CRYP->CR = CRYP_ContextRestore->CR_bits9to2; CRYP->CR = CRYP_ContextRestore->CR_CurrentConfig;
/* restore The key value */ /* restore The key value */
CRYP->K0LR = CRYP_ContextRestore->CRYP_K0LR; CRYP->K0LR = CRYP_ContextRestore->CRYP_K0LR;
@@ -570,6 +621,25 @@ void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore)
CRYP->IV1LR = CRYP_ContextRestore->CRYP_IV1LR; CRYP->IV1LR = CRYP_ContextRestore->CRYP_IV1LR;
CRYP->IV1RR = CRYP_ContextRestore->CRYP_IV1RR; CRYP->IV1RR = CRYP_ContextRestore->CRYP_IV1RR;
/* Restore the content of context swap registers */
CRYP->CSGCMCCM0R = CRYP_ContextRestore->CRYP_CSGCMCCMR[0];
CRYP->CSGCMCCM1R = CRYP_ContextRestore->CRYP_CSGCMCCMR[1];
CRYP->CSGCMCCM2R = CRYP_ContextRestore->CRYP_CSGCMCCMR[2];
CRYP->CSGCMCCM3R = CRYP_ContextRestore->CRYP_CSGCMCCMR[3];
CRYP->CSGCMCCM4R = CRYP_ContextRestore->CRYP_CSGCMCCMR[4];
CRYP->CSGCMCCM5R = CRYP_ContextRestore->CRYP_CSGCMCCMR[5];
CRYP->CSGCMCCM6R = CRYP_ContextRestore->CRYP_CSGCMCCMR[6];
CRYP->CSGCMCCM7R = CRYP_ContextRestore->CRYP_CSGCMCCMR[7];
CRYP->CSGCM0R = CRYP_ContextRestore->CRYP_CSGCMR[0];
CRYP->CSGCM1R = CRYP_ContextRestore->CRYP_CSGCMR[1];
CRYP->CSGCM2R = CRYP_ContextRestore->CRYP_CSGCMR[2];
CRYP->CSGCM3R = CRYP_ContextRestore->CRYP_CSGCMR[3];
CRYP->CSGCM4R = CRYP_ContextRestore->CRYP_CSGCMR[4];
CRYP->CSGCM5R = CRYP_ContextRestore->CRYP_CSGCMR[5];
CRYP->CSGCM6R = CRYP_ContextRestore->CRYP_CSGCMR[6];
CRYP->CSGCM7R = CRYP_ContextRestore->CRYP_CSGCMR[7];
/* Enable the cryptographic processor */ /* Enable the cryptographic processor */
CRYP->CR |= CRYP_CR_CRYPEN; CRYP->CR |= CRYP_CR_CRYPEN;
} }
@@ -582,18 +652,17 @@ void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
CRYP's DMA interface Configuration function ##### CRYP's DMA interface Configuration function #####
=============================================================================== ===============================================================================
[..] This section provides functions allowing to configure the DMA interface for
This section provides functions allowing to configure the DMA interface for CRYP data input and output transfer.
CRYP data input and output transfer.
When the DMA mode is enabled (using the CRYP_DMACmd() function), data can be [..] When the DMA mode is enabled (using the CRYP_DMACmd() function), data can be
transferred: transferred:
- From memory to the CRYP IN FIFO using the DMA peripheral by enabling (+) From memory to the CRYP IN FIFO using the DMA peripheral by enabling
the CRYP_DMAReq_DataIN request. the CRYP_DMAReq_DataIN request.
- From the CRYP OUT FIFO to the memory using the DMA peripheral by enabling (+) From the CRYP OUT FIFO to the memory using the DMA peripheral by enabling
the CRYP_DMAReq_DataOUT request. the CRYP_DMAReq_DataOUT request.
@endverbatim @endverbatim
* @{ * @{
@@ -635,90 +704,83 @@ void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Interrupts and flags management functions ##### Interrupts and flags management functions #####
=============================================================================== ===============================================================================
[..] This section provides functions allowing to configure the CRYP Interrupts and
to get the status and Interrupts pending bits.
This section provides functions allowing to configure the CRYP Interrupts and [..] The CRYP provides 2 Interrupts sources and 7 Flags:
to get the status and Interrupts pending bits.
The CRYP provides 2 Interrupts sources and 7 Flags: *** Flags : ***
===============
Flags : [..]
------- (#) CRYP_FLAG_IFEM : Set when Input FIFO is empty. This Flag is cleared only
by hardware.
1. CRYP_FLAG_IFEM : Set when Input FIFO is empty.
This Flag is cleared only by hardware.
2. CRYP_FLAG_IFNF : Set when Input FIFO is not full. (#) CRYP_FLAG_IFNF : Set when Input FIFO is not full. This Flag is cleared
This Flag is cleared only by hardware. only by hardware.
3. CRYP_FLAG_INRIS : Set when Input FIFO Raw interrupt is pending (#) CRYP_FLAG_INRIS : Set when Input FIFO Raw interrupt is pending it gives
it gives the raw interrupt state prior to masking the raw interrupt state prior to masking of the input FIFO service interrupt.
of the input FIFO service interrupt. This Flag is cleared only by hardware.
This Flag is cleared only by hardware.
4. CRYP_FLAG_OFNE : Set when Output FIFO not empty. (#) CRYP_FLAG_OFNE : Set when Output FIFO not empty. This Flag is cleared
This Flag is cleared only by hardware. only by hardware.
5. CRYP_FLAG_OFFU : Set when Output FIFO is full. (#) CRYP_FLAG_OFFU : Set when Output FIFO is full. This Flag is cleared only
This Flag is cleared only by hardware. by hardware.
6. CRYP_FLAG_OUTRIS : Set when Output FIFO Raw interrupt is pending (#) CRYP_FLAG_OUTRIS : Set when Output FIFO Raw interrupt is pending it gives
it gives the raw interrupt state prior to masking the raw interrupt state prior to masking of the output FIFO service interrupt.
of the output FIFO service interrupt. This Flag is cleared only by hardware.
This Flag is cleared only by hardware.
7. CRYP_FLAG_BUSY : Set when the CRYP core is currently processing a (#) CRYP_FLAG_BUSY : Set when the CRYP core is currently processing a block
block of data or a key preparation (for AES of data or a key preparation (for AES decryption). This Flag is cleared
decryption). only by hardware. To clear it, the CRYP core must be disabled and the last
This Flag is cleared only by hardware. processing has completed.
To clear it, the CRYP core must be disabled and the
last processing has completed.
Interrupts : *** Interrupts : ***
------------ ====================
[..]
(#) CRYP_IT_INI : The input FIFO service interrupt is asserted when there
are less than 4 words in the input FIFO. This interrupt is associated to
CRYP_FLAG_INRIS flag.
1. CRYP_IT_INI : The input FIFO service interrupt is asserted when there -@- This interrupt is cleared by performing write operations to the input FIFO
are less than 4 words in the input FIFO. until it holds 4 or more words. The input FIFO service interrupt INMIS is
This interrupt is associated to CRYP_FLAG_INRIS flag. enabled with the CRYP enable bit. Consequently, when CRYP is disabled, the
INMIS signal is low even if the input FIFO is empty.
@note This interrupt is cleared by performing write operations
to the input FIFO until it holds 4 or more words. The
input FIFO service interrupt INMIS is enabled with the
CRYP enable bit. Consequently, when CRYP is disabled, the
INMIS signal is low even if the input FIFO is empty.
2. CRYP_IT_OUTI : The output FIFO service interrupt is asserted when there (#) CRYP_IT_OUTI : The output FIFO service interrupt is asserted when there
is one or more (32-bit word) data items in the output FIFO. is one or more (32-bit word) data items in the output FIFO. This interrupt
This interrupt is associated to CRYP_FLAG_OUTRIS flag. is associated to CRYP_FLAG_OUTRIS flag.
@note This interrupt is cleared by reading data from the output -@- This interrupt is cleared by reading data from the output FIFO until there
FIFO until there is no valid (32-bit) word left (that is, is no valid (32-bit) word left (that is, the interrupt follows the state
the interrupt follows the state of the OFNE (output FIFO of the OFNE (output FIFO not empty) flag).
not empty) flag).
*** Managing the CRYP controller events : ***
=============================================
[..] The user should identify which mode will be used in his application to manage
the CRYP controller events: Polling mode or Interrupt mode.
(#) In the Polling Mode it is advised to use the following functions:
(++) CRYP_GetFlagStatus() : to check if flags events occur.
-@@- The CRYPT flags do not need to be cleared since they are cleared as
soon as the associated event are reset.
Managing the CRYP controller events : (#) In the Interrupt Mode it is advised to use the following functions:
------------------------------------ (++) CRYP_ITConfig() : to enable or disable the interrupt source.
The user should identify which mode will be used in his application to manage (++) CRYP_GetITStatus() : to check if Interrupt occurs.
the CRYP controller events: Polling mode or Interrupt mode.
1. In the Polling Mode it is advised to use the following functions: -@@- The CRYPT interrupts have no pending bits, the interrupt is cleared as
- CRYP_GetFlagStatus() : to check if flags events occur. soon as the associated event is reset.
@note The CRYPT flags do not need to be cleared since they are cleared as
soon as the associated event are reset.
2. In the Interrupt Mode it is advised to use the following functions:
- CRYP_ITConfig() : to enable or disable the interrupt source.
- CRYP_GetITStatus() : to check if Interrupt occurs.
@note The CRYPT interrupts have no pending bits, the interrupt is cleared as
soon as the associated event is reset.
@endverbatim @endverbatim
* @{ * @{
@@ -783,6 +845,28 @@ ITStatus CRYP_GetITStatus(uint8_t CRYP_IT)
return bitstatus; return bitstatus;
} }
/**
* @brief Returns whether CRYP peripheral is enabled or disabled.
* @param none.
* @retval Current state of the CRYP peripheral (ENABLE or DISABLE).
*/
FunctionalState CRYP_GetCmdStatus(void)
{
FunctionalState state = DISABLE;
if ((CRYP->CR & CRYP_CR_CRYPEN) != 0)
{
/* CRYPEN bit is set */
state = ENABLE;
}
else
{
/* CRYPEN bit is reset */
state = DISABLE;
}
return state;
}
/** /**
* @brief Checks whether the specified CRYP flag is set or not. * @brief Checks whether the specified CRYP flag is set or not.
* @param CRYP_FLAG: specifies the CRYP flag to check. * @param CRYP_FLAG: specifies the CRYP flag to check.
@@ -847,4 +931,4 @@ FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG)
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

1135
example/libs/StmCoreNPheriph/src/stm32f4xx_cryp_aes.c
View File

File diff suppressed because it is too large Load Diff

69
example/libs/StmCoreNPheriph/src/stm32f4xx_cryp_des.c
View File

@@ -2,40 +2,45 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_cryp_des.c * @file stm32f4xx_cryp_des.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides high level functions to encrypt and decrypt an * @brief This file provides high level functions to encrypt and decrypt an
* input message using DES in ECB/CBC modes. * input message using DES in ECB/CBC modes.
* It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP * It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
* peripheral. * peripheral.
* *
* @verbatim @verbatim
*
* =================================================================== ===================================================================
* How to use this driver ##### How to use this driver #####
* =================================================================== ===================================================================
* 1. Enable The CRYP controller clock using [..]
* RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. (#) Enable The CRYP controller clock using
* RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
* 2. Encrypt and decrypt using DES in ECB Mode using CRYP_DES_ECB()
* function. (#) Encrypt and decrypt using DES in ECB Mode using CRYP_DES_ECB() function.
*
* 3. Encrypt and decrypt using DES in CBC Mode using CRYP_DES_CBC() (#) Encrypt and decrypt using DES in CBC Mode using CRYP_DES_CBC() function.
* function.
* @endverbatim
* @endverbatim
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -71,7 +76,7 @@
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
High Level DES functions ##### High Level DES functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
* @{ * @{
@@ -133,6 +138,12 @@ ErrorStatus CRYP_DES_ECB(uint8_t Mode, uint8_t Key[8], uint8_t *Input,
/* Enable Crypto processor */ /* Enable Crypto processor */
CRYP_Cmd(ENABLE); CRYP_Cmd(ENABLE);
if(CRYP_GetCmdStatus() == DISABLE)
{
/* The CRYP peripheral clock is not enabled or the device doesn't embedd
the CRYP peripheral (please check the device sales type. */
return(ERROR);
}
for(i=0; ((i<Ilength) && (status != ERROR)); i+=8) for(i=0; ((i<Ilength) && (status != ERROR)); i+=8)
{ {
@@ -236,6 +247,12 @@ ErrorStatus CRYP_DES_CBC(uint8_t Mode, uint8_t Key[8], uint8_t InitVectors[8],
/* Enable Crypto processor */ /* Enable Crypto processor */
CRYP_Cmd(ENABLE); CRYP_Cmd(ENABLE);
if(CRYP_GetCmdStatus() == DISABLE)
{
/* The CRYP peripheral clock is not enabled or the device doesn't embedd
the CRYP peripheral (please check the device sales type. */
return(ERROR);
}
for(i=0; ((i<Ilength) && (status != ERROR)); i+=8) for(i=0; ((i<Ilength) && (status != ERROR)); i+=8)
{ {
/* Write the Input block in the Input FIFO */ /* Write the Input block in the Input FIFO */
@@ -288,4 +305,4 @@ ErrorStatus CRYP_DES_CBC(uint8_t Mode, uint8_t Key[8], uint8_t InitVectors[8],
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

71
example/libs/StmCoreNPheriph/src/stm32f4xx_cryp_tdes.c
View File

@@ -2,40 +2,45 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_cryp_tdes.c * @file stm32f4xx_cryp_tdes.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides high level functions to encrypt and decrypt an * @brief This file provides high level functions to encrypt and decrypt an
* input message using TDES in ECB/CBC modes . * input message using TDES in ECB/CBC modes .
* It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP * It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
* peripheral. * peripheral.
* *
* @verbatim @verbatim
*
* =================================================================== ===============================================================================
* How to use this driver ##### How to use this driver #####
* =================================================================== ===============================================================================
* 1. Enable The CRYP controller clock using [..]
* RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. (#) Enable The CRYP controller clock using
* RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
* 2. Encrypt and decrypt using TDES in ECB Mode using CRYP_TDES_ECB()
* function. (#) Encrypt and decrypt using TDES in ECB Mode using CRYP_TDES_ECB() function.
*
* 3. Encrypt and decrypt using TDES in CBC Mode using CRYP_TDES_CBC() (#) Encrypt and decrypt using TDES in CBC Mode using CRYP_TDES_CBC() function.
* function.
* @endverbatim
* @endverbatim
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -71,10 +76,9 @@
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
High Level TDES functions ##### High Level TDES functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
* @{ * @{
*/ */
@@ -143,6 +147,12 @@ ErrorStatus CRYP_TDES_ECB(uint8_t Mode, uint8_t Key[24], uint8_t *Input,
/* Enable Crypto processor */ /* Enable Crypto processor */
CRYP_Cmd(ENABLE); CRYP_Cmd(ENABLE);
if(CRYP_GetCmdStatus() == DISABLE)
{
/* The CRYP peripheral clock is not enabled or the device doesn't embedd
the CRYP peripheral (please check the device sales type. */
return(ERROR);
}
for(i=0; ((i<Ilength) && (status != ERROR)); i+=8) for(i=0; ((i<Ilength) && (status != ERROR)); i+=8)
{ {
/* Write the Input block in the Input FIFO */ /* Write the Input block in the Input FIFO */
@@ -253,6 +263,13 @@ ErrorStatus CRYP_TDES_CBC(uint8_t Mode, uint8_t Key[24], uint8_t InitVectors[8],
/* Enable Crypto processor */ /* Enable Crypto processor */
CRYP_Cmd(ENABLE); CRYP_Cmd(ENABLE);
if(CRYP_GetCmdStatus() == DISABLE)
{
/* The CRYP peripheral clock is not enabled or the device doesn't embedd
the CRYP peripheral (please check the device sales type. */
return(ERROR);
}
for(i=0; ((i<Ilength) && (status != ERROR)); i+=8) for(i=0; ((i<Ilength) && (status != ERROR)); i+=8)
{ {
/* Write the Input block in the Input FIFO */ /* Write the Input block in the Input FIFO */
@@ -305,4 +322,4 @@ ErrorStatus CRYP_TDES_CBC(uint8_t Mode, uint8_t Key[24], uint8_t InitVectors[8],
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

223
example/libs/StmCoreNPheriph/src/stm32f4xx_dac.c
View File

@@ -2,114 +2,127 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_dac.c * @file stm32f4xx_dac.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides firmware functions to manage the following * @brief This file provides firmware functions to manage the following
* functionalities of the Digital-to-Analog Converter (DAC) peripheral: * functionalities of the Digital-to-Analog Converter (DAC) peripheral:
* - DAC channels configuration: trigger, output buffer, data format * + DAC channels configuration: trigger, output buffer, data format
* - DMA management * + DMA management
* - Interrupts and flags management * + Interrupts and flags management
* *
* @verbatim @verbatim
* ===============================================================================
* =================================================================== ##### DAC Peripheral features #####
* DAC Peripheral features ===============================================================================
* =================================================================== [..]
* *** DAC Channels ***
* DAC Channels ====================
* ============= [..]
* The device integrates two 12-bit Digital Analog Converters that can The device integrates two 12-bit Digital Analog Converters that can
* be used independently or simultaneously (dual mode): be used independently or simultaneously (dual mode):
* 1- DAC channel1 with DAC_OUT1 (PA4) as output (#) DAC channel1 with DAC_OUT1 (PA4) as output
* 1- DAC channel2 with DAC_OUT2 (PA5) as output (#) DAC channel2 with DAC_OUT2 (PA5) as output
*
* DAC Triggers *** DAC Triggers ***
* ============= ====================
* Digital to Analog conversion can be non-triggered using DAC_Trigger_None [..]
* and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register Digital to Analog conversion can be non-triggered using DAC_Trigger_None
* using DAC_SetChannel1Data() / DAC_SetChannel2Data() functions. and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register
* using DAC_SetChannel1Data() / DAC_SetChannel2Data() functions.
* Digital to Analog conversion can be triggered by: [..]
* 1- External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9. Digital to Analog conversion can be triggered by:
* The used pin (GPIOx_Pin9) must be configured in input mode. (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
* The used pin (GPIOx_Pin9) must be configured in input mode.
* 2- Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
* (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...) (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
* The timer TRGO event should be selected using TIM_SelectOutputTrigger() (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)
* The timer TRGO event should be selected using TIM_SelectOutputTrigger()
* 3- Software using DAC_Trigger_Software
* (#) Software using DAC_Trigger_Software
* DAC Buffer mode feature
* ======================== *** DAC Buffer mode feature ***
* Each DAC channel integrates an output buffer that can be used to ===============================
* reduce the output impedance, and to drive external loads directly [..]
* without having to add an external operational amplifier. Each DAC channel integrates an output buffer that can be used to
* To enable, the output buffer use reduce the output impedance, and to drive external loads directly
* DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable; without having to add an external operational amplifier.
* To enable, the output buffer use
* Refer to the device datasheet for more details about output DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
* impedance value with and without output buffer. [..]
* (@) Refer to the device datasheet for more details about output
* DAC wave generation feature impedance value with and without output buffer.
* =============================
* Both DAC channels can be used to generate *** DAC wave generation feature ***
* 1- Noise wave using DAC_WaveGeneration_Noise ===================================
* 2- Triangle wave using DAC_WaveGeneration_Triangle [..]
* Both DAC channels can be used to generate
* Wave generation can be disabled using DAC_WaveGeneration_None (#) Noise wave using DAC_WaveGeneration_Noise
* (#) Triangle wave using DAC_WaveGeneration_Triangle
* DAC data format
* ================ -@- Wave generation can be disabled using DAC_WaveGeneration_None
* The DAC data format can be:
* 1- 8-bit right alignment using DAC_Align_8b_R *** DAC data format ***
* 2- 12-bit left alignment using DAC_Align_12b_L =======================
* 3- 12-bit right alignment using DAC_Align_12b_R [..]
* The DAC data format can be:
* DAC data value to voltage correspondence (#) 8-bit right alignment using DAC_Align_8b_R
* ======================================== (#) 12-bit left alignment using DAC_Align_12b_L
* The analog output voltage on each DAC channel pin is determined (#) 12-bit right alignment using DAC_Align_12b_R
* by the following equation:
* DAC_OUTx = VREF+ * DOR / 4095 *** DAC data value to voltage correspondence ***
* with DOR is the Data Output Register ================================================
* VEF+ is the input voltage reference (refer to the device datasheet) [..]
* e.g. To set DAC_OUT1 to 0.7V, use The analog output voltage on each DAC channel pin is determined
* DAC_SetChannel1Data(DAC_Align_12b_R, 868); by the following equation:
* Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V DAC_OUTx = VREF+ * DOR / 4095
* with DOR is the Data Output Register
* DMA requests VEF+ is the input voltage reference (refer to the device datasheet)
* ============= e.g. To set DAC_OUT1 to 0.7V, use
* A DMA1 request can be generated when an external trigger (but not DAC_SetChannel1Data(DAC_Align_12b_R, 868);
* a software trigger) occurs if DMA1 requests are enabled using Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
* DAC_DMACmd()
* DMA1 requests are mapped as following: *** DMA requests ***
* 1- DAC channel1 : mapped on DMA1 Stream5 channel7 which must be =====================
* already configured [..]
* 2- DAC channel2 : mapped on DMA1 Stream6 channel7 which must be A DMA1 request can be generated when an external trigger (but not
* already configured a software trigger) occurs if DMA1 requests are enabled using
* DAC_DMACmd()
* =================================================================== [..]
* How to use this driver DMA1 requests are mapped as following:
* =================================================================== (#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be
* - DAC APB clock must be enabled to get write access to DAC already configured
* registers using (#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be
* RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE) already configured
* - Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
* - Configure the DAC channel using DAC_Init() function
* - Enable the DAC channel using DAC_Cmd() function ##### How to use this driver #####
* ===============================================================================
* @endverbatim [..]
* (+) DAC APB clock must be enabled to get write access to DAC
registers using
RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
(+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
(+) Configure the DAC channel using DAC_Init() function
(+) Enable the DAC channel using DAC_Cmd() function
@endverbatim
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -159,7 +172,7 @@
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
DAC channels configuration: trigger, output buffer, data format ##### DAC channels configuration: trigger, output buffer, data format #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -471,7 +484,7 @@ uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
DMA management functions ##### DMA management functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -520,7 +533,7 @@ void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Interrupts and flags management functions ##### Interrupts and flags management functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -698,4 +711,4 @@ void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
example/libs/StmCoreNPheriph/src/stm32f4xx_dbgmcu.c
View File

@@ -2,20 +2,26 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_dbgmcu.c * @file stm32f4xx_dbgmcu.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides all the DBGMCU firmware functions. * @brief This file provides all the DBGMCU firmware functions.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -171,4 +177,4 @@ void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

146
example/libs/StmCoreNPheriph/src/stm32f4xx_dcmi.c
View File

@@ -2,79 +2,83 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_dcmi.c * @file stm32f4xx_dcmi.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides firmware functions to manage the following * @brief This file provides firmware functions to manage the following
* functionalities of the DCMI peripheral: * functionalities of the DCMI peripheral:
* - Initialization and Configuration * + Initialization and Configuration
* - Image capture functions * + Image capture functions
* - Interrupts and flags management * + Interrupts and flags management
* *
* @verbatim @verbatim
* ===============================================================================
* ##### How to use this driver #####
* =================================================================== ===============================================================================
* How to use this driver [..]
* =================================================================== The sequence below describes how to use this driver to capture image
* from a camera module connected to the DCMI Interface.
* The sequence below describes how to use this driver to capture image This sequence does not take into account the configuration of the
* from a camera module connected to the DCMI Interface. camera module, which should be made before to configure and enable
* This sequence does not take into account the configuration of the the DCMI to capture images.
* camera module, which should be made before to configure and enable
* the DCMI to capture images. (#) Enable the clock for the DCMI and associated GPIOs using the following
* functions:
* 1. Enable the clock for the DCMI and associated GPIOs using the following functions: RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE);
* RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE); RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
* RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
* (#) DCMI pins configuration
* 2. DCMI pins configuration (++) Connect the involved DCMI pins to AF13 using the following function
* - Connect the involved DCMI pins to AF13 using the following function GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_DCMI);
* GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_DCMI); (++) Configure these DCMI pins in alternate function mode by calling
* - Configure these DCMI pins in alternate function mode by calling the function the function GPIO_Init();
* GPIO_Init();
* (#) Declare a DCMI_InitTypeDef structure, for example:
* 3. Declare a DCMI_InitTypeDef structure, for example: DCMI_InitTypeDef DCMI_InitStructure;
* DCMI_InitTypeDef DCMI_InitStructure; and fill the DCMI_InitStructure variable with the allowed values
* and fill the DCMI_InitStructure variable with the allowed values of the structure member.
* of the structure member.
* (#) Initialize the DCMI interface by calling the function
* 4. Initialize the DCMI interface by calling the function DCMI_Init(&DCMI_InitStructure);
* DCMI_Init(&DCMI_InitStructure);
* (#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR
* 5. Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR register to the destination memory buffer.
* register to the destination memory buffer.
* (#) Enable DCMI interface using the function
* 6. Enable DCMI interface using the function DCMI_Cmd(ENABLE);
* DCMI_Cmd(ENABLE);
* (#) Start the image capture using the function
* 7. Start the image capture using the function DCMI_CaptureCmd(ENABLE);
* DCMI_CaptureCmd(ENABLE);
* (#) At this stage the DCMI interface waits for the first start of frame,
* 8. At this stage the DCMI interface waits for the first start of frame, then a DMA request is generated continuously/once (depending on the
* then a DMA request is generated continuously/once (depending on the mode used, Continuous/Snapshot) to transfer the received data into
* mode used, Continuous/Snapshot) to transfer the received data into the destination memory.
* the destination memory.
* -@- If you need to capture only a rectangular window from the received
* @note If you need to capture only a rectangular window from the received image, you have to use the DCMI_CROPConfig() function to configure
* image, you have to use the DCMI_CROPConfig() function to configure the coordinates and size of the window to be captured, then enable
* the coordinates and size of the window to be captured, then enable the Crop feature using DCMI_CROPCmd(ENABLE);
* the Crop feature using DCMI_CROPCmd(ENABLE); In this case, the Crop configuration should be made before to enable
* In this case, the Crop configuration should be made before to enable and start the DCMI interface.
* and start the DCMI interface.
* @endverbatim
* @endverbatim
*
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -107,7 +111,7 @@
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Initialization and Configuration functions ##### Initialization and Configuration functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -279,7 +283,7 @@ void DCMI_JPEGCmd(FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Image capture functions ##### Image capture functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -350,7 +354,7 @@ uint32_t DCMI_ReadData(void)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Interrupts and flags management functions ##### Interrupts and flags management functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -418,7 +422,7 @@ FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG)
/* Get the DCMI register index */ /* Get the DCMI register index */
dcmireg = (((uint16_t)DCMI_FLAG) >> 12); dcmireg = (((uint16_t)DCMI_FLAG) >> 12);
if (dcmireg == 0x01) /* The FLAG is in RISR register */ if (dcmireg == 0x00) /* The FLAG is in RISR register */
{ {
tempreg= DCMI->RISR; tempreg= DCMI->RISR;
} }
@@ -531,4 +535,4 @@ void DCMI_ClearITPendingBit(uint16_t DCMI_IT)
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

474
example/libs/StmCoreNPheriph/src/stm32f4xx_dma.c
View File

@@ -2,113 +2,121 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_dma.c * @file stm32f4xx_dma.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides firmware functions to manage the following * @brief This file provides firmware functions to manage the following
* functionalities of the Direct Memory Access controller (DMA): * functionalities of the Direct Memory Access controller (DMA):
* - Initialization and Configuration * + Initialization and Configuration
* - Data Counter * + Data Counter
* - Double Buffer mode configuration and command * + Double Buffer mode configuration and command
* - Interrupts and flags management * + Interrupts and flags management
* *
* @verbatim @verbatim
* ===============================================================================
* =================================================================== ##### How to use this driver #####
* How to use this driver ===============================================================================
* =================================================================== [..]
* 1. Enable The DMA controller clock using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA1, ENABLE) (#) Enable The DMA controller clock using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA1, ENABLE)
* function for DMA1 or using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2, ENABLE) function for DMA1 or using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2, ENABLE)
* function for DMA2. function for DMA2.
*
* 2. Enable and configure the peripheral to be connected to the DMA Stream (#) Enable and configure the peripheral to be connected to the DMA Stream
* (except for internal SRAM / FLASH memories: no initialization is (except for internal SRAM / FLASH memories: no initialization is
* necessary). necessary).
*
* 3. For a given Stream, program the required configuration through following parameters: (#) For a given Stream, program the required configuration through following parameters:
* Source and Destination addresses, Transfer Direction, Transfer size, Source and Destination Source and Destination addresses, Transfer Direction, Transfer size, Source and Destination
* data formats, Circular or Normal mode, Stream Priority level, Source and Destination data formats, Circular or Normal mode, Stream Priority level, Source and Destination
* Incrementation mode, FIFO mode and its Threshold (if needed), Burst mode for Source and/or Incrementation mode, FIFO mode and its Threshold (if needed), Burst
* Destination (if needed) using the DMA_Init() function. mode for Source and/or Destination (if needed) using the DMA_Init() function.
* To avoid filling un-nesecessary fields, you can call DMA_StructInit() function To avoid filling unneccessary fields, you can call DMA_StructInit() function
* to initialize a given structure with default values (reset values), the modify to initialize a given structure with default values (reset values), the modify
* only necessary fields (ie. Source and Destination addresses, Transfer size and Data Formats). only necessary fields
* (ie. Source and Destination addresses, Transfer size and Data Formats).
* 4. Enable the NVIC and the corresponding interrupt(s) using the function
* DMA_ITConfig() if you need to use DMA interrupts. (#) Enable the NVIC and the corresponding interrupt(s) using the function
* DMA_ITConfig() if you need to use DMA interrupts.
* 5. Optionally, if the Circular mode is enabled, you can use the Double buffer mode by configuring
* the second Memory address and the first Memory to be used through the function (#) Optionally, if the Circular mode is enabled, you can use the Double buffer mode by configuring
* DMA_DoubleBufferModeConfig(). Then enable the Double buffer mode through the function the second Memory address and the first Memory to be used through the function
* DMA_DoubleBufferModeCmd(). These operations must be done before step 6. DMA_DoubleBufferModeConfig(). Then enable the Double buffer mode through the function
* DMA_DoubleBufferModeCmd(). These operations must be done before step 6.
* 6. Enable the DMA stream using the DMA_Cmd() function.
* (#) Enable the DMA stream using the DMA_Cmd() function.
* 7. Activate the needed Stream Request using PPP_DMACmd() function for
* any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) (#) Activate the needed Stream Request using PPP_DMACmd() function for
* The function allowing this operation is provided in each PPP peripheral any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
* driver (ie. SPI_DMACmd for SPI peripheral). The function allowing this operation is provided in each PPP peripheral
* Once the Stream is enabled, it is not possible to modify its configuration driver (ie. SPI_DMACmd for SPI peripheral).
* unless the stream is stopped and disabled. Once the Stream is enabled, it is not possible to modify its configuration
* After enabling the Stream, it is advised to monitor the EN bit status using unless the stream is stopped and disabled.
* the function DMA_GetCmdStatus(). In case of configuration errors or bus errors After enabling the Stream, it is advised to monitor the EN bit status using
* this bit will remain reset and all transfers on this Stream will remain on hold. the function DMA_GetCmdStatus(). In case of configuration errors or bus errors
* this bit will remain reset and all transfers on this Stream will remain on hold.
* 8. Optionally, you can configure the number of data to be transferred
* when the Stream is disabled (ie. after each Transfer Complete event (#) Optionally, you can configure the number of data to be transferred
* or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter(). when the Stream is disabled (ie. after each Transfer Complete event
* And you can get the number of remaining data to be transferred using or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
* the function DMA_GetCurrDataCounter() at run time (when the DMA Stream is And you can get the number of remaining data to be transferred using
* enabled and running). the function DMA_GetCurrDataCounter() at run time (when the DMA Stream is
* enabled and running).
* 9. To control DMA events you can use one of the following
* two methods: (#) To control DMA events you can use one of the following two methods:
* a- Check on DMA Stream flags using the function DMA_GetFlagStatus(). (##) Check on DMA Stream flags using the function DMA_GetFlagStatus().
* b- Use DMA interrupts through the function DMA_ITConfig() at initialization (##) Use DMA interrupts through the function DMA_ITConfig() at initialization
* phase and DMA_GetITStatus() function into interrupt routines in phase and DMA_GetITStatus() function into interrupt routines in
* communication phase. communication phase.
* After checking on a flag you should clear it using DMA_ClearFlag() [..]
* function. And after checking on an interrupt event you should After checking on a flag you should clear it using DMA_ClearFlag()
* clear it using DMA_ClearITPendingBit() function. function. And after checking on an interrupt event you should
* clear it using DMA_ClearITPendingBit() function.
* 10. Optionally, if Circular mode and Double Buffer mode are enabled, you can modify
* the Memory Addresses using the function DMA_MemoryTargetConfig(). Make sure that (#) Optionally, if Circular mode and Double Buffer mode are enabled, you can modify
* the Memory Address to be modified is not the one currently in use by DMA Stream. the Memory Addresses using the function DMA_MemoryTargetConfig(). Make sure that
* This condition can be monitored using the function DMA_GetCurrentMemoryTarget(). the Memory Address to be modified is not the one currently in use by DMA Stream.
* This condition can be monitored using the function DMA_GetCurrentMemoryTarget().
* 11. Optionally, Pause-Resume operations may be performed:
* The DMA_Cmd() function may be used to perform Pause-Resume operation. When a (#) Optionally, Pause-Resume operations may be performed:
* transfer is ongoing, calling this function to disable the Stream will cause the The DMA_Cmd() function may be used to perform Pause-Resume operation.
* transfer to be paused. All configuration registers and the number of remaining When a transfer is ongoing, calling this function to disable the
* data will be preserved. When calling again this function to re-enable the Stream, Stream will cause the transfer to be paused. All configuration registers
* the transfer will be resumed from the point where it was paused. and the number of remaining data will be preserved. When calling again
* this function to re-enable the Stream, the transfer will be resumed from
* @note Memory-to-Memory transfer is possible by setting the address of the memory into the point where it was paused.
* the Peripheral registers. In this mode, Circular mode and Double Buffer mode
* are not allowed. -@- Memory-to-Memory transfer is possible by setting the address of the memory into
* the Peripheral registers. In this mode, Circular mode and Double Buffer mode
* @note The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is are not allowed.
* possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
* Half-Word data size for the peripheral to access its data register and set Word data size -@- The FIFO is used mainly to reduce bus usage and to allow data
* for the Memory to gain in access time. Each two Half-words will be packed and written in packing/unpacking: it is possible to set different Data Sizes for
* a single access to a Word in the Memory). the Peripheral and the Memory (ie. you can set Half-Word data size
* for the peripheral to access its data register and set Word data size
* @note When FIFO is disabled, it is not allowed to configure different Data Sizes for Source for the Memory to gain in access time. Each two Half-words will be
* and Destination. In this case the Peripheral Data Size will be applied to both Source packed and written in a single access to a Word in the Memory).
* and Destination.
* -@- When FIFO is disabled, it is not allowed to configure different
* @endverbatim Data Sizes for Source and Destination. In this case the Peripheral
* Data Size will be applied to both Source and Destination.
@endverbatim
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -162,18 +170,18 @@
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Initialization and Configuration functions ##### Initialization and Configuration functions #####
=============================================================================== ===============================================================================
[..]
This subsection provides functions allowing to initialize the DMA Stream source This subsection provides functions allowing to initialize the DMA Stream source
and destination addresses, incrementation and data sizes, transfer direction, and destination addresses, incrementation and data sizes, transfer direction,
buffer size, circular/normal mode selection, memory-to-memory mode selection buffer size, circular/normal mode selection, memory-to-memory mode selection
and Stream priority value. and Stream priority value.
[..]
The DMA_Init() function follows the DMA configuration procedures as described in The DMA_Init() function follows the DMA configuration procedures as described in
reference manual (RM0090) except the first point: waiting on EN bit to be reset. reference manual (RM0090) except the first point: waiting on EN bit to be reset.
This condition should be checked by user application using the function DMA_GetCmdStatus() This condition should be checked by user application using the function DMA_GetCmdStatus()
before calling the DMA_Init() function. before calling the DMA_Init() function.
@endverbatim @endverbatim
* @{ * @{
@@ -566,37 +574,35 @@ void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Flo
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Data Counter functions ##### Data Counter functions #####
=============================================================================== ===============================================================================
[..]
This subsection provides function allowing to configure and read the buffer size This subsection provides function allowing to configure and read the buffer size
(number of data to be transferred). (number of data to be transferred).
[..]
The DMA data counter can be written only when the DMA Stream is disabled The DMA data counter can be written only when the DMA Stream is disabled
(ie. after transfer complete event). (ie. after transfer complete event).
[..]
The following function can be used to write the Stream data counter value: The following function can be used to write the Stream data counter value:
- void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter); (+) void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
-@- It is advised to use this function rather than DMA_Init() in situations
@note It is advised to use this function rather than DMA_Init() in situations where where only the Data buffer needs to be reloaded.
only the Data buffer needs to be reloaded. -@- If the Source and Destination Data Sizes are different, then the value
written in data counter, expressing the number of transfers, is relative
@note If the Source and Destination Data Sizes are different, then the value written in to the number of transfers from the Peripheral point of view.
data counter, expressing the number of transfers, is relative to the number of ie. If Memory data size is Word, Peripheral data size is Half-Words,
transfers from the Peripheral point of view. then the value to be configured in the data counter is the number
ie. If Memory data size is Word, Peripheral data size is Half-Words, then the value of Half-Words to be transferred from/to the peripheral.
to be configured in the data counter is the number of Half-Words to be transferred [..]
from/to the peripheral. The DMA data counter can be read to indicate the number of remaining transfers for
the relative DMA Stream. This counter is decremented at the end of each data
The DMA data counter can be read to indicate the number of remaining transfers for transfer and when the transfer is complete:
the relative DMA Stream. This counter is decremented at the end of each data (+) If Normal mode is selected: the counter is set to 0.
transfer and when the transfer is complete: (+) If Circular mode is selected: the counter is reloaded with the initial value
- If Normal mode is selected: the counter is set to 0. (configured before enabling the DMA Stream)
- If Circular mode is selected: the counter is reloaded with the initial value [..]
(configured before enabling the DMA Stream) The following function can be used to read the Stream data counter value:
(+) uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);
The following function can be used to read the Stream data counter value:
- uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);
@endverbatim @endverbatim
* @{ * @{
@@ -655,45 +661,51 @@ uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Double Buffer mode functions ##### Double Buffer mode functions #####
=============================================================================== ===============================================================================
[..]
This subsection provides function allowing to configure and control the double This subsection provides function allowing to configure and control the double
buffer mode parameters. buffer mode parameters.
[..]
The Double Buffer mode can be used only when Circular mode is enabled.
The Double Buffer mode cannot be used when transferring data from Memory to Memory.
[..]
The Double Buffer mode allows to set two different Memory addresses from/to which
the DMA controller will access alternatively (after completing transfer to/from
target memory 0, it will start transfer to/from target memory 1).
This allows to reduce software overhead for double buffering and reduce the CPU
access time.
[..]
Two functions must be called before calling the DMA_Init() function:
(+) void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx,
uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory);
(+) void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
[..]
DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address
and the first Memory target from/to which the transfer will start after
enabling the DMA Stream. Then DMA_DoubleBufferModeCmd() must be called
to enable the Double Buffer mode (or disable it when it should not be used).
The Double Buffer mode can be used only when Circular mode is enabled. [..]
The Double Buffer mode cannot be used when transferring data from Memory to Memory. Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is
stopped) to modify on of the target Memories addresses or to check wich Memory target is currently
The Double Buffer mode allows to set two different Memory addresses from/to which used:
the DMA controller will access alternatively (after completing transfer to/from target (+) void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx,
memory 0, it will start transfer to/from target memory 1). uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget);
This allows to reduce software overhead for double buffering and reduce the CPU (+) uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
access time.
[..]
Two functions must be called before calling the DMA_Init() function: DMA_MemoryTargetConfig() can be called to modify the base address of one of
- void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, the two target Memories.
uint32_t DMA_CurrentMemory); The Memory of which the base address will be modified must not be currently
- void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); be used by the DMA Stream (ie. if the DMA Stream is currently transferring
from Memory 1 then you can only modify base address of target Memory 0 and vice versa).
DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address and the first To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which
Memory target from/to which the transfer will start after enabling the DMA Stream. returns the index of the Memory target currently in use by the DMA Stream.
Then DMA_DoubleBufferModeCmd() must be called to enable the Double Buffer mode (or disable
it when it should not be used).
Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is
stopped) to modify on of the target Memories addresses or to check wich Memory target is currently
used:
- void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
uint32_t DMA_MemoryTarget);
- uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
DMA_MemoryTargetConfig() can be called to modify the base address of one of the two target Memories.
The Memory of which the base address will be modified must not be currently be used by the DMA Stream
(ie. if the DMA Stream is currently transferring from Memory 1 then you can only modify base address
of target Memory 0 and vice versa).
To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which
returns the index of the Memory target currently in use by the DMA Stream.
@endverbatim @endverbatim
* @{ * @{
@@ -842,64 +854,70 @@ uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Interrupts and flags management functions ##### Interrupts and flags management functions #####
=============================================================================== ===============================================================================
[..]
This subsection provides functions allowing to This subsection provides functions allowing to
- Check the DMA enable status (+) Check the DMA enable status
- Check the FIFO status (+) Check the FIFO status
- Configure the DMA Interrupts sources and check or clear the flags or pending bits status. (+) Configure the DMA Interrupts sources and check or clear the flags or
pending bits status.
1. DMA Enable status:
After configuring the DMA Stream (DMA_Init() function) and enabling the stream, [..]
it is recommended to check (or wait until) the DMA Stream is effectively enabled. (#) DMA Enable status:
A Stream may remain disabled if a configuration parameter is wrong. After configuring the DMA Stream (DMA_Init() function) and enabling
After disabling a DMA Stream, it is also recommended to check (or wait until) the DMA the stream, it is recommended to check (or wait until) the DMA Stream
Stream is effectively disabled. If a Stream is disabled while a data transfer is ongoing, is effectively enabled. A Stream may remain disabled if a configuration
the current data will be transferred and the Stream will be effectively disabled only after parameter is wrong. After disabling a DMA Stream, it is also recommended
this data transfer completion. to check (or wait until) the DMA Stream is effectively disabled.
To monitor this state it is possible to use the following function: If a Stream is disabled while a data transfer is ongoing, the current
- FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); data will be transferred and the Stream will be effectively disabled
only after this data transfer completion.
To monitor this state it is possible to use the following function:
(++) FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx);
2. FIFO Status: (#) FIFO Status:
It is possible to monitor the FIFO status when a transfer is ongoing using the following It is possible to monitor the FIFO status when a transfer is ongoing
function: using the following function:
- uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); (++) uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx);
3. DMA Interrupts and Flags: (#) DMA Interrupts and Flags:
The user should identify which mode will be used in his application to manage the The user should identify which mode will be used in his application
DMA controller events: Polling mode or Interrupt mode. to manage the DMA controller events: Polling mode or Interrupt mode.
Polling Mode *** Polling Mode ***
============= ====================
[..]
Each DMA stream can be managed through 4 event Flags: Each DMA stream can be managed through 4 event Flags:
(x : DMA Stream number ) (x : DMA Stream number )
1. DMA_FLAG_FEIFx : to indicate that a FIFO Mode Transfer Error event occurred. (#) DMA_FLAG_FEIFx : to indicate that a FIFO Mode Transfer Error event occurred.
2. DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred. (#) DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred.
3. DMA_FLAG_TEIFx : to indicate that a Transfer Error event occurred. (#) DMA_FLAG_TEIFx : to indicate that a Transfer Error event occurred.
4. DMA_FLAG_HTIFx : to indicate that a Half-Transfer Complete event occurred. (#) DMA_FLAG_HTIFx : to indicate that a Half-Transfer Complete event occurred.
5. DMA_FLAG_TCIFx : to indicate that a Transfer Complete event occurred . (#) DMA_FLAG_TCIFx : to indicate that a Transfer Complete event occurred .
[..]
In this Mode it is advised to use the following functions:
(+) FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
(+) void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
In this Mode it is advised to use the following functions: *** Interrupt Mode ***
- FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); ======================
- void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); [..]
Interrupt Mode
===============
Each DMA Stream can be managed through 4 Interrupts: Each DMA Stream can be managed through 4 Interrupts:
Interrupt Source *** Interrupt Source ***
---------------- ========================
1. DMA_IT_FEIFx : specifies the interrupt source for the FIFO Mode Transfer Error event. [..]
2. DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event. (#) DMA_IT_FEIFx : specifies the interrupt source for the FIFO Mode Transfer Error event.
3. DMA_IT_TEIFx : specifies the interrupt source for the Transfer Error event. (#) DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event.
4. DMA_IT_HTIFx : specifies the interrupt source for the Half-Transfer Complete event. (#) DMA_IT_TEIFx : specifies the interrupt source for the Transfer Error event.
5. DMA_IT_TCIFx : specifies the interrupt source for the a Transfer Complete event. (#) DMA_IT_HTIFx : specifies the interrupt source for the Half-Transfer Complete event.
(#) DMA_IT_TCIFx : specifies the interrupt source for the a Transfer Complete event.
In this Mode it is advised to use the following functions: [..]
- void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); In this Mode it is advised to use the following functions:
- ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); (+) void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
- void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); (+) ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
(+) void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
@endverbatim @endverbatim
* @{ * @{
@@ -1280,4 +1298,4 @@ void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT)
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

784
example/libs/StmCoreNPheriph/src/stm32f4xx_dma2d.c Normal file
View File

@@ -0,0 +1,784 @@
/**
******************************************************************************
* @file stm32f4xx_dma2d.c
* @author MCD Application Team
* @version V1.4.0
* @date 04-August-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the DMA2D controller (DMA2D) peripheral:
* + Initialization and configuration
* + Interrupts and flags management
*
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
(#) Enable DMA2D clock using
RCC_APB2PeriphResetCmd(RCC_APB2Periph_DMA2D, ENABLE) function.
(#) Configures DMA2D
(++) transfer mode
(++) pixel format, line_number, pixel_per_line
(++) output memory address
(++) alpha value
(++) output offset
(++) Default color (RGB)
(#) Configures Foreground or/and background
(++) memory address
(++) alpha value
(++) offset and default color
(#) Call the DMA2D_Start() to enable the DMA2D controller.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_dma2d.h"
#include "stm32f4xx_rcc.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @defgroup DMA2D
* @brief DMA2D driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
#define CR_MASK ((uint32_t)0xFFFCE0FC) /* DMA2D CR Mask */
#define PFCCR_MASK ((uint32_t)0x00FC00C0) /* DMA2D FGPFCCR Mask */
#define DEAD_MASK ((uint32_t)0xFFFF00FE) /* DMA2D DEAD Mask */
/** @defgroup DMA2D_Private_Functions
* @{
*/
/** @defgroup DMA2D_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the DMA2D
(+) Start/Abort/Suspend Transfer
(+) Initialize, configure and set Foreground and background
(+) configure and enable DeadTime
(+) configure lineWatermark
@endverbatim
* @{
*/
/**
* @brief Deinitializes the DMA2D peripheral registers to their default reset
* values.
* @param None
* @retval None
*/
void DMA2D_DeInit(void)
{
/* Enable DMA2D reset state */
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2D, ENABLE);
/* Release DMA2D from reset state */
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2D, DISABLE);
}
/**
* @brief Initializes the DMA2D peripheral according to the specified parameters
* in the DMA2D_InitStruct.
* @note This function can be used only when the DMA2D is disabled.
* @param DMA2D_InitStruct: pointer to a DMA2D_InitTypeDef structure that contains
* the configuration information for the specified DMA2D peripheral.
* @retval None
*/
void DMA2D_Init(DMA2D_InitTypeDef* DMA2D_InitStruct)
{
uint32_t outgreen = 0;
uint32_t outred = 0;
uint32_t outalpha = 0;
uint32_t pixline = 0;
/* Check the parameters */
assert_param(IS_DMA2D_MODE(DMA2D_InitStruct->DMA2D_Mode));
assert_param(IS_DMA2D_CMODE(DMA2D_InitStruct->DMA2D_CMode));
assert_param(IS_DMA2D_OGREEN(DMA2D_InitStruct->DMA2D_OutputGreen));
assert_param(IS_DMA2D_ORED(DMA2D_InitStruct->DMA2D_OutputRed));
assert_param(IS_DMA2D_OBLUE(DMA2D_InitStruct->DMA2D_OutputBlue));
assert_param(IS_DMA2D_OALPHA(DMA2D_InitStruct->DMA2D_OutputAlpha));
assert_param(IS_DMA2D_OUTPUT_OFFSET(DMA2D_InitStruct->DMA2D_OutputOffset));
assert_param(IS_DMA2D_LINE(DMA2D_InitStruct->DMA2D_NumberOfLine));
assert_param(IS_DMA2D_PIXEL(DMA2D_InitStruct->DMA2D_PixelPerLine));
/* Configures the DMA2D operation mode */
DMA2D->CR &= (uint32_t)CR_MASK;
DMA2D->CR |= (DMA2D_InitStruct->DMA2D_Mode);
/* Configures the color mode of the output image */
DMA2D->OPFCCR &= ~(uint32_t)DMA2D_OPFCCR_CM;
DMA2D->OPFCCR |= (DMA2D_InitStruct->DMA2D_CMode);
/* Configures the output color */
if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_ARGB8888)
{
outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 8;
outred = DMA2D_InitStruct->DMA2D_OutputRed << 16;
outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 24;
}
else
if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_RGB888)
{
outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 8;
outred = DMA2D_InitStruct->DMA2D_OutputRed << 16;
outalpha = (uint32_t)0x00000000;
}
else
if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_RGB565)
{
outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 5;
outred = DMA2D_InitStruct->DMA2D_OutputRed << 11;
outalpha = (uint32_t)0x00000000;
}
else
if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_ARGB1555)
{
outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 5;
outred = DMA2D_InitStruct->DMA2D_OutputRed << 10;
outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 15;
}
else /* DMA2D_CMode = DMA2D_ARGB4444 */
{
outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 4;
outred = DMA2D_InitStruct->DMA2D_OutputRed << 8;
outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 12;
}
DMA2D->OCOLR |= ((outgreen) | (outred) | (DMA2D_InitStruct->DMA2D_OutputBlue) | (outalpha));
/* Configures the output memory address */
DMA2D->OMAR = (DMA2D_InitStruct->DMA2D_OutputMemoryAdd);
/* Configure the line Offset */
DMA2D->OOR &= ~(uint32_t)DMA2D_OOR_LO;
DMA2D->OOR |= (DMA2D_InitStruct->DMA2D_OutputOffset);
/* Configure the number of line and pixel per line */
pixline = DMA2D_InitStruct->DMA2D_PixelPerLine << 16;
DMA2D->NLR &= ~(DMA2D_NLR_NL | DMA2D_NLR_PL);
DMA2D->NLR |= ((DMA2D_InitStruct->DMA2D_NumberOfLine) | (pixline));
/**
* @brief Fills each DMA2D_InitStruct member with its default value.
* @param DMA2D_InitStruct: pointer to a DMA2D_InitTypeDef structure which will
* be initialized.
* @retval None
*/
}
void DMA2D_StructInit(DMA2D_InitTypeDef* DMA2D_InitStruct)
{
/* Initialize the transfer mode member */
DMA2D_InitStruct->DMA2D_Mode = DMA2D_M2M;
/* Initialize the output color mode members */
DMA2D_InitStruct->DMA2D_CMode = DMA2D_ARGB8888;
/* Initialize the alpha and RGB values */
DMA2D_InitStruct->DMA2D_OutputGreen = 0x00;
DMA2D_InitStruct->DMA2D_OutputBlue = 0x00;
DMA2D_InitStruct->DMA2D_OutputRed = 0x00;
DMA2D_InitStruct->DMA2D_OutputAlpha = 0x00;
/* Initialize the output memory address */
DMA2D_InitStruct->DMA2D_OutputMemoryAdd = 0x00;
/* Initialize the output offset */
DMA2D_InitStruct->DMA2D_OutputOffset = 0x00;
/* Initialize the number of line and the number of pixel per line */
DMA2D_InitStruct->DMA2D_NumberOfLine = 0x00;
DMA2D_InitStruct->DMA2D_PixelPerLine = 0x00;
}
/**
* @brief Start the DMA2D transfer.
* @param
* @retval None
*/
void DMA2D_StartTransfer(void)
{
/* Start DMA2D transfer by setting START bit */
DMA2D->CR |= (uint32_t)DMA2D_CR_START;
}
/**
* @brief Aboart the DMA2D transfer.
* @param
* @retval None
*/
void DMA2D_AbortTransfer(void)
{
/* Start DMA2D transfer by setting START bit */
DMA2D->CR |= (uint32_t)DMA2D_CR_ABORT;
}
/**
* @brief Stop or continue the DMA2D transfer.
* @param NewState: new state of the DMA2D peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DMA2D_Suspend(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Suspend DMA2D transfer by setting STOP bit */
DMA2D->CR |= (uint32_t)DMA2D_CR_SUSP;
}
else
{
/* Continue DMA2D transfer by clearing STOP bit */
DMA2D->CR &= ~(uint32_t)DMA2D_CR_SUSP;
}
}
/**
* @brief Configures the Foreground according to the specified parameters
* in the DMA2D_FGStruct.
* @note This function can be used only when the transfer is disabled.
* @param DMA2D_FGStruct: pointer to a DMA2D_FGTypeDef structure that contains
* the configuration information for the specified Background.
* @retval None
*/
void DMA2D_FGConfig(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct)
{
uint32_t fg_clutcolormode = 0;
uint32_t fg_clutsize = 0;
uint32_t fg_alpha_mode = 0;
uint32_t fg_alphavalue = 0;
uint32_t fg_colorgreen = 0;
uint32_t fg_colorred = 0;
assert_param(IS_DMA2D_FGO(DMA2D_FG_InitStruct->DMA2D_FGO));
assert_param(IS_DMA2D_FGCM(DMA2D_FG_InitStruct->DMA2D_FGCM));
assert_param(IS_DMA2D_FG_CLUT_CM(DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM));
assert_param(IS_DMA2D_FG_CLUT_SIZE(DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE));
assert_param(IS_DMA2D_FG_ALPHA_MODE(DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE));
assert_param(IS_DMA2D_FG_ALPHA_VALUE(DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE));
assert_param(IS_DMA2D_FGC_BLUE(DMA2D_FG_InitStruct->DMA2D_FGC_BLUE));
assert_param(IS_DMA2D_FGC_GREEN(DMA2D_FG_InitStruct->DMA2D_FGC_GREEN));
assert_param(IS_DMA2D_FGC_RED(DMA2D_FG_InitStruct->DMA2D_FGC_RED));
/* Configures the FG memory address */
DMA2D->FGMAR = (DMA2D_FG_InitStruct->DMA2D_FGMA);
/* Configures the FG offset */
DMA2D->FGOR &= ~(uint32_t)DMA2D_FGOR_LO;
DMA2D->FGOR |= (DMA2D_FG_InitStruct->DMA2D_FGO);
/* Configures foreground Pixel Format Convertor */
DMA2D->FGPFCCR &= (uint32_t)PFCCR_MASK;
fg_clutcolormode = DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM << 4;
fg_clutsize = DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE << 8;
fg_alpha_mode = DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE << 16;
fg_alphavalue = DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE << 24;
DMA2D->FGPFCCR |= (DMA2D_FG_InitStruct->DMA2D_FGCM | fg_clutcolormode | fg_clutsize | \
fg_alpha_mode | fg_alphavalue);
/* Configures foreground color */
DMA2D->FGCOLR &= ~(DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_RED);
fg_colorgreen = DMA2D_FG_InitStruct->DMA2D_FGC_GREEN << 8;
fg_colorred = DMA2D_FG_InitStruct->DMA2D_FGC_RED << 16;
DMA2D->FGCOLR |= (DMA2D_FG_InitStruct->DMA2D_FGC_BLUE | fg_colorgreen | fg_colorred);
/* Configures foreground CLUT memory address */
DMA2D->FGCMAR = DMA2D_FG_InitStruct->DMA2D_FGCMAR;
}
/**
* @brief Fills each DMA2D_FGStruct member with its default value.
* @param DMA2D_FGStruct: pointer to a DMA2D_FGTypeDef structure which will
* be initialized.
* @retval None
*/
void DMA2D_FG_StructInit(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct)
{
/*!< Initialize the DMA2D foreground memory address */
DMA2D_FG_InitStruct->DMA2D_FGMA = 0x00;
/*!< Initialize the DMA2D foreground offset */
DMA2D_FG_InitStruct->DMA2D_FGO = 0x00;
/*!< Initialize the DMA2D foreground color mode */
DMA2D_FG_InitStruct->DMA2D_FGCM = CM_ARGB8888;
/*!< Initialize the DMA2D foreground CLUT color mode */
DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM = CLUT_CM_ARGB8888;
/*!< Initialize the DMA2D foreground CLUT size */
DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE = 0x00;
/*!< Initialize the DMA2D foreground alpha mode */
DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE;
/*!< Initialize the DMA2D foreground alpha value */
DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE = 0x00;
/*!< Initialize the DMA2D foreground blue value */
DMA2D_FG_InitStruct->DMA2D_FGC_BLUE = 0x00;
/*!< Initialize the DMA2D foreground green value */
DMA2D_FG_InitStruct->DMA2D_FGC_GREEN = 0x00;
/*!< Initialize the DMA2D foreground red value */
DMA2D_FG_InitStruct->DMA2D_FGC_RED = 0x00;
/*!< Initialize the DMA2D foreground CLUT memory address */
DMA2D_FG_InitStruct->DMA2D_FGCMAR = 0x00;
}
/**
* @brief Configures the Background according to the specified parameters
* in the DMA2D_BGStruct.
* @note This function can be used only when the transfer is disabled.
* @param DMA2D_BGStruct: pointer to a DMA2D_BGTypeDef structure that contains
* the configuration information for the specified Background.
* @retval None
*/
void DMA2D_BGConfig(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct)
{
uint32_t bg_clutcolormode = 0;
uint32_t bg_clutsize = 0;
uint32_t bg_alpha_mode = 0;
uint32_t bg_alphavalue = 0;
uint32_t bg_colorgreen = 0;
uint32_t bg_colorred = 0;
assert_param(IS_DMA2D_BGO(DMA2D_BG_InitStruct->DMA2D_BGO));
assert_param(IS_DMA2D_BGCM(DMA2D_BG_InitStruct->DMA2D_BGCM));
assert_param(IS_DMA2D_BG_CLUT_CM(DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM));
assert_param(IS_DMA2D_BG_CLUT_SIZE(DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE));
assert_param(IS_DMA2D_BG_ALPHA_MODE(DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE));
assert_param(IS_DMA2D_BG_ALPHA_VALUE(DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE));
assert_param(IS_DMA2D_BGC_BLUE(DMA2D_BG_InitStruct->DMA2D_BGC_BLUE));
assert_param(IS_DMA2D_BGC_GREEN(DMA2D_BG_InitStruct->DMA2D_BGC_GREEN));
assert_param(IS_DMA2D_BGC_RED(DMA2D_BG_InitStruct->DMA2D_BGC_RED));
/* Configures the BG memory address */
DMA2D->BGMAR = (DMA2D_BG_InitStruct->DMA2D_BGMA);
/* Configures the BG offset */
DMA2D->BGOR &= ~(uint32_t)DMA2D_BGOR_LO;
DMA2D->BGOR |= (DMA2D_BG_InitStruct->DMA2D_BGO);
/* Configures background Pixel Format Convertor */
DMA2D->BGPFCCR &= (uint32_t)PFCCR_MASK;
bg_clutcolormode = DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM << 4;
bg_clutsize = DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE << 8;
bg_alpha_mode = DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE << 16;
bg_alphavalue = DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE << 24;
DMA2D->BGPFCCR |= (DMA2D_BG_InitStruct->DMA2D_BGCM | bg_clutcolormode | bg_clutsize | \
bg_alpha_mode | bg_alphavalue);
/* Configures background color */
DMA2D->BGCOLR &= ~(DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_RED);
bg_colorgreen = DMA2D_BG_InitStruct->DMA2D_BGC_GREEN << 8;
bg_colorred = DMA2D_BG_InitStruct->DMA2D_BGC_RED << 16;
DMA2D->BGCOLR |= (DMA2D_BG_InitStruct->DMA2D_BGC_BLUE | bg_colorgreen | bg_colorred);
/* Configures background CLUT memory address */
DMA2D->BGCMAR = DMA2D_BG_InitStruct->DMA2D_BGCMAR;
}
/**
* @brief Fills each DMA2D_BGStruct member with its default value.
* @param DMA2D_BGStruct: pointer to a DMA2D_BGTypeDef structure which will
* be initialized.
* @retval None
*/
void DMA2D_BG_StructInit(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct)
{
/*!< Initialize the DMA2D background memory address */
DMA2D_BG_InitStruct->DMA2D_BGMA = 0x00;
/*!< Initialize the DMA2D background offset */
DMA2D_BG_InitStruct->DMA2D_BGO = 0x00;
/*!< Initialize the DMA2D background color mode */
DMA2D_BG_InitStruct->DMA2D_BGCM = CM_ARGB8888;
/*!< Initialize the DMA2D background CLUT color mode */
DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM = CLUT_CM_ARGB8888;
/*!< Initialize the DMA2D background CLUT size */
DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE = 0x00;
/*!< Initialize the DMA2D background alpha mode */
DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE;
/*!< Initialize the DMA2D background alpha value */
DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE = 0x00;
/*!< Initialize the DMA2D background blue value */
DMA2D_BG_InitStruct->DMA2D_BGC_BLUE = 0x00;
/*!< Initialize the DMA2D background green value */
DMA2D_BG_InitStruct->DMA2D_BGC_GREEN = 0x00;
/*!< Initialize the DMA2D background red value */
DMA2D_BG_InitStruct->DMA2D_BGC_RED = 0x00;
/*!< Initialize the DMA2D background CLUT memory address */
DMA2D_BG_InitStruct->DMA2D_BGCMAR = 0x00;
}
/**
* @brief Start the automatic loading of the CLUT or abort the transfer.
* @param NewState: new state of the DMA2D peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DMA2D_FGStart(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Start the automatic loading of the CLUT */
DMA2D->FGPFCCR |= DMA2D_FGPFCCR_START;
}
else
{
/* abort the transfer */
DMA2D->FGPFCCR &= (uint32_t)~DMA2D_FGPFCCR_START;
}
}
/**
* @brief Start the automatic loading of the CLUT or abort the transfer.
* @param NewState: new state of the DMA2D peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DMA2D_BGStart(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Start the automatic loading of the CLUT */
DMA2D->BGPFCCR |= DMA2D_BGPFCCR_START;
}
else
{
/* abort the transfer */
DMA2D->BGPFCCR &= (uint32_t)~DMA2D_BGPFCCR_START;
}
}
/**
* @brief Configures the DMA2D dead time.
* @param DMA2D_DeadTime: specifies the DMA2D dead time.
* This parameter can be one of the following values:
* @retval None
*/
void DMA2D_DeadTimeConfig(uint32_t DMA2D_DeadTime, FunctionalState NewState)
{
uint32_t DeadTime;
/* Check the parameters */
assert_param(IS_DMA2D_DEAD_TIME(DMA2D_DeadTime));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable and Configures the dead time */
DMA2D->AMTCR &= (uint32_t)DEAD_MASK;
DeadTime = DMA2D_DeadTime << 8;
DMA2D->AMTCR |= (DeadTime | DMA2D_AMTCR_EN);
}
else
{
DMA2D->AMTCR &= ~(uint32_t)DMA2D_AMTCR_EN;
}
}
/**
* @brief Define the configuration of the line watermark .
* @param DMA2D_LWatermarkConfig: Line Watermark configuration.
* @retval None
*/
void DMA2D_LineWatermarkConfig(uint32_t DMA2D_LWatermarkConfig)
{
/* Check the parameters */
assert_param(IS_DMA2D_LineWatermark(DMA2D_LWatermarkConfig));
/* Sets the Line watermark configuration */
DMA2D->LWR = (uint32_t)DMA2D_LWatermarkConfig;
}
/**
* @}
*/
/** @defgroup DMA2D_Group2 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
===============================================================================
##### Interrupts and flags management functions #####
===============================================================================
[..] This section provides functions allowing to configure the DMA2D
Interrupts and to get the status and clear flags and Interrupts
pending bits.
[..] The DMA2D provides 6 Interrupts sources and 6 Flags
*** Flags ***
=============
[..]
(+) DMA2D_FLAG_CE : Configuration Error Interrupt flag
(+) DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag
(+) DMA2D_FLAG_TW: Transfer Watermark Interrupt flag
(+) DMA2D_FLAG_TC: Transfer Complete interrupt flag
(+) DMA2D_FLAG_TE: Transfer Error interrupt flag
(+) DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag
*** Interrupts ***
==================
[..]
(+) DMA2D_IT_CE: Configuration Error Interrupt is generated when a wrong
configuration is detected
(+) DMA2D_IT_CAE: CLUT Access Error Interrupt
(+) DMA2D_IT_TW: Transfer Watermark Interrupt is generated when
the programmed watermark is reached
(+) DMA2D_IT_TE: Transfer Error interrupt is generated when the CPU trying
to access the CLUT while a CLUT loading or a DMA2D1 transfer
is on going
(+) DMA2D_IT_CTC: CLUT Transfer Complete Interrupt
(+) DMA2D_IT_TC: Transfer Complete interrupt
@endverbatim
* @{
*/
/**
* @brief Enables or disables the specified DMA2D's interrupts.
* @param DMA2D_IT: specifies the DMA2D interrupts sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg DMA2D_IT_CE: Configuration Error Interrupt Enable.
* @arg DMA2D_IT_CTC: CLUT Transfer Complete Interrupt Enable.
* @arg DMA2D_IT_CAE: CLUT Access Error Interrupt Enable.
* @arg DMA2D_IT_TW: Transfer Watermark Interrupt Enable.
* @arg DMA2D_IT_TC: Transfer Complete interrupt enable.
* @arg DMA2D_IT_TE: Transfer Error interrupt enable.
* @param NewState: new state of the specified DMA2D interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DMA2D_ITConfig(uint32_t DMA2D_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DMA2D_IT(DMA2D_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DMA2D interrupts */
DMA2D->CR |= DMA2D_IT;
}
else
{
/* Disable the selected DMA2D interrupts */
DMA2D->CR &= (uint32_t)~DMA2D_IT;
}
}
/**
* @brief Checks whether the specified DMA2D's flag is set or not.
* @param DMA2D_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg DMA2D_FLAG_CE: Configuration Error Interrupt flag.
* @arg DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag.
* @arg DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag.
* @arg DMA2D_FLAG_TW: Transfer Watermark Interrupt flag.
* @arg DMA2D_FLAG_TC: Transfer Complete interrupt flag.
* @arg DMA2D_FLAG_TE: Transfer Error interrupt flag.
* @retval The new state of DMA2D_FLAG (SET or RESET).
*/
FlagStatus DMA2D_GetFlagStatus(uint32_t DMA2D_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_DMA2D_GET_FLAG(DMA2D_FLAG));
/* Check the status of the specified DMA2D flag */
if (((DMA2D->ISR) & DMA2D_FLAG) != (uint32_t)RESET)
{
/* DMA2D_FLAG is set */
bitstatus = SET;
}
else
{
/* DMA2D_FLAG is reset */
bitstatus = RESET;
}
/* Return the DMA2D_FLAG status */
return bitstatus;
}
/**
* @brief Clears the DMA2D's pending flags.
* @param DMA2D_FLAG: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA2D_FLAG_CE: Configuration Error Interrupt flag.
* @arg DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag.
* @arg DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag.
* @arg DMA2D_FLAG_TW: Transfer Watermark Interrupt flag.
* @arg DMA2D_FLAG_TC: Transfer Complete interrupt flag.
* @arg DMA2D_FLAG_TE: Transfer Error interrupt flag.
* @retval None
*/
void DMA2D_ClearFlag(uint32_t DMA2D_FLAG)
{
/* Check the parameters */
assert_param(IS_DMA2D_GET_FLAG(DMA2D_FLAG));
/* Clear the corresponding DMA2D flag */
DMA2D->IFCR = (uint32_t)DMA2D_FLAG;
}
/**
* @brief Checks whether the specified DMA2D's interrupt has occurred or not.
* @param DMA2D_IT: specifies the DMA2D interrupts sources to check.
* This parameter can be one of the following values:
* @arg DMA2D_IT_CE: Configuration Error Interrupt Enable.
* @arg DMA2D_IT_CTC: CLUT Transfer Complete Interrupt Enable.
* @arg DMA2D_IT_CAE: CLUT Access Error Interrupt Enable.
* @arg DMA2D_IT_TW: Transfer Watermark Interrupt Enable.
* @arg DMA2D_IT_TC: Transfer Complete interrupt enable.
* @arg DMA2D_IT_TE: Transfer Error interrupt enable.
* @retval The new state of the DMA2D_IT (SET or RESET).
*/
ITStatus DMA2D_GetITStatus(uint32_t DMA2D_IT)
{
ITStatus bitstatus = RESET;
uint32_t DMA2D_IT_FLAG = DMA2D_IT >> 8;
/* Check the parameters */
assert_param(IS_DMA2D_IT(DMA2D_IT));
if ((DMA2D->ISR & DMA2D_IT_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
if (((DMA2D->CR & DMA2D_IT) != (uint32_t)RESET) && (bitstatus != (uint32_t)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears the DMA2D's interrupt pending bits.
* @param DMA2D_IT: specifies the interrupt pending bit to clear.
* This parameter can be any combination of the following values:
* @arg DMA2D_IT_CE: Configuration Error Interrupt.
* @arg DMA2D_IT_CTC: CLUT Transfer Complete Interrupt.
* @arg DMA2D_IT_CAE: CLUT Access Error Interrupt.
* @arg DMA2D_IT_TW: Transfer Watermark Interrupt.
* @arg DMA2D_IT_TC: Transfer Complete interrupt.
* @arg DMA2D_IT_TE: Transfer Error interrupt.
* @retval None
*/
void DMA2D_ClearITPendingBit(uint32_t DMA2D_IT)
{
/* Check the parameters */
assert_param(IS_DMA2D_IT(DMA2D_IT));
DMA2D_IT = DMA2D_IT >> 8;
/* Clear the corresponding DMA2D Interrupt */
DMA2D->IFCR = (uint32_t)DMA2D_IT;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

111
example/libs/StmCoreNPheriph/src/stm32f4xx_exti.c
View File

@@ -2,58 +2,64 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_exti.c * @file stm32f4xx_exti.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides firmware functions to manage the following * @brief This file provides firmware functions to manage the following
* functionalities of the EXTI peripheral: * functionalities of the EXTI peripheral:
* - Initialization and Configuration * + Initialization and Configuration
* - Interrupts and flags management * + Interrupts and flags management
* *
* @verbatim @verbatim
*
* =================================================================== ===============================================================================
* EXTI features ##### EXTI features #####
* =================================================================== ===============================================================================
*
* External interrupt/event lines are mapped as following: [..] External interrupt/event lines are mapped as following:
* 1- All available GPIO pins are connected to the 16 external (#) All available GPIO pins are connected to the 16 external
* interrupt/event lines from EXTI0 to EXTI15. interrupt/event lines from EXTI0 to EXTI15.
* 2- EXTI line 16 is connected to the PVD Output (#) EXTI line 16 is connected to the PVD Output
* 3- EXTI line 17 is connected to the RTC Alarm event (#) EXTI line 17 is connected to the RTC Alarm event
* 4- EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event (#) EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event
* 5- EXTI line 19 is connected to the Ethernet Wakeup event (#) EXTI line 19 is connected to the Ethernet Wakeup event
* 6- EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event (#) EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event
* 7- EXTI line 21 is connected to the RTC Tamper and Time Stamp events (#) EXTI line 21 is connected to the RTC Tamper and Time Stamp events
* 8- EXTI line 22 is connected to the RTC Wakeup event (#) EXTI line 22 is connected to the RTC Wakeup event
*
* =================================================================== ##### How to use this driver #####
* How to use this driver ===============================================================================
* ===================================================================
* [..] In order to use an I/O pin as an external interrupt source, follow steps
* In order to use an I/O pin as an external interrupt source, follow below:
* steps below: (#) Configure the I/O in input mode using GPIO_Init()
* 1- Configure the I/O in input mode using GPIO_Init() (#) Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig()
* 2- Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig() (#) Select the mode(interrupt, event) and configure the trigger
* 3- Select the mode(interrupt, event) and configure the trigger selection (Rising, falling or both) using EXTI_Init()
* selection (Rising, falling or both) using EXTI_Init() (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()
* 4- Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()
* [..]
* @note SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
* registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
*
* @endverbatim @endverbatim
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -88,8 +94,8 @@
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Initialization and Configuration functions ##### Initialization and Configuration functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
* @{ * @{
@@ -204,8 +210,8 @@ void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Interrupts and flags management functions ##### Interrupts and flags management functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
* @{ * @{
@@ -256,13 +262,11 @@ void EXTI_ClearFlag(uint32_t EXTI_Line)
*/ */
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
{ {
ITStatus bitstatus = RESET; FlagStatus bitstatus = RESET;
uint32_t enablestatus = 0;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_GET_EXTI_LINE(EXTI_Line)); assert_param(IS_GET_EXTI_LINE(EXTI_Line));
enablestatus = EXTI->IMR & EXTI_Line; if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
{ {
bitstatus = SET; bitstatus = SET;
} }
@@ -271,6 +275,7 @@ ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
bitstatus = RESET; bitstatus = RESET;
} }
return bitstatus; return bitstatus;
} }
/** /**
@@ -303,4 +308,4 @@ void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

896
example/libs/StmCoreNPheriph/src/stm32f4xx_flash.c
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File diff suppressed because it is too large Load Diff

158
example/libs/StmCoreNPheriph/src/stm32f4xx_flash_ramfunc.c Normal file
View File

@@ -0,0 +1,158 @@
/**
******************************************************************************
* @file stm32f4xx_flash_ramfunc.c
* @author MCD Application Team
* @version V1.4.0
* @date 04-August-2014
* @brief FLASH RAMFUNC module driver.
* This file provides a FLASH firmware functions which should be
* executed from internal SRAM
* + Stop/Start the flash interface while System Run
* + Enable/Disable the flash sleep while System Run
*
@verbatim
==============================================================================
##### APIs executed from Internal RAM #####
==============================================================================
[..]
*** ARM Compiler ***
--------------------
[..] RAM functions are defined using the toolchain options.
Functions that are be executed in RAM should reside in a separate
source module. Using the 'Options for File' dialog you can simply change
the 'Code / Const' area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the
Options for Target' dialog.
*** ICCARM Compiler ***
-----------------------
[..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
*** GNU Compiler ***
--------------------
[..] RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_flash_ramfunc.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @defgroup FLASH RAMFUNC
* @brief FLASH RAMFUNC driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup FLASH_RAMFUNC_Private_Functions
* @{
*/
/** @defgroup FLASH_RAMFUNC_Group1 Peripheral features functions executed from internal RAM
* @brief Peripheral Extended features functions
*
@verbatim
===============================================================================
##### ramfunc functions #####
===============================================================================
[..]
This subsection provides a set of functions that should be executed from RAM
transfers.
@endverbatim
* @{
*/
/**
* @brief Start/Stop the flash interface while System Run
* @note This mode is only available for STM32F411xx devices.
* @note This mode could n't be set while executing with the flash itself.
* It should be done with specific routine executed from RAM.
* @param NewState: new state of the Smart Card mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
__RAM_FUNC FLASH_FlashInterfaceCmd(FunctionalState NewState)
{
if (NewState != DISABLE)
{
/* Start the flash interface while System Run */
CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
}
else
{
/* Stop the flash interface while System Run */
SET_BIT(PWR->CR, PWR_CR_FISSR);
}
}
/**
* @brief Enable/Disable the flash sleep while System Run
* @note This mode is only available for STM32F411xx devices.
* @note This mode could n't be set while executing with the flash itself.
* It should be done with specific routine executed from RAM.
* @param NewState: new state of the Smart Card mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
__RAM_FUNC FLASH_FlashSleepModeCmd(FunctionalState NewState)
{
if (NewState != DISABLE)
{
/* Enable the flash sleep while System Run */
SET_BIT(PWR->CR, PWR_CR_FMSSR);
}
else
{
/* Disable the flash sleep while System Run */
CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

177
example/libs/StmCoreNPheriph/src/stm32f4xx_fsmc.c
View File

@@ -2,27 +2,32 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_fsmc.c * @file stm32f4xx_fsmc.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides firmware functions to manage the following * @brief This file provides firmware functions to manage the following
* functionalities of the FSMC peripheral: * functionalities of the FSMC peripheral:
* - Interface with SRAM, PSRAM, NOR and OneNAND memories * + Interface with SRAM, PSRAM, NOR and OneNAND memories
* - Interface with NAND memories * + Interface with NAND memories
* - Interface with 16-bit PC Card compatible memories * + Interface with 16-bit PC Card compatible memories
* - Interrupts and flags management * + Interrupts and flags management
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -40,6 +45,14 @@
*/ */
/* Private typedef -----------------------------------------------------------*/ /* Private typedef -----------------------------------------------------------*/
const FSMC_NORSRAMTimingInitTypeDef FSMC_DefaultTimingStruct = {0x0F, /* FSMC_AddressSetupTime */
0x0F, /* FSMC_AddressHoldTime */
0xFF, /* FSMC_DataSetupTime */
0x0F, /* FSMC_BusTurnAroundDuration */
0x0F, /* FSMC_CLKDivision */
0x0F, /* FSMC_DataLatency */
FSMC_AccessMode_A /* FSMC_AccessMode */
};
/* Private define ------------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/
/* --------------------- FSMC registers bit mask ---------------------------- */ /* --------------------- FSMC registers bit mask ---------------------------- */
@@ -69,41 +82,41 @@
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
NOR/SRAM Controller functions ##### NOR and SRAM Controller functions #####
=============================================================================== ===============================================================================
The following sequence should be followed to configure the FSMC to interface with [..] The following sequence should be followed to configure the FSMC to interface
SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank: with SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank:
1. Enable the clock for the FSMC and associated GPIOs using the following functions: (#) Enable the clock for the FSMC and associated GPIOs using the following functions:
RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
2. FSMC pins configuration (#) FSMC pins configuration
- Connect the involved FSMC pins to AF12 using the following function (++) Connect the involved FSMC pins to AF12 using the following function
GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
- Configure these FSMC pins in alternate function mode by calling the function (++) Configure these FSMC pins in alternate function mode by calling the function
GPIO_Init(); GPIO_Init();
3. Declare a FSMC_NORSRAMInitTypeDef structure, for example: (#) Declare a FSMC_NORSRAMInitTypeDef structure, for example:
FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
and fill the FSMC_NORSRAMInitStructure variable with the allowed values of and fill the FSMC_NORSRAMInitStructure variable with the allowed values of
the structure member. the structure member.
4. Initialize the NOR/SRAM Controller by calling the function (#) Initialize the NOR/SRAM Controller by calling the function
FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
5. Then enable the NOR/SRAM Bank, for example: (#) Then enable the NOR/SRAM Bank, for example:
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE); FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
6. At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank. (#) At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank.
@endverbatim @endverbatim
* @{ * @{
*/ */
/** /**
* @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default * @brief De-initializes the FSMC NOR/SRAM Banks registers to their default
* reset values. * reset values.
* @param FSMC_Bank: specifies the FSMC Bank to be used * @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values: * This parameter can be one of the following values:
@@ -238,20 +251,8 @@ void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct = (FSMC_NORSRAMTimingInitTypeDef*)&FSMC_DefaultTimingStruct;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct = (FSMC_NORSRAMTimingInitTypeDef*)&FSMC_DefaultTimingStruct;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
} }
/** /**
@@ -290,46 +291,48 @@ void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
NAND Controller functions ##### NAND Controller functions #####
=============================================================================== ===============================================================================
The following sequence should be followed to configure the FSMC to interface with [..] The following sequence should be followed to configure the FSMC to interface
8-bit or 16-bit NAND memory connected to the NAND Bank: with 8-bit or 16-bit NAND memory connected to the NAND Bank:
1. Enable the clock for the FSMC and associated GPIOs using the following functions: (#) Enable the clock for the FSMC and associated GPIOs using the following functions:
RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
2. FSMC pins configuration (#) FSMC pins configuration
- Connect the involved FSMC pins to AF12 using the following function (++) Connect the involved FSMC pins to AF12 using the following function
GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
- Configure these FSMC pins in alternate function mode by calling the function (++) Configure these FSMC pins in alternate function mode by calling the function
GPIO_Init(); GPIO_Init();
3. Declare a FSMC_NANDInitTypeDef structure, for example: (#) Declare a FSMC_NANDInitTypeDef structure, for example:
FSMC_NANDInitTypeDef FSMC_NANDInitStructure; FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
and fill the FSMC_NANDInitStructure variable with the allowed values of and fill the FSMC_NANDInitStructure variable with the allowed values of
the structure member. the structure member.
4. Initialize the NAND Controller by calling the function (#) Initialize the NAND Controller by calling the function
FSMC_NANDInit(&FSMC_NANDInitStructure); FSMC_NANDInit(&FSMC_NANDInitStructure);
5. Then enable the NAND Bank, for example: (#) Then enable the NAND Bank, for example:
FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE); FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE);
6. At this stage you can read/write from/to the memory connected to the NAND Bank. (#) At this stage you can read/write from/to the memory connected to the NAND Bank.
@note To enable the Error Correction Code (ECC), you have to use the function [..]
FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE); (@) To enable the Error Correction Code (ECC), you have to use the function
and to get the current ECC value you have to use the function FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE);
ECCval = FSMC_GetECC(FSMC_Bank3_NAND); [..]
(@) and to get the current ECC value you have to use the function
ECCval = FSMC_GetECC(FSMC_Bank3_NAND);
@endverbatim @endverbatim
* @{ * @{
*/ */
/** /**
* @brief Deinitializes the FSMC NAND Banks registers to their default reset values. * @brief De-initializes the FSMC NAND Banks registers to their default reset values.
* @param FSMC_Bank: specifies the FSMC Bank to be used * @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
@@ -566,41 +569,41 @@ uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
PCCARD Controller functions ##### PCCARD Controller functions #####
=============================================================================== ===============================================================================
The following sequence should be followed to configure the FSMC to interface with [..] he following sequence should be followed to configure the FSMC to interface
16-bit PC Card compatible memory connected to the PCCARD Bank: with 16-bit PC Card compatible memory connected to the PCCARD Bank:
1. Enable the clock for the FSMC and associated GPIOs using the following functions: (#) Enable the clock for the FSMC and associated GPIOs using the following functions:
RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
2. FSMC pins configuration (#) FSMC pins configuration
- Connect the involved FSMC pins to AF12 using the following function (++) Connect the involved FSMC pins to AF12 using the following function
GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
- Configure these FSMC pins in alternate function mode by calling the function (++) Configure these FSMC pins in alternate function mode by calling the function
GPIO_Init(); GPIO_Init();
3. Declare a FSMC_PCCARDInitTypeDef structure, for example: (#) Declare a FSMC_PCCARDInitTypeDef structure, for example:
FSMC_PCCARDInitTypeDef FSMC_PCCARDInitStructure; FSMC_PCCARDInitTypeDef FSMC_PCCARDInitStructure;
and fill the FSMC_PCCARDInitStructure variable with the allowed values of and fill the FSMC_PCCARDInitStructure variable with the allowed values of
the structure member. the structure member.
4. Initialize the PCCARD Controller by calling the function (#) Initialize the PCCARD Controller by calling the function
FSMC_PCCARDInit(&FSMC_PCCARDInitStructure); FSMC_PCCARDInit(&FSMC_PCCARDInitStructure);
5. Then enable the PCCARD Bank: (#) Then enable the PCCARD Bank:
FSMC_PCCARDCmd(ENABLE); FSMC_PCCARDCmd(ENABLE);
6. At this stage you can read/write from/to the memory connected to the PCCARD Bank. (#) At this stage you can read/write from/to the memory connected to the PCCARD Bank.
@endverbatim @endverbatim
* @{ * @{
*/ */
/** /**
* @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values. * @brief De-initializes the FSMC PCCARD Bank registers to their default reset values.
* @param None * @param None
* @retval None * @retval None
*/ */
@@ -723,8 +726,8 @@ void FSMC_PCCARDCmd(FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Interrupts and flags management functions ##### Interrupts and flags management functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
* @{ * @{
@@ -979,4 +982,4 @@ void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

222
example/libs/StmCoreNPheriph/src/stm32f4xx_gpio.c
View File

@@ -2,76 +2,81 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_gpio.c * @file stm32f4xx_gpio.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides firmware functions to manage the following * @brief This file provides firmware functions to manage the following
* functionalities of the GPIO peripheral: * functionalities of the GPIO peripheral:
* - Initialization and Configuration * + Initialization and Configuration
* - GPIO Read and Write * + GPIO Read and Write
* - GPIO Alternate functions configuration * + GPIO Alternate functions configuration
* *
* @verbatim @verbatim
* ===============================================================================
* =================================================================== ##### How to use this driver #####
* How to use this driver ===============================================================================
* =================================================================== [..]
* 1. Enable the GPIO AHB clock using the following function (#) Enable the GPIO AHB clock using the following function
* RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
*
* 2. Configure the GPIO pin(s) using GPIO_Init() (#) Configure the GPIO pin(s) using GPIO_Init()
* Four possible configuration are available for each pin: Four possible configuration are available for each pin:
* - Input: Floating, Pull-up, Pull-down. (++) Input: Floating, Pull-up, Pull-down.
* - Output: Push-Pull (Pull-up, Pull-down or no Pull) (++) Output: Push-Pull (Pull-up, Pull-down or no Pull)
* Open Drain (Pull-up, Pull-down or no Pull). Open Drain (Pull-up, Pull-down or no Pull). In output mode, the speed
* In output mode, the speed is configurable: 2 MHz, 25 MHz, is configurable: 2 MHz, 25 MHz, 50 MHz or 100 MHz.
* 50 MHz or 100 MHz. (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) Open
* - Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) Drain (Pull-up, Pull-down or no Pull).
* Open Drain (Pull-up, Pull-down or no Pull). (++) Analog: required mode when a pin is to be used as ADC channel or DAC
* - Analog: required mode when a pin is to be used as ADC channel output.
* or DAC output.
* (#) Peripherals alternate function:
* 3- Peripherals alternate function: (++) For ADC and DAC, configure the desired pin in analog mode using
* - For ADC and DAC, configure the desired pin in analog mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN;
* GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN; (+++) For other peripherals (TIM, USART...):
* - For other peripherals (TIM, USART...): (+++) Connect the pin to the desired peripherals' Alternate
* - Connect the pin to the desired peripherals' Alternate Function (AF) using GPIO_PinAFConfig() function
* Function (AF) using GPIO_PinAFConfig() function (+++) Configure the desired pin in alternate function mode using
* - Configure the desired pin in alternate function mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
* GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF (+++) Select the type, pull-up/pull-down and output speed via
* - Select the type, pull-up/pull-down and output speed via GPIO_PuPd, GPIO_OType and GPIO_Speed members
* GPIO_PuPd, GPIO_OType and GPIO_Speed members (+++) Call GPIO_Init() function
* - Call GPIO_Init() function
* (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
* 4. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
* (#) To set/reset the level of a pin configured in output mode use
* 5. To set/reset the level of a pin configured in output mode use GPIO_SetBits()/GPIO_ResetBits()
* GPIO_SetBits()/GPIO_ResetBits()
* (#) During and just after reset, the alternate functions are not
* 6. During and just after reset, the alternate functions are not active and the GPIO pins are configured in input floating mode (except JTAG
* active and the GPIO pins are configured in input floating mode pins).
* (except JTAG pins).
* (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
* 7. The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
* general-purpose (PC14 and PC15, respectively) when the LSE priority over the GPIO function.
* oscillator is off. The LSE has priority over the GPIO function.
* (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
* 8. The HSE oscillator pins OSC_IN/OSC_OUT can be used as general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
* general-purpose PH0 and PH1, respectively, when the HSE The HSE has priority over the GPIO function.
* oscillator is off. The HSE has priority over the GPIO function.
* @endverbatim
* @endverbatim
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -104,7 +109,7 @@
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Initialization and Configuration ##### Initialization and Configuration #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -112,9 +117,11 @@
*/ */
/** /**
* @brief Deinitializes the GPIOx peripheral registers to their default reset values. * @brief De-initializes the GPIOx peripheral registers to their default reset values.
* @note By default, The GPIO pins are configured in input floating mode (except JTAG pins). * @note By default, The GPIO pins are configured in input floating mode (except JTAG pins).
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @retval None * @retval None
*/ */
void GPIO_DeInit(GPIO_TypeDef* GPIOx) void GPIO_DeInit(GPIO_TypeDef* GPIOx)
@@ -162,19 +169,32 @@ void GPIO_DeInit(GPIO_TypeDef* GPIOx)
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE); RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE);
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE); RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE);
} }
else if (GPIOx == GPIOI)
{
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE);
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE);
}
else if (GPIOx == GPIOJ)
{
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, ENABLE);
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, DISABLE);
}
else else
{ {
if (GPIOx == GPIOI) if (GPIOx == GPIOK)
{ {
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE); RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, ENABLE);
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE); RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, DISABLE);
} }
} }
} }
/** /**
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct. * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral. * the configuration information for the specified GPIO peripheral.
* @retval None * @retval None
@@ -189,7 +209,7 @@ void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
/* -------------------------Configure the port pins---------------- */ /* ------------------------- Configure the port pins ---------------- */
/*-- GPIO Mode Configuration --*/ /*-- GPIO Mode Configuration --*/
for (pinpos = 0x00; pinpos < 0x10; pinpos++) for (pinpos = 0x00; pinpos < 0x10; pinpos++)
{ {
@@ -247,7 +267,9 @@ void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
* @note The configuration of the locked GPIO pins can no longer be modified * @note The configuration of the locked GPIO pins can no longer be modified
* until the next reset. * until the next reset.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param GPIO_Pin: specifies the port bit to be locked. * @param GPIO_Pin: specifies the port bit to be locked.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None * @retval None
@@ -282,7 +304,7 @@ void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
GPIO Read and Write ##### GPIO Read and Write #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -291,7 +313,9 @@ void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
/** /**
* @brief Reads the specified input port pin. * @brief Reads the specified input port pin.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param GPIO_Pin: specifies the port bit to read. * @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15). * This parameter can be GPIO_Pin_x where x can be (0..15).
* @retval The input port pin value. * @retval The input port pin value.
@@ -317,7 +341,9 @@ uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
/** /**
* @brief Reads the specified GPIO input data port. * @brief Reads the specified GPIO input data port.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @retval GPIO input data port value. * @retval GPIO input data port value.
*/ */
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
@@ -330,7 +356,9 @@ uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
/** /**
* @brief Reads the specified output data port bit. * @brief Reads the specified output data port bit.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param GPIO_Pin: specifies the port bit to read. * @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15). * This parameter can be GPIO_Pin_x where x can be (0..15).
* @retval The output port pin value. * @retval The output port pin value.
@@ -343,7 +371,7 @@ uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) if (((GPIOx->ODR) & GPIO_Pin) != (uint32_t)Bit_RESET)
{ {
bitstatus = (uint8_t)Bit_SET; bitstatus = (uint8_t)Bit_SET;
} }
@@ -356,7 +384,9 @@ uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
/** /**
* @brief Reads the specified GPIO output data port. * @brief Reads the specified GPIO output data port.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @retval GPIO output data port value. * @retval GPIO output data port value.
*/ */
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
@@ -372,7 +402,9 @@ uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
* @note This functions uses GPIOx_BSRR register to allow atomic read/modify * @note This functions uses GPIOx_BSRR register to allow atomic read/modify
* accesses. In this way, there is no risk of an IRQ occurring between * accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access. * the read and the modify access.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param GPIO_Pin: specifies the port bits to be written. * @param GPIO_Pin: specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None * @retval None
@@ -391,7 +423,9 @@ void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
* @note This functions uses GPIOx_BSRR register to allow atomic read/modify * @note This functions uses GPIOx_BSRR register to allow atomic read/modify
* accesses. In this way, there is no risk of an IRQ occurring between * accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access. * the read and the modify access.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param GPIO_Pin: specifies the port bits to be written. * @param GPIO_Pin: specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None * @retval None
@@ -407,7 +441,9 @@ void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
/** /**
* @brief Sets or clears the selected data port bit. * @brief Sets or clears the selected data port bit.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param GPIO_Pin: specifies the port bit to be written. * @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_Pin_x where x can be (0..15). * This parameter can be one of GPIO_Pin_x where x can be (0..15).
* @param BitVal: specifies the value to be written to the selected bit. * @param BitVal: specifies the value to be written to the selected bit.
@@ -435,7 +471,9 @@ void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
/** /**
* @brief Writes data to the specified GPIO data port. * @brief Writes data to the specified GPIO data port.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param PortVal: specifies the value to be written to the port output data register. * @param PortVal: specifies the value to be written to the port output data register.
* @retval None * @retval None
*/ */
@@ -449,7 +487,9 @@ void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
/** /**
* @brief Toggles the specified GPIO pins.. * @brief Toggles the specified GPIO pins..
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param GPIO_Pin: Specifies the pins to be toggled. * @param GPIO_Pin: Specifies the pins to be toggled.
* @retval None * @retval None
*/ */
@@ -470,7 +510,7 @@ void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
GPIO Alternate functions configuration function ##### GPIO Alternate functions configuration function #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -479,7 +519,9 @@ void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
/** /**
* @brief Changes the mapping of the specified pin. * @brief Changes the mapping of the specified pin.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral. * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param GPIO_PinSource: specifies the pin for the Alternate function. * @param GPIO_PinSource: specifies the pin for the Alternate function.
* This parameter can be GPIO_PinSourcex where x can be (0..15). * This parameter can be GPIO_PinSourcex where x can be (0..15).
* @param GPIO_AFSelection: selects the pin to used as Alternate function. * @param GPIO_AFSelection: selects the pin to used as Alternate function.
@@ -503,6 +545,10 @@ void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
* @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4 * @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4
* @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5 * @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5
* @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5 * @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5
* @arg GPIO_AF_SPI4: Connect SPI4 pins to AF5
* @arg GPIO_AF_SPI5: Connect SPI5 pins to AF5
* @arg GPIO_AF_SPI6: Connect SPI6 pins to AF5
* @arg GPIO_AF_SAI1: Connect SAI1 pins to AF6 for STM32F42xxx/43xxx devices.
* @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6 * @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6
* @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7 * @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7
* @arg GPIO_AF_USART1: Connect USART1 pins to AF7 * @arg GPIO_AF_USART1: Connect USART1 pins to AF7
@@ -511,6 +557,8 @@ void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
* @arg GPIO_AF_UART4: Connect UART4 pins to AF8 * @arg GPIO_AF_UART4: Connect UART4 pins to AF8
* @arg GPIO_AF_UART5: Connect UART5 pins to AF8 * @arg GPIO_AF_UART5: Connect UART5 pins to AF8
* @arg GPIO_AF_USART6: Connect USART6 pins to AF8 * @arg GPIO_AF_USART6: Connect USART6 pins to AF8
* @arg GPIO_AF_UART7: Connect UART7 pins to AF8
* @arg GPIO_AF_UART8: Connect UART8 pins to AF8
* @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9 * @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9
* @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9 * @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9
* @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9 * @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9
@@ -519,10 +567,12 @@ void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
* @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10 * @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10
* @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10 * @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10
* @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11 * @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11
* @arg GPIO_AF_FSMC: Connect FSMC pins to AF12 * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12
* @arg GPIO_AF_FMC: Connect FMC pins to AF12 for STM32F42xxx/43xxx devices.
* @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12 * @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12
* @arg GPIO_AF_SDIO: Connect SDIO pins to AF12 * @arg GPIO_AF_SDIO: Connect SDIO pins to AF12
* @arg GPIO_AF_DCMI: Connect DCMI pins to AF13 * @arg GPIO_AF_DCMI: Connect DCMI pins to AF13
* @arg GPIO_AF_LTDC: Connect LTDC pins to AF14 for STM32F429xx/439xx devices.
* @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15 * @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15
* @retval None * @retval None
*/ */
@@ -558,4 +608,4 @@ void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

406
example/libs/StmCoreNPheriph/src/stm32f4xx_hash.c
View File

@@ -2,8 +2,8 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_hash.c * @file stm32f4xx_hash.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides firmware functions to manage the following * @brief This file provides firmware functions to manage the following
* functionalities of the HASH / HMAC Processor (HASH) peripheral: * functionalities of the HASH / HMAC Processor (HASH) peripheral:
* - Initialization and Configuration functions * - Initialization and Configuration functions
@@ -12,110 +12,110 @@
* - DMA interface function * - DMA interface function
* - Interrupts and flags management * - Interrupts and flags management
* *
* @verbatim @verbatim
* ===================================================================
* =================================================================== ##### How to use this driver #####
* How to use this driver ===================================================================
* ===================================================================
* HASH operation : *** HASH operation : ***
* ---------------- ========================
* 1. Enable the HASH controller clock using [..]
* RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function. (#) Enable the HASH controller clock using
* RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function.
* 2. Initialise the HASH using HASH_Init() function.
* (#) Initialise the HASH using HASH_Init() function.
* 3 . Reset the HASH processor core, so that the HASH will be ready
* to compute he message digest of a new message by using (#) Reset the HASH processor core, so that the HASH will be ready
* HASH_Reset() function. to compute he message digest of a new message by using HASH_Reset() function.
*
* 4. Enable the HASH controller using the HASH_Cmd() function. (#) Enable the HASH controller using the HASH_Cmd() function.
*
* 5. if using DMA for Data input transfer, Activate the DMA Request (#) if using DMA for Data input transfer, Activate the DMA Request
* using HASH_DMACmd() function using HASH_DMACmd() function
*
* 6. if DMA is not used for data transfer, use HASH_DataIn() function (#) if DMA is not used for data transfer, use HASH_DataIn() function
* to enter data to IN FIFO. to enter data to IN FIFO.
*
*
* 7. Configure the Number of valid bits in last word of the message (#) Configure the Number of valid bits in last word of the message
* using HASH_SetLastWordValidBitsNbr() function. using HASH_SetLastWordValidBitsNbr() function.
*
* 8. if the message length is not an exact multiple of 512 bits, (#) if the message length is not an exact multiple of 512 bits,
* then the function HASH_StartDigest() must be called to then the function HASH_StartDigest() must be called to launch the computation
* launch the computation of the final digest. of the final digest.
*
* 9. Once computed, the digest can be read using HASH_GetDigest() (#) Once computed, the digest can be read using HASH_GetDigest() function.
* function.
* (#) To control HASH events you can use one of the following wo methods:
* 10. To control HASH events you can use one of the following (++) Check on HASH flags using the HASH_GetFlagStatus() function.
* two methods: (++) Use HASH interrupts through the function HASH_ITConfig() at
* a- Check on HASH flags using the HASH_GetFlagStatus() function. initialization phase and HASH_GetITStatus() function into
* b- Use HASH interrupts through the function HASH_ITConfig() at interrupt routines in hashing phase.
* initialization phase and HASH_GetITStatus() function into After checking on a flag you should clear it using HASH_ClearFlag()
* interrupt routines in hashing phase. function. And after checking on an interrupt event you should
* After checking on a flag you should clear it using HASH_ClearFlag() clear it using HASH_ClearITPendingBit() function.
* function. And after checking on an interrupt event you should
* clear it using HASH_ClearITPendingBit() function. (#) Save and restore hash processor context using
* HASH_SaveContext() and HASH_RestoreContext() functions.
* 11. Save and restore hash processor context using
* HASH_SaveContext() and HASH_RestoreContext() functions.
*
* *** HMAC operation : ***
* ========================
* HMAC operation : [..] The HMAC algorithm is used for message authentication, by
* ---------------- irreversibly binding the message being processed to a key chosen
* The HMAC algorithm is used for message authentication, by by the user.
* irreversibly binding the message being processed to a key chosen For HMAC specifications, refer to "HMAC: keyed-hashing for message
* by the user. authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997"
* For HMAC specifications, refer to "HMAC: keyed-hashing for message
* authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997" [..] Basically, the HMAC algorithm consists of two nested hash operations:
* HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)]
* Basically, the HMAC algorithm consists of two nested hash operations: where:
* HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)] (+) "pad" is a sequence of zeroes needed to extend the key to the
* where: length of the underlying hash function data block (that is
* - "pad" is a sequence of zeroes needed to extend the key to the 512 bits for both the SHA-1 and MD5 hash algorithms)
* length of the underlying hash function data block (that is (+) "|" represents the concatenation operator
* 512 bits for both the SHA-1 and MD5 hash algorithms)
* - "|" represents the concatenation operator
* [..]To compute the HMAC, four different phases are required:
* (#) Initialise the HASH using HASH_Init() function to do HMAC
* To compute the HMAC, four different phases are required: operation.
*
* 1. Initialise the HASH using HASH_Init() function to do HMAC (#) The key (to be used for the inner hash function) is then given to the core.
* operation. This operation follows the same mechanism as the one used to send the
* message in the hash operation (that is, by HASH_DataIn() function and,
* 2. The key (to be used for the inner hash function) is then given finally, HASH_StartDigest() function.
* to the core. This operation follows the same mechanism as the
* one used to send the message in the hash operation (that is, (#) Once the last word has been entered and computation has started,
* by HASH_DataIn() function and, finally, the hash processor elaborates the key. It is then ready to accept the message
* HASH_StartDigest() function. text using the same mechanism as the one used to send the message in the
* hash operation.
* 3. Once the last word has been entered and computation has started,
* the hash processor elaborates the key. It is then ready to (#) After the first hash round, the hash processor returns "ready" to indicate
* accept the message text using the same mechanism as the one that it is ready to receive the key to be used for the outer hash function
* used to send the message in the hash operation. (normally, this key is the same as the one used for the inner hash function).
* When the last word of the key is entered and computation starts, the HMAC
* 4. After the first hash round, the hash processor returns "ready" result is made available using HASH_GetDigest() function.
* to indicate that it is ready to receive the key to be used for
* the outer hash function (normally, this key is the same as the @endverbatim
* one used for the inner hash function). When the last word of
* the key is entered and computation starts, the HMAC result is
* made available using HASH_GetDigest() function.
*
*
* @endverbatim
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -148,23 +148,23 @@
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Initialization and Configuration functions ##### Initialization and Configuration functions #####
=============================================================================== ===============================================================================
This section provides functions allowing to [..] This section provides functions allowing to
- Initialize the HASH peripheral (+) Initialize the HASH peripheral
- Configure the HASH Processor (+) Configure the HASH Processor
- MD5/SHA1, (+) MD5/SHA1,
- HASH/HMAC, (+) HASH/HMAC,
- datatype (+) datatype
- HMAC Key (if mode = HMAC) (+) HMAC Key (if mode = HMAC)
- Reset the HASH Processor (+) Reset the HASH Processor
@endverbatim @endverbatim
* @{ * @{
*/ */
/** /**
* @brief Deinitializes the HASH peripheral registers to their default reset values * @brief De-initializes the HASH peripheral registers to their default reset values
* @param None * @param None
* @retval None * @retval None
*/ */
@@ -260,14 +260,14 @@ void HASH_Reset(void)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Message Digest generation functions ##### Message Digest generation functions #####
=============================================================================== ===============================================================================
This section provides functions allowing the generation of message digest: [..] This section provides functions allowing the generation of message digest:
- Push data in the IN FIFO : using HASH_DataIn() (+) Push data in the IN FIFO : using HASH_DataIn()
- Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr() (+) Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr()
- set the last word valid bits number using HASH_SetLastWordValidBitsNbr() (+) set the last word valid bits number using HASH_SetLastWordValidBitsNbr()
- start digest calculation : using HASH_StartDigest() (+) start digest calculation : using HASH_StartDigest()
- Get the Digest message : using HASH_GetDigest() (+) Get the Digest message : using HASH_GetDigest()
@endverbatim @endverbatim
* @{ * @{
@@ -322,7 +322,11 @@ uint8_t HASH_GetInFIFOWordsNbr(void)
/** /**
* @brief Provides the message digest result. * @brief Provides the message digest result.
* @note In MD5 mode, Data[4] filed of HASH_MsgDigest structure is not used * @note In MD5 mode, Data[7] to Data[4] filed of HASH_MsgDigest structure is not used
* and is read as zero.
* In SHA-1 mode, Data[7] to Data[5] filed of HASH_MsgDigest structure is not used
* and is read as zero.
* In SHA-224 mode, Data[7] filed of HASH_MsgDigest structure is not used
* and is read as zero. * and is read as zero.
* @param HASH_MessageDigest: pointer to a HASH_MsgDigest structure which will * @param HASH_MessageDigest: pointer to a HASH_MsgDigest structure which will
* hold the message digest result * hold the message digest result
@@ -336,6 +340,9 @@ void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest)
HASH_MessageDigest->Data[2] = HASH->HR[2]; HASH_MessageDigest->Data[2] = HASH->HR[2];
HASH_MessageDigest->Data[3] = HASH->HR[3]; HASH_MessageDigest->Data[3] = HASH->HR[3];
HASH_MessageDigest->Data[4] = HASH->HR[4]; HASH_MessageDigest->Data[4] = HASH->HR[4];
HASH_MessageDigest->Data[5] = HASH_DIGEST->HR[5];
HASH_MessageDigest->Data[6] = HASH_DIGEST->HR[6];
HASH_MessageDigest->Data[7] = HASH_DIGEST->HR[7];
} }
/** /**
@@ -357,19 +364,19 @@ void HASH_StartDigest(void)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Context swapping functions ##### Context swapping functions #####
=============================================================================== ===============================================================================
This section provides functions allowing to save and store HASH Context [..] This section provides functions allowing to save and store HASH Context
It is possible to interrupt a HASH/HMAC process to perform another processing [..] It is possible to interrupt a HASH/HMAC process to perform another processing
with a higher priority, and to complete the interrupted process later on, when with a higher priority, and to complete the interrupted process later on, when
the higher priority task is complete. To do so, the context of the interrupted the higher priority task is complete. To do so, the context of the interrupted
task must be saved from the HASH registers to memory, and then be restored task must be saved from the HASH registers to memory, and then be restored
from memory to the HASH registers. from memory to the HASH registers.
1. To save the current context, use HASH_SaveContext() function (#) To save the current context, use HASH_SaveContext() function
2. To restore the saved context, use HASH_RestoreContext() function (#) To restore the saved context, use HASH_RestoreContext() function
@endverbatim @endverbatim
@@ -394,7 +401,7 @@ void HASH_SaveContext(HASH_Context* HASH_ContextSave)
HASH_ContextSave->HASH_IMR = HASH->IMR; HASH_ContextSave->HASH_IMR = HASH->IMR;
HASH_ContextSave->HASH_STR = HASH->STR; HASH_ContextSave->HASH_STR = HASH->STR;
HASH_ContextSave->HASH_CR = HASH->CR; HASH_ContextSave->HASH_CR = HASH->CR;
for(i=0; i<=50;i++) for(i=0; i<=53;i++)
{ {
HASH_ContextSave->HASH_CSR[i] = HASH->CSR[i]; HASH_ContextSave->HASH_CSR[i] = HASH->CSR[i];
} }
@@ -421,7 +428,7 @@ void HASH_RestoreContext(HASH_Context* HASH_ContextRestore)
HASH->CR |= HASH_CR_INIT; HASH->CR |= HASH_CR_INIT;
/* continue restoring context registers */ /* continue restoring context registers */
for(i=0; i<=50;i++) for(i=0; i<=53;i++)
{ {
HASH->CSR[i] = HASH_ContextRestore->HASH_CSR[i]; HASH->CSR[i] = HASH_ContextRestore->HASH_CSR[i];
} }
@@ -435,20 +442,42 @@ void HASH_RestoreContext(HASH_Context* HASH_ContextRestore)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
HASH's DMA interface Configuration function ##### HASH's DMA interface Configuration function #####
=============================================================================== ===============================================================================
This section provides functions allowing to configure the DMA interface for [..] This section provides functions allowing to configure the DMA interface for
HASH/ HMAC data input transfer. HASH/ HMAC data input transfer.
When the DMA mode is enabled (using the HASH_DMACmd() function), data can be [..] When the DMA mode is enabled (using the HASH_DMACmd() function), data can be
sent to the IN FIFO using the DMA peripheral. sent to the IN FIFO using the DMA peripheral.
@endverbatim @endverbatim
* @{ * @{
*/ */
/**
* @brief Enables or disables auto-start message padding and
* calculation of the final message digest at the end of DMA transfer.
* @param NewState: new state of the selected HASH DMA transfer request.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void HASH_AutoStartDigest(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the auto start of the final message digest at the end of DMA transfer */
HASH->CR &= ~HASH_CR_MDMAT;
}
else
{
/* Disable the auto start of the final message digest at the end of DMA transfer */
HASH->CR |= HASH_CR_MDMAT;
}
}
/** /**
* @brief Enables or disables the HASH DMA interface. * @brief Enables or disables the HASH DMA interface.
@@ -482,61 +511,58 @@ void HASH_DMACmd(FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Interrupts and flags management functions ##### Interrupts and flags management functions #####
=============================================================================== ===============================================================================
This section provides functions allowing to configure the HASH Interrupts and [..] This section provides functions allowing to configure the HASH Interrupts and
to get the status and clear flags and Interrupts pending bits. to get the status and clear flags and Interrupts pending bits.
The HASH provides 2 Interrupts sources and 5 Flags: [..] The HASH provides 2 Interrupts sources and 5 Flags:
Flags : *** Flags : ***
---------- ===============
1. HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO [..]
which means that a new block (512 bit) can be entered (#) HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO
into the input buffer. which means that a new block (512 bit) can be entered into the input buffer.
2. HASH_FLAG_DCIS : set when Digest calculation is complete (#) HASH_FLAG_DCIS : set when Digest calculation is complete
3. HASH_FLAG_DMAS : set when HASH's DMA interface is enabled (DMAE=1) or (#) HASH_FLAG_DMAS : set when HASH's DMA interface is enabled (DMAE=1) or
a transfer is ongoing. a transfer is ongoing. This Flag is cleared only by hardware.
This Flag is cleared only by hardware.
4. HASH_FLAG_BUSY : set when The hash core is processing a block of data (#) HASH_FLAG_BUSY : set when The hash core is processing a block of data
This Flag is cleared only by hardware. This Flag is cleared only by hardware.
5. HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that (#) HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that
the Data IN FIFO contains at least one word of data. the Data IN FIFO contains at least one word of data. This Flag is cleared
This Flag is cleared only by hardware. only by hardware.
Interrupts : *** Interrupts : ***
------------ ====================
[..]
1. HASH_IT_DINI : if enabled, this interrupt source is pending when 16 (#) HASH_IT_DINI : if enabled, this interrupt source is pending when 16
locations are free in the Data IN FIFO which means that locations are free in the Data IN FIFO which means that a new block (512 bit)
a new block (512 bit) can be entered into the input buffer. can be entered into the input buffer. This interrupt source is cleared using
This interrupt source is cleared using HASH_ClearITPendingBit(HASH_IT_DINI) function.
HASH_ClearITPendingBit(HASH_IT_DINI) function.
2. HASH_IT_DCI : if enabled, this interrupt source is pending when Digest (#) HASH_IT_DCI : if enabled, this interrupt source is pending when Digest
calculation is complete. calculation is complete. This interrupt source is cleared using
This interrupt source is cleared using HASH_ClearITPendingBit(HASH_IT_DCI) function.
HASH_ClearITPendingBit(HASH_IT_DCI) function.
Managing the HASH controller events : *** Managing the HASH controller events : ***
------------------------------------ =============================================
The user should identify which mode will be used in his application to manage [..] The user should identify which mode will be used in his application to manage
the HASH controller events: Polling mode or Interrupt mode. the HASH controller events: Polling mode or Interrupt mode.
1. In the Polling Mode it is advised to use the following functions: (#) In the Polling Mode it is advised to use the following functions:
- HASH_GetFlagStatus() : to check if flags events occur. (++) HASH_GetFlagStatus() : to check if flags events occur.
- HASH_ClearFlag() : to clear the flags events. (++) HASH_ClearFlag() : to clear the flags events.
2. In the Interrupt Mode it is advised to use the following functions: (#) In the Interrupt Mode it is advised to use the following functions:
- HASH_ITConfig() : to enable or disable the interrupt source. (++) HASH_ITConfig() : to enable or disable the interrupt source.
- HASH_GetITStatus() : to check if Interrupt occurs. (++) HASH_GetITStatus() : to check if Interrupt occurs.
- HASH_ClearITPendingBit() : to clear the Interrupt pending Bit (++) HASH_ClearITPendingBit() : to clear the Interrupt pending Bit
(corresponding Flag). (corresponding Flag).
@endverbatim @endverbatim
* @{ * @{
@@ -552,7 +578,7 @@ void HASH_DMACmd(FunctionalState NewState)
* This parameter can be: ENABLE or DISABLE. * This parameter can be: ENABLE or DISABLE.
* @retval None * @retval None
*/ */
void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState) void HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState)
{ {
/* Check the parameters */ /* Check the parameters */
assert_param(IS_HASH_IT(HASH_IT)); assert_param(IS_HASH_IT(HASH_IT));
@@ -566,7 +592,7 @@ void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState)
else else
{ {
/* Disable the selected HASH interrupt */ /* Disable the selected HASH interrupt */
HASH->IMR &= (uint8_t) ~HASH_IT; HASH->IMR &= (uint32_t)(~HASH_IT);
} }
} }
@@ -581,7 +607,7 @@ void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState)
* @arg HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag * @arg HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag
* @retval The new state of HASH_FLAG (SET or RESET) * @retval The new state of HASH_FLAG (SET or RESET)
*/ */
FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG) FlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG)
{ {
FlagStatus bitstatus = RESET; FlagStatus bitstatus = RESET;
uint32_t tempreg = 0; uint32_t tempreg = 0;
@@ -590,7 +616,7 @@ FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG)
assert_param(IS_HASH_GET_FLAG(HASH_FLAG)); assert_param(IS_HASH_GET_FLAG(HASH_FLAG));
/* check if the FLAG is in CR register */ /* check if the FLAG is in CR register */
if ((HASH_FLAG & HASH_FLAG_DINNE) != (uint16_t)RESET ) if ((HASH_FLAG & HASH_FLAG_DINNE) != (uint32_t)RESET )
{ {
tempreg = HASH->CR; tempreg = HASH->CR;
} }
@@ -600,7 +626,7 @@ FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG)
} }
/* Check the status of the specified HASH flag */ /* Check the status of the specified HASH flag */
if ((tempreg & HASH_FLAG) != (uint16_t)RESET) if ((tempreg & HASH_FLAG) != (uint32_t)RESET)
{ {
/* HASH is set */ /* HASH is set */
bitstatus = SET; bitstatus = SET;
@@ -622,7 +648,7 @@ FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG)
* @arg HASH_FLAG_DCIS: Digest Calculation Completion Flag * @arg HASH_FLAG_DCIS: Digest Calculation Completion Flag
* @retval None * @retval None
*/ */
void HASH_ClearFlag(uint16_t HASH_FLAG) void HASH_ClearFlag(uint32_t HASH_FLAG)
{ {
/* Check the parameters */ /* Check the parameters */
assert_param(IS_HASH_CLEAR_FLAG(HASH_FLAG)); assert_param(IS_HASH_CLEAR_FLAG(HASH_FLAG));
@@ -638,7 +664,7 @@ void HASH_ClearFlag(uint16_t HASH_FLAG)
* @arg HASH_IT_DCI: Digest Calculation Completion Interrupt * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
* @retval The new state of HASH_IT (SET or RESET). * @retval The new state of HASH_IT (SET or RESET).
*/ */
ITStatus HASH_GetITStatus(uint8_t HASH_IT) ITStatus HASH_GetITStatus(uint32_t HASH_IT)
{ {
ITStatus bitstatus = RESET; ITStatus bitstatus = RESET;
uint32_t tmpreg = 0; uint32_t tmpreg = 0;
@@ -672,13 +698,13 @@ ITStatus HASH_GetITStatus(uint8_t HASH_IT)
* @arg HASH_IT_DCI: Digest Calculation Completion Interrupt * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
* @retval None * @retval None
*/ */
void HASH_ClearITPendingBit(uint8_t HASH_IT) void HASH_ClearITPendingBit(uint32_t HASH_IT)
{ {
/* Check the parameters */ /* Check the parameters */
assert_param(IS_HASH_IT(HASH_IT)); assert_param(IS_HASH_IT(HASH_IT));
/* Clear the selected HASH interrupt pending bit */ /* Clear the selected HASH interrupt pending bit */
HASH->SR = (uint8_t)~HASH_IT; HASH->SR = (uint32_t)(~HASH_IT);
} }
/** /**
@@ -697,4 +723,4 @@ void HASH_ClearITPendingBit(uint8_t HASH_IT)
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

54
example/libs/StmCoreNPheriph/src/stm32f4xx_hash_md5.c
View File

@@ -2,38 +2,44 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_hash_md5.c * @file stm32f4xx_hash_md5.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides high level functions to compute the HASH MD5 and * @brief This file provides high level functions to compute the HASH MD5 and
* HMAC MD5 Digest of an input message. * HMAC MD5 Digest of an input message.
* It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH * It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH
* peripheral. * peripheral.
* *
* @verbatim @verbatim
* ===================================================================
* =================================================================== ##### How to use this driver #####
* How to use this driver ===================================================================
* =================================================================== [..]
* 1. Enable The HASH controller clock using (#) Enable The HASH controller clock using
* RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function. RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function.
*
* 2. Calculate the HASH MD5 Digest using HASH_MD5() function. (#) Calculate the HASH MD5 Digest using HASH_MD5() function.
*
* 3. Calculate the HMAC MD5 Digest using HMAC_MD5() function. (#) Calculate the HMAC MD5 Digest using HMAC_MD5() function.
*
* @endverbatim @endverbatim
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -67,7 +73,7 @@
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
High Level MD5 Hash and HMAC functions ##### High Level MD5 Hash and HMAC functions #####
=============================================================================== ===============================================================================
@@ -310,5 +316,5 @@ ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen, uint8_t *Input,
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

54
example/libs/StmCoreNPheriph/src/stm32f4xx_hash_sha1.c
View File

@@ -2,38 +2,44 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_hash_sha1.c * @file stm32f4xx_hash_sha1.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides high level functions to compute the HASH SHA1 and * @brief This file provides high level functions to compute the HASH SHA1 and
* HMAC SHA1 Digest of an input message. * HMAC SHA1 Digest of an input message.
* It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH * It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH
* peripheral. * peripheral.
* *
* @verbatim @verbatim
* ===================================================================
* =================================================================== ##### How to use this driver #####
* How to use this driver ===================================================================
* =================================================================== [..]
* 1. Enable The HASH controller clock using (#) Enable The HASH controller clock using
* RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function. RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function.
*
* 2. Calculate the HASH SHA1 Digest using HASH_SHA1() function. (#) Calculate the HASH SHA1 Digest using HASH_SHA1() function.
*
* 3. Calculate the HMAC SHA1 Digest using HMAC_SHA1() function. (#) Calculate the HMAC SHA1 Digest using HMAC_SHA1() function.
*
* @endverbatim @endverbatim
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -67,7 +73,7 @@
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
High Level SHA1 Hash and HMAC functions ##### High Level SHA1 Hash and HMAC functions #####
=============================================================================== ===============================================================================
@@ -314,4 +320,4 @@ ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen, uint8_t *Input,
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

309
example/libs/StmCoreNPheriph/src/stm32f4xx_i2c.c
View File

@@ -2,84 +2,89 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_i2c.c * @file stm32f4xx_i2c.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides firmware functions to manage the following * @brief This file provides firmware functions to manage the following
* functionalities of the Inter-integrated circuit (I2C) * functionalities of the Inter-integrated circuit (I2C)
* - Initialization and Configuration * + Initialization and Configuration
* - Data transfers * + Data transfers
* - PEC management * + PEC management
* - DMA transfers management * + DMA transfers management
* - Interrupts, events and flags management * + Interrupts, events and flags management
* *
* @verbatim @verbatim
* ===============================================================================
* =================================================================== ##### How to use this driver #####
* How to use this driver ===============================================================================
* =================================================================== [..]
* 1. Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE) (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE)
* function for I2C1, I2C2 or I2C3. function for I2C1, I2C2 or I2C3.
*
* 2. Enable SDA, SCL and SMBA (when used) GPIO clocks using (#) Enable SDA, SCL and SMBA (when used) GPIO clocks using
* RCC_AHBPeriphClockCmd() function. RCC_AHBPeriphClockCmd() function.
*
* 3. Peripherals alternate function: (#) Peripherals alternate function:
* - Connect the pin to the desired peripherals' Alternate (++) Connect the pin to the desired peripherals' Alternate
* Function (AF) using GPIO_PinAFConfig() function Function (AF) using GPIO_PinAFConfig() function
* - Configure the desired pin in alternate function by: (++) Configure the desired pin in alternate function by:
* GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
* - Select the type, pull-up/pull-down and output speed via (++) Select the type, pull-up/pull-down and output speed via
* GPIO_PuPd, GPIO_OType and GPIO_Speed members GPIO_PuPd, GPIO_OType and GPIO_Speed members
* - Call GPIO_Init() function (++) Call GPIO_Init() function
* Recommended configuration is Push-Pull, Pull-up, Open-Drain. Recommended configuration is Push-Pull, Pull-up, Open-Drain.
* Add an external pull up if necessary (typically 4.7 KOhm). Add an external pull up if necessary (typically 4.7 KOhm).
*
* 4. Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged (#) Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged
* Address using the I2C_Init() function. Address using the I2C_Init() function.
*
* 5. Optionally you can enable/configure the following parameters without (#) Optionally you can enable/configure the following parameters without
* re-initialization (i.e there is no need to call again I2C_Init() function): re-initialization (i.e there is no need to call again I2C_Init() function):
* - Enable the acknowledge feature using I2C_AcknowledgeConfig() function (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function
* - Enable the dual addressing mode using I2C_DualAddressCmd() function (++) Enable the dual addressing mode using I2C_DualAddressCmd() function
* - Enable the general call using the I2C_GeneralCallCmd() function (++) Enable the general call using the I2C_GeneralCallCmd() function
* - Enable the clock stretching using I2C_StretchClockCmd() function (++) Enable the clock stretching using I2C_StretchClockCmd() function
* - Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig() (++) Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig()
* function. function.
* - Configure the NACK position for Master Receiver mode in case of (++) Configure the NACK position for Master Receiver mode in case of
* 2 bytes reception using the function I2C_NACKPositionConfig(). 2 bytes reception using the function I2C_NACKPositionConfig().
* - Enable the PEC Calculation using I2C_CalculatePEC() function (++) Enable the PEC Calculation using I2C_CalculatePEC() function
* - For SMBus Mode: (++) For SMBus Mode:
* - Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function (+++) Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function
* - Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function (+++) Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function
*
* 6. Enable the NVIC and the corresponding interrupt using the function (#) Enable the NVIC and the corresponding interrupt using the function
* I2C_ITConfig() if you need to use interrupt mode. I2C_ITConfig() if you need to use interrupt mode.
*
* 7. When using the DMA mode (#) When using the DMA mode
* - Configure the DMA using DMA_Init() function (++) Configure the DMA using DMA_Init() function
* - Active the needed channel Request using I2C_DMACmd() or (++) Active the needed channel Request using I2C_DMACmd() or
* I2C_DMALastTransferCmd() function. I2C_DMALastTransferCmd() function.
* @note When using DMA mode, I2C interrupts may be used at the same time to -@@- When using DMA mode, I2C interrupts may be used at the same time to
* control the communication flow (Start/Stop/Ack... events and errors). control the communication flow (Start/Stop/Ack... events and errors).
*
* 8. Enable the I2C using the I2C_Cmd() function. (#) Enable the I2C using the I2C_Cmd() function.
*
* 9. Enable the DMA using the DMA_Cmd() function when using DMA mode in the (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the
* transfers. transfers.
*
* @endverbatim @endverbatim
*
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -117,7 +122,7 @@
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Initialization and Configuration functions ##### Initialization and Configuration functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -322,6 +327,68 @@ void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
} }
} }
/**
* @brief Enables or disables the Analog filter of I2C peripheral.
*
* @note This function can be used only for STM32F42xxx/STM3243xxx, STM32F401xx and STM32F411xE devices.
*
* @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
* @param NewState: new state of the Analog filter.
* This parameter can be: ENABLE or DISABLE.
* @note This function should be called before initializing and enabling
the I2C Peripheral.
* @retval None
*/
void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the analog filter */
I2Cx->FLTR &= (uint16_t)~((uint16_t)I2C_FLTR_ANOFF);
}
else
{
/* Disable the analog filter */
I2Cx->FLTR |= I2C_FLTR_ANOFF;
}
}
/**
* @brief Configures the Digital noise filter of I2C peripheral.
*
* @note This function can be used only for STM32F42xxx/STM3243xxx, STM32F401xx and STM32F411xE devices.
*
* @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
* @param I2C_DigitalFilter: Coefficient of digital noise filter.
* This parameter can be a number between 0x00 and 0x0F.
* @note This function should be called before initializing and enabling
the I2C Peripheral.
* @retval None
*/
void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter)
{
uint16_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
assert_param(IS_I2C_DIGITAL_FILTER(I2C_DigitalFilter));
/* Get the old register value */
tmpreg = I2Cx->FLTR;
/* Reset I2Cx DNF bit [3:0] */
tmpreg &= (uint16_t)~((uint16_t)I2C_FLTR_DNF);
/* Set I2Cx DNF coefficient */
tmpreg |= (uint16_t)((uint16_t)I2C_DigitalFilter & I2C_FLTR_DNF);
/* Store the new register value */
I2Cx->FLTR = tmpreg;
}
/** /**
* @brief Generates I2Cx communication START condition. * @brief Generates I2Cx communication START condition.
* @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
@@ -673,7 +740,7 @@ void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Data transfers functions ##### Data transfers functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -716,7 +783,7 @@ uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
PEC management functions ##### PEC management functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -824,7 +891,7 @@ uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
DMA transfers management functions ##### DMA transfers management functions #####
=============================================================================== ===============================================================================
This section provides functions allowing to configure the I2C DMA channels This section provides functions allowing to configure the I2C DMA channels
requests. requests.
@@ -890,94 +957,94 @@ void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Interrupts, events and flags management functions ##### Interrupts, events and flags management functions #####
===============================================================================
This section provides functions allowing to configure the I2C Interrupts
sources and check or clear the flags or pending bits status.
The user should identify which mode will be used in his application to manage
the communication: Polling mode, Interrupt mode or DMA mode.
=============================================================================== ===============================================================================
I2C State Monitoring Functions [..]
=============================================================================== This section provides functions allowing to configure the I2C Interrupts
This I2C driver provides three different ways for I2C state monitoring sources and check or clear the flags or pending bits status.
depending on the application requirements and constraints: The user should identify which mode will be used in his application to manage
the communication: Polling mode, Interrupt mode or DMA mode.
##### I2C State Monitoring Functions #####
===============================================================================
[..]
This I2C driver provides three different ways for I2C state monitoring
depending on the application requirements and constraints:
1. Basic state monitoring (Using I2C_CheckEvent() function) (#) Basic state monitoring (Using I2C_CheckEvent() function)
-----------------------------------------------------------
It compares the status registers (SR1 and SR2) content to a given event It compares the status registers (SR1 and SR2) content to a given event
(can be the combination of one or more flags). (can be the combination of one or more flags).
It returns SUCCESS if the current status includes the given flags It returns SUCCESS if the current status includes the given flags
and returns ERROR if one or more flags are missing in the current status. and returns ERROR if one or more flags are missing in the current status.
- When to use (++) When to use
- This function is suitable for most applications as well as for startup (+++) This function is suitable for most applications as well as for startup
activity since the events are fully described in the product reference activity since the events are fully described in the product reference
manual (RM0090). manual (RM0090).
- It is also suitable for users who need to define their own events. (+++) It is also suitable for users who need to define their own events.
- Limitations (++) Limitations
- If an error occurs (ie. error flags are set besides to the monitored If an error occurs (ie. error flags are set besides to the monitored
flags), the I2C_CheckEvent() function may return SUCCESS despite flags), the I2C_CheckEvent() function may return SUCCESS despite
the communication hold or corrupted real state. the communication hold or corrupted real state.
In this case, it is advised to use error interrupts to monitor In this case, it is advised to use error interrupts to monitor
the error events and handle them in the interrupt IRQ handler. the error events and handle them in the interrupt IRQ handler.
@note -@@- For error management, it is advised to use the following functions:
For error management, it is advised to use the following functions: (+@@) I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
- I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). (+@@) I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
- I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. Where x is the peripheral instance (I2C1, I2C2 ...)
Where x is the peripheral instance (I2C1, I2C2 ...) (+@@) I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
- I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the I2Cx_ER_IRQHandler() function in order to determine which error occurred.
I2Cx_ER_IRQHandler() function in order to determine which error occurred. (+@@) I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
- I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() and/or I2C_GenerateStop() in order to clear the error flag and source
and/or I2C_GenerateStop() in order to clear the error flag and source and return to correct communication status.
and return to correct communication status.
2. Advanced state monitoring (Using the function I2C_GetLastEvent()) (#) Advanced state monitoring (Using the function I2C_GetLastEvent())
--------------------------------------------------------------------
Using the function I2C_GetLastEvent() which returns the image of both status Using the function I2C_GetLastEvent() which returns the image of both status
registers in a single word (uint32_t) (Status Register 2 value is shifted left registers in a single word (uint32_t) (Status Register 2 value is shifted left
by 16 bits and concatenated to Status Register 1). by 16 bits and concatenated to Status Register 1).
- When to use (++) When to use
- This function is suitable for the same applications above but it (+++) This function is suitable for the same applications above but it
allows to overcome the mentioned limitation of I2C_GetFlagStatus() allows to overcome the mentioned limitation of I2C_GetFlagStatus()
function. function.
- The returned value could be compared to events already defined in (+++) The returned value could be compared to events already defined in
the library (stm32f4xx_i2c.h) or to custom values defined by user. the library (stm32f4xx_i2c.h) or to custom values defined by user.
This function is suitable when multiple flags are monitored at the This function is suitable when multiple flags are monitored at the
same time. same time.
- At the opposite of I2C_CheckEvent() function, this function allows (+++) At the opposite of I2C_CheckEvent() function, this function allows
user to choose when an event is accepted (when all events flags are user to choose when an event is accepted (when all events flags are
set and no other flags are set or just when the needed flags are set set and no other flags are set or just when the needed flags are set
like I2C_CheckEvent() function. like I2C_CheckEvent() function.
- Limitations (++) Limitations
- User may need to define his own events. (+++) User may need to define his own events.
- Same remark concerning the error management is applicable for this (+++) Same remark concerning the error management is applicable for this
function if user decides to check only regular communication flags function if user decides to check only regular communication flags
(and ignores error flags). (and ignores error flags).
3. Flag-based state monitoring (Using the function I2C_GetFlagStatus()) (#) Flag-based state monitoring (Using the function I2C_GetFlagStatus())
-----------------------------------------------------------------------
Using the function I2C_GetFlagStatus() which simply returns the status of Using the function I2C_GetFlagStatus() which simply returns the status of
one single flag (ie. I2C_FLAG_RXNE ...). one single flag (ie. I2C_FLAG_RXNE ...).
- When to use (++) When to use
- This function could be used for specific applications or in debug (+++) This function could be used for specific applications or in debug
phase. phase.
- It is suitable when only one flag checking is needed (most I2C (+++) It is suitable when only one flag checking is needed (most I2C
events are monitored through multiple flags). events are monitored through multiple flags).
- Limitations: (++) Limitations:
- When calling this function, the Status register is accessed. (+++) When calling this function, the Status register is accessed.
Some flags are cleared when the status register is accessed. Some flags are cleared when the status register is accessed.
So checking the status of one Flag, may clear other ones. So checking the status of one Flag, may clear other ones.
- Function may need to be called twice or more in order to monitor (+++) Function may need to be called twice or more in order to monitor
one single event. one single event.
For detailed description of Events, please refer to section I2C_Events in For detailed description of Events, please refer to section I2C_Events in
@@ -1392,4 +1459,4 @@ void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

143
example/libs/StmCoreNPheriph/src/stm32f4xx_iwdg.c
View File

@@ -2,79 +2,82 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_iwdg.c * @file stm32f4xx_iwdg.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides firmware functions to manage the following * @brief This file provides firmware functions to manage the following
* functionalities of the Independent watchdog (IWDG) peripheral: * functionalities of the Independent watchdog (IWDG) peripheral:
* - Prescaler and Counter configuration * + Prescaler and Counter configuration
* - IWDG activation * + IWDG activation
* - Flag management * + Flag management
* *
* @verbatim @verbatim
* ===============================================================================
* =================================================================== ##### IWDG features #####
* IWDG features ===============================================================================
* =================================================================== [..]
* The IWDG can be started by either software or hardware (configurable
* The IWDG can be started by either software or hardware (configurable through option byte).
* through option byte).
* The IWDG is clocked by its own dedicated low-speed clock (LSI) and
* The IWDG is clocked by its own dedicated low-speed clock (LSI) and thus stays active even if the main clock fails.
* thus stays active even if the main clock fails. Once the IWDG is started, the LSI is forced ON and cannot be disabled
* Once the IWDG is started, the LSI is forced ON and cannot be disabled (LSI cannot be disabled too), and the counter starts counting down from
* (LSI cannot be disabled too), and the counter starts counting down from the reset value of 0xFFF. When it reaches the end of count value (0x000)
* the reset value of 0xFFF. When it reaches the end of count value (0x000) a system reset is generated.
* a system reset is generated. The IWDG counter should be reloaded at regular intervals to prevent
* The IWDG counter should be reloaded at regular intervals to prevent an MCU reset.
* an MCU reset.
* The IWDG is implemented in the VDD voltage domain that is still functional
* The IWDG is implemented in the VDD voltage domain that is still functional in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
* in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
* IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
* IWDGRST flag in RCC_CSR register can be used to inform when a IWDG reset occurs.
* reset occurs.
* Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
* Min-max timeout value @32KHz (LSI): ~125us / ~32.7s The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx
* The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx devices provide the capability to measure the LSI frequency (LSI clock
* devices provide the capability to measure the LSI frequency (LSI clock connected internally to TIM5 CH4 input capture). The measured value
* connected internally to TIM5 CH4 input capture). The measured value can be used to have an IWDG timeout with an acceptable accuracy.
* can be used to have an IWDG timeout with an acceptable accuracy. For more information, please refer to the STM32F4xx Reference manual
* For more information, please refer to the STM32F4xx Reference manual
* ##### How to use this driver #####
* ===============================================================================
* =================================================================== [..]
* How to use this driver (#) Enable write access to IWDG_PR and IWDG_RLR registers using
* =================================================================== IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function
* 1. Enable write access to IWDG_PR and IWDG_RLR registers using
* IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function (#) Configure the IWDG prescaler using IWDG_SetPrescaler() function
*
* 2. Configure the IWDG prescaler using IWDG_SetPrescaler() function (#) Configure the IWDG counter value using IWDG_SetReload() function.
* This value will be loaded in the IWDG counter each time the counter
* 3. Configure the IWDG counter value using IWDG_SetReload() function. is reloaded, then the IWDG will start counting down from this value.
* This value will be loaded in the IWDG counter each time the counter
* is reloaded, then the IWDG will start counting down from this value. (#) Start the IWDG using IWDG_Enable() function, when the IWDG is used
* in software mode (no need to enable the LSI, it will be enabled
* 4. Start the IWDG using IWDG_Enable() function, when the IWDG is used by hardware)
* in software mode (no need to enable the LSI, it will be enabled
* by hardware) (#) Then the application program must reload the IWDG counter at regular
* intervals during normal operation to prevent an MCU reset, using
* 5. Then the application program must reload the IWDG counter at regular IWDG_ReloadCounter() function.
* intervals during normal operation to prevent an MCU reset, using
* IWDG_ReloadCounter() function. @endverbatim
*
* @endverbatim
*
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -111,7 +114,7 @@
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Prescaler and Counter configuration functions ##### Prescaler and Counter configuration functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -186,7 +189,7 @@ void IWDG_ReloadCounter(void)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
IWDG activation function ##### IWDG activation function #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -212,7 +215,7 @@ void IWDG_Enable(void)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Flag management function ##### Flag management function #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -260,4 +263,4 @@ FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

1110
example/libs/StmCoreNPheriph/src/stm32f4xx_ltdc.c Normal file
View File

File diff suppressed because it is too large Load Diff

657
example/libs/StmCoreNPheriph/src/stm32f4xx_pwr.c
View File

@@ -2,29 +2,35 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_pwr.c * @file stm32f4xx_pwr.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides firmware functions to manage the following * @brief This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral: * functionalities of the Power Controller (PWR) peripheral:
* - Backup Domain Access * + Backup Domain Access
* - PVD configuration * + PVD configuration
* - WakeUp pin configuration * + WakeUp pin configuration
* - Main and Backup Regulators configuration * + Main and Backup Regulators configuration
* - FLASH Power Down configuration * + FLASH Power Down configuration
* - Low Power modes configuration * + Low Power modes configuration
* - Flags management * + Flags management
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -65,6 +71,21 @@
#define PMODE_BitNumber 0x0E #define PMODE_BitNumber 0x0E
#define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4)) #define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
/* Alias word address of ODEN bit */
#define ODEN_BitNumber 0x10
#define CR_ODEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODEN_BitNumber * 4))
/* Alias word address of ODSWEN bit */
#define ODSWEN_BitNumber 0x11
#define CR_ODSWEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODSWEN_BitNumber * 4))
/* Alias word address of MRLVDS bit */
#define MRLVDS_BitNumber 0x0B
#define CR_MRLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MRLVDS_BitNumber * 4))
/* Alias word address of LPLVDS bit */
#define LPLVDS_BitNumber 0x0A
#define CR_LPLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LPLVDS_BitNumber * 4))
/* --- CSR Register ---*/ /* --- CSR Register ---*/
@@ -80,8 +101,9 @@
/* ------------------ PWR registers bit mask ------------------------ */ /* ------------------ PWR registers bit mask ------------------------ */
/* CR register bit mask */ /* CR register bit mask */
#define CR_DS_MASK ((uint32_t)0xFFFFFFFC) #define CR_DS_MASK ((uint32_t)0xFFFFF3FC)
#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) #define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
#define CR_VOS_MASK ((uint32_t)0xFFFF3FFF)
/* Private macro -------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
@@ -97,16 +119,16 @@
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Backup Domain Access function ##### Backup Domain Access function #####
=============================================================================== ===============================================================================
[..]
After reset, the backup domain (RTC registers, RTC backup data After reset, the backup domain (RTC registers, RTC backup data
registers and backup SRAM) is protected against possible unwanted registers and backup SRAM) is protected against possible unwanted
write accesses. write accesses.
To enable access to the RTC Domain and RTC registers, proceed as follows: To enable access to the RTC Domain and RTC registers, proceed as follows:
- Enable the Power Controller (PWR) APB1 interface clock using the (+) Enable the Power Controller (PWR) APB1 interface clock using the
RCC_APB1PeriphClockCmd() function. RCC_APB1PeriphClockCmd() function.
- Enable access to RTC domain using the PWR_BackupAccessCmd() function. (+) Enable access to RTC domain using the PWR_BackupAccessCmd() function.
@endverbatim @endverbatim
* @{ * @{
@@ -149,15 +171,15 @@ void PWR_BackupAccessCmd(FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
PVD configuration functions ##### PVD configuration functions #####
=============================================================================== ===============================================================================
[..]
- The PVD is used to monitor the VDD power supply by comparing it to a threshold (+) The PVD is used to monitor the VDD power supply by comparing it to a
selected by the PVD Level (PLS[2:0] bits in the PWR_CR). threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
- A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
PVD threshold. This event is internally connected to the EXTI line16 than the PVD threshold. This event is internally connected to the EXTI
and can generate an interrupt if enabled through the EXTI registers. line16 and can generate an interrupt if enabled through the EXTI registers.
- The PVD is stopped in Standby mode. (+) The PVD is stopped in Standby mode.
@endverbatim @endverbatim
* @{ * @{
@@ -167,15 +189,17 @@ void PWR_BackupAccessCmd(FunctionalState NewState)
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
* @param PWR_PVDLevel: specifies the PVD detection level * @param PWR_PVDLevel: specifies the PVD detection level
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg PWR_PVDLevel_0: PVD detection level set to 2.0V * @arg PWR_PVDLevel_0
* @arg PWR_PVDLevel_1: PVD detection level set to 2.2V * @arg PWR_PVDLevel_1
* @arg PWR_PVDLevel_2: PVD detection level set to 2.3V * @arg PWR_PVDLevel_2
* @arg PWR_PVDLevel_3: PVD detection level set to 2.5V * @arg PWR_PVDLevel_3
* @arg PWR_PVDLevel_4: PVD detection level set to 2.7V * @arg PWR_PVDLevel_4
* @arg PWR_PVDLevel_5: PVD detection level set to 2.8V * @arg PWR_PVDLevel_5
* @arg PWR_PVDLevel_6: PVD detection level set to 2.9V * @arg PWR_PVDLevel_6
* @arg PWR_PVDLevel_7: PVD detection level set to 3.0V * @arg PWR_PVDLevel_7
* @note Refer to the electrical characteristics of you device datasheet for more details. * @note Refer to the electrical characteristics of your device datasheet for
* more details about the voltage threshold corresponding to each
* detection level.
* @retval None * @retval None
*/ */
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
@@ -220,12 +244,12 @@ void PWR_PVDCmd(FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
WakeUp pin configuration functions ##### WakeUp pin configuration functions #####
=============================================================================== ===============================================================================
[..]
- WakeUp pin is used to wakeup the system from Standby mode. This pin is (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
forced in input pull down configuration and is active on rising edges. forced in input pull down configuration and is active on rising edges.
- There is only one WakeUp pin: WakeUp Pin 1 on PA.00. (+) There is only one WakeUp pin: WakeUp Pin 1 on PA.00.
@endverbatim @endverbatim
* @{ * @{
@@ -254,37 +278,76 @@ void PWR_WakeUpPinCmd(FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Main and Backup Regulators configuration functions ##### Main and Backup Regulators configuration functions #####
=============================================================================== ===============================================================================
[..]
(+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
retained even in Standby or VBAT mode when the low power backup regulator
is enabled. It can be considered as an internal EEPROM when VBAT is
always present. You can use the PWR_BackupRegulatorCmd() function to
enable the low power backup regulator and use the PWR_GetFlagStatus
(PWR_FLAG_BRR) to check if it is ready or not.
- The backup domain includes 4 Kbytes of backup SRAM accessible only from the (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is retained the backup SRAM is powered from VDD which replaces the VBAT power supply to
even in Standby or VBAT mode when the low power backup regulator is enabled. save battery life.
It can be considered as an internal EEPROM when VBAT is always present.
You can use the PWR_BackupRegulatorCmd() function to enable the low power
backup regulator and use the PWR_GetFlagStatus(PWR_FLAG_BRR) to check if it is
ready or not.
- When the backup domain is supplied by VDD (analog switch connected to VDD) (+) The backup SRAM is not mass erased by an tamper event. It is read
the backup SRAM is powered from VDD which replaces the VBAT power supply to protected to prevent confidential data, such as cryptographic private
save battery life. key, from being accessed. The backup SRAM can be erased only through
the Flash interface when a protection level change from level 1 to
level 0 is requested.
-@- Refer to the description of Read protection (RDP) in the reference manual.
- The backup SRAM is not mass erased by an tamper event. It is read protected (+) The main internal regulator can be configured to have a tradeoff between
to prevent confidential data, such as cryptographic private key, from being performance and power consumption when the device does not operate at
accessed. The backup SRAM can be erased only through the Flash interface when the maximum frequency.
a protection level change from level 1 to level 0 is requested. (+) For STM32F405xx/407xx and STM32F415xx/417xx Devices, the regulator can be
Refer to the description of Read protection (RDP) in the Flash programming manual. configured on the fly through PWR_MainRegulatorModeConfig() function which
configure VOS bit in PWR_CR register:
- The main internal regulator can be configured to have a tradeoff between performance (++) When this bit is set (Regulator voltage output Scale 1 mode selected)
and power consumption when the device does not operate at the maximum frequency. the System frequency can go up to 168 MHz.
This is done through PWR_MainRegulatorModeConfig() function which configure VOS bit (++) When this bit is reset (Regulator voltage output Scale 2 mode selected)
in PWR_CR register: the System frequency can go up to 144 MHz.
- When this bit is set (Regulator voltage output Scale 1 mode selected) the System
frequency can go up to 168 MHz. (+) For STM32F42xxx/43xxx Devices, the regulator can be configured through
- When this bit is reset (Regulator voltage output Scale 2 mode selected) the System PWR_MainRegulatorModeConfig() function which configure VOS[1:0] bits in
frequency can go up to 144 MHz. PWR_CR register:
Refer to the datasheets for more details. which configure VOS[1:0] bits in PWR_CR register:
(++) When VOS[1:0] = 11 (Regulator voltage output Scale 1 mode selected)
the System frequency can go up to 168 MHz.
(++) When VOS[1:0] = 10 (Regulator voltage output Scale 2 mode selected)
the System frequency can go up to 144 MHz.
(++) When VOS[1:0] = 01 (Regulator voltage output Scale 3 mode selected)
the System frequency can go up to 120 MHz.
(+) For STM32F42xxx/43xxx Devices, the scale can be modified only when the PLL
is OFF and the HSI or HSE clock source is selected as system clock.
The new value programmed is active only when the PLL is ON.
When the PLL is OFF, the voltage scale 3 is automatically selected.
Refer to the datasheets for more details.
(+) For STM32F42xxx/43xxx Devices, in Run mode: the main regulator has
2 operating modes available:
(++) Normal mode: The CPU and core logic operate at maximum frequency at a given
voltage scaling (scale 1, scale 2 or scale 3)
(++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
higher frequency than the normal mode for a given voltage scaling (scale 1,
scale 2 or scale 3). This mode is enabled through PWR_OverDriveCmd() function and
PWR_OverDriveSWCmd() function, to enter or exit from Over-drive mode please follow
the sequence described in Reference manual.
(+) For STM32F42xxx/43xxx Devices, in Stop mode: the main regulator or low power regulator
supplies a low power voltage to the 1.2V domain, thus preserving the content of registers
and internal SRAM. 2 operating modes are available:
(++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
available when the main regulator or the low power regulator is used in Scale 3 or
low voltage mode.
(++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
available when the main regulator or the low power regulator is in low voltage mode.
This mode is enabled through PWR_UnderDriveCmd() function.
@endverbatim @endverbatim
* @{ * @{
*/ */
@@ -313,20 +376,152 @@ void PWR_BackupRegulatorCmd(FunctionalState NewState)
* System frequency up to 168 MHz. * System frequency up to 168 MHz.
* @arg PWR_Regulator_Voltage_Scale2: Regulator voltage output Scale 2 mode, * @arg PWR_Regulator_Voltage_Scale2: Regulator voltage output Scale 2 mode,
* System frequency up to 144 MHz. * System frequency up to 144 MHz.
* @arg PWR_Regulator_Voltage_Scale3: Regulator voltage output Scale 3 mode,
* System frequency up to 120 MHz (only for STM32F42xxx/43xxx devices)
* @retval None * @retval None
*/ */
void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage) void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
{ {
uint32_t tmpreg = 0;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage)); assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage));
if (PWR_Regulator_Voltage == PWR_Regulator_Voltage_Scale2) tmpreg = PWR->CR;
/* Clear VOS[15:14] bits */
tmpreg &= CR_VOS_MASK;
/* Set VOS[15:14] bits according to PWR_Regulator_Voltage value */
tmpreg |= PWR_Regulator_Voltage;
/* Store the new value */
PWR->CR = tmpreg;
}
/**
* @brief Enables or disables the Over-Drive.
*
* @note This function can be used only for STM32F42xxx/STM3243xxx devices.
* This mode allows the CPU and the core logic to operate at a higher frequency
* than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
*
* @note It is recommended to enter or exit Over-drive mode when the application is not running
* critical tasks and when the system clock source is either HSI or HSE.
* During the Over-drive switch activation, no peripheral clocks should be enabled.
* The peripheral clocks must be enabled once the Over-drive mode is activated.
*
* @param NewState: new state of the Over Drive mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_OverDriveCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Set/Reset the ODEN bit to enable/disable the Over Drive mode */
*(__IO uint32_t *) CR_ODEN_BB = (uint32_t)NewState;
}
/**
* @brief Enables or disables the Over-Drive switching.
*
* @note This function can be used only for STM32F42xxx/STM3243xxx devices.
*
* @param NewState: new state of the Over Drive switching mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_OverDriveSWCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Set/Reset the ODSWEN bit to enable/disable the Over Drive switching mode */
*(__IO uint32_t *) CR_ODSWEN_BB = (uint32_t)NewState;
}
/**
* @brief Enables or disables the Under-Drive mode.
*
* @note This function can be used only for STM32F42xxx/STM3243xxx devices.
* @note This mode is enabled only with STOP low power mode.
* In this mode, the 1.2V domain is preserved in reduced leakage mode. This
* mode is only available when the main regulator or the low power regulator
* is in low voltage mode
*
* @note If the Under-drive mode was enabled, it is automatically disabled after
* exiting Stop mode.
* When the voltage regulator operates in Under-drive mode, an additional
* startup delay is induced when waking up from Stop mode.
*
* @param NewState: new state of the Under Drive mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_UnderDriveCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{ {
PWR->CR &= ~PWR_Regulator_Voltage_Scale1; /* Set the UDEN[1:0] bits to enable the Under Drive mode */
PWR->CR |= (uint32_t)PWR_CR_UDEN;
} }
else else
{ {
PWR->CR |= PWR_Regulator_Voltage_Scale1; /* Reset the UDEN[1:0] bits to disable the Under Drive mode */
PWR->CR &= (uint32_t)(~PWR_CR_UDEN);
}
}
/**
* @brief Enables or disables the Main Regulator low voltage mode.
*
* @note This mode is only available for STM32F401xx/STM32F411xx devices.
*
* @param NewState: new state of the Under Drive mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_MainRegulatorLowVoltageCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
*(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE;
}
else
{
*(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE;
}
}
/**
* @brief Enables or disables the Low Power Regulator low voltage mode.
*
* @note This mode is only available for STM32F401xx/STM32F411xx devices.
*
* @param NewState: new state of the Under Drive mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_LowRegulatorLowVoltageCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
*(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE;
}
else
{
*(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE;
} }
} }
@@ -339,14 +534,14 @@ void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
FLASH Power Down configuration functions ##### FLASH Power Down configuration functions #####
=============================================================================== ===============================================================================
[..]
- By setting the FPDS bit in the PWR_CR register by using the PWR_FlashPowerDownCmd() (+) By setting the FPDS bit in the PWR_CR register by using the
function, the Flash memory also enters power down mode when the device enters PWR_FlashPowerDownCmd() function, the Flash memory also enters power
Stop mode. When the Flash memory is in power down mode, an additional startup down mode when the device enters Stop mode. When the Flash memory
delay is incurred when waking up from Stop mode. is in power down mode, an additional startup delay is incurred when
waking up from Stop mode.
@endverbatim @endverbatim
* @{ * @{
*/ */
@@ -374,103 +569,109 @@ void PWR_FlashPowerDownCmd(FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Low Power modes configuration functions ##### Low Power modes configuration functions #####
=============================================================================== ===============================================================================
[..]
The devices feature 3 low-power modes: The devices feature 3 low-power modes:
- Sleep mode: Cortex-M4 core stopped, peripherals kept running. (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
- Stop mode: all clocks are stopped, regulator running, regulator in low power mode (+) Stop mode: all clocks are stopped, regulator running, regulator
- Standby mode: 1.2V domain powered off. in low power mode
(+) Standby mode: 1.2V domain powered off.
Sleep mode *** Sleep mode ***
=========== ==================
- Entry: [..]
- The Sleep mode is entered by using the __WFI() or __WFE() functions. (+) Entry:
- Exit: (++) The Sleep mode is entered by using the __WFI() or __WFE() functions.
- Any peripheral interrupt acknowledged by the nested vectored interrupt (+) Exit:
controller (NVIC) can wake up the device from Sleep mode. (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
controller (NVIC) can wake up the device from Sleep mode.
Stop mode *** Stop mode ***
========== =================
In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, [..]
and the HSE RC oscillators are disabled. Internal SRAM and register contents In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
are preserved. and the HSE RC oscillators are disabled. Internal SRAM and register contents
The voltage regulator can be configured either in normal or low-power mode. are preserved.
To minimize the consumption In Stop mode, FLASH can be powered off before The voltage regulator can be configured either in normal or low-power mode.
entering the Stop mode. It can be switched on again by software after exiting To minimize the consumption In Stop mode, FLASH can be powered off before
the Stop mode using the PWR_FlashPowerDownCmd() function. entering the Stop mode. It can be switched on again by software after exiting
the Stop mode using the PWR_FlashPowerDownCmd() function.
- Entry: (+) Entry:
- The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_MainRegulator_ON)
function with regulator in LowPower or with Regulator ON. function with:
- Exit: (+++) Main regulator ON.
- Any EXTI Line (Internal or External) configured in Interrupt/Event mode. (+++) Low Power regulator ON.
(+) Exit:
(++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
Standby mode *** Standby mode ***
============ ====================
The Standby mode allows to achieve the lowest power consumption. It is based [..]
on the Cortex-M4 deepsleep mode, with the voltage regulator disabled. The Standby mode allows to achieve the lowest power consumption. It is based
The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and on the Cortex-M4 deepsleep mode, with the voltage regulator disabled.
the HSE oscillator are also switched off. SRAM and register contents are lost The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
except for the RTC registers, RTC backup registers, backup SRAM and Standby the HSE oscillator are also switched off. SRAM and register contents are lost
circuitry. except for the RTC registers, RTC backup registers, backup SRAM and Standby
circuitry.
The voltage regulator is OFF. The voltage regulator is OFF.
- Entry: (+) Entry:
- The Standby mode is entered using the PWR_EnterSTANDBYMode() function. (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
- Exit: (+) Exit:
- WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
tamper event, time-stamp event, external reset in NRST pin, IWDG reset. tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
Auto-wakeup (AWU) from low-power mode *** Auto-wakeup (AWU) from low-power mode ***
===================================== =============================================
The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC [..]
Wakeup event, a tamper event, a time-stamp event, or a comparator event, The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
without depending on an external interrupt (Auto-wakeup mode). Wakeup event, a tamper event, a time-stamp event, or a comparator event,
without depending on an external interrupt (Auto-wakeup mode).
- RTC auto-wakeup (AWU) from the Stop mode (#) RTC auto-wakeup (AWU) from the Stop mode
----------------------------------------
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
- To wake up from the Stop mode with an RTC alarm event, it is necessary to: (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
- Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt or Event modes) using the EXTI_Init() function.
or Event modes) using the EXTI_Init() function. (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
- Enable the RTC Alarm Interrupt using the RTC_ITConfig() function (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
- Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() and RTC_AlarmCmd() functions.
and RTC_AlarmCmd() functions. (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
- To wake up from the Stop mode with an RTC Tamper or time stamp event, it is necessary to:
is necessary to: (+++) Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt
- Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt or Event modes) using the EXTI_Init() function.
or Event modes) using the EXTI_Init() function. (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
- Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() function
function (+++) Configure the RTC to detect the tamper or time stamp event using the
- Configure the RTC to detect the tamper or time stamp event using the RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.
functions. (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
- To wake up from the Stop mode with an RTC WakeUp event, it is necessary to: (+++) Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt
- Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt or Event modes) using the EXTI_Init() function.
or Event modes) using the EXTI_Init() function. (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
- Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
- Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
- RTC auto-wakeup (AWU) from the Standby mode (#) RTC auto-wakeup (AWU) from the Standby mode
-------------------------------------------
- To wake up from the Standby mode with an RTC alarm event, it is necessary to: (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
- Enable the RTC Alarm Interrupt using the RTC_ITConfig() function (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
- Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
and RTC_AlarmCmd() functions. and RTC_AlarmCmd() functions.
- To wake up from the Standby mode with an RTC Tamper or time stamp event, it (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
is necessary to: is necessary to:
- Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
function function
- Configure the RTC to detect the tamper or time stamp event using the (+++) Configure the RTC to detect the tamper or time stamp event using the
RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
functions. functions.
- To wake up from the Standby mode with an RTC WakeUp event, it is necessary to: (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
- Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
- Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
@endverbatim @endverbatim
* @{ * @{
@@ -485,12 +686,12 @@ void PWR_FlashPowerDownCmd(FunctionalState NewState)
* @note When the voltage regulator operates in low power mode, an additional * @note When the voltage regulator operates in low power mode, an additional
* startup delay is incurred when waking up from Stop mode. * startup delay is incurred when waking up from Stop mode.
* By keeping the internal regulator ON during Stop mode, the consumption * By keeping the internal regulator ON during Stop mode, the consumption
* is higher although the startup time is reduced. * is higher although the startup time is reduced.
* *
* @param PWR_Regulator: specifies the regulator state in STOP mode. * @param PWR_Regulator: specifies the regulator state in STOP mode.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg PWR_Regulator_ON: STOP mode with regulator ON * @arg PWR_MainRegulator_ON: STOP mode with regulator ON
* @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode * @arg PWR_LowPowerRegulator_ON: STOP mode with low power regulator ON
* @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
@@ -507,10 +708,74 @@ void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
/* Select the regulator state in STOP mode ---------------------------------*/ /* Select the regulator state in STOP mode ---------------------------------*/
tmpreg = PWR->CR; tmpreg = PWR->CR;
/* Clear PDDS and LPDSR bits */ /* Clear PDDS and LPDS bits */
tmpreg &= CR_DS_MASK; tmpreg &= CR_DS_MASK;
/* Set LPDSR bit according to PWR_Regulator value */ /* Set LPDS, MRLVDS and LPLVDS bits according to PWR_Regulator value */
tmpreg |= PWR_Regulator;
/* Store the new value */
PWR->CR = tmpreg;
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
/* Select STOP mode entry --------------------------------------------------*/
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__WFE();
}
/* Reset SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
}
/**
* @brief Enters in Under-Drive STOP mode.
*
* @note This mode is only available for STM32F42xxx/STM3243xxx devices.
*
* @note This mode can be selected only when the Under-Drive is already active
*
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
* @note When exiting Stop mode by issuing an interrupt or a wakeup event,
* the HSI RC oscillator is selected as system clock.
* @note When the voltage regulator operates in low power mode, an additional
* startup delay is incurred when waking up from Stop mode.
* By keeping the internal regulator ON during Stop mode, the consumption
* is higher although the startup time is reduced.
*
* @param PWR_Regulator: specifies the regulator state in STOP mode.
* This parameter can be one of the following values:
* @arg PWR_MainRegulator_UnderDrive_ON: Main Regulator in under-drive mode
* and Flash memory in power-down when the device is in Stop under-drive mode
* @arg PWR_LowPowerRegulator_UnderDrive_ON: Low Power Regulator in under-drive mode
* and Flash memory in power-down when the device is in Stop under-drive mode
* @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
* @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
* @retval None
*/
void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_PWR_REGULATOR_UNDERDRIVE(PWR_Regulator));
assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
/* Select the regulator state in STOP mode ---------------------------------*/
tmpreg = PWR->CR;
/* Clear PDDS and LPDS bits */
tmpreg &= CR_DS_MASK;
/* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
tmpreg |= PWR_Regulator; tmpreg |= PWR_Regulator;
/* Store the new value */ /* Store the new value */
@@ -541,22 +806,20 @@ void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
* - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
* Alarm out, or RTC clock calibration out. * Alarm out, or RTC clock calibration out.
* - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
* - WKUP pin 1 (PA0) if enabled. * - WKUP pin 1 (PA0) if enabled.
* @note The Wakeup flag (WUF) need to be cleared at application level before to call this function
* @param None * @param None
* @retval None * @retval None
*/ */
void PWR_EnterSTANDBYMode(void) void PWR_EnterSTANDBYMode(void)
{ {
/* Clear Wakeup flag */
PWR->CR |= PWR_CR_CWUF;
/* Select STANDBY mode */ /* Select STANDBY mode */
PWR->CR |= PWR_CR_PDDS; PWR->CR |= PWR_CR_PDDS;
/* Set SLEEPDEEP bit of Cortex System Control Register */ /* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
/* This option is used to ensure that store operations are completed */ /* This option is used to ensure that store operations are completed */
#if defined ( __CC_ARM ) #if defined ( __CC_ARM )
__force_stores(); __force_stores();
#endif #endif
@@ -573,7 +836,7 @@ void PWR_EnterSTANDBYMode(void)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Flags management functions ##### Flags management functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -599,7 +862,13 @@ void PWR_EnterSTANDBYMode(void)
* when the device wakes up from Standby mode or by a system reset * when the device wakes up from Standby mode or by a system reset
* or power reset. * or power reset.
* @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
* scaling output selection is ready. * scaling output selection is ready.
* @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
* is ready (STM32F42xxx/43xxx devices)
* @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
* switcching is ready (STM32F42xxx/43xxx devices)
* @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
* is enabled in Stop mode (STM32F42xxx/43xxx devices)
* @retval The new state of PWR_FLAG (SET or RESET). * @retval The new state of PWR_FLAG (SET or RESET).
*/ */
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
@@ -627,14 +896,28 @@ FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg PWR_FLAG_WU: Wake Up flag * @arg PWR_FLAG_WU: Wake Up flag
* @arg PWR_FLAG_SB: StandBy flag * @arg PWR_FLAG_SB: StandBy flag
* @arg PWR_FLAG_UDRDY: Under-drive ready flag (STM32F42xxx/43xxx devices)
* @retval None * @retval None
*/ */
void PWR_ClearFlag(uint32_t PWR_FLAG) void PWR_ClearFlag(uint32_t PWR_FLAG)
{ {
/* Check the parameters */ /* Check the parameters */
assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
if (PWR_FLAG != PWR_FLAG_UDRDY)
{
PWR->CR |= PWR_FLAG << 2;
}
else
{
PWR->CSR |= PWR_FLAG_UDRDY;
}
#endif /* STM32F427_437xx || STM32F429_439xx */
#if defined (STM32F40_41xxx) || defined (STM32F401xx) || defined (STM32F411xE)
PWR->CR |= PWR_FLAG << 2; PWR->CR |= PWR_FLAG << 2;
#endif /* STM32F40_41xxx || STM32F401xx || STM32F411xE */
} }
/** /**
@@ -653,4 +936,4 @@ void PWR_ClearFlag(uint32_t PWR_FLAG)
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

767
example/libs/StmCoreNPheriph/src/stm32f4xx_rcc.c
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File diff suppressed because it is too large Load Diff

186
example/libs/StmCoreNPheriph/src/stm32f4xx_rng.c
View File

@@ -2,48 +2,53 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_rng.c * @file stm32f4xx_rng.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides firmware functions to manage the following * @brief This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral: * functionalities of the Random Number Generator (RNG) peripheral:
* - Initialization and Configuration * + Initialization and Configuration
* - Get 32 bit Random number * + Get 32 bit Random number
* - Interrupts and flags management * + Interrupts and flags management
* *
* @verbatim @verbatim
*
* =================================================================== ===================================================================
* How to use this driver ##### How to use this driver #####
* =================================================================== ===================================================================
* 1. Enable The RNG controller clock using [..]
* RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE) function. (#) Enable The RNG controller clock using
* RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE) function.
* 2. Activate the RNG peripheral using RNG_Cmd() function.
* (#) Activate the RNG peripheral using RNG_Cmd() function.
* 3. Wait until the 32 bit Random number Generator contains a valid
* random data (using polling/interrupt mode). For more details, (#) Wait until the 32 bit Random number Generator contains a valid random data
* refer to "Interrupts and flags management functions" module (using polling/interrupt mode). For more details, refer to "Interrupts and
* description. flags management functions" module description.
*
* 4. Get the 32 bit Random number using RNG_GetRandomNumber() function (#) Get the 32 bit Random number using RNG_GetRandomNumber() function
*
* 5. To get another 32 bit Random number, go to step 3. (#) To get another 32 bit Random number, go to step 3.
*
*
* @endverbatim
* @endverbatim
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -76,18 +81,18 @@
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Initialization and Configuration functions ##### Initialization and Configuration functions #####
=============================================================================== ===============================================================================
This section provides functions allowing to [..] This section provides functions allowing to
- Initialize the RNG peripheral (+) Initialize the RNG peripheral
- Enable or disable the RNG peripheral (+) Enable or disable the RNG peripheral
@endverbatim @endverbatim
* @{ * @{
*/ */
/** /**
* @brief Deinitializes the RNG peripheral registers to their default reset values. * @brief De-initializes the RNG peripheral registers to their default reset values.
* @param None * @param None
* @retval None * @retval None
*/ */
@@ -132,12 +137,12 @@ void RNG_Cmd(FunctionalState NewState)
@verbatim @verbatim
=============================================================================== ===============================================================================
Get 32 bit Random number function ##### Get 32 bit Random number function #####
=============================================================================== ===============================================================================
This section provides a function allowing to get the 32 bit Random number [..] This section provides a function allowing to get the 32 bit Random number
@note Before to call this function you have to wait till DRDY flag is set, (@) Before to call this function you have to wait till DRDY flag is set,
using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. using RNG_GetFlagStatus(RNG_FLAG_DRDY) function.
@endverbatim @endverbatim
* @{ * @{
@@ -184,69 +189,63 @@ uint32_t RNG_GetRandomNumber(void)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Interrupts and flags management functions ##### Interrupts and flags management functions #####
=============================================================================== ===============================================================================
This section provides functions allowing to configure the RNG Interrupts and [..] This section provides functions allowing to configure the RNG Interrupts and
to get the status and clear flags and Interrupts pending bits. to get the status and clear flags and Interrupts pending bits.
The RNG provides 3 Interrupts sources and 3 Flags: [..] The RNG provides 3 Interrupts sources and 3 Flags:
Flags : *** Flags : ***
---------- ===============
1. RNG_FLAG_DRDY : In the case of the RNG_DR register contains valid [..]
random data. it is cleared by reading the valid data (#) RNG_FLAG_DRDY : In the case of the RNG_DR register contains valid
(using RNG_GetRandomNumber() function). random data. it is cleared by reading the valid data(using
RNG_GetRandomNumber() function).
2. RNG_FLAG_CECS : In the case of a seed error detection. (#) RNG_FLAG_CECS : In the case of a seed error detection.
3. RNG_FLAG_SECS : In the case of a clock error detection. (#) RNG_FLAG_SECS : In the case of a clock error detection.
*** Interrupts ***
Interrupts : ==================
------------ [..] If enabled, an RNG interrupt is pending :
if enabled, an RNG interrupt is pending :
1. In the case of the RNG_DR register contains valid random data. (#) In the case of the RNG_DR register contains valid random data.
This interrupt source is cleared once the RNG_DR register has been read This interrupt source is cleared once the RNG_DR register has been read
(using RNG_GetRandomNumber() function) until a new valid value is (using RNG_GetRandomNumber() function) until a new valid value is
computed. computed; or
(#) In the case of a seed error : One of the following faulty sequences has
or been detected:
2. In the case of a seed error : One of the following faulty sequences has (++) More than 64 consecutive bits at the same value (0 or 1)
been detected: (++) More than 32 consecutive alternance of 0 and 1 (0101010101...01)
- More than 64 consecutive bits at the same value (0 or 1) This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_SEI)
- More than 32 consecutive alternance of 0 and 1 (0101010101...01) function; or
This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_SEI) (#) In the case of a clock error : the PLL48CLK (RNG peripheral clock source)
function. was not correctly detected (fPLL48CLK< fHCLK/16). This interrupt source is
cleared using RNG_ClearITPendingBit(RNG_IT_CEI) function.
or -@- note In this case, User have to check that the clock controller is
3. In the case of a clock error : the PLL48CLK (RNG peripheral clock source) correctly configured to provide the RNG clock.
was not correctly detected (fPLL48CLK< fHCLK/16).
This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_CEI)
function.
@note In this case, User have to check that the clock controller is
correctly configured to provide the RNG clock.
Managing the RNG controller events : *** Managing the RNG controller events : ***
------------------------------------ ============================================
The user should identify which mode will be used in his application to manage [..] The user should identify which mode will be used in his application to manage
the RNG controller events: Polling mode or Interrupt mode. the RNG controller events: Polling mode or Interrupt mode.
1. In the Polling Mode it is advised to use the following functions: (#) In the Polling Mode it is advised to use the following functions:
- RNG_GetFlagStatus() : to check if flags events occur. (++) RNG_GetFlagStatus() : to check if flags events occur.
- RNG_ClearFlag() : to clear the flags events. (++) RNG_ClearFlag() : to clear the flags events.
@note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag(). it is cleared only -@@- RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag(). it is cleared only
by reading the Random number data. by reading the Random number data.
2. In the Interrupt Mode it is advised to use the following functions: (#) In the Interrupt Mode it is advised to use the following functions:
- RNG_ITConfig() : to enable or disable the interrupt source. (++) RNG_ITConfig() : to enable or disable the interrupt source.
- RNG_GetITStatus() : to check if Interrupt occurs. (++) RNG_GetITStatus() : to check if Interrupt occurs.
- RNG_ClearITPendingBit() : to clear the Interrupt pending Bit (++) RNG_ClearITPendingBit() : to clear the Interrupt pending Bit
(corresponding Flag). (corresponding Flag).
@endverbatim @endverbatim
* @{ * @{
*/ */
@@ -390,10 +389,9 @@ void RNG_ClearITPendingBit(uint8_t RNG_IT)
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

755
example/libs/StmCoreNPheriph/src/stm32f4xx_rtc.c
View File

@@ -2,280 +2,287 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_rtc.c * @file stm32f4xx_rtc.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides firmware functions to manage the following * @brief This file provides firmware functions to manage the following
* functionalities of the Real-Time Clock (RTC) peripheral: * functionalities of the Real-Time Clock (RTC) peripheral:
* - Initialization * + Initialization
* - Calendar (Time and Date) configuration * + Calendar (Time and Date) configuration
* - Alarms (Alarm A and Alarm B) configuration * + Alarms (Alarm A and Alarm B) configuration
* - WakeUp Timer configuration * + WakeUp Timer configuration
* - Daylight Saving configuration * + Daylight Saving configuration
* - Output pin Configuration * + Output pin Configuration
* - Coarse digital Calibration configuration * + Coarse digital Calibration configuration
* - Smooth digital Calibration configuration * + Smooth digital Calibration configuration
* - TimeStamp configuration * + TimeStamp configuration
* - Tampers configuration * + Tampers configuration
* - Backup Data Registers configuration * + Backup Data Registers configuration
* - Shift control synchronisation * + Shift control synchronisation
* - RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration * + RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration
* - Interrupts and flags management * + Interrupts and flags management
*
* @verbatim
*
* ===================================================================
* Backup Domain Operating Condition
* ===================================================================
* The real-time clock (RTC), the RTC backup registers, and the backup
* SRAM (BKP SRAM) can be powered from the VBAT voltage when the main
* VDD supply is powered off.
* To retain the content of the RTC backup registers, backup SRAM,
* and supply the RTC when VDD is turned off, VBAT pin can be connected
* to an optional standby voltage supplied by a battery or by another
* source.
*
* To allow the RTC to operate even when the main digital supply (VDD)
* is turned off, the VBAT pin powers the following blocks:
* 1 - The RTC
* 2 - The LSE oscillator
* 3 - The backup SRAM when the low power backup regulator is enabled
* 4 - PC13 to PC15 I/Os, plus PI8 I/O (when available)
*
* When the backup domain is supplied by VDD (analog switch connected
* to VDD), the following functions are available:
* 1 - PC14 and PC15 can be used as either GPIO or LSE pins
* 2 - PC13 can be used as a GPIO or as the RTC_AF1 pin
* 3 - PI8 can be used as a GPIO or as the RTC_AF2 pin
*
* When the backup domain is supplied by VBAT (analog switch connected
* to VBAT because VDD is not present), the following functions are available:
* 1 - PC14 and PC15 can be used as LSE pins only
* 2 - PC13 can be used as the RTC_AF1 pin
* 3 - PI8 can be used as the RTC_AF2 pin
*
* ===================================================================
* Backup Domain Reset
* ===================================================================
* The backup domain reset sets all RTC registers and the RCC_BDCR
* register to their reset values. The BKPSRAM is not affected by this
* reset. The only way of resetting the BKPSRAM is through the Flash
* interface by requesting a protection level change from 1 to 0.
* A backup domain reset is generated when one of the following events
* occurs:
* 1 - Software reset, triggered by setting the BDRST bit in the
* RCC Backup domain control register (RCC_BDCR). You can use the
* RCC_BackupResetCmd().
* 2 - VDD or VBAT power on, if both supplies have previously been
* powered off.
*
* ===================================================================
* Backup Domain Access
* ===================================================================
* After reset, the backup domain (RTC registers, RTC backup data
* registers and backup SRAM) is protected against possible unwanted
* write accesses.
* To enable access to the RTC Domain and RTC registers, proceed as follows:
* - Enable the Power Controller (PWR) APB1 interface clock using the
* RCC_APB1PeriphClockCmd() function.
* - Enable access to RTC domain using the PWR_BackupAccessCmd() function.
* - Select the RTC clock source using the RCC_RTCCLKConfig() function.
* - Enable RTC Clock using the RCC_RTCCLKCmd() function.
*
* ===================================================================
* RTC Driver: how to use it
* ===================================================================
* - Enable the RTC domain access (see description in the section above)
* - Configure the RTC Prescaler (Asynchronous and Synchronous) and
* RTC hour format using the RTC_Init() function.
*
* Time and Date configuration
* ===========================
* - To configure the RTC Calendar (Time and Date) use the RTC_SetTime()
* and RTC_SetDate() functions.
* - To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate()
* functions.
* - Use the RTC_DayLightSavingConfig() function to add or sub one
* hour to the RTC Calendar.
*
* Alarm configuration
* ===================
* - To configure the RTC Alarm use the RTC_SetAlarm() function.
* - Enable the selected RTC Alarm using the RTC_AlarmCmd() function
* - To read the RTC Alarm, use the RTC_GetAlarm() function.
* - To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function.
*
* RTC Wakeup configuration
* ========================
* - Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig()
* function.
* - Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter()
* function
* - Enable the RTC WakeUp using the RTC_WakeUpCmd() function
* - To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter()
* function.
*
* Outputs configuration
* =====================
* The RTC has 2 different outputs:
* - AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B
* and WaKeUp signals.
* To output the selected RTC signal on RTC_AF1 pin, use the
* RTC_OutputConfig() function.
* - AFO_CALIB: this output is 512Hz signal or 1Hz .
* To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd()
* function.
*
* Smooth digital Calibration configuration
* =================================
* - Configure the RTC Original Digital Calibration Value and the corresponding
* calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig()
* function.
*
* Coarse digital Calibration configuration
* =================================
* - Configure the RTC Coarse Calibration Value and the corresponding
* sign using the RTC_CoarseCalibConfig() function.
* - Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd()
* function
*
* TimeStamp configuration
* =======================
* - Configure the RTC_AF1 trigger and enables the RTC TimeStamp
* using the RTC_TimeStampCmd() function.
* - To read the RTC TimeStamp Time and Date register, use the
* RTC_GetTimeStamp() function.
* - To read the RTC TimeStamp SubSecond register, use the
* RTC_GetTimeStampSubSecond() function.
* - The TAMPER1 alternate function can be mapped either to RTC_AF1(PC13)
* or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in
* RTC_TAFCR register. You can use the RTC_TamperPinSelection()
* function to select the corresponding pin.
*
* Tamper configuration
* ====================
* - Enable the RTC Tamper using the RTC_TamperCmd() function.
* - Configure the Tamper filter count using RTC_TamperFilterConfig()
* function.
* - Configure the RTC Tamper trigger Edge or Level according to the Tamper
* filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() function.
* - Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig()
* function.
* - Configure the Tamper precharge or discharge duration using
* RTC_TamperPinsPrechargeDuration() function.
* - Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function.
* - Enable the Time stamp on Tamper detection event using
* RTC_TSOnTamperDetecCmd() function.
* - The TIMESTAMP alternate function can be mapped to either RTC_AF1
* or RTC_AF2 depending on the value of the TSINSEL bit in the
* RTC_TAFCR register. You can use the RTC_TimeStampPinSelection()
* function to select the corresponding pin.
*
* Backup Data Registers configuration
* ===================================
* - To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()
* function.
* - To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()
* function.
*
* ===================================================================
* RTC and low power modes
* ===================================================================
* The MCU can be woken up from a low power mode by an RTC alternate
* function.
* The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
* RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
* These RTC alternate functions can wake up the system from the Stop
* and Standby lowpower modes.
* The system can also wake up from low power modes without depending
* on an external interrupt (Auto-wakeup mode), by using the RTC alarm
* or the RTC wakeup events.
* The RTC provides a programmable time base for waking up from the
* Stop or Standby mode at regular intervals.
* Wakeup from STOP and Standby modes is possible only when the RTC
* clock source is LSE or LSI.
*
* ===================================================================
* Selection of RTC_AF1 alternate functions
* ===================================================================
* The RTC_AF1 pin (PC13) can be used for the following purposes:
* - AFO_ALARM output
* - AFO_CALIB output
* - AFI_TAMPER
* - AFI_TIMESTAMP
*
* +-------------------------------------------------------------------------------------------------------------+
* | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE |
* | configuration | ENABLED | ENABLED | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM |
* | and function | | | | | selection | selection |Configuration |
* |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
* | Alarm out | | | | | Don't | Don't | |
* | output OD | 1 |Don't care|Don't care | Don't care | care | care | 0 |
* |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
* | Alarm out | | | | | Don't | Don't | |
* | output PP | 1 |Don't care|Don't care | Don't care | care | care | 1 |
* |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
* | Calibration out | | | | | Don't | Don't | |
* | output PP | 0 | 1 |Don't care | Don't care | care | care | Don't care |
* |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
* | TAMPER input | | | | | | Don't | |
* | floating | 0 | 0 | 1 | 0 | 0 | care | Don't care |
* |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
* | TIMESTAMP and | | | | | | | |
* | TAMPER input | 0 | 0 | 1 | 1 | 0 | 0 | Don't care |
* | floating | | | | | | | |
* |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
* | TIMESTAMP input | | | | | Don't | | |
* | floating | 0 | 0 | 0 | 1 | care | 0 | Don't care |
* |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
* | Standard GPIO | 0 | 0 | 0 | 0 | Don't care | Don't care | Don't care |
* +-------------------------------------------------------------------------------------------------------------+
*
*
* ===================================================================
* Selection of RTC_AF2 alternate functions
* ===================================================================
* The RTC_AF2 pin (PI8) can be used for the following purposes:
* - AFI_TAMPER
* - AFI_TIMESTAMP
*
* +---------------------------------------------------------------------------------------+
* | Pin |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE |
* | configuration | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM |
* | and function | | | selection | selection |Configuration |
* |-----------------|-----------|--------------|------------|--------------|--------------|
* | TAMPER input | | | | Don't | |
* | floating | 1 | 0 | 1 | care | Don't care |
* |-----------------|-----------|--------------|------------|--------------|--------------|
* | TIMESTAMP and | | | | | |
* | TAMPER input | 1 | 1 | 1 | 1 | Don't care |
* | floating | | | | | |
* |-----------------|-----------|--------------|------------|--------------|--------------|
* | TIMESTAMP input | | | Don't | | |
* | floating | 0 | 1 | care | 1 | Don't care |
* |-----------------|-----------|--------------|------------|--------------|--------------|
* | Standard GPIO | 0 | 0 | Don't care | Don't care | Don't care |
* +---------------------------------------------------------------------------------------+
*
*
* @endverbatim
* *
@verbatim
===================================================================
##### Backup Domain Operating Condition #####
===================================================================
[..] The real-time clock (RTC), the RTC backup registers, and the backup
SRAM (BKP SRAM) can be powered from the VBAT voltage when the main
VDD supply is powered off.
To retain the content of the RTC backup registers, backup SRAM, and supply
the RTC when VDD is turned off, VBAT pin can be connected to an optional
standby voltage supplied by a battery or by another source.
[..] To allow the RTC to operate even when the main digital supply (VDD) is turned
off, the VBAT pin powers the following blocks:
(#) The RTC
(#) The LSE oscillator
(#) The backup SRAM when the low power backup regulator is enabled
(#) PC13 to PC15 I/Os, plus PI8 I/O (when available)
[..] When the backup domain is supplied by VDD (analog switch connected to VDD),
the following functions are available:
(#) PC14 and PC15 can be used as either GPIO or LSE pins
(#) PC13 can be used as a GPIO or as the RTC_AF1 pin
(#) PI8 can be used as a GPIO or as the RTC_AF2 pin
[..] When the backup domain is supplied by VBAT (analog switch connected to VBAT
because VDD is not present), the following functions are available:
(#) PC14 and PC15 can be used as LSE pins only
(#) PC13 can be used as the RTC_AF1 pin
(#) PI8 can be used as the RTC_AF2 pin
##### Backup Domain Reset #####
===================================================================
[..] The backup domain reset sets all RTC registers and the RCC_BDCR register
to their reset values. The BKPSRAM is not affected by this reset. The only
way of resetting the BKPSRAM is through the Flash interface by requesting
a protection level change from 1 to 0.
[..] A backup domain reset is generated when one of the following events occurs:
(#) Software reset, triggered by setting the BDRST bit in the
RCC Backup domain control register (RCC_BDCR). You can use the
RCC_BackupResetCmd().
(#) VDD or VBAT power on, if both supplies have previously been powered off.
##### Backup Domain Access #####
===================================================================
[..] After reset, the backup domain (RTC registers, RTC backup data
registers and backup SRAM) is protected against possible unwanted write
accesses.
[..] To enable access to the RTC Domain and RTC registers, proceed as follows:
(+) Enable the Power Controller (PWR) APB1 interface clock using the
RCC_APB1PeriphClockCmd() function.
(+) Enable access to RTC domain using the PWR_BackupAccessCmd() function.
(+) Select the RTC clock source using the RCC_RTCCLKConfig() function.
(+) Enable RTC Clock using the RCC_RTCCLKCmd() function.
##### How to use RTC Driver #####
===================================================================
[..]
(+) Enable the RTC domain access (see description in the section above)
(+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
format using the RTC_Init() function.
*** Time and Date configuration ***
===================================
[..]
(+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime()
and RTC_SetDate() functions.
(+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate() functions.
(+) Use the RTC_DayLightSavingConfig() function to add or sub one
hour to the RTC Calendar.
*** Alarm configuration ***
===========================
[..]
(+) To configure the RTC Alarm use the RTC_SetAlarm() function.
(+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function
(+) To read the RTC Alarm, use the RTC_GetAlarm() function.
(+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function.
*** RTC Wakeup configuration ***
================================
[..]
(+) Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig()
function.
(+) Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() function
(+) Enable the RTC WakeUp using the RTC_WakeUpCmd() function
(+) To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter()
function.
*** Outputs configuration ***
=============================
[..] The RTC has 2 different outputs:
(+) AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B
and WaKeUp signals. To output the selected RTC signal on RTC_AF1 pin, use the
RTC_OutputConfig() function.
(+) AFO_CALIB: this output is 512Hz signal or 1Hz. To output the RTC Clock on
RTC_AF1 pin, use the RTC_CalibOutputCmd() function.
*** Smooth digital Calibration configuration ***
================================================
[..]
(+) Configure the RTC Original Digital Calibration Value and the corresponding
calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig()
function.
*** Coarse digital Calibration configuration ***
================================================
[..]
(+) Configure the RTC Coarse Calibration Value and the corresponding
sign using the RTC_CoarseCalibConfig() function.
(+) Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd() function
*** TimeStamp configuration ***
===============================
[..]
(+) Configure the RTC_AF1 trigger and enables the RTC TimeStamp using the RTC
_TimeStampCmd() function.
(+) To read the RTC TimeStamp Time and Date register, use the RTC_GetTimeStamp()
function.
(+) To read the RTC TimeStamp SubSecond register, use the
RTC_GetTimeStampSubSecond() function.
(+) The TAMPER1 alternate function can be mapped either to RTC_AF1(PC13)
or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in
RTC_TAFCR register. You can use the RTC_TamperPinSelection() function to
select the corresponding pin.
*** Tamper configuration ***
============================
[..]
(+) Enable the RTC Tamper using the RTC_TamperCmd() function.
(+) Configure the Tamper filter count using RTC_TamperFilterConfig()
function.
(+) Configure the RTC Tamper trigger Edge or Level according to the Tamper
filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig()
function.
(+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig()
function.
(+) Configure the Tamper precharge or discharge duration using
RTC_TamperPinsPrechargeDuration() function.
(+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function.
(+) Enable the Time stamp on Tamper detection event using
TC_TSOnTamperDetecCmd() function.
(+) The TIMESTAMP alternate function can be mapped to either RTC_AF1
or RTC_AF2 depending on the value of the TSINSEL bit in the RTC_TAFCR
register. You can use the RTC_TimeStampPinSelection() function to select
the corresponding pin.
*** Backup Data Registers configuration ***
===========================================
[..]
(+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()
function.
(+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()
function.
##### RTC and low power modes #####
===================================================================
[..] The MCU can be woken up from a low power mode by an RTC alternate
function.
[..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
These RTC alternate functions can wake up the system from the Stop and
Standby lowpower modes.
[..] The system can also wake up from low power modes without depending
on an external interrupt (Auto-wakeup mode), by using the RTC alarm
or the RTC wakeup events.
[..] The RTC provides a programmable time base for waking up from the
Stop or Standby mode at regular intervals.
Wakeup from STOP and Standby modes is possible only when the RTC clock source
is LSE or LSI.
##### Selection of RTC_AF1 alternate functions #####
===================================================================
[..] The RTC_AF1 pin (PC13) can be used for the following purposes:
(+) AFO_ALARM output
(+) AFO_CALIB output
(+) AFI_TAMPER
(+) AFI_TIMESTAMP
[..]
+-------------------------------------------------------------------------------------------------------------+
| Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE |
| configuration | ENABLED | ENABLED | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM |
| and function | | | | | selection | selection |Configuration |
|-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
| Alarm out | | | | | Don't | Don't | |
| output OD | 1 |Don't care|Don't care | Don't care | care | care | 0 |
|-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
| Alarm out | | | | | Don't | Don't | |
| output PP | 1 |Don't care|Don't care | Don't care | care | care | 1 |
|-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
| Calibration out | | | | | Don't | Don't | |
| output PP | 0 | 1 |Don't care | Don't care | care | care | Don't care |
|-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
| TAMPER input | | | | | | Don't | |
| floating | 0 | 0 | 1 | 0 | 0 | care | Don't care |
|-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
| TIMESTAMP and | | | | | | | |
| TAMPER input | 0 | 0 | 1 | 1 | 0 | 0 | Don't care |
| floating | | | | | | | |
|-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
| TIMESTAMP input | | | | | Don't | | |
| floating | 0 | 0 | 0 | 1 | care | 0 | Don't care |
|-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
| Standard GPIO | 0 | 0 | 0 | 0 | Don't care | Don't care | Don't care |
+-------------------------------------------------------------------------------------------------------------+
##### Selection of RTC_AF2 alternate functions #####
===================================================================
[..] The RTC_AF2 pin (PI8) can be used for the following purposes:
(+) AFI_TAMPER
(+) AFI_TIMESTAMP
[..]
+---------------------------------------------------------------------------------------+
| Pin |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE |
| configuration | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM |
| and function | | | selection | selection |Configuration |
|-----------------|-----------|--------------|------------|--------------|--------------|
| TAMPER input | | | | Don't | |
| floating | 1 | 0 | 1 | care | Don't care |
|-----------------|-----------|--------------|------------|--------------|--------------|
| TIMESTAMP and | | | | | |
| TAMPER input | 1 | 1 | 1 | 1 | Don't care |
| floating | | | | | |
|-----------------|-----------|--------------|------------|--------------|--------------|
| TIMESTAMP input | | | Don't | | |
| floating | 0 | 1 | care | 1 | Don't care |
|-----------------|-----------|--------------|------------|--------------|--------------|
| Standard GPIO | 0 | 0 | Don't care | Don't care | Don't care |
+---------------------------------------------------------------------------------------+
@endverbatim
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_rtc.h" #include "stm32f4xx_rtc.h"
#include "stm32f4xx_rcc.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver /** @addtogroup STM32F4xx_StdPeriph_Driver
* @{ * @{
@@ -297,7 +304,8 @@
#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \ #define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \ RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \ RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F )) RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
RTC_FLAG_RECALPF | RTC_FLAG_SHPF))
#define INITMODE_TIMEOUT ((uint32_t) 0x00010000) #define INITMODE_TIMEOUT ((uint32_t) 0x00010000)
#define SYNCHRO_TIMEOUT ((uint32_t) 0x00020000) #define SYNCHRO_TIMEOUT ((uint32_t) 0x00020000)
@@ -321,35 +329,35 @@ static uint8_t RTC_Bcd2ToByte(uint8_t Value);
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Initialization and Configuration functions ##### Initialization and Configuration functions #####
=============================================================================== ===============================================================================
This section provide functions allowing to initialize and configure the RTC [..] This section provide functions allowing to initialize and configure the RTC
Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers
Write protection, enter and exit the RTC initialization mode, RTC registers Write protection, enter and exit the RTC initialization mode, RTC registers
synchronization check and reference clock detection enable. synchronization check and reference clock detection enable.
1. The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is
split into 2 programmable prescalers to minimize power consumption. split into 2 programmable prescalers to minimize power consumption.
- A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler. (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.
- When both prescalers are used, it is recommended to configure the asynchronous (++) When both prescalers are used, it is recommended to configure the
prescaler to a high value to minimize consumption. asynchronous prescaler to a high value to minimize consumption.
2. All RTC registers are Write protected. Writing to the RTC registers (#) All RTC registers are Write protected. Writing to the RTC registers
is enabled by writing a key into the Write Protection register, RTC_WPR. is enabled by writing a key into the Write Protection register, RTC_WPR.
3. To Configure the RTC Calendar, user application should enter initialization (#) To Configure the RTC Calendar, user application should enter initialization
mode. In this mode, the calendar counter is stopped and its value can be mode. In this mode, the calendar counter is stopped and its value can be
updated. When the initialization sequence is complete, the calendar restarts updated. When the initialization sequence is complete, the calendar restarts
counting after 4 RTCCLK cycles. counting after 4 RTCCLK cycles.
4. To read the calendar through the shadow registers after Calendar initialization, (#) To read the calendar through the shadow registers after Calendar initialization,
calendar update or after wakeup from low power modes the software must first calendar update or after wakeup from low power modes the software must first
clear the RSF flag. The software must then wait until it is set again before clear the RSF flag. The software must then wait until it is set again before
reading the calendar, which means that the calendar registers have been reading the calendar, which means that the calendar registers have been
correctly copied into the RTC_TR and RTC_DR shadow registers. correctly copied into the RTC_TR and RTC_DR shadow registers.
The RTC_WaitForSynchro() function implements the above software sequence The RTC_WaitForSynchro() function implements the above software sequence
(RSF clear and RSF check). (RSF clear and RSF check).
@endverbatim @endverbatim
* @{ * @{
@@ -407,6 +415,10 @@ ErrorStatus RTC_DeInit(void)
RTC->CALIBR = (uint32_t)0x00000000; RTC->CALIBR = (uint32_t)0x00000000;
RTC->ALRMAR = (uint32_t)0x00000000; RTC->ALRMAR = (uint32_t)0x00000000;
RTC->ALRMBR = (uint32_t)0x00000000; RTC->ALRMBR = (uint32_t)0x00000000;
RTC->SHIFTR = (uint32_t)0x00000000;
RTC->CALR = (uint32_t)0x00000000;
RTC->ALRMASSR = (uint32_t)0x00000000;
RTC->ALRMBSSR = (uint32_t)0x00000000;
/* Reset ISR register and exit initialization mode */ /* Reset ISR register and exit initialization mode */
RTC->ISR = (uint32_t)0x00000000; RTC->ISR = (uint32_t)0x00000000;
@@ -728,11 +740,11 @@ void RTC_BypassShadowCmd(FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Time and Date configuration functions ##### Time and Date configuration functions #####
=============================================================================== ===============================================================================
This section provide functions allowing to program and read the RTC Calendar [..] This section provide functions allowing to program and read the RTC Calendar
(Time and Date). (Time and Date).
@endverbatim @endverbatim
* @{ * @{
@@ -823,6 +835,9 @@ ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
/* Exit Initialization mode */ /* Exit Initialization mode */
RTC_ExitInitMode(); RTC_ExitInitMode();
/* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
{
if(RTC_WaitForSynchro() == ERROR) if(RTC_WaitForSynchro() == ERROR)
{ {
status = ERROR; status = ERROR;
@@ -831,7 +846,11 @@ ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
{ {
status = SUCCESS; status = SUCCESS;
} }
}
else
{
status = SUCCESS;
}
} }
/* Enable the write protection for RTC registers */ /* Enable the write protection for RTC registers */
RTC->WPR = 0xFF; RTC->WPR = 0xFF;
@@ -892,17 +911,17 @@ void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
} }
/** /**
* @brief Gets the RTC current Calendar Subseconds value. * @brief Gets the RTC current Calendar Sub seconds value.
* @note This function freeze the Time and Date registers after reading the * @note This function freeze the Time and Date registers after reading the
* SSR register. * SSR register.
* @param None * @param None
* @retval RTC current Calendar Subseconds value. * @retval RTC current Calendar Sub seconds value.
*/ */
uint32_t RTC_GetSubSecond(void) uint32_t RTC_GetSubSecond(void)
{ {
uint32_t tmpreg = 0; uint32_t tmpreg = 0;
/* Get subseconds values from the correspondent registers*/ /* Get sub seconds values from the correspondent registers*/
tmpreg = (uint32_t)(RTC->SSR); tmpreg = (uint32_t)(RTC->SSR);
/* Read DR register to unfroze calendar registers */ /* Read DR register to unfroze calendar registers */
@@ -984,6 +1003,9 @@ ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
/* Exit Initialization mode */ /* Exit Initialization mode */
RTC_ExitInitMode(); RTC_ExitInitMode();
/* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
{
if(RTC_WaitForSynchro() == ERROR) if(RTC_WaitForSynchro() == ERROR)
{ {
status = ERROR; status = ERROR;
@@ -992,6 +1014,11 @@ ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
{ {
status = SUCCESS; status = SUCCESS;
} }
}
else
{
status = SUCCESS;
}
} }
/* Enable the write protection for RTC registers */ /* Enable the write protection for RTC registers */
RTC->WPR = 0xFF; RTC->WPR = 0xFF;
@@ -1060,10 +1087,10 @@ void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Alarms (Alarm A and Alarm B) configuration functions ##### Alarms A and B configuration functions #####
=============================================================================== ===============================================================================
This section provide functions allowing to program and read the RTC Alarms. [..] This section provide functions allowing to program and read the RTC Alarms.
@endverbatim @endverbatim
* @{ * @{
@@ -1330,15 +1357,15 @@ ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState)
} }
/** /**
* @brief Configure the RTC AlarmA/B Subseconds value and mask.* * @brief Configure the RTC AlarmA/B Sub seconds value and mask.*
* @note This function is performed only when the Alarm is disabled. * @note This function is performed only when the Alarm is disabled.
* @param RTC_Alarm: specifies the alarm to be configured. * @param RTC_Alarm: specifies the alarm to be configured.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg RTC_Alarm_A: to select Alarm A * @arg RTC_Alarm_A: to select Alarm A
* @arg RTC_Alarm_B: to select Alarm B * @arg RTC_Alarm_B: to select Alarm B
* @param RTC_AlarmSubSecondValue: specifies the Subseconds value. * @param RTC_AlarmSubSecondValue: specifies the Sub seconds value.
* This parameter can be a value from 0 to 0x00007FFF. * This parameter can be a value from 0 to 0x00007FFF.
* @param RTC_AlarmSubSecondMask: specifies the Subseconds Mask. * @param RTC_AlarmSubSecondMask: specifies the Sub seconds Mask.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg RTC_AlarmSubSecondMask_All : All Alarm SS fields are masked. * @arg RTC_AlarmSubSecondMask_All : All Alarm SS fields are masked.
* There is no comparison on sub seconds for Alarm. * There is no comparison on sub seconds for Alarm.
@@ -1387,17 +1414,17 @@ void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondVal
RTC->WPR = 0xCA; RTC->WPR = 0xCA;
RTC->WPR = 0x53; RTC->WPR = 0x53;
/* Configure the Alarm A or Alarm B SubSecond registers */ /* Configure the Alarm A or Alarm B Sub Second registers */
tmpreg = (uint32_t) (uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask); tmpreg = (uint32_t) (uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask);
if (RTC_Alarm == RTC_Alarm_A) if (RTC_Alarm == RTC_Alarm_A)
{ {
/* Configure the AlarmA SubSecond register */ /* Configure the Alarm A Sub Second register */
RTC->ALRMASSR = tmpreg; RTC->ALRMASSR = tmpreg;
} }
else else
{ {
/* Configure the Alarm B SubSecond register */ /* Configure the Alarm B Sub Second register */
RTC->ALRMBSSR = tmpreg; RTC->ALRMBSSR = tmpreg;
} }
@@ -1407,13 +1434,13 @@ void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondVal
} }
/** /**
* @brief Gets the RTC Alarm Subseconds value. * @brief Gets the RTC Alarm Sub seconds value.
* @param RTC_Alarm: specifies the alarm to be read. * @param RTC_Alarm: specifies the alarm to be read.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg RTC_Alarm_A: to select Alarm A * @arg RTC_Alarm_A: to select Alarm A
* @arg RTC_Alarm_B: to select Alarm B * @arg RTC_Alarm_B: to select Alarm B
* @param None * @param None
* @retval RTC Alarm Subseconds value. * @retval RTC Alarm Sub seconds value.
*/ */
uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm) uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)
{ {
@@ -1441,10 +1468,10 @@ uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
WakeUp Timer configuration functions ##### WakeUp Timer configuration functions #####
=============================================================================== ===============================================================================
This section provide functions allowing to program and read the RTC WakeUp. [..] This section provide functions allowing to program and read the RTC WakeUp.
@endverbatim @endverbatim
* @{ * @{
@@ -1579,10 +1606,10 @@ ErrorStatus RTC_WakeUpCmd(FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Daylight Saving configuration functions ##### Daylight Saving configuration functions #####
=============================================================================== ===============================================================================
This section provide functions allowing to configure the RTC DayLight Saving. [..] This section provide functions allowing to configure the RTC DayLight Saving.
@endverbatim @endverbatim
* @{ * @{
@@ -1642,10 +1669,10 @@ uint32_t RTC_GetStoreOperation(void)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Output pin Configuration function ##### Output pin Configuration function #####
=============================================================================== ===============================================================================
This section provide functions allowing to configure the RTC Output source. [..] This section provide functions allowing to configure the RTC Output source.
@endverbatim @endverbatim
* @{ * @{
@@ -1696,7 +1723,7 @@ void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Digital Calibration configuration functions ##### Digital Calibration configuration functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -1849,7 +1876,7 @@ void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput)
RTC->WPR = 0xCA; RTC->WPR = 0xCA;
RTC->WPR = 0x53; RTC->WPR = 0x53;
/*clear flags before config*/ /*clear flags before configuration */
RTC->CR &= (uint32_t)~(RTC_CR_COSEL); RTC->CR &= (uint32_t)~(RTC_CR_COSEL);
/* Configure the RTC_CR register */ /* Configure the RTC_CR register */
@@ -1863,9 +1890,9 @@ void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput)
* @brief Configures the Smooth Calibration Settings. * @brief Configures the Smooth Calibration Settings.
* @param RTC_SmoothCalibPeriod : Select the Smooth Calibration Period. * @param RTC_SmoothCalibPeriod : Select the Smooth Calibration Period.
* This parameter can be can be one of the following values: * This parameter can be can be one of the following values:
* @arg RTC_SmoothCalibPeriod_32sec : The smooth calibration periode is 32s. * @arg RTC_SmoothCalibPeriod_32sec : The smooth calibration period is 32s.
* @arg RTC_SmoothCalibPeriod_16sec : The smooth calibration periode is 16s. * @arg RTC_SmoothCalibPeriod_16sec : The smooth calibration period is 16s.
* @arg RTC_SmoothCalibPeriod_8sec : The smooth calibartion periode is 8s. * @arg RTC_SmoothCalibPeriod_8sec : The smooth calibartion period is 8s.
* @param RTC_SmoothCalibPlusPulses : Select to Set or reset the CALP bit. * @param RTC_SmoothCalibPlusPulses : Select to Set or reset the CALP bit.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg RTC_SmoothCalibPlusPulses_Set : Add one RTCCLK puls every 2**11 pulses. * @arg RTC_SmoothCalibPlusPulses_Set : Add one RTCCLK puls every 2**11 pulses.
@@ -1931,7 +1958,7 @@ ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
TimeStamp configuration functions ##### TimeStamp configuration functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -2036,13 +2063,13 @@ void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
} }
/** /**
* @brief Get the RTC timestamp Subseconds value. * @brief Get the RTC timestamp Sub seconds value.
* @param None * @param None
* @retval RTC current timestamp Subseconds value. * @retval RTC current timestamp Sub seconds value.
*/ */
uint32_t RTC_GetTimeStampSubSecond(void) uint32_t RTC_GetTimeStampSubSecond(void)
{ {
/* Get timestamp subseconds values from the correspondent registers */ /* Get timestamp sub seconds values from the correspondent registers */
return (uint32_t)(RTC->TSSSR); return (uint32_t)(RTC->TSSSR);
} }
@@ -2055,7 +2082,7 @@ uint32_t RTC_GetTimeStampSubSecond(void)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Tampers configuration functions ##### Tampers configuration functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -2183,10 +2210,10 @@ void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq)
* @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input
* Precharge Duration. * Precharge Duration.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are precharged before sampling during 1 RTCCLK cycle
* @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are precharged before sampling during 2 RTCCLK cycle
* @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are precharged before sampling during 4 RTCCLK cycle
* @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are precharged before sampling during 8 RTCCLK cycle
* @retval None * @retval None
*/ */
void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration) void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration)
@@ -2258,7 +2285,7 @@ void RTC_TamperPullUpCmd(FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Backup Data Registers configuration functions ##### Backup Data Registers configuration functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -2317,10 +2344,9 @@ uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)
* configuration functions * configuration functions
* *
@verbatim @verbatim
=============================================================================== ==================================================================================================
RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration ##### RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions #####
functions ==================================================================================================
===============================================================================
@endverbatim @endverbatim
* @{ * @{
@@ -2388,7 +2414,7 @@ void RTC_OutputTypeConfig(uint32_t RTC_OutputType)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Shift control synchronisation functions ##### Shift control synchronisation functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -2474,41 +2500,42 @@ ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSu
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Interrupts and flags management functions ##### Interrupts and flags management functions #####
=============================================================================== ===============================================================================
All RTC interrupts are connected to the EXTI controller. [..] All RTC interrupts are connected to the EXTI controller.
- To enable the RTC Alarm interrupt, the following sequence is required: (+) To enable the RTC Alarm interrupt, the following sequence is required:
- Configure and enable the EXTI Line 17 in interrupt mode and select the rising (++) Configure and enable the EXTI Line 17 in interrupt mode and select
edge sensitivity using the EXTI_Init() function. the rising edge sensitivity using the EXTI_Init() function.
- Configure and enable the RTC_Alarm IRQ channel in the NVIC using the NVIC_Init() (++) Configure and enable the RTC_Alarm IRQ channel in the NVIC using the
function. NVIC_Init() function.
- Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) using (++) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) using
the RTC_SetAlarm() and RTC_AlarmCmd() functions. the RTC_SetAlarm() and RTC_AlarmCmd() functions.
- To enable the RTC Wakeup interrupt, the following sequence is required: (+) To enable the RTC Wakeup interrupt, the following sequence is required:
- Configure and enable the EXTI Line 22 in interrupt mode and select the rising (++) Configure and enable the EXTI Line 22 in interrupt mode and select the
edge sensitivity using the EXTI_Init() function. rising edge sensitivity using the EXTI_Init() function.
- Configure and enable the RTC_WKUP IRQ channel in the NVIC using the NVIC_Init() (++) Configure and enable the RTC_WKUP IRQ channel in the NVIC using the
function. NVIC_Init() function.
- Configure the RTC to generate the RTC wakeup timer event using the (++) Configure the RTC to generate the RTC wakeup timer event using the
RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd()
functions.
- To enable the RTC Tamper interrupt, the following sequence is required: (+) To enable the RTC Tamper interrupt, the following sequence is required:
- Configure and enable the EXTI Line 21 in interrupt mode and select the rising (++) Configure and enable the EXTI Line 21 in interrupt mode and select
edge sensitivity using the EXTI_Init() function. the rising edge sensitivity using the EXTI_Init() function.
- Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the
function. NVIC_Init() function.
- Configure the RTC to detect the RTC tamper event using the (++) Configure the RTC to detect the RTC tamper event using the
RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.
- To enable the RTC TimeStamp interrupt, the following sequence is required: (+) To enable the RTC TimeStamp interrupt, the following sequence is required:
- Configure and enable the EXTI Line 21 in interrupt mode and select the rising (++) Configure and enable the EXTI Line 21 in interrupt mode and select the
edge sensitivity using the EXTI_Init() function. rising edge sensitivity using the EXTI_Init() function.
- Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the
function. NVIC_Init() function.
- Configure the RTC to detect the RTC time-stamp event using the (++) Configure the RTC to detect the RTC time stamp event using the
RTC_TimeStampCmd() functions. RTC_TimeStampCmd() functions.
@endverbatim @endverbatim
* @{ * @{
@@ -2559,6 +2586,7 @@ void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)
* @brief Checks whether the specified RTC flag is set or not. * @brief Checks whether the specified RTC flag is set or not.
* @param RTC_FLAG: specifies the flag to check. * @param RTC_FLAG: specifies the flag to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg RTC_FLAG_RECALPF: RECALPF event flag.
* @arg RTC_FLAG_TAMP1F: Tamper 1 event flag * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
* @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag
* @arg RTC_FLAG_TSF: Time Stamp event flag * @arg RTC_FLAG_TSF: Time Stamp event flag
@@ -2568,6 +2596,7 @@ void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)
* @arg RTC_FLAG_INITF: Initialization mode flag * @arg RTC_FLAG_INITF: Initialization mode flag
* @arg RTC_FLAG_RSF: Registers Synchronized flag * @arg RTC_FLAG_RSF: Registers Synchronized flag
* @arg RTC_FLAG_INITS: Registers Configured flag * @arg RTC_FLAG_INITS: Registers Configured flag
* @arg RTC_FLAG_SHPF: Shift operation pending flag.
* @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag * @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag
* @arg RTC_FLAG_ALRBWF: Alarm B Write flag * @arg RTC_FLAG_ALRBWF: Alarm B Write flag
* @arg RTC_FLAG_ALRAWF: Alarm A write flag * @arg RTC_FLAG_ALRAWF: Alarm A write flag
@@ -2729,4 +2758,4 @@ static uint8_t RTC_Bcd2ToByte(uint8_t Value)
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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example/libs/StmCoreNPheriph/src/stm32f4xx_sai.c Normal file
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283
example/libs/StmCoreNPheriph/src/stm32f4xx_sdio.c
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@@ -2,146 +2,153 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_sdio.c * @file stm32f4xx_sdio.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides firmware functions to manage the following * @brief This file provides firmware functions to manage the following
* functionalities of the Secure digital input/output interface (SDIO) * functionalities of the Secure digital input/output interface (SDIO)
* peripheral: * peripheral:
* - Initialization and Configuration * + Initialization and Configuration
* - Command path state machine (CPSM) management * + Command path state machine (CPSM) management
* - Data path state machine (DPSM) management * + Data path state machine (DPSM) management
* - SDIO IO Cards mode management * + SDIO IO Cards mode management
* - CE-ATA mode management * + CE-ATA mode management
* - DMA transfers management * + DMA transfers management
* - Interrupts and flags management * + Interrupts and flags management
* *
* @verbatim @verbatim
*
* ===================================================================
* =================================================================== ##### How to use this driver #####
* How to use this driver ===================================================================
* =================================================================== [..]
* 1. The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output (#) The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output of PLL
* of PLL (PLL48CLK). Before to start working with SDIO peripheral (PLL48CLK). Before to start working with SDIO peripheral make sure that the
* make sure that the PLL is well configured. PLL is well configured.
* The SDIO peripheral uses two clock signals: The SDIO peripheral uses two clock signals:
* - SDIO adapter clock (SDIOCLK = 48 MHz) (++) SDIO adapter clock (SDIOCLK = 48 MHz)
* - APB2 bus clock (PCLK2) (++) APB2 bus clock (PCLK2)
* PCLK2 and SDIO_CK clock frequencies must respect the following condition:
* Frequenc(PCLK2) >= (3 / 8 x Frequency(SDIO_CK)) -@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition:
* Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK))
* 2. Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE).
* (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE).
* 3. According to the SDIO mode, enable the GPIO clocks using
* RCC_AHB1PeriphClockCmd() function. (#) According to the SDIO mode, enable the GPIO clocks using
* The I/O can be one of the following configurations: RCC_AHB1PeriphClockCmd() function.
* - 1-bit data length: SDIO_CMD, SDIO_CK and D0. The I/O can be one of the following configurations:
* - 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0]. (++) 1-bit data length: SDIO_CMD, SDIO_CK and D0.
* - 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0]. (++) 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0].
* (++) 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0].
* 4. Peripheral's alternate function:
* - Connect the pin to the desired peripherals' Alternate (#) Peripheral alternate function:
* Function (AF) using GPIO_PinAFConfig() function (++) Connect the pin to the desired peripherals' Alternate Function (AF)
* - Configure the desired pin in alternate function by: using GPIO_PinAFConfig() function
* GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF (++) Configure the desired pin in alternate function by:
* - Select the type, pull-up/pull-down and output speed via GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
* GPIO_PuPd, GPIO_OType and GPIO_Speed members (++) Select the type, pull-up/pull-down and output speed via GPIO_PuPd,
* - Call GPIO_Init() function GPIO_OType and GPIO_Speed members
* (++) Call GPIO_Init() function
* 5. Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide,
* hardware, flow control and the Clock Divider using the SDIO_Init() (#) Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide,
* function. hardware, flow control and the Clock Divider using the SDIO_Init()
* function.
* 6. Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON)
* function. (#) Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON)
* function.
* 7. Enable the clock using the SDIO_ClockCmd() function.
* (#) Enable the clock using the SDIO_ClockCmd() function.
* 8. Enable the NVIC and the corresponding interrupt using the function
* SDIO_ITConfig() if you need to use interrupt mode. (#) Enable the NVIC and the corresponding interrupt using the function
* SDIO_ITConfig() if you need to use interrupt mode.
* 9. When using the DMA mode
* - Configure the DMA using DMA_Init() function (#) When using the DMA mode
* - Active the needed channel Request using SDIO_DMACmd() function (++) Configure the DMA using DMA_Init() function
* (++) Active the needed channel Request using SDIO_DMACmd() function
* 10. Enable the DMA using the DMA_Cmd() function, when using DMA mode.
* (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.
* 11. To control the CPSM (Command Path State Machine) and send
* commands to the card use the SDIO_SendCommand(), (#) To control the CPSM (Command Path State Machine) and send
* SDIO_GetCommandResponse() and SDIO_GetResponse() functions. commands to the card use the SDIO_SendCommand(),
* First, user has to fill the command structure (pointer to SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has
* SDIO_CmdInitTypeDef) according to the selected command to be sent. to fill the command structure (pointer to SDIO_CmdInitTypeDef) according
* The parameters that should be filled are: to the selected command to be sent.
* - Command Argument The parameters that should be filled are:
* - Command Index (++) Command Argument
* - Command Response type (++) Command Index
* - Command Wait (++) Command Response type
* - CPSM Status (Enable or Disable) (++) Command Wait
* (++) CPSM Status (Enable or Disable).
* To check if the command is well received, read the SDIO_CMDRESP
* register using the SDIO_GetCommandResponse(). -@@- To check if the command is well received, read the SDIO_CMDRESP
* The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the register using the SDIO_GetCommandResponse().
* SDIO_GetResponse() function. The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the
* SDIO_GetResponse() function.
* 12. To control the DPSM (Data Path State Machine) and send/receive
* data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), (#) To control the DPSM (Data Path State Machine) and send/receive
* SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions. data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(),
* SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions.
* Read Operations
* --------------- *** Read Operations ***
* a) First, user has to fill the data structure (pointer to =======================
* SDIO_DataInitTypeDef) according to the selected data type to [..]
* be received. (#) First, user has to fill the data structure (pointer to
* The parameters that should be filled are: SDIO_DataInitTypeDef) according to the selected data type to be received.
* - Data TimeOut The parameters that should be filled are:
* - Data Length (++) Data TimeOut
* - Data Block size (++) Data Length
* - Data Transfer direction: should be from card (To SDIO) (++) Data Block size
* - Data Transfer mode (++) Data Transfer direction: should be from card (To SDIO)
* - DPSM Status (Enable or Disable) (++) Data Transfer mode
* (++) DPSM Status (Enable or Disable)
* b) Configure the SDIO resources to receive the data from the card
* according to selected transfer mode (Refer to Step 8, 9 and 10). (#) Configure the SDIO resources to receive the data from the card
* according to selected transfer mode (Refer to Step 8, 9 and 10).
* c) Send the selected Read command (refer to step 11).
* (#) Send the selected Read command (refer to step 11).
* d) Use the SDIO flags/interrupts to check the transfer status.
* (#) Use the SDIO flags/interrupts to check the transfer status.
* Write Operations
* --------------- *** Write Operations ***
* a) First, user has to fill the data structure (pointer to ========================
* SDIO_DataInitTypeDef) according to the selected data type to [..]
* be received. (#) First, user has to fill the data structure (pointer to
* The parameters that should be filled are: SDIO_DataInitTypeDef) according to the selected data type to be received.
* - Data TimeOut The parameters that should be filled are:
* - Data Length (++) Data TimeOut
* - Data Block size (++) Data Length
* - Data Transfer direction: should be to card (To CARD) (++) Data Block size
* - Data Transfer mode (++) Data Transfer direction: should be to card (To CARD)
* - DPSM Status (Enable or Disable) (++) Data Transfer mode
* (++) DPSM Status (Enable or Disable)
* b) Configure the SDIO resources to send the data to the card
* according to selected transfer mode (Refer to Step 8, 9 and 10). (#) Configure the SDIO resources to send the data to the card according to
* selected transfer mode (Refer to Step 8, 9 and 10).
* c) Send the selected Write command (refer to step 11).
* (#) Send the selected Write command (refer to step 11).
* d) Use the SDIO flags/interrupts to check the transfer status.
* (#) Use the SDIO flags/interrupts to check the transfer status.
*
* @endverbatim
@endverbatim
* *
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -244,7 +251,7 @@
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Initialization and Configuration functions ##### Initialization and Configuration functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -371,7 +378,7 @@ uint32_t SDIO_GetPowerState(void)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Command path state machine (CPSM) management functions ##### Command path state machine (CPSM) management functions #####
=============================================================================== ===============================================================================
This section provide functions allowing to program and read the Command path This section provide functions allowing to program and read the Command path
@@ -476,7 +483,7 @@ uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Data path state machine (DPSM) management functions ##### Data path state machine (DPSM) management functions #####
=============================================================================== ===============================================================================
This section provide functions allowing to program and read the Data path This section provide functions allowing to program and read the Data path
@@ -594,7 +601,7 @@ uint32_t SDIO_GetFIFOCount(void)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
SDIO IO Cards mode management functions ##### SDIO IO Cards mode management functions #####
=============================================================================== ===============================================================================
This section provide functions allowing to program and read the SDIO IO Cards. This section provide functions allowing to program and read the SDIO IO Cards.
@@ -684,7 +691,7 @@ void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
CE-ATA mode management functions ##### CE-ATA mode management functions #####
=============================================================================== ===============================================================================
This section provide functions allowing to program and read the CE-ATA card. This section provide functions allowing to program and read the CE-ATA card.
@@ -744,7 +751,7 @@ void SDIO_SendCEATACmd(FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
DMA transfers management functions ##### DMA transfers management functions #####
=============================================================================== ===============================================================================
This section provide functions allowing to program SDIO DMA transfer. This section provide functions allowing to program SDIO DMA transfer.
@@ -776,7 +783,7 @@ void SDIO_DMACmd(FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Interrupts and flags management functions ##### Interrupts and flags management functions #####
=============================================================================== ===============================================================================
@@ -1001,4 +1008,4 @@ void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

605
example/libs/StmCoreNPheriph/src/stm32f4xx_spi.c
View File

@@ -2,149 +2,156 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_spi.c * @file stm32f4xx_spi.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides firmware functions to manage the following * @brief This file provides firmware functions to manage the following
* functionalities of the Serial peripheral interface (SPI): * functionalities of the Serial peripheral interface (SPI):
* - Initialization and Configuration * + Initialization and Configuration
* - Data transfers functions * + Data transfers functions
* - Hardware CRC Calculation * + Hardware CRC Calculation
* - DMA transfers management * + DMA transfers management
* - Interrupts and flags management * + Interrupts and flags management
* *
* @verbatim @verbatim
*
* ===================================================================
* =================================================================== ##### How to use this driver #####
* How to use this driver ===================================================================
* =================================================================== [..]
* (#) Enable peripheral clock using the following functions
* 1. Enable peripheral clock using the following functions RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1
* RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1 RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2
* RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3
* RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3. RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI4
* RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI5
* 2. Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd() RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI6.
* function.
* In I2S mode, if an external clock source is used then the I2S CKIN pin GPIO (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd()
* clock should also be enabled. function. In I2S mode, if an external clock source is used then the I2S
* CKIN pin GPIO clock should also be enabled.
* 3. Peripherals alternate function:
* - Connect the pin to the desired peripherals' Alternate (#) Peripherals alternate function:
* Function (AF) using GPIO_PinAFConfig() function (++) Connect the pin to the desired peripherals' Alternate Function (AF)
* - Configure the desired pin in alternate function by: using GPIO_PinAFConfig() function
* GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF (++) Configure the desired pin in alternate function by:
* - Select the type, pull-up/pull-down and output speed via GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
* GPIO_PuPd, GPIO_OType and GPIO_Speed members (++) Select the type, pull-up/pull-down and output speed via GPIO_PuPd,
* - Call GPIO_Init() function GPIO_OType and GPIO_Speed members
* In I2S mode, if an external clock source is used then the I2S CKIN pin (++) Call GPIO_Init() function In I2S mode, if an external clock source is
* should be also configured in Alternate function Push-pull pull-up mode. used then the I2S CKIN pin should be also configured in Alternate
* function Push-pull pull-up mode.
* 4. Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave
* Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave
* function. Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
* In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio function.
* frequency and Polarity using I2S_Init() function. In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio
* For I2S mode, make sure that either: frequency and Polarity using I2S_Init() function. For I2S mode, make sure
* - I2S PLL is configured using the functions RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S), that either:
* RCC_PLLI2SCmd(ENABLE) and RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY). (++) I2S PLL is configured using the functions
* or RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S), RCC_PLLI2SCmd(ENABLE) and
* - External clock source is configured using the function RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY); or
* RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly the define constant (++) External clock source is configured using the function
* I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file. RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly
* the define constant I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file.
* 5. Enable the NVIC and the corresponding interrupt using the function
* SPI_ITConfig() if you need to use interrupt mode. (#) Enable the NVIC and the corresponding interrupt using the function
* SPI_ITConfig() if you need to use interrupt mode.
* 6. When using the DMA mode
* - Configure the DMA using DMA_Init() function (#) When using the DMA mode
* - Active the needed channel Request using SPI_I2S_DMACmd() function (++) Configure the DMA using DMA_Init() function
* (++) Active the needed channel Request using SPI_I2S_DMACmd() function
* 7. Enable the SPI using the SPI_Cmd() function or enable the I2S using
* I2S_Cmd(). (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using
* I2S_Cmd().
* 8. Enable the DMA using the DMA_Cmd() function when using DMA mode.
* (#) Enable the DMA using the DMA_Cmd() function when using DMA mode.
* 9. Optionally, you can enable/configure the following parameters without
* re-initialization (i.e there is no need to call again SPI_Init() function): (#) Optionally, you can enable/configure the following parameters without
* - When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx) re-initialization (i.e there is no need to call again SPI_Init() function):
* is programmed as Data direction parameter using the SPI_Init() function (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
* it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx is programmed as Data direction parameter using the SPI_Init() function
* using the SPI_BiDirectionalLineConfig() function. it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx
* - When SPI_NSS_Soft is selected as Slave Select Management parameter using the SPI_BiDirectionalLineConfig() function.
* using the SPI_Init() function it can be possible to manage the (++) When SPI_NSS_Soft is selected as Slave Select Management parameter
* NSS internal signal using the SPI_NSSInternalSoftwareConfig() function. using the SPI_Init() function it can be possible to manage the
* - Reconfigure the data size using the SPI_DataSizeConfig() function NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
* - Enable or disable the SS output using the SPI_SSOutputCmd() function (++) Reconfigure the data size using the SPI_DataSizeConfig() function
* (++) Enable or disable the SS output using the SPI_SSOutputCmd() function
* 10. To use the CRC Hardware calculation feature refer to the Peripheral
* CRC hardware Calculation subsection. (#) To use the CRC Hardware calculation feature refer to the Peripheral
* CRC hardware Calculation subsection.
*
* It is possible to use SPI in I2S full duplex mode, in this case, each SPI
* peripheral is able to manage sending and receiving data simultaneously [..] It is possible to use SPI in I2S full duplex mode, in this case, each SPI
* using two data lines. Each SPI peripheral has an extended block called I2Sxext peripheral is able to manage sending and receiving data simultaneously
* (ie. I2S2ext for SPI2 and I2S3ext for SPI3). using two data lines. Each SPI peripheral has an extended block called I2Sxext
* The extension block is not a full SPI IP, it is used only as I2S slave to (ie. I2S2ext for SPI2 and I2S3ext for SPI3).
* implement full duplex mode. The extension block uses the same clock sources The extension block is not a full SPI IP, it is used only as I2S slave to
* as its master. implement full duplex mode. The extension block uses the same clock sources
* To configure I2S full duplex you have to: as its master.
* To configure I2S full duplex you have to:
* 1. Configure SPIx in I2S mode (I2S_Init() function) as described above.
* (#) Configure SPIx in I2S mode (I2S_Init() function) as described above.
* 2. Call the I2S_FullDuplexConfig() function using the same strucutre passed to
* I2S_Init() function. (#) Call the I2S_FullDuplexConfig() function using the same strucutre passed to
* I2S_Init() function.
* 3. Call I2S_Cmd() for SPIx then for its extended block.
* (#) Call I2S_Cmd() for SPIx then for its extended block.
* 4. To configure interrupts or DMA requests and to get/clear flag status,
* use I2Sxext instance for the extension block. (#) To configure interrupts or DMA requests and to get/clear flag status,
* use I2Sxext instance for the extension block.
* Functions that can be called with I2Sxext instances are:
* I2S_Cmd(), I2S_FullDuplexConfig(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(), [..] Functions that can be called with I2Sxext instances are: I2S_Cmd(),
* SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(), SPI_I2S_ClearFlag(), I2S_FullDuplexConfig(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(),
* SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit(). SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(),
* SPI_I2S_ClearFlag(), SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit().
* Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx):
* Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx):
* RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
* I2S_StructInit(&I2SInitStruct); RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
* I2SInitStruct.Mode = I2S_Mode_MasterTx; I2S_StructInit(&I2SInitStruct);
* I2S_Init(SPI3, &I2SInitStruct); I2SInitStruct.Mode = I2S_Mode_MasterTx;
* I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct) I2S_Init(SPI3, &I2SInitStruct);
* I2S_Cmd(SPI3, ENABLE); I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct)
* I2S_Cmd(SPI3ext, ENABLE); I2S_Cmd(SPI3, ENABLE);
* ... I2S_Cmd(SPI3ext, ENABLE);
* while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET) ...
* {} while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
* SPI_I2S_SendData(SPI3, txdata[i]); {}
* ... SPI_I2S_SendData(SPI3, txdata[i]);
* while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET) ...
* {} while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET)
* rxdata[i] = SPI_I2S_ReceiveData(I2S3ext); {}
* ... rxdata[i] = SPI_I2S_ReceiveData(I2S3ext);
* ...
*
* @note In I2S mode: if an external clock is used as source clock for the I2S, [..]
* then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should (@) In I2S mode: if an external clock is used as source clock for the I2S,
* be enabled and set to the value of the source clock frequency (in Hz). then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should
* be enabled and set to the value of the source clock frequency (in Hz).
* @note In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd()
* just after calling the function SPI_Init(). (@) In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd()
* just after calling the function SPI_Init().
* @endverbatim
@endverbatim
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -189,28 +196,27 @@
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Initialization and Configuration functions ##### Initialization and Configuration functions #####
=============================================================================== ===============================================================================
[..] This section provides a set of functions allowing to initialize the SPI
This section provides a set of functions allowing to initialize the SPI Direction, Direction, SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS
SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud Management, SPI Baud Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
The SPI_Init() function follows the SPI configuration procedures for Master mode [..] The SPI_Init() function follows the SPI configuration procedures for Master
and Slave mode (details for these procedures are available in reference manual mode and Slave mode (details for these procedures are available in reference
(RM0090)). manual (RM0090)).
@endverbatim @endverbatim
* @{ * @{
*/ */
/** /**
* @brief Deinitialize the SPIx peripheral registers to their default reset values. * @brief De-initialize the SPIx peripheral registers to their default reset values.
* @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
* in SPI mode or 2 or 3 in I2S mode. * in SPI mode or 2 or 3 in I2S mode.
* *
* @note The extended I2S blocks (ie. I2S2ext and I2S3ext blocks) are deinitialized * @note The extended I2S blocks (ie. I2S2ext and I2S3ext blocks) are de-initialized
* when the relative I2S peripheral is deinitialized (the extended block's clock * when the relative I2S peripheral is de-initialized (the extended block's clock
* is managed by the I2S peripheral clock). * is managed by the I2S peripheral clock).
* *
* @retval None * @retval None
@@ -233,15 +239,36 @@ void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
/* Release SPI2 from reset state */ /* Release SPI2 from reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
} }
else else if (SPIx == SPI3)
{ {
if (SPIx == SPI3) /* Enable SPI3 reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
/* Release SPI3 from reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
}
else if (SPIx == SPI4)
{
/* Enable SPI4 reset state */
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, ENABLE);
/* Release SPI4 from reset state */
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, DISABLE);
}
else if (SPIx == SPI5)
{
/* Enable SPI5 reset state */
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI5, ENABLE);
/* Release SPI5 from reset state */
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI5, DISABLE);
}
else
{
if (SPIx == SPI6)
{ {
/* Enable SPI3 reset state */ /* Enable SPI6 reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI6, ENABLE);
/* Release SPI3 from reset state */ /* Release SPI6 from reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI6, DISABLE);
} }
} }
} }
@@ -249,7 +276,7 @@ void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
/** /**
* @brief Initializes the SPIx peripheral according to the specified * @brief Initializes the SPIx peripheral according to the specified
* parameters in the SPI_InitStruct. * parameters in the SPI_InitStruct.
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
* @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
* contains the configuration information for the specified SPI peripheral. * contains the configuration information for the specified SPI peripheral.
* @retval None * @retval None
@@ -394,10 +421,17 @@ void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
(RCC_PLLI2SCFGR_PLLI2SR >> 28)); (RCC_PLLI2SCFGR_PLLI2SR >> 28));
/* Get the PLLM value */ /* Get the PLLM value */
pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
/* Get the I2S source clock value */ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)
i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr); {
/* Get the I2S source clock value */
i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr);
}
else
{ /* Get the I2S source clock value */
i2sclk = (uint32_t)(((HSI_VALUE / pllm) * plln) / pllr);
}
#endif /* I2S_EXTERNAL_CLOCK_VAL */ #endif /* I2S_EXTERNAL_CLOCK_VAL */
/* Compute the Real divider depending on the MCLK output state, with a floating point */ /* Compute the Real divider depending on the MCLK output state, with a floating point */
@@ -502,7 +536,7 @@ void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
/** /**
* @brief Enables or disables the specified SPI peripheral. * @brief Enables or disables the specified SPI peripheral.
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
* @param NewState: new state of the SPIx peripheral. * @param NewState: new state of the SPIx peripheral.
* This parameter can be: ENABLE or DISABLE. * This parameter can be: ENABLE or DISABLE.
* @retval None * @retval None
@@ -552,7 +586,7 @@ void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
/** /**
* @brief Configures the data size for the selected SPI. * @brief Configures the data size for the selected SPI.
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
* @param SPI_DataSize: specifies the SPI data size. * @param SPI_DataSize: specifies the SPI data size.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg SPI_DataSize_16b: Set data frame format to 16bit * @arg SPI_DataSize_16b: Set data frame format to 16bit
@@ -572,7 +606,7 @@ void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
/** /**
* @brief Selects the data transfer direction in bidirectional mode for the specified SPI. * @brief Selects the data transfer direction in bidirectional mode for the specified SPI.
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
* @param SPI_Direction: specifies the data transfer direction in bidirectional mode. * @param SPI_Direction: specifies the data transfer direction in bidirectional mode.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg SPI_Direction_Tx: Selects Tx transmission direction * @arg SPI_Direction_Tx: Selects Tx transmission direction
@@ -598,7 +632,7 @@ void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
/** /**
* @brief Configures internally by software the NSS pin for the selected SPI. * @brief Configures internally by software the NSS pin for the selected SPI.
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
* @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg SPI_NSSInternalSoft_Set: Set NSS pin internally * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
@@ -624,7 +658,7 @@ void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSo
/** /**
* @brief Enables or disables the SS output for the selected SPI. * @brief Enables or disables the SS output for the selected SPI.
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
* @param NewState: new state of the SPIx SS output. * @param NewState: new state of the SPIx SS output.
* This parameter can be: ENABLE or DISABLE. * This parameter can be: ENABLE or DISABLE.
* @retval None * @retval None
@@ -655,7 +689,7 @@ void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
* are not taken into consideration and are configured by hardware * are not taken into consideration and are configured by hardware
* respectively to the TI mode requirements. * respectively to the TI mode requirements.
* *
* @param SPIx: where x can be 1, 2 or 3 * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6
* @param NewState: new state of the selected SPI TI communication mode. * @param NewState: new state of the selected SPI TI communication mode.
* This parameter can be: ENABLE or DISABLE. * This parameter can be: ENABLE or DISABLE.
* @retval None * @retval None
@@ -748,19 +782,18 @@ void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Data transfers functions ##### Data transfers functions #####
=============================================================================== ===============================================================================
This section provides a set of functions allowing to manage the SPI data transfers [..] This section provides a set of functions allowing to manage the SPI data
transfers. In reception, data are received and then stored into an internal
In reception, data are received and then stored into an internal Rx buffer while Rx buffer while. In transmission, data are first stored into an internal Tx
In transmission, data are first stored into an internal Tx buffer before being buffer before being transmitted.
transmitted.
The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData() [..] The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData()
function and returns the Rx buffered value. Whereas a write access to the SPI_DR function and returns the Rx buffered value. Whereas a write access to the SPI_DR
can be done using SPI_I2S_SendData() function and stores the written data into can be done using SPI_I2S_SendData() function and stores the written data into
Tx buffer. Tx buffer.
@endverbatim @endverbatim
* @{ * @{
@@ -768,7 +801,7 @@ void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct)
/** /**
* @brief Returns the most recent received data by the SPIx/I2Sx peripheral. * @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
* @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
* in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
* @retval The value of the received data. * @retval The value of the received data.
*/ */
@@ -783,7 +816,7 @@ uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
/** /**
* @brief Transmits a Data through the SPIx/I2Sx peripheral. * @brief Transmits a Data through the SPIx/I2Sx peripheral.
* @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
* in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
* @param Data: Data to be transmitted. * @param Data: Data to be transmitted.
* @retval None * @retval None
@@ -806,65 +839,66 @@ void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Hardware CRC Calculation functions ##### Hardware CRC Calculation functions #####
=============================================================================== ===============================================================================
This section provides a set of functions allowing to manage the SPI CRC hardware [..] This section provides a set of functions allowing to manage the SPI CRC hardware
calculation calculation
SPI communication using CRC is possible through the following procedure: [..] SPI communication using CRC is possible through the following procedure:
1. Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler,
Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
function. function.
2. Enable the CRC calculation using the SPI_CalculateCRC() function. (#) Enable the CRC calculation using the SPI_CalculateCRC() function.
3. Enable the SPI using the SPI_Cmd() function (#) Enable the SPI using the SPI_Cmd() function
4. Before writing the last data to the TX buffer, set the CRCNext bit using the (#) Before writing the last data to the TX buffer, set the CRCNext bit using the
SPI_TransmitCRC() function to indicate that after transmission of the last SPI_TransmitCRC() function to indicate that after transmission of the last
data, the CRC should be transmitted. data, the CRC should be transmitted.
5. After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT
bit is reset. The CRC is also received and compared against the SPI_RXCRCR bit is reset. The CRC is also received and compared against the SPI_RXCRCR
value. value.
If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt
can be generated when the SPI_I2S_IT_ERR interrupt is enabled. can be generated when the SPI_I2S_IT_ERR interrupt is enabled.
@note It is advised not to read the calculated CRC values during the communication. [..]
(@) It is advised not to read the calculated CRC values during the communication.
@note When the SPI is in slave mode, be careful to enable CRC calculation only (@) When the SPI is in slave mode, be careful to enable CRC calculation only
when the clock is stable, that is, when the clock is in the steady state. when the clock is stable, that is, when the clock is in the steady state.
If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive
to the SCK slave input clock as soon as CRCEN is set, and this, whatever to the SCK slave input clock as soon as CRCEN is set, and this, whatever
the value of the SPE bit. the value of the SPE bit.
@note With high bitrate frequencies, be careful when transmitting the CRC. (@) With high bitrate frequencies, be careful when transmitting the CRC.
As the number of used CPU cycles has to be as low as possible in the CRC As the number of used CPU cycles has to be as low as possible in the CRC
transfer phase, it is forbidden to call software functions in the CRC transfer phase, it is forbidden to call software functions in the CRC
transmission sequence to avoid errors in the last data and CRC reception. transmission sequence to avoid errors in the last data and CRC reception.
In fact, CRCNEXT bit has to be written before the end of the transmission/reception In fact, CRCNEXT bit has to be written before the end of the transmission/reception
of the last data. of the last data.
@note For high bit rate frequencies, it is advised to use the DMA mode to avoid the (@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the
degradation of the SPI speed performance due to CPU accesses impacting the degradation of the SPI speed performance due to CPU accesses impacting the
SPI bandwidth. SPI bandwidth.
@note When the STM32F4xx is configured as slave and the NSS hardware mode is (@) When the STM32F4xx is configured as slave and the NSS hardware mode is
used, the NSS pin needs to be kept low between the data phase and the CRC used, the NSS pin needs to be kept low between the data phase and the CRC
phase. phase.
@note When the SPI is configured in slave mode with the CRC feature enabled, CRC (@) When the SPI is configured in slave mode with the CRC feature enabled, CRC
calculation takes place even if a high level is applied on the NSS pin. calculation takes place even if a high level is applied on the NSS pin.
This may happen for example in case of a multi-slave environment where the This may happen for example in case of a multi-slave environment where the
communication master addresses slaves alternately. communication master addresses slaves alternately.
@note Between a slave de-selection (high level on NSS) and a new slave selection (@) Between a slave de-selection (high level on NSS) and a new slave selection
(low level on NSS), the CRC value should be cleared on both master and slave (low level on NSS), the CRC value should be cleared on both master and slave
sides in order to resynchronize the master and slave for their respective sides in order to resynchronize the master and slave for their respective
CRC calculation. CRC calculation.
@note To clear the CRC, follow the procedure below: (@) To clear the CRC, follow the procedure below:
1. Disable SPI using the SPI_Cmd() function (#@) Disable SPI using the SPI_Cmd() function
2. Disable the CRC calculation using the SPI_CalculateCRC() function. (#@) Disable the CRC calculation using the SPI_CalculateCRC() function.
3. Enable the CRC calculation using the SPI_CalculateCRC() function. (#@) Enable the CRC calculation using the SPI_CalculateCRC() function.
4. Enable SPI using the SPI_Cmd() function. (#@) Enable SPI using the SPI_Cmd() function.
@endverbatim @endverbatim
* @{ * @{
@@ -872,7 +906,7 @@ void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
/** /**
* @brief Enables or disables the CRC value calculation of the transferred bytes. * @brief Enables or disables the CRC value calculation of the transferred bytes.
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
* @param NewState: new state of the SPIx CRC value calculation. * @param NewState: new state of the SPIx CRC value calculation.
* This parameter can be: ENABLE or DISABLE. * This parameter can be: ENABLE or DISABLE.
* @retval None * @retval None
@@ -896,7 +930,7 @@ void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
/** /**
* @brief Transmit the SPIx CRC value. * @brief Transmit the SPIx CRC value.
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
* @retval None * @retval None
*/ */
void SPI_TransmitCRC(SPI_TypeDef* SPIx) void SPI_TransmitCRC(SPI_TypeDef* SPIx)
@@ -910,7 +944,7 @@ void SPI_TransmitCRC(SPI_TypeDef* SPIx)
/** /**
* @brief Returns the transmit or the receive CRC register value for the specified SPI. * @brief Returns the transmit or the receive CRC register value for the specified SPI.
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
* @param SPI_CRC: specifies the CRC register to be read. * @param SPI_CRC: specifies the CRC register to be read.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg SPI_CRC_Tx: Selects Tx CRC register * @arg SPI_CRC_Tx: Selects Tx CRC register
@@ -939,7 +973,7 @@ uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
/** /**
* @brief Returns the CRC Polynomial register value for the specified SPI. * @brief Returns the CRC Polynomial register value for the specified SPI.
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
* @retval The CRC Polynomial register value. * @retval The CRC Polynomial register value.
*/ */
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
@@ -960,7 +994,7 @@ uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
DMA transfers management functions ##### DMA transfers management functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -969,7 +1003,7 @@ uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
/** /**
* @brief Enables or disables the SPIx/I2Sx DMA interface. * @brief Enables or disables the SPIx/I2Sx DMA interface.
* @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
* in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
* @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
@@ -1007,69 +1041,68 @@ void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Interrupts and flags management functions ##### Interrupts and flags management functions #####
=============================================================================== ===============================================================================
This section provides a set of functions allowing to configure the SPI Interrupts [..] This section provides a set of functions allowing to configure the SPI Interrupts
sources and check or clear the flags or pending bits status. sources and check or clear the flags or pending bits status.
The user should identify which mode will be used in his application to manage The user should identify which mode will be used in his application to manage
the communication: Polling mode, Interrupt mode or DMA mode. the communication: Polling mode, Interrupt mode or DMA mode.
Polling Mode *** Polling Mode ***
============= ====================
In Polling Mode, the SPI/I2S communication can be managed by 9 flags: [..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags:
1. SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register
2. SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register
3. SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI. (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI.
4. SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur
5. SPI_FLAG_MODF : to indicate if a Mode Fault error occur (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur
6. SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur
7. I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs. (#) I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs.
8. I2S_FLAG_UDR: to indicate an Underrun error occurs. (#) I2S_FLAG_UDR: to indicate an Underrun error occurs.
9. I2S_FLAG_CHSIDE: to indicate Channel Side. (#) I2S_FLAG_CHSIDE: to indicate Channel Side.
@note Do not use the BSY flag to handle each data transmission or reception. It is (@) Do not use the BSY flag to handle each data transmission or reception. It is
better to use the TXE and RXNE flags instead. better to use the TXE and RXNE flags instead.
In this Mode it is advised to use the following functions: [..] In this Mode it is advised to use the following functions:
- FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
- void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
Interrupt Mode *** Interrupt Mode ***
=============== ======================
In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources [..] In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources
and 7 pending bits: and 7 pending bits:
Pending Bits: (+) Pending Bits:
------------- (##) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register
1. SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register (##) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register
2. SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register (##) SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only)
3. SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only) (##) SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only)
4. SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only) (##) SPI_I2S_IT_OVR : to indicate if an Overrun error occur
5. SPI_I2S_IT_OVR : to indicate if an Overrun error occur (##) I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only).
6. I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only). (##) I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only).
7. I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only).
Interrupt Source: (+) Interrupt Source:
----------------- (##) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty
1. SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty interrupt.
interrupt. (##) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not
2. SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not empty interrupt.
empty interrupt. (##) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.
3. SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.
In this Mode it is advised to use the following functions: [..] In this Mode it is advised to use the following functions:
- void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
- ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
- void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); (+) void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
DMA Mode *** DMA Mode ***
======== ================
In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests: [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests:
1. SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request
2. SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request
In this Mode it is advised to use the following function: [..] In this Mode it is advised to use the following function:
- void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState
NewState);
@endverbatim @endverbatim
* @{ * @{
@@ -1077,7 +1110,7 @@ void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState
/** /**
* @brief Enables or disables the specified SPI/I2S interrupts. * @brief Enables or disables the specified SPI/I2S interrupts.
* @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
* in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
* @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled.
* This parameter can be one of the following values: * This parameter can be one of the following values:
@@ -1117,7 +1150,7 @@ void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState New
/** /**
* @brief Checks whether the specified SPIx/I2Sx flag is set or not. * @brief Checks whether the specified SPIx/I2Sx flag is set or not.
* @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
* in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
* @param SPI_I2S_FLAG: specifies the SPI flag to check. * @param SPI_I2S_FLAG: specifies the SPI flag to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
@@ -1156,7 +1189,7 @@ FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
/** /**
* @brief Clears the SPIx CRC Error (CRCERR) flag. * @brief Clears the SPIx CRC Error (CRCERR) flag.
* @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
* in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
* @param SPI_I2S_FLAG: specifies the SPI flag to clear. * @param SPI_I2S_FLAG: specifies the SPI flag to clear.
* This function clears only CRCERR flag. * This function clears only CRCERR flag.
@@ -1185,7 +1218,7 @@ void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
/** /**
* @brief Checks whether the specified SPIx/I2Sx interrupt has occurred or not. * @brief Checks whether the specified SPIx/I2Sx interrupt has occurred or not.
* @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
* in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
* @param SPI_I2S_IT: specifies the SPI interrupt source to check. * @param SPI_I2S_IT: specifies the SPI interrupt source to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
@@ -1236,7 +1269,7 @@ ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
/** /**
* @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
* @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6
* in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.
* @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
* This function clears only CRCERR interrupt pending bit. * This function clears only CRCERR interrupt pending bit.
@@ -1283,4 +1316,4 @@ void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

107
example/libs/StmCoreNPheriph/src/stm32f4xx_syscfg.c
View File

@@ -2,40 +2,47 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_syscfg.c * @file stm32f4xx_syscfg.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides firmware functions to manage the SYSCFG peripheral. * @brief This file provides firmware functions to manage the SYSCFG peripheral.
* *
* @verbatim @verbatim
*
* =================================================================== ===============================================================================
* How to use this driver ##### How to use this driver #####
* =================================================================== ===============================================================================
* [..] This driver provides functions for:
* This driver provides functions for:
* (#) Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig()
* 1. Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig()
* (#) Swapping the internal flash Bank1 and Bank2 this features is only visible for
* 2. Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig() STM32F42xxx/43xxx devices Devices.
*
* 3. Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig() (#) Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig()
*
* @note SYSCFG APB clock must be enabled to get write access to SYSCFG registers, (#) Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig()
* using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
* -@- SYSCFG APB clock must be enabled to get write access to SYSCFG registers,
* @endverbatim using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
*
@endverbatim
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -56,6 +63,13 @@
/* Private define ------------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/
/* ------------ RCC registers bit address in the alias region ----------- */ /* ------------ RCC registers bit address in the alias region ----------- */
#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) #define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
/* --- MEMRMP Register ---*/
/* Alias word address of UFB_MODE bit */
#define MEMRMP_OFFSET SYSCFG_OFFSET
#define UFB_MODE_BitNumber ((uint8_t)0x8)
#define UFB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (UFB_MODE_BitNumber * 4))
/* --- PMC Register ---*/ /* --- PMC Register ---*/
/* Alias word address of MII_RMII_SEL bit */ /* Alias word address of MII_RMII_SEL bit */
#define PMC_OFFSET (SYSCFG_OFFSET + 0x04) #define PMC_OFFSET (SYSCFG_OFFSET + 0x04)
@@ -95,8 +109,10 @@ void SYSCFG_DeInit(void)
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000 * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 * @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F405xx/407xx and STM32F415xx/417xx devices.
* @arg SYSCFG_MemoryRemap_FMC: FMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F42xxx/43xxx devices.
* @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000 * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_SDRAM: FMC (External SDRAM) mapped at 0x00000000 for STM32F42xxx/43xxx devices.
* @retval None * @retval None
*/ */
void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap) void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)
@@ -107,13 +123,40 @@ void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)
SYSCFG->MEMRMP = SYSCFG_MemoryRemap; SYSCFG->MEMRMP = SYSCFG_MemoryRemap;
} }
/**
* @brief Enables or disables the Interal FLASH Bank Swapping.
*
* @note This function can be used only for STM32F42xxx/43xxx devices.
*
* @param NewState: new state of Interal FLASH Bank swapping.
* This parameter can be one of the following values:
* @arg ENABLE: Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
* and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)
* @arg DISABLE:(the default state) Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000)
and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000)
* @retval None
*/
void SYSCFG_MemorySwappingBank(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) UFB_MODE_BB = (uint32_t)NewState;
}
/** /**
* @brief Selects the GPIO pin used as EXTI Line. * @brief Selects the GPIO pin used as EXTI Line.
* @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for
* EXTI lines where x can be (A..I). * EXTI lines where x can be (A..K) for STM32F42xxx/43xxx devices, (A..I)
* for STM32F405xx/407xx and STM32F415xx/417xx devices or (A, B, C, D and H)
* for STM32401xx devices.
*
* @param EXTI_PinSourcex: specifies the EXTI line to be configured. * @param EXTI_PinSourcex: specifies the EXTI line to be configured.
* This parameter can be EXTI_PinSourcex where x can be (0..15, except * This parameter can be EXTI_PinSourcex where x can be (0..15, except
* for EXTI_PortSourceGPIOI x can be (0..11). * for EXTI_PortSourceGPIOI x can be (0..11) for STM32F405xx/407xx
* and STM32F405xx/407xx devices and for EXTI_PortSourceGPIOK x can
* be (0..7) for STM32F42xxx/43xxx devices.
*
* @retval None * @retval None
*/ */
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex) void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
@@ -194,4 +237,4 @@ FlagStatus SYSCFG_GetCompensationCellStatus(void)
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

425
example/libs/StmCoreNPheriph/src/stm32f4xx_tim.c
View File

@@ -2,111 +2,116 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_tim.c * @file stm32f4xx_tim.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides firmware functions to manage the following * @brief This file provides firmware functions to manage the following
* functionalities of the TIM peripheral: * functionalities of the TIM peripheral:
* - TimeBase management * + TimeBase management
* - Output Compare management * + Output Compare management
* - Input Capture management * + Input Capture management
* - Advanced-control timers (TIM1 and TIM8) specific features * + Advanced-control timers (TIM1 and TIM8) specific features
* - Interrupts, DMA and flags management * + Interrupts, DMA and flags management
* - Clocks management * + Clocks management
* - Synchronization management * + Synchronization management
* - Specific interface management * + Specific interface management
* - Specific remapping management * + Specific remapping management
* *
* @verbatim @verbatim
* ===============================================================================
* =================================================================== ##### How to use this driver #####
* How to use this driver ===============================================================================
* =================================================================== [..]
* This driver provides functions to configure and program the TIM This driver provides functions to configure and program the TIM
* of all STM32F4xx devices. of all STM32F4xx devices.
* These functions are split in 9 groups: These functions are split in 9 groups:
*
* 1. TIM TimeBase management: this group includes all needed functions (#) TIM TimeBase management: this group includes all needed functions
* to configure the TM Timebase unit: to configure the TM Timebase unit:
* - Set/Get Prescaler (++) Set/Get Prescaler
* - Set/Get Autoreload (++) Set/Get Autoreload
* - Counter modes configuration (++) Counter modes configuration
* - Set Clock division (++) Set Clock division
* - Select the One Pulse mode (++) Select the One Pulse mode
* - Update Request Configuration (++) Update Request Configuration
* - Update Disable Configuration (++) Update Disable Configuration
* - Auto-Preload Configuration (++) Auto-Preload Configuration
* - Enable/Disable the counter (++) Enable/Disable the counter
*
* 2. TIM Output Compare management: this group includes all needed (#) TIM Output Compare management: this group includes all needed
* functions to configure the Capture/Compare unit used in Output functions to configure the Capture/Compare unit used in Output
* compare mode: compare mode:
* - Configure each channel, independently, in Output Compare mode (++) Configure each channel, independently, in Output Compare mode
* - Select the output compare modes (++) Select the output compare modes
* - Select the Polarities of each channel (++) Select the Polarities of each channel
* - Set/Get the Capture/Compare register values (++) Set/Get the Capture/Compare register values
* - Select the Output Compare Fast mode (++) Select the Output Compare Fast mode
* - Select the Output Compare Forced mode (++) Select the Output Compare Forced mode
* - Output Compare-Preload Configuration (++) Output Compare-Preload Configuration
* - Clear Output Compare Reference (++) Clear Output Compare Reference
* - Select the OCREF Clear signal (++) Select the OCREF Clear signal
* - Enable/Disable the Capture/Compare Channels (++) Enable/Disable the Capture/Compare Channels
*
* 3. TIM Input Capture management: this group includes all needed (#) TIM Input Capture management: this group includes all needed
* functions to configure the Capture/Compare unit used in functions to configure the Capture/Compare unit used in
* Input Capture mode: Input Capture mode:
* - Configure each channel in input capture mode (++) Configure each channel in input capture mode
* - Configure Channel1/2 in PWM Input mode (++) Configure Channel1/2 in PWM Input mode
* - Set the Input Capture Prescaler (++) Set the Input Capture Prescaler
* - Get the Capture/Compare values (++) Get the Capture/Compare values
*
* 4. Advanced-control timers (TIM1 and TIM8) specific features (#) Advanced-control timers (TIM1 and TIM8) specific features
* - Configures the Break input, dead time, Lock level, the OSSI, (++) Configures the Break input, dead time, Lock level, the OSSI,
* the OSSR State and the AOE(automatic output enable) the OSSR State and the AOE(automatic output enable)
* - Enable/Disable the TIM peripheral Main Outputs (++) Enable/Disable the TIM peripheral Main Outputs
* - Select the Commutation event (++) Select the Commutation event
* - Set/Reset the Capture Compare Preload Control bit (++) Set/Reset the Capture Compare Preload Control bit
*
* 5. TIM interrupts, DMA and flags management (#) TIM interrupts, DMA and flags management
* - Enable/Disable interrupt sources (++) Enable/Disable interrupt sources
* - Get flags status (++) Get flags status
* - Clear flags/ Pending bits (++) Clear flags/ Pending bits
* - Enable/Disable DMA requests (++) Enable/Disable DMA requests
* - Configure DMA burst mode (++) Configure DMA burst mode
* - Select CaptureCompare DMA request (++) Select CaptureCompare DMA request
*
* 6. TIM clocks management: this group includes all needed functions (#) TIM clocks management: this group includes all needed functions
* to configure the clock controller unit: to configure the clock controller unit:
* - Select internal/External clock (++) Select internal/External clock
* - Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx
*
* 7. TIM synchronization management: this group includes all needed (#) TIM synchronization management: this group includes all needed
* functions to configure the Synchronization unit: functions to configure the Synchronization unit:
* - Select Input Trigger (++) Select Input Trigger
* - Select Output Trigger (++) Select Output Trigger
* - Select Master Slave Mode (++) Select Master Slave Mode
* - ETR Configuration when used as external trigger (++) ETR Configuration when used as external trigger
*
* 8. TIM specific interface management, this group includes all (#) TIM specific interface management, this group includes all
* needed functions to use the specific TIM interface: needed functions to use the specific TIM interface:
* - Encoder Interface Configuration (++) Encoder Interface Configuration
* - Select Hall Sensor (++) Select Hall Sensor
*
* 9. TIM specific remapping management includes the Remapping (#) TIM specific remapping management includes the Remapping
* configuration of specific timers configuration of specific timers
*
* @endverbatim @endverbatim
*
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -157,29 +162,30 @@ static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
TimeBase management functions ##### TimeBase management functions #####
=============================================================================== ===============================================================================
===================================================================
TIM Driver: how to use it in Timing(Time base) Mode ##### TIM Driver: how to use it in Timing(Time base) Mode #####
=================================================================== ===============================================================================
To use the Timer in Timing(Time base) mode, the following steps are mandatory: [..]
To use the Timer in Timing(Time base) mode, the following steps are mandatory:
1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
2. Fill the TIM_TimeBaseInitStruct with the desired parameters. (#) Fill the TIM_TimeBaseInitStruct with the desired parameters.
3. Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit
with the corresponding configuration with the corresponding configuration
4. Enable the NVIC if you need to generate the update interrupt. (#) Enable the NVIC if you need to generate the update interrupt.
5. Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update) (#) Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update)
6. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
Note1: All other functions can be used separately to modify, if needed, -@- All other functions can be used separately to modify, if needed,
a specific feature of the Timer. a specific feature of the Timer.
@endverbatim @endverbatim
* @{ * @{
@@ -609,46 +615,48 @@ void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Output Compare management functions ##### Output Compare management functions #####
=============================================================================== ===============================================================================
===================================================================
TIM Driver: how to use it in Output Compare Mode ##### TIM Driver: how to use it in Output Compare Mode #####
=================================================================== ===============================================================================
To use the Timer in Output Compare mode, the following steps are mandatory: [..]
To use the Timer in Output Compare mode, the following steps are mandatory:
1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE)
function
2. Configure the TIM pins by configuring the corresponding GPIO pins (#) Configure the TIM pins by configuring the corresponding GPIO pins
2. Configure the Time base unit as described in the first part of this driver, (#) Configure the Time base unit as described in the first part of this driver,
if needed, else the Timer will run with the default configuration: (++) if needed, else the Timer will run with the default configuration:
- Autoreload value = 0xFFFF Autoreload value = 0xFFFF
- Prescaler value = 0x0000 (++) Prescaler value = 0x0000
- Counter mode = Up counting (++) Counter mode = Up counting
- Clock Division = TIM_CKD_DIV1 (++) Clock Division = TIM_CKD_DIV1
3. Fill the TIM_OCInitStruct with the desired parameters including: (#) Fill the TIM_OCInitStruct with the desired parameters including:
- The TIM Output Compare mode: TIM_OCMode (++) The TIM Output Compare mode: TIM_OCMode
- TIM Output State: TIM_OutputState (++) TIM Output State: TIM_OutputState
- TIM Pulse value: TIM_Pulse (++) TIM Pulse value: TIM_Pulse
- TIM Output Compare Polarity : TIM_OCPolarity (++) TIM Output Compare Polarity : TIM_OCPolarity
4. Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired
corresponding configuration channel with the corresponding configuration
5. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
Note1: All other functions can be used separately to modify, if needed, -@- All other functions can be used separately to modify, if needed,
a specific feature of the Timer. a specific feature of the Timer.
Note2: In case of PWM mode, this function is mandatory: -@- In case of PWM mode, this function is mandatory:
TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE);
Note3: If the corresponding interrupt or DMA request are needed, the user should: -@- If the corresponding interrupt or DMA request are needed, the user should:
1. Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). (+@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests).
2. Enable the corresponding interrupt (or DMA request) using the function (+@) Enable the corresponding interrupt (or DMA request) using the function
TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
@endverbatim @endverbatim
* @{ * @{
@@ -1831,49 +1839,51 @@ void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Input Capture management functions ##### Input Capture management functions #####
=============================================================================== ===============================================================================
=================================================================== ##### TIM Driver: how to use it in Input Capture Mode #####
TIM Driver: how to use it in Input Capture Mode ===============================================================================
=================================================================== [..]
To use the Timer in Input Capture mode, the following steps are mandatory: To use the Timer in Input Capture mode, the following steps are mandatory:
1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE)
function
2. Configure the TIM pins by configuring the corresponding GPIO pins (#) Configure the TIM pins by configuring the corresponding GPIO pins
2. Configure the Time base unit as described in the first part of this driver, (#) Configure the Time base unit as described in the first part of this driver,
if needed, else the Timer will run with the default configuration: if needed, else the Timer will run with the default configuration:
- Autoreload value = 0xFFFF (++) Autoreload value = 0xFFFF
- Prescaler value = 0x0000 (++) Prescaler value = 0x0000
- Counter mode = Up counting (++) Counter mode = Up counting
- Clock Division = TIM_CKD_DIV1 (++) Clock Division = TIM_CKD_DIV1
3. Fill the TIM_ICInitStruct with the desired parameters including: (#) Fill the TIM_ICInitStruct with the desired parameters including:
- TIM Channel: TIM_Channel (++) TIM Channel: TIM_Channel
- TIM Input Capture polarity: TIM_ICPolarity (++) TIM Input Capture polarity: TIM_ICPolarity
- TIM Input Capture selection: TIM_ICSelection (++) TIM Input Capture selection: TIM_ICSelection
- TIM Input Capture Prescaler: TIM_ICPrescaler (++) TIM Input Capture Prescaler: TIM_ICPrescaler
- TIM Input CApture filter value: TIM_ICFilter (++) TIM Input CApture filter value: TIM_ICFilter
4. Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel
corresponding configuration and to measure only frequency or duty cycle of the input signal, with the corresponding configuration and to measure only frequency
or, or duty cycle of the input signal, or, Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct)
Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the to configure the desired channels with the corresponding configuration
corresponding configuration and to measure the frequency and the duty cycle of the input signal and to measure the frequency and the duty cycle of the input signal
5. Enable the NVIC or the DMA to read the measured frequency. (#) Enable the NVIC or the DMA to read the measured frequency.
6. Enable the corresponding interrupt (or DMA request) to read the Captured value, (#) Enable the corresponding interrupt (or DMA request) to read the Captured
using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx)
(or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
7. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
8. Use TIM_GetCapturex(TIMx); to read the captured value. (#) Use TIM_GetCapturex(TIMx); to read the captured value.
Note1: All other functions can be used separately to modify, if needed, -@- All other functions can be used separately to modify, if needed,
a specific feature of the Timer. a specific feature of the Timer.
@endverbatim @endverbatim
* @{ * @{
@@ -2176,23 +2186,23 @@ void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Advanced-control timers (TIM1 and TIM8) specific features ##### Advanced-control timers (TIM1 and TIM8) specific features #####
=============================================================================== ===============================================================================
=================================================================== ##### TIM Driver: how to use the Break feature #####
TIM Driver: how to use the Break feature ===============================================================================
=================================================================== [..]
After configuring the Timer channel(s) in the appropriate Output Compare mode: After configuring the Timer channel(s) in the appropriate Output Compare mode:
1. Fill the TIM_BDTRInitStruct with the desired parameters for the Timer (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer
Break Polarity, dead time, Lock level, the OSSI/OSSR State and the Break Polarity, dead time, Lock level, the OSSI/OSSR State and the
AOE(automatic output enable). AOE(automatic output enable).
2. Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer
3. Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE)
4. Once the break even occurs, the Timer's output signals are put in reset (#) Once the break even occurs, the Timer's output signals are put in reset
state or in a known state (according to the configuration made in state or in a known state (according to the configuration made in
TIM_BDTRConfig() function). TIM_BDTRConfig() function).
@@ -2327,7 +2337,7 @@ void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Interrupts, DMA and flags management functions ##### Interrupts, DMA and flags management functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -2657,7 +2667,7 @@ void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Clocks management functions ##### Clocks management functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -2832,29 +2842,32 @@ void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Synchronization management functions ##### Synchronization management functions #####
=============================================================================== ===============================================================================
=================================================================== ##### TIM Driver: how to use it in synchronization Mode #####
TIM Driver: how to use it in synchronization Mode ===============================================================================
=================================================================== [..]
Case of two/several Timers
************************** *** Case of two/several Timers ***
1. Configure the Master Timers using the following functions: ==================================
- void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); [..]
- void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); (#) Configure the Master Timers using the following functions:
2. Configure the Slave Timers using the following functions: (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
- void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
- void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); (#) Configure the Slave Timers using the following functions:
(++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
(++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
Case of Timers and external trigger(ETR pin) *** Case of Timers and external trigger(ETR pin) ***
******************************************** ====================================================
1. Configure the External trigger using this function: [..]
- void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, (#) Configure the External trigger using this function:
(++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
uint16_t ExtTRGFilter); uint16_t ExtTRGFilter);
2. Configure the Slave Timers using the following functions: (#) Configure the Slave Timers using the following functions:
- void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
- void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
@endverbatim @endverbatim
* @{ * @{
@@ -3027,7 +3040,7 @@ void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Specific interface management functions ##### Specific interface management functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -3132,7 +3145,7 @@ void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Specific remapping management function ##### Specific remapping management function #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -3349,4 +3362,4 @@ static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

705
example/libs/StmCoreNPheriph/src/stm32f4xx_usart.c
View File

@@ -2,82 +2,89 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_usart.c * @file stm32f4xx_usart.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides firmware functions to manage the following * @brief This file provides firmware functions to manage the following
* functionalities of the Universal synchronous asynchronous receiver * functionalities of the Universal synchronous asynchronous receiver
* transmitter (USART): * transmitter (USART):
* - Initialization and Configuration * + Initialization and Configuration
* - Data transfers * + Data transfers
* - Multi-Processor Communication * + Multi-Processor Communication
* - LIN mode * + LIN mode
* - Half-duplex mode * + Half-duplex mode
* - Smartcard mode * + Smartcard mode
* - IrDA mode * + IrDA mode
* - DMA transfers management * + DMA transfers management
* - Interrupts and flags management * + Interrupts and flags management
* *
* @verbatim @verbatim
* ===============================================================================
* =================================================================== ##### How to use this driver #####
* How to use this driver ===============================================================================
* =================================================================== [..]
* 1. Enable peripheral clock using the follwoing functions (#) Enable peripheral clock using the following functions
* RCC_APB2PeriphClockCmd(RCC_APB2Periph_USARTx, ENABLE) for USART1 and USART6 RCC_APB2PeriphClockCmd(RCC_APB2Periph_USARTx, ENABLE) for USART1 and USART6
* RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) for USART2, USART3, UART4 or UART5. RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) for USART2, USART3,
* UART4 or UART5.
* 2. According to the USART mode, enable the GPIO clocks using
* RCC_AHB1PeriphClockCmd() function. (The I/O can be TX, RX, CTS, (#) According to the USART mode, enable the GPIO clocks using
* or/and SCLK). RCC_AHB1PeriphClockCmd() function. (The I/O can be TX, RX, CTS,
* or/and SCLK).
* 3. Peripheral's alternate function:
* - Connect the pin to the desired peripherals' Alternate (#) Peripheral's alternate function:
* Function (AF) using GPIO_PinAFConfig() function (++) Connect the pin to the desired peripherals' Alternate
* - Configure the desired pin in alternate function by: Function (AF) using GPIO_PinAFConfig() function
* GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF (++) Configure the desired pin in alternate function by:
* - Select the type, pull-up/pull-down and output speed via GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
* GPIO_PuPd, GPIO_OType and GPIO_Speed members (++) Select the type, pull-up/pull-down and output speed via
* - Call GPIO_Init() function GPIO_PuPd, GPIO_OType and GPIO_Speed members
* (++) Call GPIO_Init() function
* 4. Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
* flow control and Mode(Receiver/Transmitter) using the USART_Init() (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
* function. flow control and Mode(Receiver/Transmitter) using the USART_Init()
* function.
* 5. For synchronous mode, enable the clock and program the polarity,
* phase and last bit using the USART_ClockInit() function. (#) For synchronous mode, enable the clock and program the polarity,
* phase and last bit using the USART_ClockInit() function.
* 5. Enable the NVIC and the corresponding interrupt using the function
* USART_ITConfig() if you need to use interrupt mode. (#) Enable the NVIC and the corresponding interrupt using the function
* USART_ITConfig() if you need to use interrupt mode.
* 6. When using the DMA mode
* - Configure the DMA using DMA_Init() function (#) When using the DMA mode
* - Active the needed channel Request using USART_DMACmd() function (++) Configure the DMA using DMA_Init() function
* (++) Active the needed channel Request using USART_DMACmd() function
* 7. Enable the USART using the USART_Cmd() function.
* (#) Enable the USART using the USART_Cmd() function.
* 8. Enable the DMA using the DMA_Cmd() function, when using DMA mode.
* (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.
* Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections
* for more details -@- Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections
* for more details
* In order to reach higher communication baudrates, it is possible to
* enable the oversampling by 8 mode using the function USART_OverSampling8Cmd(). [..]
* This function should be called after enabling the USART clock (RCC_APBxPeriphClockCmd()) In order to reach higher communication baudrates, it is possible to
* and before calling the function USART_Init(). enable the oversampling by 8 mode using the function USART_OverSampling8Cmd().
* This function should be called after enabling the USART clock (RCC_APBxPeriphClockCmd())
* @endverbatim and before calling the function USART_Init().
*
@endverbatim
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -126,19 +133,19 @@
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Initialization and Configuration functions ##### Initialization and Configuration functions #####
=============================================================================== ===============================================================================
[..]
This subsection provides a set of functions allowing to initialize the USART This subsection provides a set of functions allowing to initialize the USART
in asynchronous and in synchronous modes. in asynchronous and in synchronous modes.
- For the asynchronous mode only these parameters can be configured: (+) For the asynchronous mode only these parameters can be configured:
- Baud Rate (++) Baud Rate
- Word Length (++) Word Length
- Stop Bit (++) Stop Bit
- Parity: If the parity is enabled, then the MSB bit of the data written (++) Parity: If the parity is enabled, then the MSB bit of the data written
in the data register is transmitted but is changed by the parity bit. in the data register is transmitted but is changed by the parity bit.
Depending on the frame length defined by the M bit (8-bits or 9-bits), Depending on the frame length defined by the M bit (8-bits or 9-bits),
the possible USART frame formats are as listed in the following table: the possible USART frame formats are as listed in the following table:
+-------------------------------------------------------------+ +-------------------------------------------------------------+
| M bit | PCE bit | USART frame | | M bit | PCE bit | USART frame |
|---------------------|---------------------------------------| |---------------------|---------------------------------------|
@@ -150,20 +157,22 @@
|---------|-----------|---------------------------------------| |---------|-----------|---------------------------------------|
| 1 | 1 | | SB | 8 bit data | PB | STB | | | 1 | 1 | | SB | 8 bit data | PB | STB | |
+-------------------------------------------------------------+ +-------------------------------------------------------------+
- Hardware flow control (++) Hardware flow control
- Receiver/transmitter modes (++) Receiver/transmitter modes
The USART_Init() function follows the USART asynchronous configuration procedure [..]
(details for the procedure are available in reference manual (RM0090)). The USART_Init() function follows the USART asynchronous configuration
procedure (details for the procedure are available in reference manual (RM0090)).
- For the synchronous mode in addition to the asynchronous mode parameters these (+) For the synchronous mode in addition to the asynchronous mode parameters these
parameters should be also configured: parameters should be also configured:
- USART Clock Enabled (++) USART Clock Enabled
- USART polarity (++) USART polarity
- USART phase (++) USART phase
- USART LastBit (++) USART LastBit
These parameters can be configured using the USART_ClockInit() function. [..]
These parameters can be configured using the USART_ClockInit() function.
@endverbatim @endverbatim
* @{ * @{
@@ -171,7 +180,7 @@
/** /**
* @brief Deinitializes the USARTx peripheral registers to their default reset values. * @brief Deinitializes the USARTx peripheral registers to their default reset values.
* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral. * UART peripheral.
* @retval None * @retval None
*/ */
@@ -204,13 +213,23 @@ void USART_DeInit(USART_TypeDef* USARTx)
{ {
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
}
else if (USARTx == USART6)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE);
}
else if (USARTx == UART7)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, DISABLE);
} }
else else
{ {
if (USARTx == USART6) if (USARTx == UART8)
{ {
RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, DISABLE);
} }
} }
} }
@@ -218,7 +237,7 @@ void USART_DeInit(USART_TypeDef* USARTx)
/** /**
* @brief Initializes the USARTx peripheral according to the specified * @brief Initializes the USARTx peripheral according to the specified
* parameters in the USART_InitStruct . * parameters in the USART_InitStruct .
* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral. * UART peripheral.
* @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains
* the configuration information for the specified USART peripheral. * the configuration information for the specified USART peripheral.
@@ -399,7 +418,7 @@ void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
/** /**
* @brief Enables or disables the specified USART peripheral. * @brief Enables or disables the specified USART peripheral.
* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral. * UART peripheral.
* @param NewState: new state of the USARTx peripheral. * @param NewState: new state of the USARTx peripheral.
* This parameter can be: ENABLE or DISABLE. * This parameter can be: ENABLE or DISABLE.
@@ -425,7 +444,7 @@ void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
/** /**
* @brief Sets the system clock prescaler. * @brief Sets the system clock prescaler.
* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral. * UART peripheral.
* @param USART_Prescaler: specifies the prescaler clock. * @param USART_Prescaler: specifies the prescaler clock.
* @note The function is used for IrDA mode with UART4 and UART5. * @note The function is used for IrDA mode with UART4 and UART5.
@@ -446,7 +465,7 @@ void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
* @brief Enables or disables the USART's 8x oversampling mode. * @brief Enables or disables the USART's 8x oversampling mode.
* @note This function has to be called before calling USART_Init() function * @note This function has to be called before calling USART_Init() function
* in order to have correct baudrate Divider value. * in order to have correct baudrate Divider value.
* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral. * UART peripheral.
* @param NewState: new state of the USART 8x oversampling mode. * @param NewState: new state of the USART 8x oversampling mode.
* This parameter can be: ENABLE or DISABLE. * This parameter can be: ENABLE or DISABLE.
@@ -472,7 +491,7 @@ void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
/** /**
* @brief Enables or disables the USART's one bit sampling method. * @brief Enables or disables the USART's one bit sampling method.
* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral. * UART peripheral.
* @param NewState: new state of the USART one bit sampling method. * @param NewState: new state of the USART one bit sampling method.
* This parameter can be: ENABLE or DISABLE. * This parameter can be: ENABLE or DISABLE.
@@ -505,24 +524,24 @@ void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Data transfers functions ##### Data transfers functions #####
=============================================================================== ===============================================================================
[..]
This subsection provides a set of functions allowing to manage the USART data This subsection provides a set of functions allowing to manage the USART data
transfers. transfers.
[..]
During an USART reception, data shifts in least significant bit first through During an USART reception, data shifts in least significant bit first through
the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) the RX pin. In this mode, the USART_DR register consists of a buffer (RDR)
between the internal bus and the received shift register. between the internal bus and the received shift register.
[..]
When a transmission is taking place, a write instruction to the USART_DR register When a transmission is taking place, a write instruction to the USART_DR register
stores the data in the TDR register and which is copied in the shift register stores the data in the TDR register and which is copied in the shift register
at the end of the current transmission. at the end of the current transmission.
[..]
The read access of the USART_DR register can be done using the USART_ReceiveData() The read access of the USART_DR register can be done using the USART_ReceiveData()
function and returns the RDR buffered value. Whereas a write access to the USART_DR function and returns the RDR buffered value. Whereas a write access to the USART_DR
can be done using USART_SendData() function and stores the written data into can be done using USART_SendData() function and stores the written data into
TDR buffer. TDR buffer.
@endverbatim @endverbatim
* @{ * @{
@@ -530,7 +549,7 @@ void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
/** /**
* @brief Transmits single data through the USARTx peripheral. * @brief Transmits single data through the USARTx peripheral.
* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral. * UART peripheral.
* @param Data: the data to transmit. * @param Data: the data to transmit.
* @retval None * @retval None
@@ -547,7 +566,7 @@ void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
/** /**
* @brief Returns the most recent received data by the USARTx peripheral. * @brief Returns the most recent received data by the USARTx peripheral.
* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral. * UART peripheral.
* @retval The received data. * @retval The received data.
*/ */
@@ -569,27 +588,28 @@ uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Multi-Processor Communication functions ##### Multi-Processor Communication functions #####
=============================================================================== ===============================================================================
[..]
This subsection provides a set of functions allowing to manage the USART This subsection provides a set of functions allowing to manage the USART
multiprocessor communication. multiprocessor communication.
[..]
For instance one of the USARTs can be the master, its TX output is connected to For instance one of the USARTs can be the master, its TX output is connected
the RX input of the other USART. The others are slaves, their respective TX outputs to the RX input of the other USART. The others are slaves, their respective
are logically ANDed together and connected to the RX input of the master. TX outputs are logically ANDed together and connected to the RX input of the
master.
USART multiprocessor communication is possible through the following procedure: [..]
1. Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode transmitter USART multiprocessor communication is possible through the following procedure:
or Mode receiver and hardware flow control values using the USART_Init() (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode
function. transmitter or Mode receiver and hardware flow control values using
2. Configures the USART address using the USART_SetAddress() function. the USART_Init() function.
3. Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark) (#) Configures the USART address using the USART_SetAddress() function.
using USART_WakeUpConfig() function only for the slaves. (#) Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark)
4. Enable the USART using the USART_Cmd() function. using USART_WakeUpConfig() function only for the slaves.
5. Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function. (#) Enable the USART using the USART_Cmd() function.
(#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function.
The USART Slave exit from mute mode when receive the wake up condition. [..]
The USART Slave exit from mute mode when receive the wake up condition.
@endverbatim @endverbatim
* @{ * @{
@@ -597,7 +617,7 @@ uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
/** /**
* @brief Sets the address of the USART node. * @brief Sets the address of the USART node.
* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral. * UART peripheral.
* @param USART_Address: Indicates the address of the USART node. * @param USART_Address: Indicates the address of the USART node.
* @retval None * @retval None
@@ -616,7 +636,7 @@ void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
/** /**
* @brief Determines if the USART is in mute mode or not. * @brief Determines if the USART is in mute mode or not.
* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral. * UART peripheral.
* @param NewState: new state of the USART mute mode. * @param NewState: new state of the USART mute mode.
* This parameter can be: ENABLE or DISABLE. * This parameter can be: ENABLE or DISABLE.
@@ -641,7 +661,7 @@ void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
} }
/** /**
* @brief Selects the USART WakeUp method. * @brief Selects the USART WakeUp method.
* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral. * UART peripheral.
* @param USART_WakeUp: specifies the USART wakeup method. * @param USART_WakeUp: specifies the USART wakeup method.
* This parameter can be one of the following values: * This parameter can be one of the following values:
@@ -668,41 +688,41 @@ void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
LIN mode functions ##### LIN mode functions #####
=============================================================================== ===============================================================================
[..]
This subsection provides a set of functions allowing to manage the USART LIN
Mode communication.
[..]
In LIN mode, 8-bit data format with 1 stop bit is required in accordance with
the LIN standard.
[..]
Only this LIN Feature is supported by the USART IP:
(+) LIN Master Synchronous Break send capability and LIN slave break detection
capability : 13-bit break generation and 10/11 bit break detection
This subsection provides a set of functions allowing to manage the USART LIN [..]
Mode communication. USART LIN Master transmitter communication is possible through the following
procedure:
In LIN mode, 8-bit data format with 1 stop bit is required in accordance with (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity,
the LIN standard.
Only this LIN Feature is supported by the USART IP:
- LIN Master Synchronous Break send capability and LIN slave break detection
capability : 13-bit break generation and 10/11 bit break detection
USART LIN Master transmitter communication is possible through the following procedure:
1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity,
Mode transmitter or Mode receiver and hardware flow control values using Mode transmitter or Mode receiver and hardware flow control values using
the USART_Init() function. the USART_Init() function.
2. Enable the USART using the USART_Cmd() function. (#) Enable the USART using the USART_Cmd() function.
3. Enable the LIN mode using the USART_LINCmd() function. (#) Enable the LIN mode using the USART_LINCmd() function.
4. Send the break character using USART_SendBreak() function. (#) Send the break character using USART_SendBreak() function.
[..]
USART LIN Master receiver communication is possible through the following procedure:
(#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity,
Mode transmitter or Mode receiver and hardware flow control values using
the USART_Init() function.
(#) Enable the USART using the USART_Cmd() function.
(#) Configures the break detection length using the USART_LINBreakDetectLengthConfig()
function.
(#) Enable the LIN mode using the USART_LINCmd() function.
USART LIN Master receiver communication is possible through the following procedure: -@- In LIN mode, the following bits must be kept cleared:
1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, (+@) CLKEN in the USART_CR2 register,
Mode transmitter or Mode receiver and hardware flow control values using (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.
the USART_Init() function.
2. Enable the USART using the USART_Cmd() function.
3. Configures the break detection length using the USART_LINBreakDetectLengthConfig()
function.
4. Enable the LIN mode using the USART_LINCmd() function.
@note In LIN mode, the following bits must be kept cleared:
- CLKEN in the USART_CR2 register,
- STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.
@endverbatim @endverbatim
* @{ * @{
@@ -710,7 +730,7 @@ void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)
/** /**
* @brief Sets the USART LIN Break detection length. * @brief Sets the USART LIN Break detection length.
* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral. * UART peripheral.
* @param USART_LINBreakDetectLength: specifies the LIN break detection length. * @param USART_LINBreakDetectLength: specifies the LIN break detection length.
* This parameter can be one of the following values: * This parameter can be one of the following values:
@@ -730,7 +750,7 @@ void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINB
/** /**
* @brief Enables or disables the USART's LIN mode. * @brief Enables or disables the USART's LIN mode.
* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral. * UART peripheral.
* @param NewState: new state of the USART LIN mode. * @param NewState: new state of the USART LIN mode.
* This parameter can be: ENABLE or DISABLE. * This parameter can be: ENABLE or DISABLE.
@@ -756,7 +776,7 @@ void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
/** /**
* @brief Transmits break characters. * @brief Transmits break characters.
* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral. * UART peripheral.
* @retval None * @retval None
*/ */
@@ -778,28 +798,28 @@ void USART_SendBreak(USART_TypeDef* USARTx)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Half-duplex mode function ##### Half-duplex mode function #####
=============================================================================== ===============================================================================
[..]
This subsection provides a set of functions allowing to manage the USART This subsection provides a set of functions allowing to manage the USART
Half-duplex communication. Half-duplex communication.
[..]
The USART can be configured to follow a single-wire half-duplex protocol where The USART can be configured to follow a single-wire half-duplex protocol where
the TX and RX lines are internally connected. the TX and RX lines are internally connected.
[..]
USART Half duplex communication is possible through the following procedure: USART Half duplex communication is possible through the following procedure:
1. Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter
or Mode receiver and hardware flow control values using the USART_Init() or Mode receiver and hardware flow control values using the USART_Init()
function. function.
2. Configures the USART address using the USART_SetAddress() function. (#) Configures the USART address using the USART_SetAddress() function.
3. Enable the USART using the USART_Cmd() function. (#) Enable the USART using the USART_Cmd() function.
4. Enable the half duplex mode using USART_HalfDuplexCmd() function. (#) Enable the half duplex mode using USART_HalfDuplexCmd() function.
@note The RX pin is no longer used -@- The RX pin is no longer used
@note In Half-duplex mode the following bits must be kept cleared: -@- In Half-duplex mode the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register. (+@) LINEN and CLKEN bits in the USART_CR2 register.
- SCEN and IREN bits in the USART_CR3 register. (+@) SCEN and IREN bits in the USART_CR3 register.
@endverbatim @endverbatim
* @{ * @{
@@ -807,7 +827,7 @@ void USART_SendBreak(USART_TypeDef* USARTx)
/** /**
* @brief Enables or disables the USART's Half Duplex communication. * @brief Enables or disables the USART's Half Duplex communication.
* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral. * UART peripheral.
* @param NewState: new state of the USART Communication. * @param NewState: new state of the USART Communication.
* This parameter can be: ENABLE or DISABLE. * This parameter can be: ENABLE or DISABLE.
@@ -841,51 +861,50 @@ void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Smartcard mode functions ##### Smartcard mode functions #####
=============================================================================== ===============================================================================
[..]
This subsection provides a set of functions allowing to manage the USART
Smartcard communication.
[..]
The Smartcard interface is designed to support asynchronous protocol Smartcards as
defined in the ISO 7816-3 standard.
[..]
The USART can provide a clock to the smartcard through the SCLK output.
In smartcard mode, SCLK is not associated to the communication but is simply derived
from the internal peripheral input clock through a 5-bit prescaler.
[..]
Smartcard communication is possible through the following procedure:
(#) Configures the Smartcard Prescaler using the USART_SetPrescaler() function.
(#) Configures the Smartcard Guard Time using the USART_SetGuardTime() function.
(#) Program the USART clock using the USART_ClockInit() function as following:
(++) USART Clock enabled
(++) USART CPOL Low
(++) USART CPHA on first edge
(++) USART Last Bit Clock Enabled
(#) Program the Smartcard interface using the USART_Init() function as following:
(++) Word Length = 9 Bits
(++) 1.5 Stop Bit
(++) Even parity
(++) BaudRate = 12096 baud
(++) Hardware flow control disabled (RTS and CTS signals)
(++) Tx and Rx enabled
(#) POptionally you can enable the parity error interrupt using the USART_ITConfig()
function
(#) PEnable the USART using the USART_Cmd() function.
(#) PEnable the Smartcard NACK using the USART_SmartCardNACKCmd() function.
(#) PEnable the Smartcard interface using the USART_SmartCardCmd() function.
This subsection provides a set of functions allowing to manage the USART Please refer to the ISO 7816-3 specification for more details.
Smartcard communication.
The Smartcard interface is designed to support asynchronous protocol Smartcards as
defined in the ISO 7816-3 standard.
The USART can provide a clock to the smartcard through the SCLK output. -@- It is also possible to choose 0.5 stop bit for receiving but it is recommended
In smartcard mode, SCLK is not associated to the communication but is simply derived to use 1.5 stop bits for both transmitting and receiving to avoid switching
from the internal peripheral input clock through a 5-bit prescaler. between the two configurations.
-@- In smartcard mode, the following bits must be kept cleared:
Smartcard communication is possible through the following procedure: (+@) LINEN bit in the USART_CR2 register.
1. Configures the Smartcard Prescaler using the USART_SetPrescaler() function. (+@) HDSEL and IREN bits in the USART_CR3 register.
2. Configures the Smartcard Guard Time using the USART_SetGuardTime() function. -@- Smartcard mode is available on USART peripherals only (not available on UART4
3. Program the USART clock using the USART_ClockInit() function as following: and UART5 peripherals).
- USART Clock enabled
- USART CPOL Low
- USART CPHA on first edge
- USART Last Bit Clock Enabled
4. Program the Smartcard interface using the USART_Init() function as following:
- Word Length = 9 Bits
- 1.5 Stop Bit
- Even parity
- BaudRate = 12096 baud
- Hardware flow control disabled (RTS and CTS signals)
- Tx and Rx enabled
5. Optionally you can enable the parity error interrupt using the USART_ITConfig()
function
6. Enable the USART using the USART_Cmd() function.
7. Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function.
8. Enable the Smartcard interface using the USART_SmartCardCmd() function.
Please refer to the ISO 7816-3 specification for more details.
@note It is also possible to choose 0.5 stop bit for receiving but it is recommended
to use 1.5 stop bits for both transmitting and receiving to avoid switching
between the two configurations.
@note In smartcard mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register.
- HDSEL and IREN bits in the USART_CR3 register.
@note Smartcard mode is available on USART peripherals only (not available on UART4
and UART5 peripherals).
@endverbatim @endverbatim
* @{ * @{
@@ -968,36 +987,36 @@ void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
IrDA mode functions ##### IrDA mode functions #####
=============================================================================== ===============================================================================
[..]
This subsection provides a set of functions allowing to manage the USART
IrDA communication.
[..]
IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
While receiving data, transmission should be avoided as the data to be transmitted
could be corrupted.
[..]
IrDA communication is possible through the following procedure:
(#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver
modes and hardware flow control values using the USART_Init() function.
(#) Enable the USART using the USART_Cmd() function.
(#) Configures the IrDA pulse width by configuring the prescaler using
the USART_SetPrescaler() function.
(#) Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode
using the USART_IrDAConfig() function.
(#) Enable the IrDA using the USART_IrDACmd() function.
This subsection provides a set of functions allowing to manage the USART -@- A pulse of width less than two and greater than one PSC period(s) may or may
IrDA communication. not be rejected.
-@- The receiver set up time should be managed by software. The IrDA physical layer
IrDA is a half duplex communication protocol. If the Transmitter is busy, any data specification specifies a minimum of 10 ms delay between transmission and
on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver reception (IrDA is a half duplex protocol).
is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. -@- In IrDA mode, the following bits must be kept cleared:
While receiving data, transmission should be avoided as the data to be transmitted (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register.
could be corrupted. (+@) SCEN and HDSEL bits in the USART_CR3 register.
IrDA communication is possible through the following procedure:
1. Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver
modes and hardware flow control values using the USART_Init() function.
2. Enable the USART using the USART_Cmd() function.
3. Configures the IrDA pulse width by configuring the prescaler using
the USART_SetPrescaler() function.
4. Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode
using the USART_IrDAConfig() function.
5. Enable the IrDA using the USART_IrDACmd() function.
@note A pulse of width less than two and greater than one PSC period(s) may or may
not be rejected.
@note The receiver set up time should be managed by software. The IrDA physical layer
specification specifies a minimum of 10 ms delay between transmission and
reception (IrDA is a half duplex protocol).
@note In IrDA mode, the following bits must be kept cleared:
- LINEN, STOP and CLKEN bits in the USART_CR2 register.
- SCEN and HDSEL bits in the USART_CR3 register.
@endverbatim @endverbatim
* @{ * @{
@@ -1005,7 +1024,7 @@ void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
/** /**
* @brief Configures the USART's IrDA interface. * @brief Configures the USART's IrDA interface.
* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral. * UART peripheral.
* @param USART_IrDAMode: specifies the IrDA mode. * @param USART_IrDAMode: specifies the IrDA mode.
* This parameter can be one of the following values: * This parameter can be one of the following values:
@@ -1025,7 +1044,7 @@ void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)
/** /**
* @brief Enables or disables the USART's IrDA interface. * @brief Enables or disables the USART's IrDA interface.
* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral. * UART peripheral.
* @param NewState: new state of the IrDA mode. * @param NewState: new state of the IrDA mode.
* This parameter can be: ENABLE or DISABLE. * This parameter can be: ENABLE or DISABLE.
@@ -1058,7 +1077,7 @@ void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
DMA transfers management functions ##### DMA transfers management functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -1067,7 +1086,7 @@ void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
/** /**
* @brief Enables or disables the USART's DMA interface. * @brief Enables or disables the USART's DMA interface.
* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral. * UART peripheral.
* @param USART_DMAReq: specifies the DMA request. * @param USART_DMAReq: specifies the DMA request.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
@@ -1107,81 +1126,85 @@ void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Interrupts and flags management functions ##### Interrupts and flags management functions #####
=============================================================================== ===============================================================================
[..]
This subsection provides a set of functions allowing to configure the USART This subsection provides a set of functions allowing to configure the USART
Interrupts sources, DMA channels requests and check or clear the flags or Interrupts sources, DMA channels requests and check or clear the flags or
pending bits status. pending bits status.
The user should identify which mode will be used in his application to manage The user should identify which mode will be used in his application to manage
the communication: Polling mode, Interrupt mode or DMA mode. the communication: Polling mode, Interrupt mode or DMA mode.
Polling Mode *** Polling Mode ***
============= ====================
In Polling Mode, the SPI communication can be managed by 10 flags: [..]
1. USART_FLAG_TXE : to indicate the status of the transmit buffer register In Polling Mode, the SPI communication can be managed by 10 flags:
2. USART_FLAG_RXNE : to indicate the status of the receive buffer register (#) USART_FLAG_TXE : to indicate the status of the transmit buffer register
3. USART_FLAG_TC : to indicate the status of the transmit operation (#) USART_FLAG_RXNE : to indicate the status of the receive buffer register
4. USART_FLAG_IDLE : to indicate the status of the Idle Line (#) USART_FLAG_TC : to indicate the status of the transmit operation
5. USART_FLAG_CTS : to indicate the status of the nCTS input (#) USART_FLAG_IDLE : to indicate the status of the Idle Line
6. USART_FLAG_LBD : to indicate the status of the LIN break detection (#) USART_FLAG_CTS : to indicate the status of the nCTS input
7. USART_FLAG_NE : to indicate if a noise error occur (#) USART_FLAG_LBD : to indicate the status of the LIN break detection
8. USART_FLAG_FE : to indicate if a frame error occur (#) USART_FLAG_NE : to indicate if a noise error occur
9. USART_FLAG_PE : to indicate if a parity error occur (#) USART_FLAG_FE : to indicate if a frame error occur
10. USART_FLAG_ORE : to indicate if an Overrun error occur (#) USART_FLAG_PE : to indicate if a parity error occur
(#) USART_FLAG_ORE : to indicate if an Overrun error occur
[..]
In this Mode it is advised to use the following functions:
(+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
(+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
In this Mode it is advised to use the following functions: *** Interrupt Mode ***
- FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); ======================
- void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); [..]
In Interrupt Mode, the USART communication can be managed by 8 interrupt sources
and 10 pending bits:
Interrupt Mode (#) Pending Bits:
===============
In Interrupt Mode, the USART communication can be managed by 8 interrupt sources
and 10 pending bits:
Pending Bits: (##) USART_IT_TXE : to indicate the status of the transmit buffer register
------------- (##) USART_IT_RXNE : to indicate the status of the receive buffer register
1. USART_IT_TXE : to indicate the status of the transmit buffer register (##) USART_IT_TC : to indicate the status of the transmit operation
2. USART_IT_RXNE : to indicate the status of the receive buffer register (##) USART_IT_IDLE : to indicate the status of the Idle Line
3. USART_IT_TC : to indicate the status of the transmit operation (##) USART_IT_CTS : to indicate the status of the nCTS input
4. USART_IT_IDLE : to indicate the status of the Idle Line (##) USART_IT_LBD : to indicate the status of the LIN break detection
5. USART_IT_CTS : to indicate the status of the nCTS input (##) USART_IT_NE : to indicate if a noise error occur
6. USART_IT_LBD : to indicate the status of the LIN break detection (##) USART_IT_FE : to indicate if a frame error occur
7. USART_IT_NE : to indicate if a noise error occur (##) USART_IT_PE : to indicate if a parity error occur
8. USART_IT_FE : to indicate if a frame error occur (##) USART_IT_ORE : to indicate if an Overrun error occur
9. USART_IT_PE : to indicate if a parity error occur
10. USART_IT_ORE : to indicate if an Overrun error occur
Interrupt Source: (#) Interrupt Source:
-----------------
1. USART_IT_TXE : specifies the interrupt source for the Tx buffer empty
interrupt.
2. USART_IT_RXNE : specifies the interrupt source for the Rx buffer not
empty interrupt.
3. USART_IT_TC : specifies the interrupt source for the Transmit complete
interrupt.
4. USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt.
5. USART_IT_CTS : specifies the interrupt source for the CTS interrupt.
6. USART_IT_LBD : specifies the interrupt source for the LIN break detection
interrupt.
7. USART_IT_PE : specifies the interrupt source for the parity error interrupt.
8. USART_IT_ERR : specifies the interrupt source for the errors interrupt.
@note Some parameters are coded in order to use them as interrupt source or as pending bits. (##) USART_IT_TXE : specifies the interrupt source for the Tx buffer empty
interrupt.
(##) USART_IT_RXNE : specifies the interrupt source for the Rx buffer not
empty interrupt.
(##) USART_IT_TC : specifies the interrupt source for the Transmit complete
interrupt.
(##) USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt.
(##) USART_IT_CTS : specifies the interrupt source for the CTS interrupt.
(##) USART_IT_LBD : specifies the interrupt source for the LIN break detection
interrupt.
(##) USART_IT_PE : specifies the interrupt source for the parity error interrupt.
(##) USART_IT_ERR : specifies the interrupt source for the errors interrupt.
In this Mode it is advised to use the following functions: -@@- Some parameters are coded in order to use them as interrupt source
- void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); or as pending bits.
- ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); [..]
- void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); In this Mode it is advised to use the following functions:
(+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
(+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
(+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
DMA Mode *** DMA Mode ***
======== ================
In DMA Mode, the USART communication can be managed by 2 DMA Channel requests: [..]
1. USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request In DMA Mode, the USART communication can be managed by 2 DMA Channel requests:
2. USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request
(#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request
In this Mode it is advised to use the following function: [..]
- void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); In this Mode it is advised to use the following function:
(+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
@endverbatim @endverbatim
* @{ * @{
@@ -1189,7 +1212,7 @@ void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState
/** /**
* @brief Enables or disables the specified USART interrupts. * @brief Enables or disables the specified USART interrupts.
* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral. * UART peripheral.
* @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.
* This parameter can be one of the following values: * This parameter can be one of the following values:
@@ -1253,7 +1276,7 @@ void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState Ne
/** /**
* @brief Checks whether the specified USART flag is set or not. * @brief Checks whether the specified USART flag is set or not.
* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral. * UART peripheral.
* @param USART_FLAG: specifies the flag to check. * @param USART_FLAG: specifies the flag to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
@@ -1295,7 +1318,7 @@ FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)
/** /**
* @brief Clears the USARTx's pending flags. * @brief Clears the USARTx's pending flags.
* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral. * UART peripheral.
* @param USART_FLAG: specifies the flag to clear. * @param USART_FLAG: specifies the flag to clear.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
@@ -1335,7 +1358,7 @@ void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
/** /**
* @brief Checks whether the specified USART interrupt has occurred or not. * @brief Checks whether the specified USART interrupt has occurred or not.
* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral. * UART peripheral.
* @param USART_IT: specifies the USART interrupt source to check. * @param USART_IT: specifies the USART interrupt source to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
@@ -1402,7 +1425,7 @@ ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)
/** /**
* @brief Clears the USARTx's interrupt pending bits. * @brief Clears the USARTx's interrupt pending bits.
* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral. * UART peripheral.
* @param USART_IT: specifies the interrupt pending bit to clear. * @param USART_IT: specifies the interrupt pending bit to clear.
* This parameter can be one of the following values: * This parameter can be one of the following values:
@@ -1460,4 +1483,4 @@ void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

140
example/libs/StmCoreNPheriph/src/stm32f4xx_wwdg.c
View File

@@ -2,77 +2,81 @@
****************************************************************************** ******************************************************************************
* @file stm32f4xx_wwdg.c * @file stm32f4xx_wwdg.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.0.0 * @version V1.4.0
* @date 30-September-2011 * @date 04-August-2014
* @brief This file provides firmware functions to manage the following * @brief This file provides firmware functions to manage the following
* functionalities of the Window watchdog (WWDG) peripheral: * functionalities of the Window watchdog (WWDG) peripheral:
* - Prescaler, Refresh window and Counter configuration * + Prescaler, Refresh window and Counter configuration
* - WWDG activation * + WWDG activation
* - Interrupts and flags management * + Interrupts and flags management
* *
* @verbatim @verbatim
* ===============================================================================
* =================================================================== ##### WWDG features #####
* WWDG features ===============================================================================
* =================================================================== [..]
* Once enabled the WWDG generates a system reset on expiry of a programmed
* Once enabled the WWDG generates a system reset on expiry of a programmed time period, unless the program refreshes the counter (downcounter)
* time period, unless the program refreshes the counter (downcounter) before to reach 0x3F value (i.e. a reset is generated when the counter
* before to reach 0x3F value (i.e. a reset is generated when the counter value rolls over from 0x40 to 0x3F).
* value rolls over from 0x40 to 0x3F). An MCU reset is also generated if the counter value is refreshed
* An MCU reset is also generated if the counter value is refreshed before the counter has reached the refresh window value. This
* before the counter has reached the refresh window value. This implies that the counter must be refreshed in a limited window.
* implies that the counter must be refreshed in a limited window.
* Once enabled the WWDG cannot be disabled except by a system reset.
* Once enabled the WWDG cannot be disabled except by a system reset.
* WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
* WWDGRST flag in RCC_CSR register can be used to inform when a WWDG reset occurs.
* reset occurs.
* The WWDG counter input clock is derived from the APB clock divided
* The WWDG counter input clock is derived from the APB clock divided by a programmable prescaler.
* by a programmable prescaler.
* WWDG counter clock = PCLK1 / Prescaler
* WWDG counter clock = PCLK1 / Prescaler WWDG timeout = (WWDG counter clock) * (counter value)
* WWDG timeout = (WWDG counter clock) * (counter value)
* Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms
* Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms
* ##### How to use this driver #####
* =================================================================== ===============================================================================
* How to use this driver [..]
* =================================================================== (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function
* 1. Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function
* (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function
* 2. Configure the WWDG prescaler using WWDG_SetPrescaler() function
* (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function
* 3. Configure the WWDG refresh window using WWDG_SetWindowValue() function
* (#) Set the WWDG counter value and start it using WWDG_Enable() function.
* 4. Set the WWDG counter value and start it using WWDG_Enable() function. When the WWDG is enabled the counter value should be configured to
* When the WWDG is enabled the counter value should be configured to a value greater than 0x40 to prevent generating an immediate reset.
* a value greater than 0x40 to prevent generating an immediate reset.
* (#) Optionally you can enable the Early wakeup interrupt which is
* 5. Optionally you can enable the Early wakeup interrupt which is generated when the counter reach 0x40.
* generated when the counter reach 0x40. Once enabled this interrupt cannot be disabled except by a system reset.
* Once enabled this interrupt cannot be disabled except by a system reset.
* (#) Then the application program must refresh the WWDG counter at regular
* 6. Then the application program must refresh the WWDG counter at regular intervals during normal operation to prevent an MCU reset, using
* intervals during normal operation to prevent an MCU reset, using WWDG_SetCounter() function. This operation must occur only when
* WWDG_SetCounter() function. This operation must occur only when the counter value is lower than the refresh window value,
* the counter value is lower than the refresh window value, programmed using WWDG_SetWindowValue().
* programmed using WWDG_SetWindowValue().
* @endverbatim
* @endverbatim
*
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE *
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * You may not use this file except in compliance with the License.
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * You may obtain a copy of the License at:
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
****************************************************************************** ******************************************************************************
*/ */
@@ -119,7 +123,7 @@
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Prescaler, Refresh window and Counter configuration functions ##### Prescaler, Refresh window and Counter configuration functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -218,7 +222,7 @@ void WWDG_SetCounter(uint8_t Counter)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
WWDG activation function ##### WWDG activation function #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -247,7 +251,7 @@ void WWDG_Enable(uint8_t Counter)
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
Interrupts and flags management functions ##### Interrupts and flags management functions #####
=============================================================================== ===============================================================================
@endverbatim @endverbatim
@@ -300,4 +304,4 @@ void WWDG_ClearFlag(void)
* @} * @}
*/ */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/