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Updated pheriph driver to 1.4

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This commit is contained in:
t-moe
2015-03-02 20:01:54 +01:00
parent cc41f75734
commit 6967573645
73 changed files with 16674 additions and 5575 deletions
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814
example/libs/StmCoreNPheriph/inc/core_cm4.h
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344
example/libs/StmCoreNPheriph/inc/core_cm4_simd.h
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@@ -1,29 +1,43 @@
/**************************************************************************//**
* @file core_cm4_simd.h
* @brief CMSIS Cortex-M4 SIMD Header File
* @version V2.10
* @date 19. July 2011
* @version V3.20
* @date 25. February 2013
*
* @note
* Copyright (C) 2010-2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifdef __cplusplus
extern "C" {
#endif
#endif
#ifndef __CORE_CM4_SIMD_H
#define __CORE_CM4_SIMD_H
@@ -43,7 +57,7 @@
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
@@ -110,6 +124,8 @@
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32) ) >> 32))
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
@@ -118,70 +134,18 @@
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
#include <cmsis_iar.h>
/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/
/* intrinsic __SADD8 see intrinsics.h */
/* intrinsic __QADD8 see intrinsics.h */
/* intrinsic __SHADD8 see intrinsics.h */
/* intrinsic __UADD8 see intrinsics.h */
/* intrinsic __UQADD8 see intrinsics.h */
/* intrinsic __UHADD8 see intrinsics.h */
/* intrinsic __SSUB8 see intrinsics.h */
/* intrinsic __QSUB8 see intrinsics.h */
/* intrinsic __SHSUB8 see intrinsics.h */
/* intrinsic __USUB8 see intrinsics.h */
/* intrinsic __UQSUB8 see intrinsics.h */
/* intrinsic __UHSUB8 see intrinsics.h */
/* intrinsic __SADD16 see intrinsics.h */
/* intrinsic __QADD16 see intrinsics.h */
/* intrinsic __SHADD16 see intrinsics.h */
/* intrinsic __UADD16 see intrinsics.h */
/* intrinsic __UQADD16 see intrinsics.h */
/* intrinsic __UHADD16 see intrinsics.h */
/* intrinsic __SSUB16 see intrinsics.h */
/* intrinsic __QSUB16 see intrinsics.h */
/* intrinsic __SHSUB16 see intrinsics.h */
/* intrinsic __USUB16 see intrinsics.h */
/* intrinsic __UQSUB16 see intrinsics.h */
/* intrinsic __UHSUB16 see intrinsics.h */
/* intrinsic __SASX see intrinsics.h */
/* intrinsic __QASX see intrinsics.h */
/* intrinsic __SHASX see intrinsics.h */
/* intrinsic __UASX see intrinsics.h */
/* intrinsic __UQASX see intrinsics.h */
/* intrinsic __UHASX see intrinsics.h */
/* intrinsic __SSAX see intrinsics.h */
/* intrinsic __QSAX see intrinsics.h */
/* intrinsic __SHSAX see intrinsics.h */
/* intrinsic __USAX see intrinsics.h */
/* intrinsic __UQSAX see intrinsics.h */
/* intrinsic __UHSAX see intrinsics.h */
/* intrinsic __USAD8 see intrinsics.h */
/* intrinsic __USADA8 see intrinsics.h */
/* intrinsic __SSAT16 see intrinsics.h */
/* intrinsic __USAT16 see intrinsics.h */
/* intrinsic __UXTB16 see intrinsics.h */
/* intrinsic __SXTB16 see intrinsics.h */
/* intrinsic __UXTAB16 see intrinsics.h */
/* intrinsic __SXTAB16 see intrinsics.h */
/* intrinsic __SMUAD see intrinsics.h */
/* intrinsic __SMUADX see intrinsics.h */
/* intrinsic __SMLAD see intrinsics.h */
/* intrinsic __SMLADX see intrinsics.h */
/* intrinsic __SMLALD see intrinsics.h */
/* intrinsic __SMLALDX see intrinsics.h */
/* intrinsic __SMUSD see intrinsics.h */
/* intrinsic __SMUSDX see intrinsics.h */
/* intrinsic __SMLSD see intrinsics.h */
/* intrinsic __SMLSDX see intrinsics.h */
/* intrinsic __SMLSLD see intrinsics.h */
/* intrinsic __SMLSLDX see intrinsics.h */
/* intrinsic __SEL see intrinsics.h */
/* intrinsic __QADD see intrinsics.h */
/* intrinsic __QSUB see intrinsics.h */
/* intrinsic __PKHBT see intrinsics.h */
/* intrinsic __PKHTB see intrinsics.h */
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
#include <cmsis_ccs.h>
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
@@ -191,308 +155,308 @@
/* GNU gcc specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
@@ -503,7 +467,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
#define __USAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
@@ -511,66 +475,66 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op
__RES; \
})
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
@@ -589,34 +553,34 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t o
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
@@ -635,15 +599,15 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t o
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
{
uint32_t result;
@@ -651,10 +615,10 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1,
return(result);
}
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
@@ -671,11 +635,19 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1,
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
if (ARG3 == 0) \
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
else \
else \
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/

183
example/libs/StmCoreNPheriph/inc/core_cmFunc.h
View File

@@ -1,32 +1,46 @@
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V2.10
* @date 26. July 2011
* @version V3.20
* @date 25. February 2013
*
* @note
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
@@ -47,7 +61,7 @@
\return Control Register value
*/
static __INLINE uint32_t __get_CONTROL(void)
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
@@ -60,20 +74,20 @@ static __INLINE uint32_t __get_CONTROL(void)
\param [in] control Control Register value to set
*/
static __INLINE void __set_CONTROL(uint32_t control)
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get ISPR Register
/** \brief Get IPSR Register
This function returns the content of the ISPR Register.
This function returns the content of the IPSR Register.
\return ISPR Register value
\return IPSR Register value
*/
static __INLINE uint32_t __get_IPSR(void)
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
@@ -86,7 +100,7 @@ static __INLINE uint32_t __get_IPSR(void)
\return APSR Register value
*/
static __INLINE uint32_t __get_APSR(void)
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
@@ -99,7 +113,7 @@ static __INLINE uint32_t __get_APSR(void)
\return xPSR Register value
*/
static __INLINE uint32_t __get_xPSR(void)
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
@@ -112,7 +126,7 @@ static __INLINE uint32_t __get_xPSR(void)
\return PSP Register value
*/
static __INLINE uint32_t __get_PSP(void)
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
@@ -125,7 +139,7 @@ static __INLINE uint32_t __get_PSP(void)
\param [in] topOfProcStack Process Stack Pointer value to set
*/
static __INLINE void __set_PSP(uint32_t topOfProcStack)
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
@@ -138,7 +152,7 @@ static __INLINE void __set_PSP(uint32_t topOfProcStack)
\return MSP Register value
*/
static __INLINE uint32_t __get_MSP(void)
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
@@ -151,7 +165,7 @@ static __INLINE uint32_t __get_MSP(void)
\param [in] topOfMainStack Main Stack Pointer value to set
*/
static __INLINE void __set_MSP(uint32_t topOfMainStack)
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
@@ -164,7 +178,7 @@ static __INLINE void __set_MSP(uint32_t topOfMainStack)
\return Priority Mask value
*/
static __INLINE uint32_t __get_PRIMASK(void)
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
@@ -177,12 +191,12 @@ static __INLINE uint32_t __get_PRIMASK(void)
\param [in] priMask Priority Mask
*/
static __INLINE void __set_PRIMASK(uint32_t priMask)
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
@@ -208,7 +222,7 @@ static __INLINE void __set_PRIMASK(uint32_t priMask)
\return Base Priority register value
*/
static __INLINE uint32_t __get_BASEPRI(void)
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
@@ -221,12 +235,12 @@ static __INLINE uint32_t __get_BASEPRI(void)
\param [in] basePri Base Priority value to set
*/
static __INLINE void __set_BASEPRI(uint32_t basePri)
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
@@ -234,7 +248,7 @@ static __INLINE void __set_BASEPRI(uint32_t basePri)
\return Fault Mask register value
*/
static __INLINE uint32_t __get_FAULTMASK(void)
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
@@ -247,7 +261,7 @@ static __INLINE uint32_t __get_FAULTMASK(void)
\param [in] faultMask Fault Mask value to set
*/
static __INLINE void __set_FAULTMASK(uint32_t faultMask)
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
@@ -264,7 +278,7 @@ static __INLINE void __set_FAULTMASK(uint32_t faultMask)
\return Floating Point Status/Control register value
*/
static __INLINE uint32_t __get_FPSCR(void)
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
@@ -281,7 +295,7 @@ static __INLINE uint32_t __get_FPSCR(void)
\param [in] fpscr Floating Point Status/Control value to set
*/
static __INLINE void __set_FPSCR(uint32_t fpscr)
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
@@ -297,6 +311,13 @@ static __INLINE void __set_FPSCR(uint32_t fpscr)
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
@@ -305,9 +326,9 @@ static __INLINE void __set_FPSCR(uint32_t fpscr)
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i");
__ASM volatile ("cpsie i" : : : "memory");
}
@@ -316,9 +337,9 @@ __attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i");
__ASM volatile ("cpsid i" : : : "memory");
}
@@ -328,7 +349,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
\return Control Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
@@ -343,19 +364,19 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
/** \brief Get ISPR Register
/** \brief Get IPSR Register
This function returns the content of the ISPR Register.
This function returns the content of the IPSR Register.
\return ISPR Register value
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
@@ -370,7 +391,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
\return APSR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
@@ -385,7 +406,7 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
@@ -400,14 +421,14 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
\return PSP Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
@@ -415,9 +436,9 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
}
@@ -427,14 +448,14 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOf
\return MSP Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
@@ -442,9 +463,9 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
}
@@ -454,7 +475,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOf
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
@@ -469,11 +490,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (__CORTEX_M >= 0x03)
@@ -482,9 +503,9 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t p
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f");
__ASM volatile ("cpsie f" : : : "memory");
}
@@ -493,9 +514,9 @@ __attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f");
__ASM volatile ("cpsid f" : : : "memory");
}
@@ -505,10 +526,10 @@ __attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
@@ -520,9 +541,9 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
}
@@ -532,10 +553,10 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t v
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
@@ -547,9 +568,9 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
@@ -563,12 +584,15 @@ __attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result);
#else
return(0);
@@ -582,10 +606,13 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
#endif
}

243
example/libs/StmCoreNPheriph/inc/core_cmInstr.h
View File

@@ -1,25 +1,39 @@
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V2.10
* @date 19. July 2011
* @version V3.20
* @date 05. March 2013
*
* @note
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
@@ -71,8 +85,8 @@
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
@@ -80,7 +94,7 @@
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
@@ -88,7 +102,7 @@
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
@@ -111,12 +125,13 @@
\param [in] value Value to reverse
\return Reversed value
*/
static __INLINE __ASM uint32_t __REV16(uint32_t value)
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/** \brief Reverse byte order in signed short value
@@ -125,11 +140,35 @@ static __INLINE __ASM uint32_t __REV16(uint32_t value)
\param [in] value Value to reverse
\return Reversed value
*/
static __INLINE __ASM int32_t __REVSH(int32_t value)
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03)
@@ -247,7 +286,7 @@ static __INLINE __ASM int32_t __REVSH(int32_t value)
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
@@ -259,14 +298,31 @@ static __INLINE __ASM int32_t __REVSH(int32_t value)
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constrant "l"
* Otherwise, use general registers, specified by constrant "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
@@ -277,7 +333,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
@@ -288,7 +344,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
@@ -298,7 +354,7 @@ __attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
@@ -306,11 +362,11 @@ __attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
@@ -318,10 +374,10 @@ __attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
@@ -329,10 +385,10 @@ __attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
@@ -345,12 +401,16 @@ __attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
@@ -361,11 +421,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
@@ -377,15 +437,44 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t val
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
#else
uint32_t result;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32 - op2));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
@@ -395,10 +484,10 @@ __attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
@@ -411,11 +500,18 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t valu
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint8_t result;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
@@ -427,11 +523,18 @@ __attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uin
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint16_t result;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
@@ -443,11 +546,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile ui
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
@@ -461,11 +564,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile ui
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
@@ -479,11 +582,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t val
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
@@ -497,11 +600,11 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t va
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
@@ -511,9 +614,9 @@ __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t va
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex");
__ASM volatile ("clrex" ::: "memory");
}
@@ -556,10 +659,10 @@ __attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint8_t result;
uint32_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}

26
example/libs/StmCoreNPheriph/inc/misc.h
View File

@@ -2,21 +2,27 @@
******************************************************************************
* @file misc.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the miscellaneous
* firmware library functions (add-on to CMSIS functions).
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -169,4 +175,4 @@ void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

3145
example/libs/StmCoreNPheriph/inc/stm32f4xx.h
View File

File diff suppressed because it is too large Load Diff

33
example/libs/StmCoreNPheriph/inc/stm32f4xx_adc.h
View File

@@ -2,21 +2,27 @@
******************************************************************************
* @file stm32f4xx_adc.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the ADC firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -319,7 +325,14 @@ typedef struct
#define ADC_Channel_17 ((uint8_t)0x11)
#define ADC_Channel_18 ((uint8_t)0x12)
#if defined (STM32F40_41xxx)
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
#endif /* STM32F40_41xxx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F411xE)
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_18)
#endif /* STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18)
@@ -640,4 +653,4 @@ void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
example/libs/StmCoreNPheriph/inc/stm32f4xx_can.h
View File

@@ -2,21 +2,27 @@
******************************************************************************
* @file stm32f4xx_can.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the CAN firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -635,4 +641,4 @@ void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

81
example/libs/StmCoreNPheriph/inc/stm32f4xx_conf.h
View File

@@ -1,54 +1,47 @@
/**
******************************************************************************
* @file IO_Toggle/stm32f4xx_conf.h
* @file Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_conf.h
* @author MCD Application Team
* @version V1.0.0
* @date 19-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief Library configuration file.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_CONF_H
#define __STM32F4xx_CONF_H
#if defined (HSE_VALUE)
/* Redefine the HSE value; it's equal to 8 MHz on the STM32F4-DISCOVERY Kit */
#undef HSE_VALUE
#define HSE_VALUE ((uint32_t)8000000)
#endif /* HSE_VALUE */
/* Includes ------------------------------------------------------------------*/
/* Uncomment the line below to enable peripheral header file inclusion */
#include "stm32f4xx_adc.h"
#include "stm32f4xx_can.h"
#include "stm32f4xx_crc.h"
#include "stm32f4xx_cryp.h"
#include "stm32f4xx_dac.h"
#include "stm32f4xx_dbgmcu.h"
#include "stm32f4xx_dcmi.h"
#include "stm32f4xx_dma.h"
#include "stm32f4xx_exti.h"
#include "stm32f4xx_flash.h"
#include "stm32f4xx_fsmc.h"
#include "stm32f4xx_hash.h"
#include "stm32f4xx_gpio.h"
#include "stm32f4xx_i2c.h"
#include "stm32f4xx_iwdg.h"
#include "stm32f4xx_pwr.h"
#include "stm32f4xx_rcc.h"
#include "stm32f4xx_rng.h"
#include "stm32f4xx_rtc.h"
#include "stm32f4xx_sdio.h"
#include "stm32f4xx_spi.h"
@@ -58,6 +51,44 @@
#include "stm32f4xx_wwdg.h"
#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
#if defined (STM32F429_439xx)
#include "stm32f4xx_cryp.h"
#include "stm32f4xx_hash.h"
#include "stm32f4xx_rng.h"
#include "stm32f4xx_can.h"
#include "stm32f4xx_dac.h"
#include "stm32f4xx_dcmi.h"
#include "stm32f4xx_dma2d.h"
#include "stm32f4xx_fmc.h"
#include "stm32f4xx_ltdc.h"
#include "stm32f4xx_sai.h"
#endif /* STM32F429_439xx */
#if defined (STM32F427_437xx)
#include "stm32f4xx_cryp.h"
#include "stm32f4xx_hash.h"
#include "stm32f4xx_rng.h"
#include "stm32f4xx_can.h"
#include "stm32f4xx_dac.h"
#include "stm32f4xx_dcmi.h"
#include "stm32f4xx_dma2d.h"
#include "stm32f4xx_fmc.h"
#include "stm32f4xx_sai.h"
#endif /* STM32F427_437xx */
#if defined (STM32F40_41xxx)
#include "stm32f4xx_cryp.h"
#include "stm32f4xx_hash.h"
#include "stm32f4xx_rng.h"
#include "stm32f4xx_can.h"
#include "stm32f4xx_dac.h"
#include "stm32f4xx_dcmi.h"
#include "stm32f4xx_fsmc.h"
#endif /* STM32F40_41xxx */
#if defined (STM32F411xE)
#include "stm32f4xx_flash_ramfunc.h"
#endif /* STM32F411xE */
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
@@ -91,4 +122,4 @@
#endif /* __STM32F4xx_CONF_H */
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
example/libs/StmCoreNPheriph/inc/stm32f4xx_crc.h
View File

@@ -2,21 +2,27 @@
******************************************************************************
* @file stm32f4xx_crc.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the CRC firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -74,4 +80,4 @@ uint8_t CRC_GetIDRegister(void);
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

114
example/libs/StmCoreNPheriph/inc/stm32f4xx_cryp.h
View File

@@ -2,21 +2,27 @@
******************************************************************************
* @file stm32f4xx_cryp.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the Cryptographic
* processor(CRYP) firmware library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -46,14 +52,14 @@
*/
typedef struct
{
uint16_t CRYP_AlgoDir; /*!< Encrypt or Decrypt. This parameter can be a
uint32_t CRYP_AlgoDir; /*!< Encrypt or Decrypt. This parameter can be a
value of @ref CRYP_Algorithm_Direction */
uint16_t CRYP_AlgoMode; /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB,
AES-CBC, AES-CTR, AES-Key. This parameter can be
a value of @ref CRYP_Algorithm_Mode */
uint16_t CRYP_DataType; /*!< 32-bit data, 16-bit data, bit data or bit-string.
uint32_t CRYP_AlgoMode; /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB,
AES-CBC, AES-CTR, AES-Key, AES-GCM and AES-CCM.
This parameter can be a value of @ref CRYP_Algorithm_Mode */
uint32_t CRYP_DataType; /*!< 32-bit data, 16-bit data, bit data or bit string.
This parameter can be a value of @ref CRYP_Data_Type */
uint16_t CRYP_KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit
uint32_t CRYP_KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit
key length. This parameter can be a value of
@ref CRYP_Key_Size_for_AES_only */
}CRYP_InitTypeDef;
@@ -88,14 +94,14 @@ typedef struct
*/
typedef struct
{
/*!< Configuration */
uint32_t CR_bits9to2;
/*!< KEY */
/*!< Current Configuration */
uint32_t CR_CurrentConfig;
/*!< IV */
uint32_t CRYP_IV0LR;
uint32_t CRYP_IV0RR;
uint32_t CRYP_IV1LR;
uint32_t CRYP_IV1RR;
/*!< IV */
/*!< KEY */
uint32_t CRYP_K0LR;
uint32_t CRYP_K0RR;
uint32_t CRYP_K1LR;
@@ -104,6 +110,8 @@ typedef struct
uint32_t CRYP_K2RR;
uint32_t CRYP_K3LR;
uint32_t CRYP_K3RR;
uint32_t CRYP_CSGCMCCMR[8];
uint32_t CRYP_CSGCMR[8];
}CRYP_Context;
@@ -130,31 +138,54 @@ typedef struct
*/
/*!< TDES Modes */
#define CRYP_AlgoMode_TDES_ECB ((uint16_t)0x0000)
#define CRYP_AlgoMode_TDES_CBC ((uint16_t)0x0008)
#define CRYP_AlgoMode_TDES_ECB ((uint32_t)0x00000000)
#define CRYP_AlgoMode_TDES_CBC ((uint32_t)0x00000008)
/*!< DES Modes */
#define CRYP_AlgoMode_DES_ECB ((uint16_t)0x0010)
#define CRYP_AlgoMode_DES_CBC ((uint16_t)0x0018)
#define CRYP_AlgoMode_DES_ECB ((uint32_t)0x00000010)
#define CRYP_AlgoMode_DES_CBC ((uint32_t)0x00000018)
/*!< AES Modes */
#define CRYP_AlgoMode_AES_ECB ((uint16_t)0x0020)
#define CRYP_AlgoMode_AES_CBC ((uint16_t)0x0028)
#define CRYP_AlgoMode_AES_CTR ((uint16_t)0x0030)
#define CRYP_AlgoMode_AES_Key ((uint16_t)0x0038)
#define CRYP_AlgoMode_AES_ECB ((uint32_t)0x00000020)
#define CRYP_AlgoMode_AES_CBC ((uint32_t)0x00000028)
#define CRYP_AlgoMode_AES_CTR ((uint32_t)0x00000030)
#define CRYP_AlgoMode_AES_Key ((uint32_t)0x00000038)
#define CRYP_AlgoMode_AES_GCM ((uint32_t)0x00080000)
#define CRYP_AlgoMode_AES_CCM ((uint32_t)0x00080008)
#define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \
((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \
((ALGOMODE) == CRYP_AlgoMode_DES_ECB)|| \
((ALGOMODE) == CRYP_AlgoMode_DES_ECB) || \
((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \
((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \
((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \
((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \
((ALGOMODE) == CRYP_AlgoMode_AES_Key))
((ALGOMODE) == CRYP_AlgoMode_AES_Key) || \
((ALGOMODE) == CRYP_AlgoMode_AES_GCM) || \
((ALGOMODE) == CRYP_AlgoMode_AES_CCM))
/**
* @}
*/
/** @defgroup CRYP_Phase
* @{
*/
/*!< The phases are valid only for AES-GCM and AES-CCM modes */
#define CRYP_Phase_Init ((uint32_t)0x00000000)
#define CRYP_Phase_Header CRYP_CR_GCM_CCMPH_0
#define CRYP_Phase_Payload CRYP_CR_GCM_CCMPH_1
#define CRYP_Phase_Final CRYP_CR_GCM_CCMPH
#define IS_CRYP_PHASE(PHASE) (((PHASE) == CRYP_Phase_Init) || \
((PHASE) == CRYP_Phase_Header) || \
((PHASE) == CRYP_Phase_Payload) || \
((PHASE) == CRYP_Phase_Final))
/**
* @}
*/
/** @defgroup CRYP_Data_Type
* @{
*/
@@ -260,23 +291,24 @@ void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);
void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);
void CRYP_Cmd(FunctionalState NewState);
void CRYP_PhaseConfig(uint32_t CRYP_Phase);
void CRYP_FIFOFlush(void);
/* CRYP Data processing functions *********************************************/
void CRYP_DataIn(uint32_t Data);
uint32_t CRYP_DataOut(void);
void CRYP_FIFOFlush(void);
/* CRYP Context swapping functions ********************************************/
ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave,
CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore);
/* CRYP's DMA interface function **********************************************/
/* CRYP DMA interface function ************************************************/
void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState);
ITStatus CRYP_GetITStatus(uint8_t CRYP_IT);
FunctionalState CRYP_GetCmdStatus(void);
FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG);
/* High Level AES functions **************************************************/
@@ -297,6 +329,20 @@ ErrorStatus CRYP_AES_CTR(uint8_t Mode,
uint8_t *Input, uint32_t Ilength,
uint8_t *Output);
ErrorStatus CRYP_AES_GCM(uint8_t Mode, uint8_t InitVectors[16],
uint8_t *Key, uint16_t Keysize,
uint8_t *Input, uint32_t ILength,
uint8_t *Header, uint32_t HLength,
uint8_t *Output, uint8_t *AuthTAG);
ErrorStatus CRYP_AES_CCM(uint8_t Mode,
uint8_t* Nonce, uint32_t NonceSize,
uint8_t* Key, uint16_t Keysize,
uint8_t* Input, uint32_t ILength,
uint8_t* Header, uint32_t HLength, uint8_t *HBuffer,
uint8_t* Output,
uint8_t* AuthTAG, uint32_t TAGSize);
/* High Level TDES functions **************************************************/
ErrorStatus CRYP_TDES_ECB(uint8_t Mode,
uint8_t Key[24],
@@ -335,4 +381,4 @@ ErrorStatus CRYP_DES_CBC(uint8_t Mode,
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
example/libs/StmCoreNPheriph/inc/stm32f4xx_dac.h
View File

@@ -2,21 +2,27 @@
******************************************************************************
* @file stm32f4xx_dac.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the DAC firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -295,4 +301,4 @@ void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
example/libs/StmCoreNPheriph/inc/stm32f4xx_dbgmcu.h
View File

@@ -2,20 +2,26 @@
******************************************************************************
* @file stm32f4xx_dbgmcu.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the DBGMCU firmware library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -100,4 +106,4 @@ void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
example/libs/StmCoreNPheriph/inc/stm32f4xx_dcmi.h
View File

@@ -2,20 +2,26 @@
******************************************************************************
* @file stm32f4xx_dcmi.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the DCMI firmware library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -303,4 +309,4 @@ void DCMI_ClearITPendingBit(uint16_t DCMI_IT);
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

28
example/libs/StmCoreNPheriph/inc/stm32f4xx_dma.h
View File

@@ -2,21 +2,27 @@
******************************************************************************
* @file stm32f4xx_dma.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the DMA firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -393,7 +399,7 @@ typedef struct
#define DMA_FLAG_TCIF7 ((uint32_t)0x28000000)
#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \
(((FLAG) & 0xC082F082) == 0x00) && ((FLAG) != 0x00))
(((FLAG) & 0xC002F082) == 0x00) && ((FLAG) != 0x00))
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \
((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \
@@ -600,4 +606,4 @@ void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

475
example/libs/StmCoreNPheriph/inc/stm32f4xx_dma2d.h Normal file
View File

@@ -0,0 +1,475 @@
/**
******************************************************************************
* @file stm32f4xx_dma2d.h
* @author MCD Application Team
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the DMA2D firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_DMA2D_H
#define __STM32F4xx_DMA2D_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup DMA2D
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief DMA2D Init structure definition
*/
typedef struct
{
uint32_t DMA2D_Mode; /*!< configures the DMA2D transfer mode.
This parameter can be one value of @ref DMA2D_MODE */
uint32_t DMA2D_CMode; /*!< configures the color format of the output image.
This parameter can be one value of @ref DMA2D_CMODE */
uint32_t DMA2D_OutputBlue; /*!< configures the blue value of the output image.
This parameter must range:
- from 0x00 to 0xFF if ARGB8888 color mode is slected
- from 0x00 to 0xFF if RGB888 color mode is slected
- from 0x00 to 0x1F if RGB565 color mode is slected
- from 0x00 to 0x1F if ARGB1555 color mode is slected
- from 0x00 to 0x0F if ARGB4444 color mode is slected */
uint32_t DMA2D_OutputGreen; /*!< configures the green value of the output image.
This parameter must range:
- from 0x00 to 0xFF if ARGB8888 color mode is slected
- from 0x00 to 0xFF if RGB888 color mode is slected
- from 0x00 to 0x2F if RGB565 color mode is slected
- from 0x00 to 0x1F if ARGB1555 color mode is slected
- from 0x00 to 0x0F if ARGB4444 color mode is slected */
uint32_t DMA2D_OutputRed; /*!< configures the red value of the output image.
This parameter must range:
- from 0x00 to 0xFF if ARGB8888 color mode is slected
- from 0x00 to 0xFF if RGB888 color mode is slected
- from 0x00 to 0x1F if RGB565 color mode is slected
- from 0x00 to 0x1F if ARGB1555 color mode is slected
- from 0x00 to 0x0F if ARGB4444 color mode is slected */
uint32_t DMA2D_OutputAlpha; /*!< configures the alpha channel of the output color.
This parameter must range:
- from 0x00 to 0xFF if ARGB8888 color mode is slected
- from 0x00 to 0x01 if ARGB1555 color mode is slected
- from 0x00 to 0x0F if ARGB4444 color mode is slected */
uint32_t DMA2D_OutputMemoryAdd; /*!< Specifies the memory address. This parameter
must be range from 0x00000000 to 0xFFFFFFFF. */
uint32_t DMA2D_OutputOffset; /*!< Specifies the Offset value. This parameter must be range from
0x0000 to 0x3FFF. */
uint32_t DMA2D_NumberOfLine; /*!< Configures the number of line of the area to be transfered.
This parameter must range from 0x0000 to 0xFFFF */
uint32_t DMA2D_PixelPerLine; /*!< Configures the number pixel per line of the area to be transfered.
This parameter must range from 0x0000 to 0x3FFF */
} DMA2D_InitTypeDef;
typedef struct
{
uint32_t DMA2D_FGMA; /*!< configures the DMA2D foreground memory address.
This parameter must be range from 0x00000000 to 0xFFFFFFFF. */
uint32_t DMA2D_FGO; /*!< configures the DMA2D foreground offset.
This parameter must be range from 0x0000 to 0x3FFF. */
uint32_t DMA2D_FGCM; /*!< configures the DMA2D foreground color mode .
This parameter can be one value of @ref DMA2D_FGCM */
uint32_t DMA2D_FG_CLUT_CM; /*!< configures the DMA2D foreground CLUT color mode.
This parameter can be one value of @ref DMA2D_FG_CLUT_CM */
uint32_t DMA2D_FG_CLUT_SIZE; /*!< configures the DMA2D foreground CLUT size.
This parameter must range from 0x00 to 0xFF. */
uint32_t DMA2D_FGPFC_ALPHA_MODE; /*!< configures the DMA2D foreground alpha mode.
This parameter can be one value of @ref DMA2D_FGPFC_ALPHA_MODE */
uint32_t DMA2D_FGPFC_ALPHA_VALUE; /*!< Specifies the DMA2D foreground alpha value
must be range from 0x00 to 0xFF. */
uint32_t DMA2D_FGC_BLUE; /*!< Specifies the DMA2D foreground blue value
must be range from 0x00 to 0xFF. */
uint32_t DMA2D_FGC_GREEN; /*!< Specifies the DMA2D foreground green value
must be range from 0x00 to 0xFF. */
uint32_t DMA2D_FGC_RED; /*!< Specifies the DMA2D foreground red value
must be range from 0x00 to 0xFF. */
uint32_t DMA2D_FGCMAR; /*!< Configures the DMA2D foreground CLUT memory address.
This parameter must range from 0x00000000 to 0xFFFFFFFF. */
} DMA2D_FG_InitTypeDef;
typedef struct
{
uint32_t DMA2D_BGMA; /*!< configures the DMA2D background memory address.
This parameter must be range from 0x00000000 to 0xFFFFFFFF. */
uint32_t DMA2D_BGO; /*!< configures the DMA2D background offset.
This parameter must be range from 0x0000 to 0x3FFF. */
uint32_t DMA2D_BGCM; /*!< configures the DMA2D background color mode .
This parameter can be one value of @ref DMA2D_FGCM */
uint32_t DMA2D_BG_CLUT_CM; /*!< configures the DMA2D background CLUT color mode.
This parameter can be one value of @ref DMA2D_FG_CLUT_CM */
uint32_t DMA2D_BG_CLUT_SIZE; /*!< configures the DMA2D background CLUT size.
This parameter must range from 0x00 to 0xFF. */
uint32_t DMA2D_BGPFC_ALPHA_MODE; /*!< configures the DMA2D background alpha mode.
This parameter can be one value of @ref DMA2D_FGPFC_ALPHA_MODE */
uint32_t DMA2D_BGPFC_ALPHA_VALUE; /*!< Specifies the DMA2D background alpha value
must be range from 0x00 to 0xFF. */
uint32_t DMA2D_BGC_BLUE; /*!< Specifies the DMA2D background blue value
must be range from 0x00 to 0xFF. */
uint32_t DMA2D_BGC_GREEN; /*!< Specifies the DMA2D background green value
must be range from 0x00 to 0xFF. */
uint32_t DMA2D_BGC_RED; /*!< Specifies the DMA2D background red value
must be range from 0x00 to 0xFF. */
uint32_t DMA2D_BGCMAR; /*!< Configures the DMA2D background CLUT memory address.
This parameter must range from 0x00000000 to 0xFFFFFFFF. */
} DMA2D_BG_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMA2D_Exported_Constants
* @{
*/
/** @defgroup DMA2D_MODE
* @{
*/
#define DMA2D_M2M ((uint32_t)0x00000000)
#define DMA2D_M2M_PFC ((uint32_t)0x00010000)
#define DMA2D_M2M_BLEND ((uint32_t)0x00020000)
#define DMA2D_R2M ((uint32_t)0x00030000)
#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
/**
* @}
*/
/** @defgroup DMA2D_CMODE
* @{
*/
#define DMA2D_ARGB8888 ((uint32_t)0x00000000)
#define DMA2D_RGB888 ((uint32_t)0x00000001)
#define DMA2D_RGB565 ((uint32_t)0x00000002)
#define DMA2D_ARGB1555 ((uint32_t)0x00000003)
#define DMA2D_ARGB4444 ((uint32_t)0x00000004)
#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \
((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \
((MODE_ARGB) == DMA2D_ARGB4444))
/**
* @}
*/
/** @defgroup DMA2D_OUTPUT_COLOR
* @{
*/
#define DMA2D_Output_Color ((uint32_t)0x000000FF)
#define IS_DMA2D_OGREEN(OGREEN) ((OGREEN) <= DMA2D_Output_Color)
#define IS_DMA2D_ORED(ORED) ((ORED) <= DMA2D_Output_Color)
#define IS_DMA2D_OBLUE(OBLUE) ((OBLUE) <= DMA2D_Output_Color)
#define IS_DMA2D_OALPHA(OALPHA) ((OALPHA) <= DMA2D_Output_Color)
/**
* @}
*/
/** @defgroup DMA2D_OUTPUT_OFFSET
* @{
*/
#define DMA2D_OUTPUT_OFFSET ((uint32_t)0x00003FFF)
#define IS_DMA2D_OUTPUT_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OUTPUT_OFFSET)
/**
* @}
*/
/** @defgroup DMA2D_SIZE
* @{
*/
#define DMA2D_pixel ((uint32_t)0x00003FFF)
#define DMA2D_Line ((uint32_t)0x0000FFFF)
#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_Line)
#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_pixel)
/**
* @}
*/
/** @defgroup DMA2D_OFFSET
* @{
*/
#define OFFSET ((uint32_t)0x00003FFF)
#define IS_DMA2D_FGO(FGO) ((FGO) <= OFFSET)
#define IS_DMA2D_BGO(BGO) ((BGO) <= OFFSET)
/**
* @}
*/
/** @defgroup DMA2D_FGCM
* @{
*/
#define CM_ARGB8888 ((uint32_t)0x00000000)
#define CM_RGB888 ((uint32_t)0x00000001)
#define CM_RGB565 ((uint32_t)0x00000002)
#define CM_ARGB1555 ((uint32_t)0x00000003)
#define CM_ARGB4444 ((uint32_t)0x00000004)
#define CM_L8 ((uint32_t)0x00000005)
#define CM_AL44 ((uint32_t)0x00000006)
#define CM_AL88 ((uint32_t)0x00000007)
#define CM_L4 ((uint32_t)0x00000008)
#define CM_A8 ((uint32_t)0x00000009)
#define CM_A4 ((uint32_t)0x0000000A)
#define IS_DMA2D_FGCM(FGCM) (((FGCM) == CM_ARGB8888) || ((FGCM) == CM_RGB888) || \
((FGCM) == CM_RGB565) || ((FGCM) == CM_ARGB1555) || \
((FGCM) == CM_ARGB4444) || ((FGCM) == CM_L8) || \
((FGCM) == CM_AL44) || ((FGCM) == CM_AL88) || \
((FGCM) == CM_L4) || ((FGCM) == CM_A8) || \
((FGCM) == CM_A4))
#define IS_DMA2D_BGCM(BGCM) (((BGCM) == CM_ARGB8888) || ((BGCM) == CM_RGB888) || \
((BGCM) == CM_RGB565) || ((BGCM) == CM_ARGB1555) || \
((BGCM) == CM_ARGB4444) || ((BGCM) == CM_L8) || \
((BGCM) == CM_AL44) || ((BGCM) == CM_AL88) || \
((BGCM) == CM_L4) || ((BGCM) == CM_A8) || \
((BGCM) == CM_A4))
/**
* @}
*/
/** @defgroup DMA2D_FG_CLUT_CM
* @{
*/
#define CLUT_CM_ARGB8888 ((uint32_t)0x00000000)
#define CLUT_CM_RGB888 ((uint32_t)0x00000001)
#define IS_DMA2D_FG_CLUT_CM(FG_CLUT_CM) (((FG_CLUT_CM) == CLUT_CM_ARGB8888) || ((FG_CLUT_CM) == CLUT_CM_RGB888))
#define IS_DMA2D_BG_CLUT_CM(BG_CLUT_CM) (((BG_CLUT_CM) == CLUT_CM_ARGB8888) || ((BG_CLUT_CM) == CLUT_CM_RGB888))
/**
* @}
*/
/** @defgroup DMA2D_FG_COLOR_VALUE
* @{
*/
#define COLOR_VALUE ((uint32_t)0x000000FF)
#define IS_DMA2D_FG_CLUT_SIZE(FG_CLUT_SIZE) ((FG_CLUT_SIZE) <= COLOR_VALUE)
#define IS_DMA2D_FG_ALPHA_VALUE(FG_ALPHA_VALUE) ((FG_ALPHA_VALUE) <= COLOR_VALUE)
#define IS_DMA2D_FGC_BLUE(FGC_BLUE) ((FGC_BLUE) <= COLOR_VALUE)
#define IS_DMA2D_FGC_GREEN(FGC_GREEN) ((FGC_GREEN) <= COLOR_VALUE)
#define IS_DMA2D_FGC_RED(FGC_RED) ((FGC_RED) <= COLOR_VALUE)
#define IS_DMA2D_BG_CLUT_SIZE(BG_CLUT_SIZE) ((BG_CLUT_SIZE) <= COLOR_VALUE)
#define IS_DMA2D_BG_ALPHA_VALUE(BG_ALPHA_VALUE) ((BG_ALPHA_VALUE) <= COLOR_VALUE)
#define IS_DMA2D_BGC_BLUE(BGC_BLUE) ((BGC_BLUE) <= COLOR_VALUE)
#define IS_DMA2D_BGC_GREEN(BGC_GREEN) ((BGC_GREEN) <= COLOR_VALUE)
#define IS_DMA2D_BGC_RED(BGC_RED) ((BGC_RED) <= COLOR_VALUE)
/**
* @}
*/
/** DMA2D_FGPFC_ALPHA_MODE
* @{
*/
#define NO_MODIF_ALPHA_VALUE ((uint32_t)0x00000000)
#define REPLACE_ALPHA_VALUE ((uint32_t)0x00000001)
#define COMBINE_ALPHA_VALUE ((uint32_t)0x00000002)
#define IS_DMA2D_FG_ALPHA_MODE(FG_ALPHA_MODE) (((FG_ALPHA_MODE) == NO_MODIF_ALPHA_VALUE) || \
((FG_ALPHA_MODE) == REPLACE_ALPHA_VALUE) || \
((FG_ALPHA_MODE) == COMBINE_ALPHA_VALUE))
#define IS_DMA2D_BG_ALPHA_MODE(BG_ALPHA_MODE) (((BG_ALPHA_MODE) == NO_MODIF_ALPHA_VALUE) || \
((BG_ALPHA_MODE) == REPLACE_ALPHA_VALUE) || \
((BG_ALPHA_MODE) == COMBINE_ALPHA_VALUE))
/**
* @}
*/
/** @defgroup DMA2D_Interrupts
* @{
*/
#define DMA2D_IT_CE DMA2D_CR_CEIE
#define DMA2D_IT_CTC DMA2D_CR_CTCIE
#define DMA2D_IT_CAE DMA2D_CR_CAEIE
#define DMA2D_IT_TW DMA2D_CR_TWIE
#define DMA2D_IT_TC DMA2D_CR_TCIE
#define DMA2D_IT_TE DMA2D_CR_TEIE
#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
/**
* @}
*/
/** @defgroup DMA2D_Flag
* @{
*/
#define DMA2D_FLAG_CE DMA2D_ISR_CEIF
#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF
#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF
#define DMA2D_FLAG_TW DMA2D_ISR_TWIF
#define DMA2D_FLAG_TC DMA2D_ISR_TCIF
#define DMA2D_FLAG_TE DMA2D_ISR_TEIF
#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
/**
* @}
*/
/** @defgroup DMA2D_DeadTime
* @{
*/
#define DEADTIME ((uint32_t)0x000000FF)
#define IS_DMA2D_DEAD_TIME(DEAD_TIME) ((DEAD_TIME) <= DEADTIME)
#define LINE_WATERMARK DMA2D_LWR_LW
#define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the DMA2D configuration to the default reset state *****/
void DMA2D_DeInit(void);
/* Initialization and Configuration functions *********************************/
void DMA2D_Init(DMA2D_InitTypeDef* DMA2D_InitStruct);
void DMA2D_StructInit(DMA2D_InitTypeDef* DMA2D_InitStruct);
void DMA2D_StartTransfer(void);
void DMA2D_AbortTransfer(void);
void DMA2D_Suspend(FunctionalState NewState);
void DMA2D_FGConfig(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct);
void DMA2D_FG_StructInit(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct);
void DMA2D_BGConfig(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct);
void DMA2D_BG_StructInit(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct);
void DMA2D_FGStart(FunctionalState NewState);
void DMA2D_BGStart(FunctionalState NewState);
void DMA2D_DeadTimeConfig(uint32_t DMA2D_DeadTime, FunctionalState NewState);
void DMA2D_LineWatermarkConfig(uint32_t DMA2D_LWatermarkConfig);
/* Interrupts and flags management functions **********************************/
void DMA2D_ITConfig(uint32_t DMA2D_IT, FunctionalState NewState);
FlagStatus DMA2D_GetFlagStatus(uint32_t DMA2D_FLAG);
void DMA2D_ClearFlag(uint32_t DMA2D_FLAG);
ITStatus DMA2D_GetITStatus(uint32_t DMA2D_IT);
void DMA2D_ClearITPendingBit(uint32_t DMA2D_IT);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_DMA2D_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
example/libs/StmCoreNPheriph/inc/stm32f4xx_exti.h
View File

@@ -2,21 +2,27 @@
******************************************************************************
* @file stm32f4xx_exti.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the EXTI firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -174,4 +180,4 @@ void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

326
example/libs/StmCoreNPheriph/inc/stm32f4xx_flash.h
View File

@@ -2,21 +2,27 @@
******************************************************************************
* @file stm32f4xx_flash.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the FLASH
* firmware library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -46,6 +52,7 @@
typedef enum
{
FLASH_BUSY = 1,
FLASH_ERROR_RD,
FLASH_ERROR_PGS,
FLASH_ERROR_PGP,
FLASH_ERROR_PGA,
@@ -64,23 +71,40 @@ typedef enum
/** @defgroup Flash_Latency
* @{
*/
#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */
#define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */
#define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */
#define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */
#define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */
#define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */
#define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */
#define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */
#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */
#define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */
#define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */
#define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */
#define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */
#define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */
#define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */
#define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */
#define FLASH_Latency_8 ((uint8_t)0x0008) /*!< FLASH Eight Latency cycles */
#define FLASH_Latency_9 ((uint8_t)0x0009) /*!< FLASH Nine Latency cycles */
#define FLASH_Latency_10 ((uint8_t)0x000A) /*!< FLASH Ten Latency cycles */
#define FLASH_Latency_11 ((uint8_t)0x000B) /*!< FLASH Eleven Latency cycles */
#define FLASH_Latency_12 ((uint8_t)0x000C) /*!< FLASH Twelve Latency cycles */
#define FLASH_Latency_13 ((uint8_t)0x000D) /*!< FLASH Thirteen Latency cycles */
#define FLASH_Latency_14 ((uint8_t)0x000E) /*!< FLASH Fourteen Latency cycles */
#define FLASH_Latency_15 ((uint8_t)0x000F) /*!< FLASH Fifteen Latency cycles */
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
((LATENCY) == FLASH_Latency_1) || \
((LATENCY) == FLASH_Latency_2) || \
((LATENCY) == FLASH_Latency_3) || \
((LATENCY) == FLASH_Latency_4) || \
((LATENCY) == FLASH_Latency_5) || \
((LATENCY) == FLASH_Latency_6) || \
((LATENCY) == FLASH_Latency_7))
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
((LATENCY) == FLASH_Latency_1) || \
((LATENCY) == FLASH_Latency_2) || \
((LATENCY) == FLASH_Latency_3) || \
((LATENCY) == FLASH_Latency_4) || \
((LATENCY) == FLASH_Latency_5) || \
((LATENCY) == FLASH_Latency_6) || \
((LATENCY) == FLASH_Latency_7) || \
((LATENCY) == FLASH_Latency_8) || \
((LATENCY) == FLASH_Latency_9) || \
((LATENCY) == FLASH_Latency_10) || \
((LATENCY) == FLASH_Latency_11) || \
((LATENCY) == FLASH_Latency_12) || \
((LATENCY) == FLASH_Latency_13) || \
((LATENCY) == FLASH_Latency_14) || \
((LATENCY) == FLASH_Latency_15))
/**
* @}
*/
@@ -96,34 +120,72 @@ typedef enum
#define IS_VOLTAGERANGE(RANGE)(((RANGE) == VoltageRange_1) || \
((RANGE) == VoltageRange_2) || \
((RANGE) == VoltageRange_3) || \
((RANGE) == VoltageRange_4))
((RANGE) == VoltageRange_4))
/**
* @}
*/
/** @defgroup FLASH_Sectors
* @{
*/
#define FLASH_Sector_0 ((uint16_t)0x0000) /*!< Sector Number 0 */
#define FLASH_Sector_1 ((uint16_t)0x0008) /*!< Sector Number 1 */
#define FLASH_Sector_2 ((uint16_t)0x0010) /*!< Sector Number 2 */
#define FLASH_Sector_3 ((uint16_t)0x0018) /*!< Sector Number 3 */
#define FLASH_Sector_4 ((uint16_t)0x0020) /*!< Sector Number 4 */
#define FLASH_Sector_5 ((uint16_t)0x0028) /*!< Sector Number 5 */
#define FLASH_Sector_6 ((uint16_t)0x0030) /*!< Sector Number 6 */
#define FLASH_Sector_7 ((uint16_t)0x0038) /*!< Sector Number 7 */
#define FLASH_Sector_8 ((uint16_t)0x0040) /*!< Sector Number 8 */
#define FLASH_Sector_9 ((uint16_t)0x0048) /*!< Sector Number 9 */
#define FLASH_Sector_10 ((uint16_t)0x0050) /*!< Sector Number 10 */
#define FLASH_Sector_11 ((uint16_t)0x0058) /*!< Sector Number 11 */
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_Sector_0) || ((SECTOR) == FLASH_Sector_1) ||\
((SECTOR) == FLASH_Sector_2) || ((SECTOR) == FLASH_Sector_3) ||\
((SECTOR) == FLASH_Sector_4) || ((SECTOR) == FLASH_Sector_5) ||\
((SECTOR) == FLASH_Sector_6) || ((SECTOR) == FLASH_Sector_7) ||\
((SECTOR) == FLASH_Sector_8) || ((SECTOR) == FLASH_Sector_9) ||\
((SECTOR) == FLASH_Sector_10) || ((SECTOR) == FLASH_Sector_11))
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))
*/
#define FLASH_Sector_0 ((uint16_t)0x0000) /*!< Sector Number 0 */
#define FLASH_Sector_1 ((uint16_t)0x0008) /*!< Sector Number 1 */
#define FLASH_Sector_2 ((uint16_t)0x0010) /*!< Sector Number 2 */
#define FLASH_Sector_3 ((uint16_t)0x0018) /*!< Sector Number 3 */
#define FLASH_Sector_4 ((uint16_t)0x0020) /*!< Sector Number 4 */
#define FLASH_Sector_5 ((uint16_t)0x0028) /*!< Sector Number 5 */
#define FLASH_Sector_6 ((uint16_t)0x0030) /*!< Sector Number 6 */
#define FLASH_Sector_7 ((uint16_t)0x0038) /*!< Sector Number 7 */
#define FLASH_Sector_8 ((uint16_t)0x0040) /*!< Sector Number 8 */
#define FLASH_Sector_9 ((uint16_t)0x0048) /*!< Sector Number 9 */
#define FLASH_Sector_10 ((uint16_t)0x0050) /*!< Sector Number 10 */
#define FLASH_Sector_11 ((uint16_t)0x0058) /*!< Sector Number 11 */
#define FLASH_Sector_12 ((uint16_t)0x0080) /*!< Sector Number 12 */
#define FLASH_Sector_13 ((uint16_t)0x0088) /*!< Sector Number 13 */
#define FLASH_Sector_14 ((uint16_t)0x0090) /*!< Sector Number 14 */
#define FLASH_Sector_15 ((uint16_t)0x0098) /*!< Sector Number 15 */
#define FLASH_Sector_16 ((uint16_t)0x00A0) /*!< Sector Number 16 */
#define FLASH_Sector_17 ((uint16_t)0x00A8) /*!< Sector Number 17 */
#define FLASH_Sector_18 ((uint16_t)0x00B0) /*!< Sector Number 18 */
#define FLASH_Sector_19 ((uint16_t)0x00B8) /*!< Sector Number 19 */
#define FLASH_Sector_20 ((uint16_t)0x00C0) /*!< Sector Number 20 */
#define FLASH_Sector_21 ((uint16_t)0x00C8) /*!< Sector Number 21 */
#define FLASH_Sector_22 ((uint16_t)0x00D0) /*!< Sector Number 22 */
#define FLASH_Sector_23 ((uint16_t)0x00D8) /*!< Sector Number 23 */
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_Sector_0) || ((SECTOR) == FLASH_Sector_1) ||\
((SECTOR) == FLASH_Sector_2) || ((SECTOR) == FLASH_Sector_3) ||\
((SECTOR) == FLASH_Sector_4) || ((SECTOR) == FLASH_Sector_5) ||\
((SECTOR) == FLASH_Sector_6) || ((SECTOR) == FLASH_Sector_7) ||\
((SECTOR) == FLASH_Sector_8) || ((SECTOR) == FLASH_Sector_9) ||\
((SECTOR) == FLASH_Sector_10) || ((SECTOR) == FLASH_Sector_11) ||\
((SECTOR) == FLASH_Sector_12) || ((SECTOR) == FLASH_Sector_13) ||\
((SECTOR) == FLASH_Sector_14) || ((SECTOR) == FLASH_Sector_15) ||\
((SECTOR) == FLASH_Sector_16) || ((SECTOR) == FLASH_Sector_17) ||\
((SECTOR) == FLASH_Sector_18) || ((SECTOR) == FLASH_Sector_19) ||\
((SECTOR) == FLASH_Sector_20) || ((SECTOR) == FLASH_Sector_21) ||\
((SECTOR) == FLASH_Sector_22) || ((SECTOR) == FLASH_Sector_23))
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x081FFFFF)) ||\
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
#endif /* STM32F427_437xx || STM32F429_439xx */
#if defined (STM32F40_41xxx)
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x080FFFFF)) ||\
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
#endif /* STM32F40_41xxx */
#if defined (STM32F401xx)
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF)) ||\
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
#endif /* STM32F401xx */
#if defined (STM32F411xE)
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0807FFFF)) ||\
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
#endif /* STM32F411xE */
/**
* @}
*/
@@ -131,18 +193,30 @@ typedef enum
/** @defgroup Option_Bytes_Write_Protection
* @{
*/
#define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
#define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
#define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
#define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
#define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
#define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
#define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */
#define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */
#define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */
#define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */
#define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */
#define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */
#define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
#define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
#define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
#define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
#define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
#define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
#define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */
#define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */
#define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */
#define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */
#define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */
#define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */
#define OB_WRP_Sector_12 ((uint32_t)0x00000001) /*!< Write protection of Sector12 */
#define OB_WRP_Sector_13 ((uint32_t)0x00000002) /*!< Write protection of Sector13 */
#define OB_WRP_Sector_14 ((uint32_t)0x00000004) /*!< Write protection of Sector14 */
#define OB_WRP_Sector_15 ((uint32_t)0x00000008) /*!< Write protection of Sector15 */
#define OB_WRP_Sector_16 ((uint32_t)0x00000010) /*!< Write protection of Sector16 */
#define OB_WRP_Sector_17 ((uint32_t)0x00000020) /*!< Write protection of Sector17 */
#define OB_WRP_Sector_18 ((uint32_t)0x00000040) /*!< Write protection of Sector18 */
#define OB_WRP_Sector_19 ((uint32_t)0x00000080) /*!< Write protection of Sector19 */
#define OB_WRP_Sector_20 ((uint32_t)0x00000100) /*!< Write protection of Sector20 */
#define OB_WRP_Sector_21 ((uint32_t)0x00000200) /*!< Write protection of Sector21 */
#define OB_WRP_Sector_22 ((uint32_t)0x00000400) /*!< Write protection of Sector22 */
#define OB_WRP_Sector_23 ((uint32_t)0x00000800) /*!< Write protection of Sector23 */
#define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
#define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
@@ -150,6 +224,50 @@ typedef enum
* @}
*/
/** @defgroup Selection_Protection_Mode
* @{
*/
#define OB_PcROP_Disable ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */
#define OB_PcROP_Enable ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i */
#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PcROP_Disable) || ((PCROP) == OB_PcROP_Enable))
/**
* @}
*/
/** @defgroup Option_Bytes_PC_ReadWrite_Protection
* @{
*/
#define OB_PCROP_Sector_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */
#define OB_PCROP_Sector_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */
#define OB_PCROP_Sector_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */
#define OB_PCROP_Sector_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */
#define OB_PCROP_Sector_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */
#define OB_PCROP_Sector_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */
#define OB_PCROP_Sector_6 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6 */
#define OB_PCROP_Sector_7 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7 */
#define OB_PCROP_Sector_8 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector8 */
#define OB_PCROP_Sector_9 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector9 */
#define OB_PCROP_Sector_10 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector10 */
#define OB_PCROP_Sector_11 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector11 */
#define OB_PCROP_Sector_12 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector12 */
#define OB_PCROP_Sector_13 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector13 */
#define OB_PCROP_Sector_14 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector14 */
#define OB_PCROP_Sector_15 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector15 */
#define OB_PCROP_Sector_16 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector16 */
#define OB_PCROP_Sector_17 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector17 */
#define OB_PCROP_Sector_18 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector18 */
#define OB_PCROP_Sector_19 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector19 */
#define OB_PCROP_Sector_20 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector20 */
#define OB_PCROP_Sector_21 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector21 */
#define OB_PCROP_Sector_22 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector22 */
#define OB_PCROP_Sector_23 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector23 */
#define OB_PCROP_Sector_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */
#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
/**
* @}
*/
/** @defgroup FLASH_Option_Bytes_Read_Protection
* @{
*/
@@ -207,6 +325,16 @@ typedef enum
/**
* @}
*/
/** @defgroup FLASH_Dual_Boot
* @{
*/
#define OB_Dual_BootEnabled ((uint8_t)0x10) /*!< Dual Bank Boot Enable */
#define OB_Dual_BootDisabled ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */
#define IS_OB_BOOT(BOOT) (((BOOT) == OB_Dual_BootEnabled) || ((BOOT) == OB_Dual_BootDisabled))
/**
* @}
*/
/** @defgroup FLASH_Interrupts
* @{
@@ -221,18 +349,19 @@ typedef enum
/** @defgroup FLASH_Flags
* @{
*/
#define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */
#define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */
#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
#define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */
#define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */
#define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */
#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
#define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */
#define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */
#define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */
#define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF0C) == 0x00000000) && ((FLAG) != 0x00000000))
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \
#define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */
#define FLASH_FLAG_RDERR ((uint32_t)0x00000100) /*!< Read Protection error flag (PCROP) */
#define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFE0C) == 0x00000000) && ((FLAG) != 0x00000000))
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \
((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \
((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \
((FLAG) == FLASH_FLAG_BSY))
((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_RDERR))
/**
* @}
*/
@@ -262,15 +391,30 @@ typedef enum
*/
/**
* @brief ACR register byte 0 (Bits[8:0]) base address
* @brief ACR register byte 0 (Bits[7:0]) base address
*/
#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
/**
* @brief OPTCR register byte 3 (Bits[24:16]) base address
* @brief OPTCR register byte 0 (Bits[7:0]) base address
*/
#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14)
/**
* @brief OPTCR register byte 1 (Bits[15:8]) base address
*/
#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)
/**
* @brief OPTCR register byte 2 (Bits[23:16]) base address
*/
#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16)
/**
* @brief OPTCR register byte 3 (Bits[31:24]) base address
*/
#define OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17)
/**
* @brief OPTCR1 register byte 0 (Bits[7:0]) base address
*/
#define OPTCR1_BYTE2_ADDRESS ((uint32_t)0x40023C1A)
/**
* @}
@@ -288,32 +432,42 @@ void FLASH_InstructionCacheReset(void);
void FLASH_DataCacheReset(void);
/* FLASH Memory Programming functions *****************************************/
void FLASH_Unlock(void);
void FLASH_Lock(void);
void FLASH_Unlock(void);
void FLASH_Lock(void);
FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange);
FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange);
FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange);
FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange);
FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data);
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data);
/* Option Bytes Programming functions *****************************************/
void FLASH_OB_Unlock(void);
void FLASH_OB_Lock(void);
void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
void FLASH_OB_RDPConfig(uint8_t OB_RDP);
void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
void FLASH_OB_BORConfig(uint8_t OB_BOR);
void FLASH_OB_Unlock(void);
void FLASH_OB_Lock(void);
void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState);
void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP);
void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState);
void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState);
void FLASH_OB_RDPConfig(uint8_t OB_RDP);
void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
void FLASH_OB_BORConfig(uint8_t OB_BOR);
void FLASH_OB_BootConfig(uint8_t OB_BOOT);
FLASH_Status FLASH_OB_Launch(void);
uint8_t FLASH_OB_GetUser(void);
uint16_t FLASH_OB_GetWRP(void);
FlagStatus FLASH_OB_GetRDP(void);
uint8_t FLASH_OB_GetBOR(void);
uint8_t FLASH_OB_GetUser(void);
uint16_t FLASH_OB_GetWRP(void);
uint16_t FLASH_OB_GetWRP1(void);
uint16_t FLASH_OB_GetPCROP(void);
uint16_t FLASH_OB_GetPCROP1(void);
FlagStatus FLASH_OB_GetRDP(void);
uint8_t FLASH_OB_GetBOR(void);
/* Interrupts and flags management functions **********************************/
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
FLASH_Status FLASH_GetStatus(void);
FLASH_Status FLASH_WaitForLastOperation(void);
@@ -331,4 +485,4 @@ FLASH_Status FLASH_WaitForLastOperation(void);
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

103
example/libs/StmCoreNPheriph/inc/stm32f4xx_flash_ramfunc.h Normal file
View File

@@ -0,0 +1,103 @@
/**
******************************************************************************
* @file stm32f4xx_flash_ramfunc.h
* @author MCD Application Team
* @version V1.4.0
* @date 04-August-2014
* @brief Header file of FLASH RAMFUNC driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_FLASH_RAMFUNC_H
#define __STM32F4xx_FLASH_RAMFUNC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup FLASH RAMFUNC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/**
* @brief __RAM_FUNC definition
*/
#if defined ( __CC_ARM )
/* ARM Compiler
------------
RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
dialog.
*/
#define __RAM_FUNC void
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
RAM functions are defined using a specific toolchain keyword "__ramfunc".
*/
#define __RAM_FUNC __ramfunc void
#elif defined ( __GNUC__ )
/* GNU Compiler
------------
RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
*/
#define __RAM_FUNC void __attribute__((section(".RamFunc")))
#endif
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
__RAM_FUNC FLASH_FlashInterfaceCmd(FunctionalState NewState);
__RAM_FUNC FLASH_FlashSleepModeCmd(FunctionalState NewState);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_FLASH_RAMFUNC_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

44
example/libs/StmCoreNPheriph/inc/stm32f4xx_fsmc.h
View File

@@ -2,21 +2,27 @@
******************************************************************************
* @file stm32f4xx_fsmc.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the FSMC firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -91,7 +97,7 @@ typedef struct
This parameter can be a value of @ref FSMC_NORSRAM_Bank */
uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
multiplexed on the databus or not.
multiplexed on the data bus or not.
This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
@@ -125,7 +131,7 @@ typedef struct
uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
This parameter can be a value of @ref FSMC_Write_Operation */
uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait state insertion via wait
signal, valid for Flash memory access in burst mode.
This parameter can be a value of @ref FSMC_Wait_Signal */
@@ -135,9 +141,9 @@ typedef struct
uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
This parameter can be a value of @ref FSMC_Write_Burst */
FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the Extended Mode is not used*/
FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the Extended Mode is used*/
}FSMC_NORSRAMInitTypeDef;
/**
@@ -146,26 +152,26 @@ typedef struct
typedef struct
{
uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
the command assertion for NAND-Flash read or write access
the command assertion for NAND Flash read or write access
to common/Attribute or I/O memory space (depending on
the memory space timing to be configured).
This parameter can be a value between 0 and 0xFF.*/
uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
command for NAND-Flash read or write access to
command for NAND Flash read or write access to
common/Attribute or I/O memory space (depending on the
memory space timing to be configured).
This parameter can be a number between 0x00 and 0xFF */
uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
(and data for write access) after the command deassertion
for NAND-Flash read or write access to common/Attribute
(and data for write access) after the command de-assertion
for NAND Flash read or write access to common/Attribute
or I/O memory space (depending on the memory space timing
to be configured).
This parameter can be a number between 0x00 and 0xFF */
uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
databus is kept in HiZ after the start of a NAND-Flash
data bus is kept in HiZ after the start of a NAND Flash
write access to common/Attribute or I/O memory space (depending
on the memory space timing to be configured).
This parameter can be a number between 0x00 and 0xFF */
@@ -666,4 +672,4 @@ void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

198
example/libs/StmCoreNPheriph/inc/stm32f4xx_gpio.h
View File

@@ -2,21 +2,27 @@
******************************************************************************
* @file stm32f4xx_gpio.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the GPIO firmware
* library.
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -49,8 +55,10 @@
((PERIPH) == GPIOF) || \
((PERIPH) == GPIOG) || \
((PERIPH) == GPIOH) || \
((PERIPH) == GPIOI))
((PERIPH) == GPIOI) || \
((PERIPH) == GPIOJ) || \
((PERIPH) == GPIOK))
/**
* @brief GPIO Configuration Mode enumeration
*/
@@ -80,13 +88,20 @@ typedef enum
*/
typedef enum
{
GPIO_Speed_2MHz = 0x00, /*!< Low speed */
GPIO_Speed_25MHz = 0x01, /*!< Medium speed */
GPIO_Speed_50MHz = 0x02, /*!< Fast speed */
GPIO_Speed_100MHz = 0x03 /*!< High speed on 30 pF (80 MHz Output max speed on 15 pF) */
GPIO_Low_Speed = 0x00, /*!< Low speed */
GPIO_Medium_Speed = 0x01, /*!< Medium speed */
GPIO_Fast_Speed = 0x02, /*!< Fast speed */
GPIO_High_Speed = 0x03 /*!< High speed */
}GPIOSpeed_TypeDef;
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_2MHz) || ((SPEED) == GPIO_Speed_25MHz) || \
((SPEED) == GPIO_Speed_50MHz)|| ((SPEED) == GPIO_Speed_100MHz))
/* Add legacy definition */
#define GPIO_Speed_2MHz GPIO_Low_Speed
#define GPIO_Speed_25MHz GPIO_Medium_Speed
#define GPIO_Speed_50MHz GPIO_Fast_Speed
#define GPIO_Speed_100MHz GPIO_High_Speed
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Low_Speed) || ((SPEED) == GPIO_Medium_Speed) || \
((SPEED) == GPIO_Fast_Speed)|| ((SPEED) == GPIO_High_Speed))
/**
* @brief GPIO Configuration PullUp PullDown enumeration
@@ -159,7 +174,8 @@ typedef struct
#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */
#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
((PIN) == GPIO_Pin_1) || \
((PIN) == GPIO_Pin_2) || \
@@ -264,38 +280,56 @@ typedef struct
/**
* @brief AF 5 selection
*/
#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
#define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping (Only for STM32F411xE Devices) */
#define GPIO_AF_SPI4 ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */
#define GPIO_AF_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
#define GPIO_AF_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
/**
* @brief AF 6 selection
*/
#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping (Only for STM32F411xE Devices) */
#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping (Only for STM32F411xE Devices) */
#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5 Alternate Function mapping (Only for STM32F411xE Devices) */
#define GPIO_AF_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
/**
* @brief AF 7 selection
*/
#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
#define GPIO_AF_I2S3ext ((uint8_t)0x07) /* I2S3ext Alternate Function mapping */
#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3ext Alternate Function mapping */
/**
* @brief AF 7 selection Legacy
*/
#define GPIO_AF_I2S3ext GPIO_AF7_SPI3
/**
* @brief AF 8 selection
*/
#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
#define GPIO_AF_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */
#define GPIO_AF_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
/**
* @brief AF 9 selection
*/
#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping (Only for STM32F401xx/STM32F411xE Devices) */
#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping (Only for STM32F401xx/STM32F411xE Devices) */
/**
* @brief AF 10 selection
*/
@@ -310,38 +344,100 @@ typedef struct
/**
* @brief AF 12 selection
*/
#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */
#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
#if defined (STM32F40_41xxx)
#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */
#endif /* STM32F40_41xxx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define GPIO_AF_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
#endif /* STM32F427_437xx || STM32F429_439xx */
#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
/**
* @brief AF 13 selection
*/
#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
/**
* @brief AF 14 selection
*/
#define GPIO_AF_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */
/**
* @brief AF 15 selection
*/
#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \
((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \
((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \
((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_FSMC) || \
((AF) == GPIO_AF_OTG_HS_FS) || ((AF) == GPIO_AF_SDIO) || \
((AF) == GPIO_AF_DCMI) || ((AF) == GPIO_AF_EVENTOUT))
#if defined (STM32F40_41xxx)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \
((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \
((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \
((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \
((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \
((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_FSMC))
#endif /* STM32F40_41xxx */
#if defined (STM32F401xx)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_USART6) || \
((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4))
#endif /* STM32F401xx */
#if defined (STM32F411xE)
#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 13) && ((AF) != 14))
#endif /* STM32F411xE */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \
((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \
((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \
((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \
((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \
((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4) || \
((AF) == GPIO_AF_SPI5) || ((AF) == GPIO_AF_SPI6) || \
((AF) == GPIO_AF_UART7) || ((AF) == GPIO_AF_UART8) || \
((AF) == GPIO_AF_FMC) || ((AF) == GPIO_AF_SAI1) || \
((AF) == GPIO_AF_LTDC))
#endif /* STM32F427_437xx || STM32F429_439xx */
/**
* @}
*/
@@ -365,7 +461,7 @@ typedef struct
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Function used to set the GPIO configuration to the default reset state ****/
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
@@ -403,4 +499,4 @@ void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

93
example/libs/StmCoreNPheriph/inc/stm32f4xx_hash.h
View File

@@ -2,21 +2,27 @@
******************************************************************************
* @file stm32f4xx_hash.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the HASH
* firmware library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -46,12 +52,12 @@
*/
typedef struct
{
uint32_t HASH_AlgoSelection; /*!< SHA-1 or MD5. This parameter can be a value
of @ref HASH_Algo_Selection */
uint32_t HASH_AlgoSelection; /*!< SHA-1, SHA-224, SHA-256 or MD5. This parameter
can be a value of @ref HASH_Algo_Selection */
uint32_t HASH_AlgoMode; /*!< HASH or HMAC. This parameter can be a value
of @ref HASH_processor_Algorithm_Mode */
uint32_t HASH_DataType; /*!< 32-bit data, 16-bit data, 8-bit data or
bit-string. This parameter can be a value of
bit string. This parameter can be a value of
@ref HASH_Data_Type */
uint32_t HASH_HMACKeyType; /*!< HMAC Short key or HMAC Long Key. This parameter
can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */
@@ -62,7 +68,9 @@ typedef struct
*/
typedef struct
{
uint32_t Data[5]; /*!< Message digest result : 5x 32bit words for SHA1 or
uint32_t Data[8]; /*!< Message digest result : 8x 32bit wors for SHA-256,
7x 32bit wors for SHA-224,
5x 32bit words for SHA-1 or
4x 32bit words for MD5 */
} HASH_MsgDigest;
@@ -74,7 +82,7 @@ typedef struct
uint32_t HASH_IMR;
uint32_t HASH_STR;
uint32_t HASH_CR;
uint32_t HASH_CSR[51];
uint32_t HASH_CSR[54];
}HASH_Context;
/* Exported constants --------------------------------------------------------*/
@@ -86,10 +94,14 @@ typedef struct
/** @defgroup HASH_Algo_Selection
* @{
*/
#define HASH_AlgoSelection_SHA1 ((uint16_t)0x0000) /*!< HASH function is SHA1 */
#define HASH_AlgoSelection_MD5 ((uint16_t)0x0080) /*!< HASH function is MD5 */
#define HASH_AlgoSelection_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */
#define HASH_AlgoSelection_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */
#define HASH_AlgoSelection_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */
#define HASH_AlgoSelection_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \
((ALGOSELECTION) == HASH_AlgoSelection_SHA224) || \
((ALGOSELECTION) == HASH_AlgoSelection_SHA256) || \
((ALGOSELECTION) == HASH_AlgoSelection_MD5))
/**
* @}
@@ -98,8 +110,8 @@ typedef struct
/** @defgroup HASH_processor_Algorithm_Mode
* @{
*/
#define HASH_AlgoMode_HASH ((uint16_t)0x0000) /*!< Algorithm is HASH */
#define HASH_AlgoMode_HMAC ((uint16_t)0x0040) /*!< Algorithm is HMAC */
#define HASH_AlgoMode_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */
#define HASH_AlgoMode_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \
((ALGOMODE) == HASH_AlgoMode_HMAC))
@@ -110,14 +122,14 @@ typedef struct
/** @defgroup HASH_Data_Type
* @{
*/
#define HASH_DataType_32b ((uint16_t)0x0000)
#define HASH_DataType_16b ((uint16_t)0x0010)
#define HASH_DataType_8b ((uint16_t)0x0020)
#define HASH_DataType_1b ((uint16_t)0x0030)
#define HASH_DataType_32b ((uint32_t)0x0000) /*!< 32-bit data. No swapping */
#define HASH_DataType_16b HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
#define HASH_DataType_8b HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
#define HASH_DataType_1b HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \
((DATATYPE) == HASH_DataType_16b)|| \
((DATATYPE) == HASH_DataType_8b)|| \
((DATATYPE) == HASH_DataType_8b) || \
((DATATYPE) == HASH_DataType_1b))
/**
* @}
@@ -127,10 +139,10 @@ typedef struct
* @{
*/
#define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */
#define HASH_HMACKeyType_LongKey ((uint32_t)0x00010000) /*!< HMAC Key is > 64 bytes */
#define HASH_HMACKeyType_LongKey HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */
#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \
((KEYTYPE) == HASH_HMACKeyType_LongKey))
((KEYTYPE) == HASH_HMACKeyType_LongKey))
/**
* @}
*/
@@ -147,10 +159,10 @@ typedef struct
/** @defgroup HASH_interrupts_definition
* @{
*/
#define HASH_IT_DINI ((uint8_t)0x01) /*!< A new block can be entered into the input buffer (DIN)*/
#define HASH_IT_DCI ((uint8_t)0x02) /*!< Digest calculation complete */
#define HASH_IT_DINI HASH_IMR_DINIM /*!< A new block can be entered into the input buffer (DIN) */
#define HASH_IT_DCI HASH_IMR_DCIM /*!< Digest calculation complete */
#define IS_HASH_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00))
#define IS_HASH_IT(IT) ((((IT) & (uint32_t)0xFFFFFFFC) == 0x00000000) && ((IT) != 0x00000000))
#define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI))
/**
@@ -160,11 +172,11 @@ typedef struct
/** @defgroup HASH_flags_definition
* @{
*/
#define HASH_FLAG_DINIS ((uint16_t)0x0001) /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer.*/
#define HASH_FLAG_DCIS ((uint16_t)0x0002) /*!< Digest calculation complete */
#define HASH_FLAG_DMAS ((uint16_t)0x0004) /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
#define HASH_FLAG_BUSY ((uint16_t)0x0008) /*!< The hash core is Busy : processing a block of data */
#define HASH_FLAG_DINNE ((uint16_t)0x1000) /*!< DIN not empty : The input buffer contains at least one word of data */
#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */
#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy : processing a block of data */
#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : The input buffer contains at least one word of data */
#define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \
((FLAG) == HASH_FLAG_DCIS) || \
@@ -199,21 +211,22 @@ void HASH_DataIn(uint32_t Data);
uint8_t HASH_GetInFIFOWordsNbr(void);
void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber);
void HASH_StartDigest(void);
void HASH_AutoStartDigest(FunctionalState NewState);
void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest);
/* HASH Context swapping functions ********************************************/
void HASH_SaveContext(HASH_Context* HASH_ContextSave);
void HASH_RestoreContext(HASH_Context* HASH_ContextRestore);
/* HASH's DMA interface function **********************************************/
/* HASH DMA interface function ************************************************/
void HASH_DMACmd(FunctionalState NewState);
/* HASH Interrupts and flags management functions *****************************/
void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState);
FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG);
void HASH_ClearFlag(uint16_t HASH_FLAG);
ITStatus HASH_GetITStatus(uint8_t HASH_IT);
void HASH_ClearITPendingBit(uint8_t HASH_IT);
void HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState);
FlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG);
void HASH_ClearFlag(uint32_t HASH_FLAG);
ITStatus HASH_GetITStatus(uint32_t HASH_IT);
void HASH_ClearITPendingBit(uint32_t HASH_IT);
/* High Level SHA1 functions **************************************************/
ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]);
@@ -241,4 +254,4 @@ ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen,
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

39
example/libs/StmCoreNPheriph/inc/stm32f4xx_i2c.h
View File

@@ -2,21 +2,27 @@
******************************************************************************
* @file stm32f4xx_i2c.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the I2C firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -76,6 +82,17 @@ typedef struct
#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
((PERIPH) == I2C2) || \
((PERIPH) == I2C3))
/** @defgroup I2C_Digital_Filter
* @{
*/
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
/**
* @}
*/
/** @defgroup I2C_mode
* @{
*/
@@ -534,6 +551,8 @@ void I2C_DeInit(I2C_TypeDef* I2Cx);
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter);
void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
@@ -689,4 +708,4 @@ void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
example/libs/StmCoreNPheriph/inc/stm32f4xx_iwdg.h
View File

@@ -2,21 +2,27 @@
******************************************************************************
* @file stm32f4xx_iwdg.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the IWDG
* firmware library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -122,4 +128,4 @@ FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

531
example/libs/StmCoreNPheriph/inc/stm32f4xx_ltdc.h Normal file
View File

@@ -0,0 +1,531 @@
/**
******************************************************************************
* @file stm32f4xx_ltdc.h
* @author MCD Application Team
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the LTDC firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_LTDC_H
#define __STM32F4xx_LTDC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup LTDC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief LTDC Init structure definition
*/
typedef struct
{
uint32_t LTDC_HSPolarity; /*!< configures the horizontal synchronization polarity.
This parameter can be one value of @ref LTDC_HSPolarity */
uint32_t LTDC_VSPolarity; /*!< configures the vertical synchronization polarity.
This parameter can be one value of @ref LTDC_VSPolarity */
uint32_t LTDC_DEPolarity; /*!< configures the data enable polarity. This parameter can
be one of value of @ref LTDC_DEPolarity */
uint32_t LTDC_PCPolarity; /*!< configures the pixel clock polarity. This parameter can
be one of value of @ref LTDC_PCPolarity */
uint32_t LTDC_HorizontalSync; /*!< configures the number of Horizontal synchronization
width. This parameter must range from 0x000 to 0xFFF. */
uint32_t LTDC_VerticalSync; /*!< configures the number of Vertical synchronization
heigh. This parameter must range from 0x000 to 0x7FF. */
uint32_t LTDC_AccumulatedHBP; /*!< configures the accumulated horizontal back porch width.
This parameter must range from LTDC_HorizontalSync to 0xFFF. */
uint32_t LTDC_AccumulatedVBP; /*!< configures the accumulated vertical back porch heigh.
This parameter must range from LTDC_VerticalSync to 0x7FF. */
uint32_t LTDC_AccumulatedActiveW; /*!< configures the accumulated active width. This parameter
must range from LTDC_AccumulatedHBP to 0xFFF. */
uint32_t LTDC_AccumulatedActiveH; /*!< configures the accumulated active heigh. This parameter
must range from LTDC_AccumulatedVBP to 0x7FF. */
uint32_t LTDC_TotalWidth; /*!< configures the total width. This parameter
must range from LTDC_AccumulatedActiveW to 0xFFF. */
uint32_t LTDC_TotalHeigh; /*!< configures the total heigh. This parameter
must range from LTDC_AccumulatedActiveH to 0x7FF. */
uint32_t LTDC_BackgroundRedValue; /*!< configures the background red value.
This parameter must range from 0x00 to 0xFF. */
uint32_t LTDC_BackgroundGreenValue; /*!< configures the background green value.
This parameter must range from 0x00 to 0xFF. */
uint32_t LTDC_BackgroundBlueValue; /*!< configures the background blue value.
This parameter must range from 0x00 to 0xFF. */
} LTDC_InitTypeDef;
/**
* @brief LTDC Layer structure definition
*/
typedef struct
{
uint32_t LTDC_HorizontalStart; /*!< Configures the Window Horizontal Start Position.
This parameter must range from 0x000 to 0xFFF. */
uint32_t LTDC_HorizontalStop; /*!< Configures the Window Horizontal Stop Position.
This parameter must range from 0x0000 to 0xFFFF. */
uint32_t LTDC_VerticalStart; /*!< Configures the Window vertical Start Position.
This parameter must range from 0x000 to 0xFFF. */
uint32_t LTDC_VerticalStop; /*!< Configures the Window vaertical Stop Position.
This parameter must range from 0x0000 to 0xFFFF. */
uint32_t LTDC_PixelFormat; /*!< Specifies the pixel format. This parameter can be
one of value of @ref LTDC_Pixelformat */
uint32_t LTDC_ConstantAlpha; /*!< Specifies the constant alpha used for blending.
This parameter must range from 0x00 to 0xFF. */
uint32_t LTDC_DefaultColorBlue; /*!< Configures the default blue value.
This parameter must range from 0x00 to 0xFF. */
uint32_t LTDC_DefaultColorGreen; /*!< Configures the default green value.
This parameter must range from 0x00 to 0xFF. */
uint32_t LTDC_DefaultColorRed; /*!< Configures the default red value.
This parameter must range from 0x00 to 0xFF. */
uint32_t LTDC_DefaultColorAlpha; /*!< Configures the default alpha value.
This parameter must range from 0x00 to 0xFF. */
uint32_t LTDC_BlendingFactor_1; /*!< Select the blending factor 1. This parameter
can be one of value of @ref LTDC_BlendingFactor1 */
uint32_t LTDC_BlendingFactor_2; /*!< Select the blending factor 2. This parameter
can be one of value of @ref LTDC_BlendingFactor2 */
uint32_t LTDC_CFBStartAdress; /*!< Configures the color frame buffer address */
uint32_t LTDC_CFBLineLength; /*!< Configures the color frame buffer line length.
This parameter must range from 0x0000 to 0x1FFF. */
uint32_t LTDC_CFBPitch; /*!< Configures the color frame buffer pitch in bytes.
This parameter must range from 0x0000 to 0x1FFF. */
uint32_t LTDC_CFBLineNumber; /*!< Specifies the number of line in frame buffer.
This parameter must range from 0x000 to 0x7FF. */
} LTDC_Layer_InitTypeDef;
/**
* @brief LTDC Position structure definition
*/
typedef struct
{
uint32_t LTDC_POSX; /*!< Current X Position */
uint32_t LTDC_POSY; /*!< Current Y Position */
} LTDC_PosTypeDef;
typedef struct
{
uint32_t LTDC_BlueWidth; /*!< Blue width */
uint32_t LTDC_GreenWidth; /*!< Green width */
uint32_t LTDC_RedWidth; /*!< Red width */
} LTDC_RGBTypeDef;
typedef struct
{
uint32_t LTDC_ColorKeyBlue; /*!< Configures the color key blue value.
This parameter must range from 0x00 to 0xFF. */
uint32_t LTDC_ColorKeyGreen; /*!< Configures the color key green value.
This parameter must range from 0x00 to 0xFF. */
uint32_t LTDC_ColorKeyRed; /*!< Configures the color key red value.
This parameter must range from 0x00 to 0xFF. */
} LTDC_ColorKeying_InitTypeDef;
typedef struct
{
uint32_t LTDC_CLUTAdress; /*!< Configures the CLUT address.
This parameter must range from 0x00 to 0xFF. */
uint32_t LTDC_BlueValue; /*!< Configures the blue value.
This parameter must range from 0x00 to 0xFF. */
uint32_t LTDC_GreenValue; /*!< Configures the green value.
This parameter must range from 0x00 to 0xFF. */
uint32_t LTDC_RedValue; /*!< Configures the red value.
This parameter must range from 0x00 to 0xFF. */
} LTDC_CLUT_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup LTDC_Exported_Constants
* @}
*/
/** @defgroup LTDC_SYNC
* @{
*/
#define LTDC_HorizontalSYNC ((uint32_t)0x00000FFF)
#define LTDC_VerticalSYNC ((uint32_t)0x000007FF)
#define IS_LTDC_HSYNC(HSYNC) ((HSYNC) <= LTDC_HorizontalSYNC)
#define IS_LTDC_VSYNC(VSYNC) ((VSYNC) <= LTDC_VerticalSYNC)
#define IS_LTDC_AHBP(AHBP) ((AHBP) <= LTDC_HorizontalSYNC)
#define IS_LTDC_AVBP(AVBP) ((AVBP) <= LTDC_VerticalSYNC)
#define IS_LTDC_AAW(AAW) ((AAW) <= LTDC_HorizontalSYNC)
#define IS_LTDC_AAH(AAH) ((AAH) <= LTDC_VerticalSYNC)
#define IS_LTDC_TOTALW(TOTALW) ((TOTALW) <= LTDC_HorizontalSYNC)
#define IS_LTDC_TOTALH(TOTALH) ((TOTALH) <= LTDC_VerticalSYNC)
/**
* @}
*/
/** @defgroup LTDC_HSPolarity
* @{
*/
#define LTDC_HSPolarity_AL ((uint32_t)0x00000000) /*!< Horizontal Synchronization is active low. */
#define LTDC_HSPolarity_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */
#define IS_LTDC_HSPOL(HSPOL) (((HSPOL) == LTDC_HSPolarity_AL) || \
((HSPOL) == LTDC_HSPolarity_AH))
/**
* @}
*/
/** @defgroup LTDC_VSPolarity
* @{
*/
#define LTDC_VSPolarity_AL ((uint32_t)0x00000000) /*!< Vertical Synchronization is active low. */
#define LTDC_VSPolarity_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */
#define IS_LTDC_VSPOL(VSPOL) (((VSPOL) == LTDC_VSPolarity_AL) || \
((VSPOL) == LTDC_VSPolarity_AH))
/**
* @}
*/
/** @defgroup LTDC_DEPolarity
* @{
*/
#define LTDC_DEPolarity_AL ((uint32_t)0x00000000) /*!< Data Enable, is active low. */
#define LTDC_DEPolarity_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */
#define IS_LTDC_DEPOL(DEPOL) (((DEPOL) == LTDC_VSPolarity_AL) || \
((DEPOL) == LTDC_DEPolarity_AH))
/**
* @}
*/
/** @defgroup LTDC_PCPolarity
* @{
*/
#define LTDC_PCPolarity_IPC ((uint32_t)0x00000000) /*!< input pixel clock. */
#define LTDC_PCPolarity_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */
#define IS_LTDC_PCPOL(PCPOL) (((PCPOL) == LTDC_PCPolarity_IPC) || \
((PCPOL) == LTDC_PCPolarity_IIPC))
/**
* @}
*/
/** @defgroup LTDC_Reload
* @{
*/
#define LTDC_IMReload LTDC_SRCR_IMR /*!< Immediately Reload. */
#define LTDC_VBReload LTDC_SRCR_VBR /*!< Vertical Blanking Reload. */
#define IS_LTDC_RELOAD(RELOAD) (((RELOAD) == LTDC_IMReload) || \
((RELOAD) == LTDC_VBReload))
/**
* @}
*/
/** @defgroup LTDC_Back_Color
* @{
*/
#define LTDC_Back_Color ((uint32_t)0x000000FF)
#define IS_LTDC_BackBlueValue(BBLUE) ((BBLUE) <= LTDC_Back_Color)
#define IS_LTDC_BackGreenValue(BGREEN) ((BGREEN) <= LTDC_Back_Color)
#define IS_LTDC_BackRedValue(BRED) ((BRED) <= LTDC_Back_Color)
/**
* @}
*/
/** @defgroup LTDC_Position
* @{
*/
#define LTDC_POS_CY LTDC_CPSR_CYPOS
#define LTDC_POS_CX LTDC_CPSR_CXPOS
#define IS_LTDC_GET_POS(POS) (((POS) <= LTDC_POS_CY))
/**
* @}
*/
/** @defgroup LTDC_LIPosition
* @{
*/
#define IS_LTDC_LIPOS(LIPOS) ((LIPOS) <= 0x7FF)
/**
* @}
*/
/** @defgroup LTDC_CurrentStatus
* @{
*/
#define LTDC_CD_VDES LTDC_CDSR_VDES
#define LTDC_CD_HDES LTDC_CDSR_HDES
#define LTDC_CD_VSYNC LTDC_CDSR_VSYNCS
#define LTDC_CD_HSYNC LTDC_CDSR_HSYNCS
#define IS_LTDC_GET_CD(CD) (((CD) == LTDC_CD_VDES) || ((CD) == LTDC_CD_HDES) || \
((CD) == LTDC_CD_VSYNC) || ((CD) == LTDC_CD_HSYNC))
/**
* @}
*/
/** @defgroup LTDC_Interrupts
* @{
*/
#define LTDC_IT_LI LTDC_IER_LIE
#define LTDC_IT_FU LTDC_IER_FUIE
#define LTDC_IT_TERR LTDC_IER_TERRIE
#define LTDC_IT_RR LTDC_IER_RRIE
#define IS_LTDC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF0) == 0x00) && ((IT) != 0x00))
/**
* @}
*/
/** @defgroup LTDC_Flag
* @{
*/
#define LTDC_FLAG_LI LTDC_ISR_LIF
#define LTDC_FLAG_FU LTDC_ISR_FUIF
#define LTDC_FLAG_TERR LTDC_ISR_TERRIF
#define LTDC_FLAG_RR LTDC_ISR_RRIF
#define IS_LTDC_FLAG(FLAG) (((FLAG) == LTDC_FLAG_LI) || ((FLAG) == LTDC_FLAG_FU) || \
((FLAG) == LTDC_FLAG_TERR) || ((FLAG) == LTDC_FLAG_RR))
/**
* @}
*/
/** @defgroup LTDC_Pixelformat
* @{
*/
#define LTDC_Pixelformat_ARGB8888 ((uint32_t)0x00000000)
#define LTDC_Pixelformat_RGB888 ((uint32_t)0x00000001)
#define LTDC_Pixelformat_RGB565 ((uint32_t)0x00000002)
#define LTDC_Pixelformat_ARGB1555 ((uint32_t)0x00000003)
#define LTDC_Pixelformat_ARGB4444 ((uint32_t)0x00000004)
#define LTDC_Pixelformat_L8 ((uint32_t)0x00000005)
#define LTDC_Pixelformat_AL44 ((uint32_t)0x00000006)
#define LTDC_Pixelformat_AL88 ((uint32_t)0x00000007)
#define IS_LTDC_Pixelformat(Pixelformat) (((Pixelformat) == LTDC_Pixelformat_ARGB8888) || ((Pixelformat) == LTDC_Pixelformat_RGB888) || \
((Pixelformat) == LTDC_Pixelformat_RGB565) || ((Pixelformat) == LTDC_Pixelformat_ARGB1555) || \
((Pixelformat) == LTDC_Pixelformat_ARGB4444) || ((Pixelformat) == LTDC_Pixelformat_L8) || \
((Pixelformat) == LTDC_Pixelformat_AL44) || ((Pixelformat) == LTDC_Pixelformat_AL88))
/**
* @}
*/
/** @defgroup LTDC_BlendingFactor1
* @{
*/
#define LTDC_BlendingFactor1_CA ((uint32_t)0x00000400)
#define LTDC_BlendingFactor1_PAxCA ((uint32_t)0x00000600)
#define IS_LTDC_BlendingFactor1(BlendingFactor1) (((BlendingFactor1) == LTDC_BlendingFactor1_CA) || ((BlendingFactor1) == LTDC_BlendingFactor1_PAxCA))
/**
* @}
*/
/** @defgroup LTDC_BlendingFactor2
* @{
*/
#define LTDC_BlendingFactor2_CA ((uint32_t)0x00000005)
#define LTDC_BlendingFactor2_PAxCA ((uint32_t)0x00000007)
#define IS_LTDC_BlendingFactor2(BlendingFactor2) (((BlendingFactor2) == LTDC_BlendingFactor2_CA) || ((BlendingFactor2) == LTDC_BlendingFactor2_PAxCA))
/**
* @}
*/
/** @defgroup LTDC_LAYER_Config
* @{
*/
#define LTDC_STOPPosition ((uint32_t)0x0000FFFF)
#define LTDC_STARTPosition ((uint32_t)0x00000FFF)
#define LTDC_DefaultColorConfig ((uint32_t)0x000000FF)
#define LTDC_ColorFrameBuffer ((uint32_t)0x00001FFF)
#define LTDC_LineNumber ((uint32_t)0x000007FF)
#define IS_LTDC_HCONFIGST(HCONFIGST) ((HCONFIGST) <= LTDC_STARTPosition)
#define IS_LTDC_HCONFIGSP(HCONFIGSP) ((HCONFIGSP) <= LTDC_STOPPosition)
#define IS_LTDC_VCONFIGST(VCONFIGST) ((VCONFIGST) <= LTDC_STARTPosition)
#define IS_LTDC_VCONFIGSP(VCONFIGSP) ((VCONFIGSP) <= LTDC_STOPPosition)
#define IS_LTDC_DEFAULTCOLOR(DEFAULTCOLOR) ((DEFAULTCOLOR) <= LTDC_DefaultColorConfig)
#define IS_LTDC_CFBP(CFBP) ((CFBP) <= LTDC_ColorFrameBuffer)
#define IS_LTDC_CFBLL(CFBLL) ((CFBLL) <= LTDC_ColorFrameBuffer)
#define IS_LTDC_CFBLNBR(CFBLNBR) ((CFBLNBR) <= LTDC_LineNumber)
/**
* @}
*/
/** @defgroup LTDC_colorkeying_Config
* @{
*/
#define LTDC_colorkeyingConfig ((uint32_t)0x000000FF)
#define IS_LTDC_CKEYING(CKEYING) ((CKEYING) <= LTDC_colorkeyingConfig)
/**
* @}
*/
/** @defgroup LTDC_CLUT_Config
* @{
*/
#define LTDC_CLUTWR ((uint32_t)0x000000FF)
#define IS_LTDC_CLUTWR(CLUTWR) ((CLUTWR) <= LTDC_CLUTWR)
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the LTDC configuration to the default reset state *****/
void LTDC_DeInit(void);
/* Initialization and Configuration functions *********************************/
void LTDC_Init(LTDC_InitTypeDef* LTDC_InitStruct);
void LTDC_StructInit(LTDC_InitTypeDef* LTDC_InitStruct);
void LTDC_Cmd(FunctionalState NewState);
void LTDC_DitherCmd(FunctionalState NewState);
LTDC_RGBTypeDef LTDC_GetRGBWidth(void);
void LTDC_RGBStructInit(LTDC_RGBTypeDef* LTDC_RGB_InitStruct);
void LTDC_LIPConfig(uint32_t LTDC_LIPositionConfig);
void LTDC_ReloadConfig(uint32_t LTDC_Reload);
void LTDC_LayerInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_Layer_InitTypeDef* LTDC_Layer_InitStruct);
void LTDC_LayerStructInit(LTDC_Layer_InitTypeDef * LTDC_Layer_InitStruct);
void LTDC_LayerCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState);
LTDC_PosTypeDef LTDC_GetPosStatus(void);
void LTDC_PosStructInit(LTDC_PosTypeDef* LTDC_Pos_InitStruct);
FlagStatus LTDC_GetCDStatus(uint32_t LTDC_CD);
void LTDC_ColorKeyingConfig(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct, FunctionalState NewState);
void LTDC_ColorKeyingStructInit(LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct);
void LTDC_CLUTCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState);
void LTDC_CLUTInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct);
void LTDC_CLUTStructInit(LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct);
void LTDC_LayerPosition(LTDC_Layer_TypeDef* LTDC_Layerx, uint16_t OffsetX, uint16_t OffsetY);
void LTDC_LayerAlpha(LTDC_Layer_TypeDef* LTDC_Layerx, uint8_t ConstantAlpha);
void LTDC_LayerAddress(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Address);
void LTDC_LayerSize(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Width, uint32_t Height);
void LTDC_LayerPixelFormat(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t PixelFormat);
/* Interrupts and flags management functions **********************************/
void LTDC_ITConfig(uint32_t LTDC_IT, FunctionalState NewState);
FlagStatus LTDC_GetFlagStatus(uint32_t LTDC_FLAG);
void LTDC_ClearFlag(uint32_t LTDC_FLAG);
ITStatus LTDC_GetITStatus(uint32_t LTDC_IT);
void LTDC_ClearITPendingBit(uint32_t LTDC_IT);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_LTDC_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

93
example/libs/StmCoreNPheriph/inc/stm32f4xx_pwr.h
View File

@@ -2,21 +2,27 @@
******************************************************************************
* @file stm32f4xx_pwr.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the PWR firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -49,7 +55,6 @@
/** @defgroup PWR_PVD_detection_level
* @{
*/
#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0
#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1
#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2
@@ -71,11 +76,29 @@
/** @defgroup PWR_Regulator_state_in_STOP_mode
* @{
*/
#define PWR_MainRegulator_ON ((uint32_t)0x00000000)
#define PWR_LowPowerRegulator_ON PWR_CR_LPDS
/* --- PWR_Legacy ---*/
#define PWR_Regulator_ON PWR_MainRegulator_ON
#define PWR_Regulator_LowPower PWR_LowPowerRegulator_ON
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MainRegulator_ON) || \
((REGULATOR) == PWR_LowPowerRegulator_ON))
/**
* @}
*/
/** @defgroup PWR_Regulator_state_in_UnderDrive_mode
* @{
*/
#define PWR_MainRegulator_UnderDrive_ON PWR_CR_MRUDS
#define PWR_LowPowerRegulator_UnderDrive_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MainRegulator_UnderDrive_ON) || \
((REGULATOR) == PWR_LowPowerRegulator_UnderDrive_ON))
#define PWR_Regulator_ON ((uint32_t)0x00000000)
#define PWR_Regulator_LowPower PWR_CR_LPDS
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
((REGULATOR) == PWR_Regulator_LowPower))
/**
* @}
*/
@@ -83,19 +106,22 @@
/** @defgroup PWR_STOP_mode_entry
* @{
*/
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
/**
* @}
*/
/** @defgroup PWR_Regulator_Voltage_Scale
* @{
*/
#define PWR_Regulator_Voltage_Scale1 ((uint32_t)0x00004000)
#define PWR_Regulator_Voltage_Scale2 ((uint32_t)0x00000000)
#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || ((VOLTAGE) == PWR_Regulator_Voltage_Scale2))
#define PWR_Regulator_Voltage_Scale1 ((uint32_t)0x0000C000)
#define PWR_Regulator_Voltage_Scale2 ((uint32_t)0x00008000)
#define PWR_Regulator_Voltage_Scale3 ((uint32_t)0x00004000)
#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || \
((VOLTAGE) == PWR_Regulator_Voltage_Scale2) || \
((VOLTAGE) == PWR_Regulator_Voltage_Scale3))
/**
* @}
*/
@@ -103,26 +129,27 @@
/** @defgroup PWR_Flag
* @{
*/
#define PWR_FLAG_WU PWR_CSR_WUF
#define PWR_FLAG_SB PWR_CSR_SBF
#define PWR_FLAG_PVDO PWR_CSR_PVDO
#define PWR_FLAG_BRR PWR_CSR_BRR
#define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
#define PWR_FLAG_ODRDY PWR_CSR_ODRDY
#define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY
#define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY
/** @defgroup PWR_Flag_Legacy
* @{
*/
/* --- FLAG Legacy ---*/
#define PWR_FLAG_REGRDY PWR_FLAG_VOSRDY
/**
* @}
*/
#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \
((FLAG) == PWR_FLAG_VOSRDY))
((FLAG) == PWR_FLAG_VOSRDY) || ((FLAG) == PWR_FLAG_ODRDY) || \
((FLAG) == PWR_FLAG_ODSWRDY) || ((FLAG) == PWR_FLAG_UDRDY))
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
((FLAG) == PWR_FLAG_UDRDY))
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
/**
* @}
*/
@@ -150,12 +177,18 @@ void PWR_WakeUpPinCmd(FunctionalState NewState);
/* Main and Backup Regulators configuration functions *************************/
void PWR_BackupRegulatorCmd(FunctionalState NewState);
void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage);
void PWR_OverDriveCmd(FunctionalState NewState);
void PWR_OverDriveSWCmd(FunctionalState NewState);
void PWR_UnderDriveCmd(FunctionalState NewState);
void PWR_MainRegulatorLowVoltageCmd(FunctionalState NewState);
void PWR_LowRegulatorLowVoltageCmd(FunctionalState NewState);
/* FLASH Power Down configuration functions ***********************************/
void PWR_FlashPowerDownCmd(FunctionalState NewState);
/* Low Power modes configuration functions ************************************/
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
void PWR_EnterSTANDBYMode(void);
/* Flags management functions *************************************************/
@@ -176,4 +209,4 @@ void PWR_ClearFlag(uint32_t PWR_FLAG);
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

274
example/libs/StmCoreNPheriph/inc/stm32f4xx_rcc.h
View File

@@ -2,20 +2,26 @@
******************************************************************************
* @file stm32f4xx_rcc.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the RCC firmware library.
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the RCC firmware library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -42,9 +48,9 @@
typedef struct
{
uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */
uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */
uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */
uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */
uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */
uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */
uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */
}RCC_ClocksTypeDef;
/* Exported constants --------------------------------------------------------*/
@@ -64,7 +70,18 @@ typedef struct
/**
* @}
*/
/** @defgroup RCC_LSE_Dual_Mode_Selection
* @{
*/
#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \
((MODE) == RCC_LSE_HIGHDRIVE_MODE))
/**
* @}
*/
/** @defgroup RCC_PLL_Clock_Source
* @{
*/
@@ -78,7 +95,26 @@ typedef struct
#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
#define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
#define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000)
#define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000)
#define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000)
#define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000)
#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\
((VALUE) == RCC_PLLSAIDivR_Div4) ||\
((VALUE) == RCC_PLLSAIDivR_Div8) ||\
((VALUE) == RCC_PLLSAIDivR_Div16))
/**
* @}
*/
@@ -140,14 +176,17 @@ typedef struct
#define RCC_IT_HSIRDY ((uint8_t)0x04)
#define RCC_IT_HSERDY ((uint8_t)0x08)
#define RCC_IT_PLLRDY ((uint8_t)0x10)
#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
#define RCC_IT_PLLSAIRDY ((uint8_t)0x40)
#define RCC_IT_CSS ((uint8_t)0x80)
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
((IT) == RCC_IT_PLLI2SRDY))
#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY))
#define IS_RCC_CLEAR_IT(IT)((IT) != 0x00)
/**
* @}
*/
@@ -245,6 +284,45 @@ typedef struct
/**
* @}
*/
/** @defgroup RCC_SAI_BlockA_Clock_Source
* @{
*/
#define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000)
#define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000)
#define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000)
#define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\
((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\
((SOURCE) == RCC_SAIACLKSource_Ext))
/**
* @}
*/
/** @defgroup RCC_SAI_BlockB_Clock_Source
* @{
*/
#define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000)
#define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000)
#define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000)
#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\
((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\
((SOURCE) == RCC_SAIBCLKSource_Ext))
/**
* @}
*/
/** @defgroup RCC_TIM_PRescaler_Selection
* @{
*/
#define RCC_TIMPrescDesactivated ((uint8_t)0x00)
#define RCC_TIMPrescActivated ((uint8_t)0x01)
#define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated))
/**
* @}
*/
/** @defgroup RCC_AHB1_Peripherals
* @{
@@ -257,24 +335,30 @@ typedef struct
#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)
#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)
#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)
#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
#define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200)
#define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400)
#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)
#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000)
#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)
#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000)
#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)
#define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000)
#define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)
#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)
#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)
#define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000)
#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)
#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)
#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000)
#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)
#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)
#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)
#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x818BEE00) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81986E00) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x810BE800) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD1FE800) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81106800) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
@@ -295,7 +379,14 @@ typedef struct
/** @defgroup RCC_AHB3_Peripherals
* @{
*/
#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
#if defined (STM32F40_41xxx)
#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
#endif /* STM32F40_41xxx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define RCC_AHB3Periph_FMC ((uint32_t)0x00000001)
#endif /* STM32F427_437xx || STM32F429_439xx */
#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
@@ -327,7 +418,9 @@ typedef struct
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC9013600) == 0x00) && ((PERIPH) != 0x00))
#define RCC_APB1Periph_UART7 ((uint32_t)0x40000000)
#define RCC_APB1Periph_UART8 ((uint32_t)0x80000000)
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x09013600) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
@@ -345,12 +438,19 @@ typedef struct
#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400)
#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800)
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
#define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000)
#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000)
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)
#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A0CC) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A6CC) == 0x00) && ((PERIPH) != 0x00))
#define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000)
#define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000)
#define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000)
#define RCC_APB2Periph_LTDC ((uint32_t)0x04000000)
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFB8880CC) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFB8886CC) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
@@ -406,6 +506,7 @@ typedef struct
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D)
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
#define RCC_FLAG_BORRST ((uint8_t)0x79)
@@ -415,13 +516,15 @@ typedef struct
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
((FLAG) == RCC_FLAG_PLLI2SRDY))
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \
((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY))
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
/**
* @}
@@ -438,60 +541,77 @@ typedef struct
void RCC_DeInit(void);
/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
void RCC_HSEConfig(uint8_t RCC_HSE);
void RCC_HSEConfig(uint8_t RCC_HSE);
ErrorStatus RCC_WaitForHSEStartUp(void);
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
void RCC_HSICmd(FunctionalState NewState);
void RCC_LSEConfig(uint8_t RCC_LSE);
void RCC_LSICmd(FunctionalState NewState);
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
void RCC_HSICmd(FunctionalState NewState);
void RCC_LSEConfig(uint8_t RCC_LSE);
void RCC_LSICmd(FunctionalState NewState);
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
void RCC_PLLCmd(FunctionalState NewState);
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
void RCC_PLLCmd(FunctionalState NewState);
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
void RCC_PLLI2SCmd(FunctionalState NewState);
#if defined (STM32F40_41xxx) || defined (STM32F401xx)
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
#elif defined (STM32F411xE)
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM);
#elif defined (STM32F427_437xx) || defined (STM32F429_439xx)
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR);
#else
#endif /* STM32F40_41xxx || STM32F401xx */
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
void RCC_PLLI2SCmd(FunctionalState NewState);
void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR);
void RCC_PLLSAICmd(FunctionalState NewState);
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
/* System, AHB and APB busses clocks configuration functions ******************/
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
uint8_t RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
void RCC_PCLK1Config(uint32_t RCC_HCLK);
void RCC_PCLK2Config(uint32_t RCC_HCLK);
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
uint8_t RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
void RCC_PCLK1Config(uint32_t RCC_HCLK);
void RCC_PCLK2Config(uint32_t RCC_HCLK);
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
/* Peripheral clocks configuration functions **********************************/
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_BackupResetCmd(FunctionalState NewState);
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_BackupResetCmd(FunctionalState NewState);
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ);
void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ);
void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource);
void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource);
void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR);
void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);
void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_LSEModeConfig(uint8_t Mode);
/* Interrupts and flags management functions **********************************/
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
void RCC_ClearITPendingBit(uint8_t RCC_IT);
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
void RCC_ClearITPendingBit(uint8_t RCC_IT);
#ifdef __cplusplus
}
@@ -507,4 +627,4 @@ void RCC_ClearITPendingBit(uint8_t RCC_IT);
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
example/libs/StmCoreNPheriph/inc/stm32f4xx_rng.h
View File

@@ -2,21 +2,27 @@
******************************************************************************
* @file stm32f4xx_rng.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the Random
* Number Generator(RNG) firmware library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -111,4 +117,4 @@ void RNG_ClearITPendingBit(uint8_t RNG_IT);
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
example/libs/StmCoreNPheriph/inc/stm32f4xx_rtc.h
View File

@@ -2,21 +2,27 @@
******************************************************************************
* @file stm32f4xx_rtc.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the RTC firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -872,4 +878,4 @@ void RTC_ClearITPendingBit(uint32_t RTC_IT);
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

611
example/libs/StmCoreNPheriph/inc/stm32f4xx_sai.h Normal file
View File

@@ -0,0 +1,611 @@
/**
******************************************************************************
* @file stm32f4xx_sai.h
* @author MCD Application Team
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the SAI
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_SAI_H
#define __STM32F4xx_SAI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup SAI
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief SAI Block Init structure definition
*/
typedef struct
{
uint32_t SAI_AudioMode; /*!< Specifies the SAI Block Audio Mode.
This parameter can be a value of @ref SAI_Block_Mode */
uint32_t SAI_Protocol; /*!< Specifies the SAI Block Protocol.
This parameter can be a value of @ref SAI_Block_Protocol */
uint32_t SAI_DataSize; /*!< Specifies the SAI Block data size.
This parameter can be a value of @ref SAI_Block_Data_Size
@note this value is ignored when AC'97 or SPDIF protocols are selected.*/
uint32_t SAI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission
@note this value has no meaning when AC'97 or SPDIF protocols are selected.*/
uint32_t SAI_ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity.
This parameter can be a value of @ref SAI_Block_Clock_Strobing */
uint32_t SAI_Synchro; /*!< Specifies SAI Block synchronization
This parameter can be a value of @ref SAI_Block_Synchronization */
uint32_t SAI_OUTDRIV; /*!< Specifies when SAI Block outputs are driven.
This parameter can be a value of @ref SAI_Block_Output_Drive
@note this value has to be set before enabling the audio block
but after the audio block configuration. */
uint32_t SAI_NoDivider; /*!< Specifies whether Master Clock will be divided or not.
This parameter can be a value of @ref SAI_Block_NoDivider */
uint32_t SAI_MasterDivider; /*!< Specifies SAI Block Master Clock Divider.
@note the Master Clock Frequency is calculated accordingly to the
following formula : MCLK_x = SAI_CK_x/(MCKDIV[3:0]*2)*/
uint32_t SAI_FIFOThreshold; /*!< Specifies SAI Block FIFO Threshold.
This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
}SAI_InitTypeDef;
/**
* @brief SAI Block Frame Init structure definition
*/
typedef struct
{
uint32_t SAI_FrameLength; /*!< Specifies the Frame Length, the number of SCK clocks
for each audio frame.
This parameter must be a number between 8 and 256.
@note If master Clock MCLK_x pin is declared as an output, the frame length
should be Aligned to a number equal to power of 2 in order to keep
in an audio frame, an integer number of MCLK pulses by bit Clock.
@note this value is ignored when AC'97 or SPDIF protocols are selected.*/
uint32_t SAI_ActiveFrameLength; /*!< Specifies the Frame synchronization active level length.
This Parameter specifies the length in number of bit clock (SCK + 1)
of the active level of FS signal in audio frame.
This parameter must be a number between 1 and 128.
@note this value is ignored when AC'97 or SPDIF protocols are selected.*/
uint32_t SAI_FSDefinition; /*!< Specifies the Frame Synchronization definition.
This parameter can be a value of @ref SAI_Block_FS_Definition
@note this value is ignored when AC'97 or SPDIF protocols are selected.*/
uint32_t SAI_FSPolarity; /*!< Specifies the Frame Synchronization Polarity.
This parameter can be a value of @ref SAI_Block_FS_Polarity
@note this value is ignored when AC'97 or SPDIF protocols are selected.*/
uint32_t SAI_FSOffset; /*!< Specifies the Frame Synchronization Offset.
This parameter can be a value of @ref SAI_Block_FS_Offset
@note this value is ignored when AC'97 or SPDIF protocols are selected.*/
}SAI_FrameInitTypeDef;
/**
* @brief SAI Block Slot Init Structure definition
*/
typedef struct
{
uint32_t SAI_FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot.
This parameter must be a number between 0 and 24.
@note this value is ignored when AC'97 or SPDIF protocols are selected.*/
uint32_t SAI_SlotSize; /*!< Specifies the Slot Size.
This parameter can be a value of @ref SAI_Block_Slot_Size
@note this value is ignored when AC'97 or SPDIF protocols are selected.*/
uint32_t SAI_SlotNumber; /*!< Specifies the number of slot in the audio frame.
This parameter must be a number between 1 and 16.
@note this value is ignored when AC'97 or SPDIF protocols are selected.*/
uint32_t SAI_SlotActive; /*!< Specifies the slots in audio frame that will be activated.
This parameter can be a value of @ ref SAI_Block_Slot_Active
@note this value is ignored when AC'97 or SPDIF protocols are selected.*/
}SAI_SlotInitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup SAI_Exported_Constants
* @{
*/
#define IS_SAI_PERIPH(PERIPH) ((PERIPH) == SAI1)
#define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \
((PERIPH) == SAI1_Block_B))
/** @defgroup SAI_Block_Mode
* @{
*/
#define SAI_Mode_MasterTx ((uint32_t)0x00000000)
#define SAI_Mode_MasterRx ((uint32_t)0x00000001)
#define SAI_Mode_SlaveTx ((uint32_t)0x00000002)
#define SAI_Mode_SlaveRx ((uint32_t)0x00000003)
#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_Mode_MasterTx) || \
((MODE) == SAI_Mode_MasterRx) || \
((MODE) == SAI_Mode_SlaveTx) || \
((MODE) == SAI_Mode_SlaveRx))
/**
* @}
*/
/** @defgroup SAI_Block_Protocol
* @{
*/
#define SAI_Free_Protocol ((uint32_t)0x00000000)
#define SAI_SPDIF_Protocol ((uint32_t)SAI_xCR1_PRTCFG_0)
#define SAI_AC97_Protocol ((uint32_t)SAI_xCR1_PRTCFG_1)
#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_Free_Protocol) || \
((PROTOCOL) == SAI_SPDIF_Protocol) || \
((PROTOCOL) == SAI_AC97_Protocol))
/**
* @}
*/
/** @defgroup SAI_Block_Data_Size
* @{
*/
#define SAI_DataSize_8b ((uint32_t)0x00000040)
#define SAI_DataSize_10b ((uint32_t)0x00000060)
#define SAI_DataSize_16b ((uint32_t)0x00000080)
#define SAI_DataSize_20b ((uint32_t)0x000000A0)
#define SAI_DataSize_24b ((uint32_t)0x000000C0)
#define SAI_DataSize_32b ((uint32_t)0x000000E0)
#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DataSize_8b) || \
((DATASIZE) == SAI_DataSize_10b) || \
((DATASIZE) == SAI_DataSize_16b) || \
((DATASIZE) == SAI_DataSize_20b) || \
((DATASIZE) == SAI_DataSize_24b) || \
((DATASIZE) == SAI_DataSize_32b))
/**
* @}
*/
/** @defgroup SAI_Block_MSB_LSB_transmission
* @{
*/
#define SAI_FirstBit_MSB ((uint32_t)0x00000000)
#define SAI_FirstBit_LSB ((uint32_t)SAI_xCR1_LSBFIRST)
#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FirstBit_MSB) || \
((BIT) == SAI_FirstBit_LSB))
/**
* @}
*/
/** @defgroup SAI_Block_Clock_Strobing
* @{
*/
#define SAI_ClockStrobing_FallingEdge ((uint32_t)0x00000000)
#define SAI_ClockStrobing_RisingEdge ((uint32_t)SAI_xCR1_CKSTR)
#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_ClockStrobing_FallingEdge) || \
((CLOCK) == SAI_ClockStrobing_RisingEdge))
/**
* @}
*/
/** @defgroup SAI_Block_Synchronization
* @{
*/
#define SAI_Asynchronous ((uint32_t)0x00000000)
#define SAI_Synchronous ((uint32_t)SAI_xCR1_SYNCEN_0)
#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_Synchronous) || \
((SYNCHRO) == SAI_Asynchronous))
/**
* @}
*/
/** @defgroup SAI_Block_Output_Drive
* @{
*/
#define SAI_OutputDrive_Disabled ((uint32_t)0x00000000)
#define SAI_OutputDrive_Enabled ((uint32_t)SAI_xCR1_OUTDRIV)
#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OutputDrive_Disabled) || \
((DRIVE) == SAI_OutputDrive_Enabled))
/**
* @}
*/
/** @defgroup SAI_Block_NoDivider
* @{
*/
#define SAI_MasterDivider_Enabled ((uint32_t)0x00000000)
#define SAI_MasterDivider_Disabled ((uint32_t)SAI_xCR1_NODIV)
#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MasterDivider_Enabled) || \
((NODIVIDER) == SAI_MasterDivider_Disabled))
/**
* @}
*/
/** @defgroup SAI_Block_Master_Divider
* @{
*/
#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)
/**
* @}
*/
/** @defgroup SAI_Block_Frame_Length
* @{
*/
#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
/**
* @}
*/
/** @defgroup SAI_Block_Active_FrameLength
* @{
*/
#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))
/**
* @}
*/
/** @defgroup SAI_Block_FS_Definition
* @{
*/
#define SAI_FS_StartFrame ((uint32_t)0x00000000)
#define I2S_FS_ChannelIdentification ((uint32_t)SAI_xFRCR_FSDEF)
#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_StartFrame) || \
((DEFINITION) == I2S_FS_ChannelIdentification))
/**
* @}
*/
/** @defgroup SAI_Block_FS_Polarity
* @{
*/
#define SAI_FS_ActiveLow ((uint32_t)0x00000000)
#define SAI_FS_ActiveHigh ((uint32_t)SAI_xFRCR_FSPO)
#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ActiveLow) || \
((POLARITY) == SAI_FS_ActiveHigh))
/**
* @}
*/
/** @defgroup SAI_Block_FS_Offset
* @{
*/
#define SAI_FS_FirstBit ((uint32_t)0x00000000)
#define SAI_FS_BeforeFirstBit ((uint32_t)SAI_xFRCR_FSOFF)
#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FirstBit) || \
((OFFSET) == SAI_FS_BeforeFirstBit))
/**
* @}
*/
/** @defgroup SAI_Block_Slot_FirstBit_Offset
* @{
*/
#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)
/**
* @}
*/
/** @defgroup SAI_Block_Slot_Size
* @{
*/
#define SAI_SlotSize_DataSize ((uint32_t)0x00000000)
#define SAI_SlotSize_16b ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
#define SAI_SlotSize_32b ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SlotSize_DataSize) || \
((SIZE) == SAI_SlotSize_16b) || \
((SIZE) == SAI_SlotSize_32b))
/**
* @}
*/
/** @defgroup SAI_Block_Slot_Number
* @{
*/
#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
/**
* @}
*/
/** @defgroup SAI_Block_Slot_Active
* @{
*/
#define SAI_Slot_NotActive ((uint32_t)0x00000000)
#define SAI_SlotActive_0 ((uint32_t)0x00010000)
#define SAI_SlotActive_1 ((uint32_t)0x00020000)
#define SAI_SlotActive_2 ((uint32_t)0x00040000)
#define SAI_SlotActive_3 ((uint32_t)0x00080000)
#define SAI_SlotActive_4 ((uint32_t)0x00100000)
#define SAI_SlotActive_5 ((uint32_t)0x00200000)
#define SAI_SlotActive_6 ((uint32_t)0x00400000)
#define SAI_SlotActive_7 ((uint32_t)0x00800000)
#define SAI_SlotActive_8 ((uint32_t)0x01000000)
#define SAI_SlotActive_9 ((uint32_t)0x02000000)
#define SAI_SlotActive_10 ((uint32_t)0x04000000)
#define SAI_SlotActive_11 ((uint32_t)0x08000000)
#define SAI_SlotActive_12 ((uint32_t)0x10000000)
#define SAI_SlotActive_13 ((uint32_t)0x20000000)
#define SAI_SlotActive_14 ((uint32_t)0x40000000)
#define SAI_SlotActive_15 ((uint32_t)0x80000000)
#define SAI_SlotActive_ALL ((uint32_t)0xFFFF0000)
#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) != 0)
/**
* @}
*/
/** @defgroup SAI_Mono_Streo_Mode
* @{
*/
#define SAI_MonoMode ((uint32_t)SAI_xCR1_MONO)
#define SAI_StreoMode ((uint32_t)0x00000000)
#define IS_SAI_BLOCK_MONO_STREO_MODE(MODE) (((MODE) == SAI_MonoMode) ||\
((MODE) == SAI_StreoMode))
/**
* @}
*/
/** @defgroup SAI_TRIState_Management
* @{
*/
#define SAI_Output_NotReleased ((uint32_t)0x00000000)
#define SAI_Output_Released ((uint32_t)SAI_xCR2_TRIS)
#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_Output_NotReleased) ||\
((STATE) == SAI_Output_Released))
/**
* @}
*/
/** @defgroup SAI_Block_Fifo_Threshold
* @{
*/
#define SAI_Threshold_FIFOEmpty ((uint32_t)0x00000000)
#define SAI_FIFOThreshold_1QuarterFull ((uint32_t)0x00000001)
#define SAI_FIFOThreshold_HalfFull ((uint32_t)0x00000002)
#define SAI_FIFOThreshold_3QuartersFull ((uint32_t)0x00000003)
#define SAI_FIFOThreshold_Full ((uint32_t)0x00000004)
#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_Threshold_FIFOEmpty) || \
((THRESHOLD) == SAI_FIFOThreshold_1QuarterFull) || \
((THRESHOLD) == SAI_FIFOThreshold_HalfFull) || \
((THRESHOLD) == SAI_FIFOThreshold_3QuartersFull) || \
((THRESHOLD) == SAI_FIFOThreshold_Full))
/**
* @}
*/
/** @defgroup SAI_Block_Companding_Mode
* @{
*/
#define SAI_NoCompanding ((uint32_t)0x00000000)
#define SAI_ULaw_1CPL_Companding ((uint32_t)0x00008000)
#define SAI_ALaw_1CPL_Companding ((uint32_t)0x0000C000)
#define SAI_ULaw_2CPL_Companding ((uint32_t)0x0000A000)
#define SAI_ALaw_2CPL_Companding ((uint32_t)0x0000E000)
#define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NoCompanding) || \
((MODE) == SAI_ULaw_1CPL_Companding) || \
((MODE) == SAI_ALaw_1CPL_Companding) || \
((MODE) == SAI_ULaw_2CPL_Companding) || \
((MODE) == SAI_ALaw_2CPL_Companding))
/**
* @}
*/
/** @defgroup SAI_Block_Mute_Value
* @{
*/
#define SAI_ZeroValue ((uint32_t)0x00000000)
#define SAI_LastSentValue ((uint32_t)SAI_xCR2_MUTEVAL)
#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZeroValue) || \
((VALUE) == SAI_LastSentValue))
/**
* @}
*/
/** @defgroup SAI_Block_Mute_Frame_Counter
* @{
*/
#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
/**
* @}
*/
/** @defgroup SAI_Block_Interrupts_Definition
* @{
*/
#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE)
#define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE)
#define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE)
#define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE)
#define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE)
#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE)
#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE)
#define IS_SAI_BLOCK_CONFIG_IT(IT) (((IT) == SAI_IT_OVRUDR) || \
((IT) == SAI_IT_MUTEDET) || \
((IT) == SAI_IT_WCKCFG) || \
((IT) == SAI_IT_FREQ) || \
((IT) == SAI_IT_CNRDY) || \
((IT) == SAI_IT_AFSDET) || \
((IT) == SAI_IT_LFSDET))
/**
* @}
*/
/** @defgroup SAI_Block_Flags_Definition
* @{
*/
#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR)
#define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET)
#define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG)
#define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ)
#define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY)
#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET)
#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET)
#define IS_SAI_BLOCK_GET_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR) || \
((FLAG) == SAI_FLAG_MUTEDET) || \
((FLAG) == SAI_FLAG_WCKCFG) || \
((FLAG) == SAI_FLAG_FREQ) || \
((FLAG) == SAI_FLAG_CNRDY) || \
((FLAG) == SAI_FLAG_AFSDET) || \
((FLAG) == SAI_FLAG_LFSDET))
#define IS_SAI_BLOCK_CLEAR_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR) || \
((FLAG) == SAI_FLAG_MUTEDET) || \
((FLAG) == SAI_FLAG_WCKCFG) || \
((FLAG) == SAI_FLAG_FREQ) || \
((FLAG) == SAI_FLAG_CNRDY) || \
((FLAG) == SAI_FLAG_AFSDET) || \
((FLAG) == SAI_FLAG_LFSDET))
/**
* @}
*/
/** @defgroup SAI_Block_Fifo_Status_Level
* @{
*/
#define SAI_FIFOStatus_Empty ((uint32_t)0x00000000)
#define SAI_FIFOStatus_Less1QuarterFull ((uint32_t)0x00010000)
#define SAI_FIFOStatus_1QuarterFull ((uint32_t)0x00020000)
#define SAI_FIFOStatus_HalfFull ((uint32_t)0x00030000)
#define SAI_FIFOStatus_3QuartersFull ((uint32_t)0x00040000)
#define SAI_FIFOStatus_Full ((uint32_t)0x00050000)
#define IS_SAI_BLOCK_FIFO_STATUS(STATUS) (((STATUS) == SAI_FIFOStatus_Less1QuarterFull ) || \
((STATUS) == SAI_FIFOStatus_HalfFull) || \
((STATUS) == SAI_FIFOStatus_1QuarterFull) || \
((STATUS) == SAI_FIFOStatus_3QuartersFull) || \
((STATUS) == SAI_FIFOStatus_Full) || \
((STATUS) == SAI_FIFOStatus_Empty))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Function used to set the SAI configuration to the default reset state *****/
void SAI_DeInit(SAI_TypeDef* SAIx);
/* Initialization and Configuration functions *********************************/
void SAI_Init(SAI_Block_TypeDef* SAI_Block_x, SAI_InitTypeDef* SAI_InitStruct);
void SAI_FrameInit(SAI_Block_TypeDef* SAI_Block_x, SAI_FrameInitTypeDef* SAI_FrameInitStruct);
void SAI_SlotInit(SAI_Block_TypeDef* SAI_Block_x, SAI_SlotInitTypeDef* SAI_SlotInitStruct);
void SAI_StructInit(SAI_InitTypeDef* SAI_InitStruct);
void SAI_FrameStructInit(SAI_FrameInitTypeDef* SAI_FrameInitStruct);
void SAI_SlotStructInit(SAI_SlotInitTypeDef* SAI_SlotInitStruct);
void SAI_Cmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState);
void SAI_MonoModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_Mono_StreoMode);
void SAI_TRIStateConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_TRIState);
void SAI_CompandingModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_CompandingMode);
void SAI_MuteModeCmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState);
void SAI_MuteValueConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteValue);
void SAI_MuteFrameCounterConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteCounter);
void SAI_FlushFIFO(SAI_Block_TypeDef* SAI_Block_x);
/* Data transfers functions ***************************************************/
void SAI_SendData(SAI_Block_TypeDef* SAI_Block_x, uint32_t Data);
uint32_t SAI_ReceiveData(SAI_Block_TypeDef* SAI_Block_x);
/* DMA transfers management functions *****************************************/
void SAI_DMACmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void SAI_ITConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState);
FlagStatus SAI_GetFlagStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG);
void SAI_ClearFlag(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG);
ITStatus SAI_GetITStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT);
void SAI_ClearITPendingBit(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT);
FunctionalState SAI_GetCmdStatus(SAI_Block_TypeDef* SAI_Block_x);
uint32_t SAI_GetFIFOStatus(SAI_Block_TypeDef* SAI_Block_x);
#ifdef __cplusplus
}
#endif
#endif /*__STM32F4xx_SAI_H */
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

32
example/libs/StmCoreNPheriph/inc/stm32f4xx_sdio.h
View File

@@ -2,21 +2,27 @@
******************************************************************************
* @file stm32f4xx_sdio.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the SDIO firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -77,7 +83,7 @@ typedef struct
uint32_t SDIO_Response; /*!< Specifies the SDIO response type.
This parameter can be a value of @ref SDIO_Response_Type */
uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait for interrupt request is enabled or disabled.
This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
@@ -453,8 +459,8 @@ typedef struct
* @{
*/
#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000)
#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001)
#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)
#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)
#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
((MODE) == SDIO_ReadWaitMode_DATA2))
/**
@@ -527,4 +533,4 @@ void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

46
example/libs/StmCoreNPheriph/inc/stm32f4xx_spi.h
View File

@@ -2,21 +2,27 @@
******************************************************************************
* @file stm32f4xx_spi.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the SPI
* firmware library.
* firmware library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -112,19 +118,25 @@ typedef struct
#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
((PERIPH) == SPI2) || \
((PERIPH) == SPI3))
((PERIPH) == SPI3) || \
((PERIPH) == SPI4) || \
((PERIPH) == SPI5) || \
((PERIPH) == SPI6))
#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \
((PERIPH) == SPI2) || \
((PERIPH) == SPI3) || \
#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \
((PERIPH) == SPI2) || \
((PERIPH) == SPI3) || \
((PERIPH) == SPI4) || \
((PERIPH) == SPI5) || \
((PERIPH) == SPI6) || \
((PERIPH) == I2S2ext) || \
((PERIPH) == I2S3ext))
#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
((PERIPH) == SPI3))
#define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \
((PERIPH) == SPI3) || \
#define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \
((PERIPH) == SPI3) || \
((PERIPH) == I2S2ext) || \
((PERIPH) == I2S3ext))
@@ -534,4 +546,4 @@ void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

123
example/libs/StmCoreNPheriph/inc/stm32f4xx_syscfg.h
View File

@@ -2,21 +2,27 @@
******************************************************************************
* @file stm32f4xx_syscfg.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the SYSCFG firmware
* library.
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -58,16 +64,21 @@
#define EXTI_PortSourceGPIOG ((uint8_t)0x06)
#define EXTI_PortSourceGPIOH ((uint8_t)0x07)
#define EXTI_PortSourceGPIOI ((uint8_t)0x08)
#define EXTI_PortSourceGPIOJ ((uint8_t)0x09)
#define EXTI_PortSourceGPIOK ((uint8_t)0x0A)
#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
((PORTSOURCE) == EXTI_PortSourceGPIOF) || \
((PORTSOURCE) == EXTI_PortSourceGPIOG) || \
((PORTSOURCE) == EXTI_PortSourceGPIOH) || \
((PORTSOURCE) == EXTI_PortSourceGPIOI))
((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
((PORTSOURCE) == EXTI_PortSourceGPIOF) || \
((PORTSOURCE) == EXTI_PortSourceGPIOG) || \
((PORTSOURCE) == EXTI_PortSourceGPIOH) || \
((PORTSOURCE) == EXTI_PortSourceGPIOI) || \
((PORTSOURCE) == EXTI_PortSourceGPIOJ) || \
((PORTSOURCE) == EXTI_PortSourceGPIOK))
/**
* @}
*/
@@ -92,16 +103,16 @@
#define EXTI_PinSource13 ((uint8_t)0x0D)
#define EXTI_PinSource14 ((uint8_t)0x0E)
#define EXTI_PinSource15 ((uint8_t)0x0F)
#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
((PINSOURCE) == EXTI_PinSource1) || \
((PINSOURCE) == EXTI_PinSource2) || \
((PINSOURCE) == EXTI_PinSource3) || \
((PINSOURCE) == EXTI_PinSource4) || \
((PINSOURCE) == EXTI_PinSource5) || \
((PINSOURCE) == EXTI_PinSource6) || \
((PINSOURCE) == EXTI_PinSource7) || \
((PINSOURCE) == EXTI_PinSource8) || \
((PINSOURCE) == EXTI_PinSource9) || \
#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
((PINSOURCE) == EXTI_PinSource1) || \
((PINSOURCE) == EXTI_PinSource2) || \
((PINSOURCE) == EXTI_PinSource3) || \
((PINSOURCE) == EXTI_PinSource4) || \
((PINSOURCE) == EXTI_PinSource5) || \
((PINSOURCE) == EXTI_PinSource6) || \
((PINSOURCE) == EXTI_PinSource7) || \
((PINSOURCE) == EXTI_PinSource8) || \
((PINSOURCE) == EXTI_PinSource9) || \
((PINSOURCE) == EXTI_PinSource10) || \
((PINSOURCE) == EXTI_PinSource11) || \
((PINSOURCE) == EXTI_PinSource12) || \
@@ -118,13 +129,38 @@
*/
#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)
#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02)
#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
((REMAP) == SYSCFG_MemoryRemap_SRAM) || \
((REMAP) == SYSCFG_MemoryRemap_FSMC))
#define SYSCFG_MemoryRemap_SDRAM ((uint8_t)0x04)
#if defined (STM32F40_41xxx)
#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02)
#endif /* STM32F40_41xxx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define SYSCFG_MemoryRemap_FMC ((uint8_t)0x02)
#endif /* STM32F427_437xx || STM32F429_439xx */
#if defined (STM32F40_41xxx)
#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
((REMAP) == SYSCFG_MemoryRemap_SRAM) || \
((REMAP) == SYSCFG_MemoryRemap_FSMC))
#endif /* STM32F40_41xxx */
#if defined (STM32F401xx) || defined (STM32F411xE)
#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
((REMAP) == SYSCFG_MemoryRemap_SRAM))
#endif /* STM32F401xx || STM32F411xE */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
((REMAP) == SYSCFG_MemoryRemap_SRAM) || \
((REMAP) == SYSCFG_MemoryRemap_SDRAM) || \
((REMAP) == SYSCFG_MemoryRemap_FMC))
#endif /* STM32F427_437xx || STM32F429_439xx */
/**
* @}
*/
@@ -133,11 +169,11 @@
/** @defgroup SYSCFG_ETHERNET_Media_Interface
* @{
*/
#define SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000)
#define SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001)
#define SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000)
#define SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001)
#define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \
((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII))
((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII))
/**
* @}
*/
@@ -150,10 +186,11 @@
/* Exported functions --------------------------------------------------------*/
void SYSCFG_DeInit(void);
void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface);
void SYSCFG_CompensationCellCmd(FunctionalState NewState);
void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);
void SYSCFG_MemorySwappingBank(FunctionalState NewState);
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface);
void SYSCFG_CompensationCellCmd(FunctionalState NewState);
FlagStatus SYSCFG_GetCompensationCellStatus(void);
#ifdef __cplusplus
@@ -170,4 +207,4 @@ FlagStatus SYSCFG_GetCompensationCellStatus(void);
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
example/libs/StmCoreNPheriph/inc/stm32f4xx_tim.h
View File

@@ -2,21 +2,27 @@
******************************************************************************
* @file stm32f4xx_tim.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the TIM firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -1141,4 +1147,4 @@ void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

32
example/libs/StmCoreNPheriph/inc/stm32f4xx_usart.h
View File

@@ -2,21 +2,27 @@
******************************************************************************
* @file stm32f4xx_usart.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the USART
* firmware library.
* firmware library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -106,7 +112,9 @@ typedef struct
((PERIPH) == USART3) || \
((PERIPH) == UART4) || \
((PERIPH) == UART5) || \
((PERIPH) == USART6))
((PERIPH) == USART6) || \
((PERIPH) == UART7) || \
((PERIPH) == UART8))
#define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \
((PERIPH) == USART2) || \
@@ -420,4 +428,4 @@ void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
example/libs/StmCoreNPheriph/inc/stm32f4xx_wwdg.h
View File

@@ -2,21 +2,27 @@
******************************************************************************
* @file stm32f4xx_wwdg.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @version V1.4.0
* @date 04-August-2014
* @brief This file contains all the functions prototypes for the WWDG firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -102,4 +108,4 @@ void WWDG_ClearFlag(void);
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

28
example/libs/StmCoreNPheriph/inc/system_stm32f4xx.h
View File

@@ -2,20 +2,26 @@
******************************************************************************
* @file system_stm32f4xx.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
* @version V1.4.0
* @date 04-August-2014
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
@@ -96,4 +102,4 @@ extern void SystemCoreClockUpdate(void);
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/